[PATCH v9 0/7] Add LMCE support

[PATCH v9 0/7] Add LMCE support

[Haozhong Zhang]

Changes in v9:
 * Minor updates in patch 1 per Jan's comments.
 * Collect Jan's R-b in patch 2.

Haozhong Zhang (7):
  [M   ] x86/domctl: generalize the restore of vMCE parameters
  [  R ] x86/vmce: emulate MSR_IA32_MCG_EXT_CTL
  [  R ] x86/vmce: enable injecting LMCE to guest on Intel host
  [  RA] x86/vmce, tools/libxl: expose LMCE capability in guest MSR_IA32_MCG_CAP
  [  R ] xen/mce: add support of vLMCE injection to XEN_MC_inject_v2
  [   A] tools/libxc: add support of injecting MC# to specified CPUs
  [   A] tools/xen-mceinj: add support of injecting LMCE

 N: new in this version
 M: modified in this version
 R: got R-b
 A: got A-b

 docs/man/xl.cfg.pod.5.in                | 24 +++++++++++++
 tools/libxc/include/xenctrl.h           |  2 ++
 tools/libxc/xc_misc.c                   | 52 ++++++++++++++++++++++++++-
 tools/libxc/xc_sr_save_x86_hvm.c        |  1 +
 tools/libxl/libxl.h                     |  7 ++++
 tools/libxl/libxl_dom.c                 | 15 ++++++++
 tools/libxl/libxl_types.idl             |  1 +
 tools/tests/mce-test/tools/xen-mceinj.c | 50 ++++++++++++++++++++++++--
 tools/xl/xl_parse.c                     | 31 ++++++++++++++--
 xen/arch/x86/cpu/mcheck/mcaction.c      | 23 ++++++++----
 xen/arch/x86/cpu/mcheck/mce.c           | 24 ++++++++++++-
 xen/arch/x86/cpu/mcheck/mce.h           |  1 +
 xen/arch/x86/cpu/mcheck/mce_intel.c     |  2 +-
 xen/arch/x86/cpu/mcheck/vmce.c          | 64 +++++++++++++++++++++++++++++++--
 xen/arch/x86/cpu/mcheck/vmce.h          |  2 +-
 xen/arch/x86/domctl.c                   | 57 ++++++++++++++++++++---------
 xen/arch/x86/hvm/hvm.c                  |  5 +++
 xen/include/asm-x86/mce.h               |  2 ++
 xen/include/public/arch-x86/hvm/save.h  |  1 +
 xen/include/public/arch-x86/xen-mca.h   |  1 +
 xen/include/public/hvm/params.h         |  7 +++-
 21 files changed, 336 insertions(+), 36 deletions(-)

-- 
2.11.0


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[PATCH v9 1/7] x86/domctl: generalize the restore of vMCE parameters

[Haozhong Zhang]

vMCE parameters in struct xen_domctl_ext_vcpucontext were extended in
the past, and is likely to be extended in the future. When migrating a
PV domain from old Xen, XEN_DOMCTL_set_ext_vcpucontext should handle
the differences.

Instead of adding ad-hoc handling code at each extension, we introduce
an array to record sizes of the current and all past versions of vMCE
parameters, and search for the largest one that does not expire the
size of passed-in parameters to determine vMCE parameters that will be
restored. If vMCE parameters are extended in the future, we only need
to adapt the array to reflect the extension.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
---
Cc: Jan Beulich <jbeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>

Changes in v9:
 * Rename "param" to "field" in macro VMCE_SIZE().
 * Use min(..., sizeof(evc->vmce)) to get the size of vMCE parameters.
---
 xen/arch/x86/domctl.c | 55 +++++++++++++++++++++++++++++++++++----------------
 1 file changed, 38 insertions(+), 17 deletions(-)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 7fa58b49af..3637d32669 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -302,6 +302,43 @@ static int update_domain_cpuid_info(struct domain *d,
     return 0;
 }
 
+static int vcpu_set_vmce(struct vcpu *v,
+                         const struct xen_domctl_ext_vcpucontext *evc)
+{
+    /*
+     * Sizes of vMCE parameters used by the current and past versions
+     * of Xen in descending order. If vMCE parameters are extended,
+     * remember to add the old size to this array by VMCE_SIZE().
+     */
+#define VMCE_SIZE(field) \
+    (offsetof(typeof(evc->vmce), field) + sizeof(evc->vmce.field))
+
+    static const unsigned int valid_sizes[] = {
+        sizeof(evc->vmce),
+        VMCE_SIZE(caps),
+    };
+#undef VMCE_SIZE
+
+    struct hvm_vmce_vcpu vmce = { };
+    unsigned int evc_vmce_size =
+        min(evc->size - offsetof(typeof(*evc), mcg_cap), sizeof(evc->vmce));
+    unsigned int i = 0;
+
+    BUILD_BUG_ON(offsetof(typeof(*evc), mcg_cap) !=
+                 offsetof(typeof(*evc), vmce.caps));
+    BUILD_BUG_ON(sizeof(evc->mcg_cap) != sizeof(evc->vmce.caps));
+
+    while ( i < ARRAY_SIZE(valid_sizes) && evc_vmce_size < valid_sizes[i] )
+        ++i;
+
+    if ( i == ARRAY_SIZE(valid_sizes) )
+        return 0;
+
+    memcpy(&vmce, &evc->vmce, valid_sizes[i]);
+
+    return vmce_restore_vcpu(v, &vmce);
+}
+
 void arch_get_domain_info(const struct domain *d,
                           struct xen_domctl_getdomaininfo *info)
 {
@@ -912,23 +949,7 @@ long arch_do_domctl(
             else
                 domain_pause(d);
 
-            BUILD_BUG_ON(offsetof(struct xen_domctl_ext_vcpucontext,
-                                  mcg_cap) !=
-                         offsetof(struct xen_domctl_ext_vcpucontext,
-                                  vmce.caps));
-            BUILD_BUG_ON(sizeof(evc->mcg_cap) != sizeof(evc->vmce.caps));
-            if ( evc->size >= offsetof(typeof(*evc), vmce) +
-                              sizeof(evc->vmce) )
-                ret = vmce_restore_vcpu(v, &evc->vmce);
-            else if ( evc->size >= offsetof(typeof(*evc), mcg_cap) +
-                                   sizeof(evc->mcg_cap) )
-            {
-                struct hvm_vmce_vcpu vmce = { .caps = evc->mcg_cap };
-
-                ret = vmce_restore_vcpu(v, &vmce);
-            }
-            else
-                ret = 0;
+            ret = vcpu_set_vmce(v, evc);
 
             domain_unpause(d);
         }
-- 
2.11.0


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[PATCH v9 2/7] x86/vmce: emulate MSR_IA32_MCG_EXT_CTL

[Haozhong Zhang]

If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then allow guest
to read/write MSR_IA32_MCG_EXT_CTL.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
Cc: Jan Beulich <jbeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/cpu/mcheck/vmce.c         | 34 +++++++++++++++++++++++++++++++++-
 xen/arch/x86/domctl.c                  |  2 ++
 xen/include/asm-x86/mce.h              |  1 +
 xen/include/public/arch-x86/hvm/save.h |  1 +
 4 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index 1356f611ab..060e2d0582 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -91,6 +91,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt)
     v->arch.vmce.mcg_cap = ctxt->caps;
     v->arch.vmce.bank[0].mci_ctl2 = ctxt->mci_ctl2_bank0;
     v->arch.vmce.bank[1].mci_ctl2 = ctxt->mci_ctl2_bank1;
+    v->arch.vmce.mcg_ext_ctl = ctxt->mcg_ext_ctl;
 
     return 0;
 }
@@ -200,6 +201,26 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val)
         mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_CTL %#"PRIx64"\n", cur, *val);
         break;
 
+    case MSR_IA32_MCG_EXT_CTL:
+        /*
+         * If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, the LMCE and LOCK
+         * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen, so it
+         * does not need to check them here.
+         */
+        if ( cur->arch.vmce.mcg_cap & MCG_LMCE_P )
+        {
+            *val = cur->arch.vmce.mcg_ext_ctl;
+            mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n",
+                       cur, *val);
+        }
+        else
+        {
+            ret = -1;
+            mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL, not supported\n",
+                       cur);
+        }
+        break;
+
     default:
         ret = mce_bank_msr(cur, msr) ? bank_mce_rdmsr(cur, msr, val) : 0;
         break;
@@ -309,6 +330,16 @@ int vmce_wrmsr(uint32_t msr, uint64_t val)
         mce_printk(MCE_VERBOSE, "MCE: %pv: MCG_CAP is r/o\n", cur);
         break;
 
+    case MSR_IA32_MCG_EXT_CTL:
+        if ( (cur->arch.vmce.mcg_cap & MCG_LMCE_P) &&
+             !(val & ~MCG_EXT_CTL_LMCE_EN) )
+            cur->arch.vmce.mcg_ext_ctl = val;
+        else
+            ret = -1;
+        mce_printk(MCE_VERBOSE, "MCE: %pv: wr MCG_EXT_CTL %"PRIx64"%s\n",
+                   cur, val, (ret == -1) ? ", not supported" : "");
+        break;
+
     default:
         ret = mce_bank_msr(cur, msr) ? bank_mce_wrmsr(cur, msr, val) : 0;
         break;
@@ -327,7 +358,8 @@ static int vmce_save_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h)
         struct hvm_vmce_vcpu ctxt = {
             .caps = v->arch.vmce.mcg_cap,
             .mci_ctl2_bank0 = v->arch.vmce.bank[0].mci_ctl2,
-            .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2
+            .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2,
+            .mcg_ext_ctl = v->arch.vmce.mcg_ext_ctl,
         };
 
         err = hvm_save_entry(VMCE_VCPU, v->vcpu_id, h, &ctxt);
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 3637d32669..3628af2f70 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -315,6 +315,7 @@ static int vcpu_set_vmce(struct vcpu *v,
 
     static const unsigned int valid_sizes[] = {
         sizeof(evc->vmce),
+        VMCE_SIZE(mci_ctl2_bank1),
         VMCE_SIZE(caps),
     };
 #undef VMCE_SIZE
@@ -908,6 +909,7 @@ long arch_do_domctl(
             evc->vmce.caps = v->arch.vmce.mcg_cap;
             evc->vmce.mci_ctl2_bank0 = v->arch.vmce.bank[0].mci_ctl2;
             evc->vmce.mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2;
+            evc->vmce.mcg_ext_ctl = v->arch.vmce.mcg_ext_ctl;
 
             ret = 0;
             vcpu_unpause(v);
diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h
index 56ad1f92dd..35f9962638 100644
--- a/xen/include/asm-x86/mce.h
+++ b/xen/include/asm-x86/mce.h
@@ -27,6 +27,7 @@ struct vmce_bank {
 struct vmce {
     uint64_t mcg_cap;
     uint64_t mcg_status;
+    uint64_t mcg_ext_ctl;
     spinlock_t lock;
     struct vmce_bank bank[GUEST_MC_BANK_NUM];
 };
diff --git a/xen/include/public/arch-x86/hvm/save.h b/xen/include/public/arch-x86/hvm/save.h
index 816973b9c2..fd7bf3fb38 100644
--- a/xen/include/public/arch-x86/hvm/save.h
+++ b/xen/include/public/arch-x86/hvm/save.h
@@ -610,6 +610,7 @@ struct hvm_vmce_vcpu {
     uint64_t caps;
     uint64_t mci_ctl2_bank0;
     uint64_t mci_ctl2_bank1;
+    uint64_t mcg_ext_ctl;
 };
 
 DECLARE_HVM_SAVE_TYPE(VMCE_VCPU, 18, struct hvm_vmce_vcpu);
-- 
2.11.0


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[PATCH v9 3/7] x86/vmce: enable injecting LMCE to guest on Intel host

[Haozhong Zhang]

Inject LMCE to guest if the host MCE is LMCE and the affected vcpu is
known. Otherwise, broadcast MCE to all vcpus on Intel host.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
Cc: Jan Beulich <jbeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/cpu/mcheck/mcaction.c | 23 ++++++++++++++++-------
 xen/arch/x86/cpu/mcheck/vmce.c     | 11 ++++++++++-
 xen/arch/x86/cpu/mcheck/vmce.h     |  2 +-
 3 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/mcaction.c b/xen/arch/x86/cpu/mcheck/mcaction.c
index ca17d22bd8..f959bed2cb 100644
--- a/xen/arch/x86/cpu/mcheck/mcaction.c
+++ b/xen/arch/x86/cpu/mcheck/mcaction.c
@@ -44,6 +44,7 @@ mc_memerr_dhandler(struct mca_binfo *binfo,
     unsigned long mfn, gfn;
     uint32_t status;
     int vmce_vcpuid;
+    unsigned int mc_vcpuid;
 
     if (!mc_check_addr(bank->mc_status, bank->mc_misc, MC_ADDR_PHYSICAL)) {
         dprintk(XENLOG_WARNING,
@@ -88,18 +89,26 @@ mc_memerr_dhandler(struct mca_binfo *binfo,
                     goto vmce_failed;
                 }
 
-                if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
-                    global->mc_vcpuid == XEN_MC_VCPUID_INVALID)
+                mc_vcpuid = global->mc_vcpuid;
+                if (mc_vcpuid == XEN_MC_VCPUID_INVALID ||
+                    /*
+                     * Because MC# may happen asynchronously with the actual
+                     * operation that triggers the error, the domain ID as
+                     * well as the vCPU ID collected in 'global' at MC# are
+                     * not always precise. In that case, fallback to broadcast.
+                     */
+                    global->mc_domid != bank->mc_domid ||
+                    (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+                     (!(global->mc_gstatus & MCG_STATUS_LMCE) ||
+                      !(d->vcpu[mc_vcpuid]->arch.vmce.mcg_ext_ctl &
+                        MCG_EXT_CTL_LMCE_EN))))
                     vmce_vcpuid = VMCE_INJECT_BROADCAST;
                 else
-                    vmce_vcpuid = global->mc_vcpuid;
+                    vmce_vcpuid = mc_vcpuid;
 
                 bank->mc_addr = gfn << PAGE_SHIFT |
                   (bank->mc_addr & (PAGE_SIZE -1 ));
-                /* TODO: support injecting LMCE */
-                if (fill_vmsr_data(bank, d,
-                                   global->mc_gstatus & ~MCG_STATUS_LMCE,
-                                   vmce_vcpuid == VMCE_INJECT_BROADCAST))
+                if (fill_vmsr_data(bank, d, global->mc_gstatus, vmce_vcpuid))
                 {
                     mce_printk(MCE_QUIET, "Fill vMCE# data for DOM%d "
                       "failed\n", bank->mc_domid);
diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index 060e2d0582..e2b3c5b8cc 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -465,14 +465,23 @@ static int vcpu_fill_mc_msrs(struct vcpu *v, uint64_t mcg_status,
 }
 
 int fill_vmsr_data(struct mcinfo_bank *mc_bank, struct domain *d,
-                   uint64_t gstatus, bool broadcast)
+                   uint64_t gstatus, int vmce_vcpuid)
 {
     struct vcpu *v = d->vcpu[0];
+    bool broadcast = (vmce_vcpuid == VMCE_INJECT_BROADCAST);
     int ret, err;
 
     if ( mc_bank->mc_domid == DOMID_INVALID )
         return -EINVAL;
 
+    if ( broadcast )
+        gstatus &= ~MCG_STATUS_LMCE;
+    else if ( gstatus & MCG_STATUS_LMCE )
+    {
+        ASSERT(vmce_vcpuid >= 0 && vmce_vcpuid < d->max_vcpus);
+        v = d->vcpu[vmce_vcpuid];
+    }
+
     /*
      * vMCE with the actual error information is injected to vCPU0,
      * and, if broadcast is required, we choose to inject less severe
diff --git a/xen/arch/x86/cpu/mcheck/vmce.h b/xen/arch/x86/cpu/mcheck/vmce.h
index 74f6381460..2797e00275 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.h
+++ b/xen/arch/x86/cpu/mcheck/vmce.h
@@ -17,7 +17,7 @@ int vmce_amd_rdmsr(const struct vcpu *, uint32_t msr, uint64_t *val);
 int vmce_amd_wrmsr(struct vcpu *, uint32_t msr, uint64_t val);
 
 int fill_vmsr_data(struct mcinfo_bank *mc_bank, struct domain *d,
-                   uint64_t gstatus, bool broadcast);
+                   uint64_t gstatus, int vmce_vcpuid);
 
 #define VMCE_INJECT_BROADCAST (-1)
 int inject_vmce(struct domain *d, int vcpu);
-- 
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[PATCH v9 4/7] x86/vmce, tools/libxl: expose LMCE capability in guest MSR_IA32_MCG_CAP

[Haozhong Zhang]

If LMCE is supported by host and ' mca_caps = [ "lmce" ] ' is present
in xl config, the LMCE capability will be exposed in guest MSR_IA32_MCG_CAP.
By default, LMCE is not exposed to guest so as to keep the backwards migration
compatibility.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com> for hypervisor side
Acked-by: Wei Liu <wei.liu2@citrix.com>
---
Cc: Ian Jackson <ian.jackson@eu.citrix.com>
Cc: Wei Liu <wei.liu2@citrix.com>
Cc: Jan Beulich <jbeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/man/xl.cfg.pod.5.in            | 24 ++++++++++++++++++++++++
 tools/libxc/xc_sr_save_x86_hvm.c    |  1 +
 tools/libxl/libxl.h                 |  7 +++++++
 tools/libxl/libxl_dom.c             | 15 +++++++++++++++
 tools/libxl/libxl_types.idl         |  1 +
 tools/xl/xl_parse.c                 | 31 +++++++++++++++++++++++++++++--
 xen/arch/x86/cpu/mcheck/mce.h       |  1 +
 xen/arch/x86/cpu/mcheck/mce_intel.c |  2 +-
 xen/arch/x86/cpu/mcheck/vmce.c      | 19 ++++++++++++++++++-
 xen/arch/x86/hvm/hvm.c              |  5 +++++
 xen/include/asm-x86/mce.h           |  1 +
 xen/include/public/hvm/params.h     |  7 ++++++-
 12 files changed, 109 insertions(+), 5 deletions(-)

diff --git a/docs/man/xl.cfg.pod.5.in b/docs/man/xl.cfg.pod.5.in
index ff3203550f..79cb2eaea7 100644
--- a/docs/man/xl.cfg.pod.5.in
+++ b/docs/man/xl.cfg.pod.5.in
@@ -2173,6 +2173,30 @@ natively or via hardware backwards compatibility support.
 
 =back
 
+=head3 x86
+
+=over 4
+
+=item B<mca_caps=[ "CAP", "CAP", ... ]>
+
+(HVM only) Enable MCA capabilities besides default ones enabled
+by Xen hypervisor for the HVM domain. "CAP" can be one in the
+following list:
+
+=over 4
+
+=item B<"lmce">
+
+Intel local MCE
+
+=item B<default>
+
+No MCA capabilities in above list are enabled.
+
+=back
+
+=back
+
 =head1 SEE ALSO
 
 =over 4
diff --git a/tools/libxc/xc_sr_save_x86_hvm.c b/tools/libxc/xc_sr_save_x86_hvm.c
index fc5c6ea93e..e17bb59146 100644
--- a/tools/libxc/xc_sr_save_x86_hvm.c
+++ b/tools/libxc/xc_sr_save_x86_hvm.c
@@ -77,6 +77,7 @@ static int write_hvm_params(struct xc_sr_context *ctx)
         HVM_PARAM_IOREQ_SERVER_PFN,
         HVM_PARAM_NR_IOREQ_SERVER_PAGES,
         HVM_PARAM_X87_FIP_WIDTH,
+        HVM_PARAM_MCA_CAP,
     };
 
     xc_interface *xch = ctx->xch;
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index cf8687aa7e..7cf0f31f68 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -922,6 +922,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, const libxl_mac *src);
  * If this is defined, the Code and Data Prioritization feature is supported.
  */
 #define LIBXL_HAVE_PSR_CDP 1
+
+/*
+ * LIBXL_HAVE_MCA_CAPS
+ *
+ * If this is defined, setting MCA capabilities for HVM domain is supported.
+ */
+#define LIBXL_HAVE_MCA_CAPS 1
 #endif
 
 /*
diff --git a/tools/libxl/libxl_dom.c b/tools/libxl/libxl_dom.c
index 5d914a59ee..f54fd49a73 100644
--- a/tools/libxl/libxl_dom.c
+++ b/tools/libxl/libxl_dom.c
@@ -279,6 +279,17 @@ err:
     libxl_bitmap_dispose(&enlightenments);
     return ERROR_FAIL;
 }
+
+static int hvm_set_mca_capabilities(libxl__gc *gc, uint32_t domid,
+                                    libxl_domain_build_info *const info)
+{
+    unsigned long caps = info->u.hvm.mca_caps;
+
+    if (!caps)
+        return 0;
+
+    return xc_hvm_param_set(CTX->xch, domid, HVM_PARAM_MCA_CAP, caps);
+}
 #endif
 
 static void hvm_set_conf_params(xc_interface *handle, uint32_t domid,
@@ -440,6 +451,10 @@ int libxl__build_pre(libxl__gc *gc, uint32_t domid,
         rc = hvm_set_viridian_features(gc, domid, info);
         if (rc)
             return rc;
+
+        rc = hvm_set_mca_capabilities(gc, domid, info);
+        if (rc)
+            return rc;
 #endif
     }
 
diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
index 22044259f3..8a9849c643 100644
--- a/tools/libxl/libxl_types.idl
+++ b/tools/libxl/libxl_types.idl
@@ -564,6 +564,7 @@ libxl_domain_build_info = Struct("domain_build_info",[
                                        ("serial_list",      libxl_string_list),
                                        ("rdm", libxl_rdm_reserve),
                                        ("rdm_mem_boundary_memkb", MemKB),
+                                       ("mca_caps",         uint64),
                                        ])),
                  ("pv", Struct(None, [("kernel", string),
                                       ("slack_memkb", MemKB),
diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
index 856a304b30..5c2bf17222 100644
--- a/tools/xl/xl_parse.c
+++ b/tools/xl/xl_parse.c
@@ -18,6 +18,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <xen/hvm/e820.h>
+#include <xen/hvm/params.h>
 
 #include <libxl.h>
 #include <libxl_utils.h>
@@ -813,8 +814,9 @@ void parse_config_data(const char *config_source,
     XLU_Config *config;
     XLU_ConfigList *cpus, *vbds, *nics, *pcis, *cvfbs, *cpuids, *vtpms,
                    *usbctrls, *usbdevs, *p9devs;
-    XLU_ConfigList *channels, *ioports, *irqs, *iomem, *viridian, *dtdevs;
-    int num_ioports, num_irqs, num_iomem, num_cpus, num_viridian;
+    XLU_ConfigList *channels, *ioports, *irqs, *iomem, *viridian, *dtdevs,
+                   *mca_caps;
+    int num_ioports, num_irqs, num_iomem, num_cpus, num_viridian, num_mca_caps;
     int pci_power_mgmt = 0;
     int pci_msitranslate = 0;
     int pci_permissive = 0;
@@ -1182,6 +1184,31 @@ void parse_config_data(const char *config_source,
 
         if (!xlu_cfg_get_long (config, "rdm_mem_boundary", &l, 0))
             b_info->u.hvm.rdm_mem_boundary_memkb = l * 1024;
+
+        switch (xlu_cfg_get_list(config, "mca_caps",
+                                 &mca_caps, &num_mca_caps, 1))
+        {
+        case 0: /* Success */
+            for (i = 0; i < num_mca_caps; i++) {
+                buf = xlu_cfg_get_listitem(mca_caps, i);
+                if (!strcmp(buf, "lmce"))
+                    b_info->u.hvm.mca_caps |= XEN_HVM_MCA_CAP_LMCE;
+                else {
+                    fprintf(stderr, "ERROR: unrecognized MCA capability '%s'.\n",
+                            buf);
+                    exit(-ERROR_FAIL);
+                }
+            }
+            break;
+
+        case ESRCH: /* Option not present */
+            break;
+
+        default:
+            fprintf(stderr, "ERROR: unable to parse mca_caps.\n");
+            exit(-ERROR_FAIL);
+        }
+
         break;
     case LIBXL_DOMAIN_TYPE_PV:
     {
diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h
index 4f13791948..664161a2af 100644
--- a/xen/arch/x86/cpu/mcheck/mce.h
+++ b/xen/arch/x86/cpu/mcheck/mce.h
@@ -38,6 +38,7 @@ enum mcheck_type {
 };
 
 extern uint8_t cmci_apic_vector;
+extern bool lmce_support;
 
 /* Init functions */
 enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *c);
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 5cb49ca697..4c001b407f 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -30,7 +30,7 @@ boolean_param("mce_fb", mce_force_broadcast);
 static int __read_mostly nr_intel_ext_msrs;
 
 /* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */
-static bool __read_mostly lmce_support;
+bool __read_mostly lmce_support;
 
 /* Intel SDM define bit15~bit0 of IA32_MCi_STATUS as the MC error code */
 #define INTEL_MCCOD_MASK 0xFFFF
diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index e2b3c5b8cc..62faae49c6 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -75,7 +75,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt)
     unsigned long guest_mcg_cap;
 
     if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
-        guest_mcg_cap = INTEL_GUEST_MCG_CAP;
+        guest_mcg_cap = INTEL_GUEST_MCG_CAP | MCG_LMCE_P;
     else
         guest_mcg_cap = AMD_GUEST_MCG_CAP;
 
@@ -547,3 +547,20 @@ int unmmap_broken_page(struct domain *d, mfn_t mfn, unsigned long gfn)
     return rc;
 }
 
+int vmce_enable_mca_cap(struct domain *d, uint64_t cap)
+{
+    struct vcpu *v;
+
+    if ( cap & ~XEN_HVM_MCA_CAP_MASK )
+        return -EINVAL;
+
+    if ( cap & XEN_HVM_MCA_CAP_LMCE )
+    {
+        if ( !lmce_support )
+            return -EINVAL;
+        for_each_vcpu(d, v)
+            v->arch.vmce.mcg_cap |= MCG_LMCE_P;
+    }
+
+    return 0;
+}
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 3ed6ec468d..8145385747 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4035,6 +4035,7 @@ static int hvm_allow_set_param(struct domain *d,
     case HVM_PARAM_IOREQ_SERVER_PFN:
     case HVM_PARAM_NR_IOREQ_SERVER_PAGES:
     case HVM_PARAM_ALTP2M:
+    case HVM_PARAM_MCA_CAP:
         if ( value != 0 && a->value != value )
             rc = -EEXIST;
         break;
@@ -4246,6 +4247,10 @@ static int hvmop_set_param(
                                                (0x10000 / 8) + 1) << 32);
         a.value |= VM86_TSS_UPDATED;
         break;
+
+    case HVM_PARAM_MCA_CAP:
+        rc = vmce_enable_mca_cap(d, a.value);
+        break;
     }
 
     if ( rc != 0 )
diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h
index 35f9962638..d2933c91bf 100644
--- a/xen/include/asm-x86/mce.h
+++ b/xen/include/asm-x86/mce.h
@@ -38,6 +38,7 @@ extern int vmce_restore_vcpu(struct vcpu *, const struct hvm_vmce_vcpu *);
 extern int vmce_wrmsr(uint32_t msr, uint64_t val);
 extern int vmce_rdmsr(uint32_t msr, uint64_t *val);
 extern bool vmce_has_lmce(const struct vcpu *v);
+extern int vmce_enable_mca_cap(struct domain *d, uint64_t cap);
 
 extern unsigned int nr_mce_banks;
 
diff --git a/xen/include/public/hvm/params.h b/xen/include/public/hvm/params.h
index 1f3ed0906d..2ec2e7c80f 100644
--- a/xen/include/public/hvm/params.h
+++ b/xen/include/public/hvm/params.h
@@ -274,6 +274,11 @@
  */
 #define HVM_PARAM_VM86_TSS_SIZED 37
 
-#define HVM_NR_PARAMS 38
+/* Enable MCA capabilities. */
+#define HVM_PARAM_MCA_CAP 38
+#define XEN_HVM_MCA_CAP_LMCE   (xen_mk_ullong(1) << 0)
+#define XEN_HVM_MCA_CAP_MASK   XEN_HVM_MCA_CAP_LMCE
+
+#define HVM_NR_PARAMS 39
 
 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
-- 
2.11.0


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[PATCH v9 5/7] xen/mce: add support of vLMCE injection to XEN_MC_inject_v2

[Haozhong Zhang]

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
Cc: Jan Beulich <jbeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/cpu/mcheck/mce.c         | 24 +++++++++++++++++++++++-
 xen/include/public/arch-x86/xen-mca.h |  1 +
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index ee04fb54ff..30525dd78b 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -1485,11 +1485,12 @@ long do_mca(XEN_GUEST_HANDLE_PARAM(xen_mc_t) u_xen_mc)
     {
         const cpumask_t *cpumap;
         cpumask_var_t cmv;
+        bool broadcast = op->u.mc_inject_v2.flags & XEN_MC_INJECT_CPU_BROADCAST;
 
         if (nr_mce_banks == 0)
             return x86_mcerr("do_mca #MC", -ENODEV);
 
-        if ( op->u.mc_inject_v2.flags & XEN_MC_INJECT_CPU_BROADCAST )
+        if ( broadcast )
             cpumap = &cpu_online_map;
         else
         {
@@ -1529,6 +1530,27 @@ long do_mca(XEN_GUEST_HANDLE_PARAM(xen_mc_t) u_xen_mc)
             }
             break;
 
+        case XEN_MC_INJECT_TYPE_LMCE:
+            if ( !lmce_support )
+            {
+                ret = x86_mcerr("No LMCE support", -EINVAL);
+                break;
+            }
+            if ( broadcast )
+            {
+                ret = x86_mcerr("Broadcast cannot be used with LMCE", -EINVAL);
+                break;
+            }
+            /* Ensure at most one CPU is specified. */
+            if ( nr_cpu_ids > cpumask_next(cpumask_first(cpumap), cpumap) )
+            {
+                ret = x86_mcerr("More than one CPU specified for LMCE",
+                                -EINVAL);
+                break;
+            }
+            on_selected_cpus(cpumap, x86_mc_mceinject, NULL, 1);
+            break;
+
         default:
             ret = x86_mcerr("Wrong mca type\n", -EINVAL);
             break;
diff --git a/xen/include/public/arch-x86/xen-mca.h b/xen/include/public/arch-x86/xen-mca.h
index 7db990723b..dc35267249 100644
--- a/xen/include/public/arch-x86/xen-mca.h
+++ b/xen/include/public/arch-x86/xen-mca.h
@@ -414,6 +414,7 @@ struct xen_mc_mceinject {
 #define XEN_MC_INJECT_TYPE_MASK     0x7
 #define XEN_MC_INJECT_TYPE_MCE      0x0
 #define XEN_MC_INJECT_TYPE_CMCI     0x1
+#define XEN_MC_INJECT_TYPE_LMCE     0x2
 
 #define XEN_MC_INJECT_CPU_BROADCAST 0x8
 
-- 
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[PATCH v9 6/7] tools/libxc: add support of injecting MC# to specified CPUs

[Haozhong Zhang]

Though XEN_MC_inject_v2 allows injecting MC# to specified CPUs, the
current xc_mca_op() does not use this feature and not provide an
interface to callers. This commit add a new xc_mca_op_inject_v2() that
receives a cpumap providing the set of target CPUs.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
---
Cc: Ian Jackson <ian.jackson@eu.citrix.com>
Cc: Wei Liu <wei.liu2@citrix.com>
---
 tools/libxc/include/xenctrl.h |  2 ++
 tools/libxc/xc_misc.c         | 52 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index c51bb3b448..552a4fd47d 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -1809,6 +1809,8 @@ int xc_cpuid_apply_policy(xc_interface *xch,
 void xc_cpuid_to_str(const unsigned int *regs,
                      char **strs); /* some strs[] may be NULL if ENOMEM */
 int xc_mca_op(xc_interface *xch, struct xen_mc *mc);
+int xc_mca_op_inject_v2(xc_interface *xch, unsigned int flags,
+                        xc_cpumap_t cpumap, unsigned int nr_cpus);
 #endif
 
 struct xc_px_val {
diff --git a/tools/libxc/xc_misc.c b/tools/libxc/xc_misc.c
index 88084fde30..2303293c6c 100644
--- a/tools/libxc/xc_misc.c
+++ b/tools/libxc/xc_misc.c
@@ -341,7 +341,57 @@ int xc_mca_op(xc_interface *xch, struct xen_mc *mc)
     xc_hypercall_bounce_post(xch, mc);
     return ret;
 }
-#endif
+
+int xc_mca_op_inject_v2(xc_interface *xch, unsigned int flags,
+                        xc_cpumap_t cpumap, unsigned int nr_bits)
+{
+    int ret = -1;
+    struct xen_mc mc_buf, *mc = &mc_buf;
+    struct xen_mc_inject_v2 *inject = &mc->u.mc_inject_v2;
+
+    DECLARE_HYPERCALL_BOUNCE(cpumap, 0, XC_HYPERCALL_BUFFER_BOUNCE_IN);
+    DECLARE_HYPERCALL_BOUNCE(mc, sizeof(*mc), XC_HYPERCALL_BUFFER_BOUNCE_BOTH);
+
+    memset(mc, 0, sizeof(*mc));
+
+    if ( cpumap )
+    {
+        if ( !nr_bits )
+        {
+            errno = EINVAL;
+            goto out;
+        }
+
+        HYPERCALL_BOUNCE_SET_SIZE(cpumap, (nr_bits + 7) / 8);
+        if ( xc_hypercall_bounce_pre(xch, cpumap) )
+        {
+            PERROR("Could not bounce cpumap memory buffer");
+            goto out;
+        }
+        set_xen_guest_handle(inject->cpumap.bitmap, cpumap);
+        inject->cpumap.nr_bits = nr_bits;
+    }
+
+    inject->flags = flags;
+    mc->cmd = XEN_MC_inject_v2;
+    mc->interface_version = XEN_MCA_INTERFACE_VERSION;
+
+    if ( xc_hypercall_bounce_pre(xch, mc) )
+    {
+        PERROR("Could not bounce xen_mc memory buffer");
+        goto out_free_cpumap;
+    }
+
+    ret = xencall1(xch->xcall, __HYPERVISOR_mca, HYPERCALL_BUFFER_AS_ARG(mc));
+
+    xc_hypercall_bounce_post(xch, mc);
+out_free_cpumap:
+    if ( cpumap )
+        xc_hypercall_bounce_post(xch, cpumap);
+out:
+    return ret;
+}
+#endif /* __i386__ || __x86_64__ */
 
 int xc_perfc_reset(xc_interface *xch)
 {
-- 
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[PATCH v9 7/7] tools/xen-mceinj: add support of injecting LMCE

[Haozhong Zhang]

If option '-l' or '--lmce' is specified and the host supports LMCE,
xen-mceinj will inject LMCE to CPU specified by '-c' (or CPU0 if '-c'
is not present).

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
---
Cc: Ian Jackson <ian.jackson@eu.citrix.com>
Cc: Wei Liu <wei.liu2@citrix.com>
---
 tools/tests/mce-test/tools/xen-mceinj.c | 50 +++++++++++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/tools/tests/mce-test/tools/xen-mceinj.c b/tools/tests/mce-test/tools/xen-mceinj.c
index bae5a46eb5..380e42190c 100644
--- a/tools/tests/mce-test/tools/xen-mceinj.c
+++ b/tools/tests/mce-test/tools/xen-mceinj.c
@@ -56,6 +56,8 @@
 #define MSR_IA32_MC0_MISC        0x00000403
 #define MSR_IA32_MC0_CTL2        0x00000280
 
+#define MCG_STATUS_LMCE          0x8
+
 struct mce_info {
     const char *description;
     uint8_t mcg_stat;
@@ -113,6 +115,7 @@ static struct mce_info mce_table[] = {
 #define LOGFILE stdout
 
 int dump;
+int lmce;
 struct xen_mc_msrinject msr_inj;
 
 static void Lprintf(const char *fmt, ...)
@@ -212,6 +215,35 @@ static int inject_mce(xc_interface *xc_handle, int cpu_nr)
     return xc_mca_op(xc_handle, &mc);
 }
 
+static int inject_lmce(xc_interface *xc_handle, unsigned int cpu)
+{
+    uint8_t *cpumap = NULL;
+    size_t cpumap_size, line, shift;
+    unsigned int nr_cpus;
+    int ret;
+
+    nr_cpus = mca_cpuinfo(xc_handle);
+    if ( !nr_cpus )
+        err(xc_handle, "Failed to get mca_cpuinfo");
+    if ( cpu >= nr_cpus )
+        err(xc_handle, "-c %u is larger than %u", cpu, nr_cpus - 1);
+
+    cpumap_size = (nr_cpus + 7) / 8;
+    cpumap = malloc(cpumap_size);
+    if ( !cpumap )
+        err(xc_handle, "Failed to allocate cpumap\n");
+    memset(cpumap, 0, cpumap_size);
+    line = cpu / 8;
+    shift = cpu % 8;
+    memset(cpumap + line, 1 << shift, 1);
+
+    ret = xc_mca_op_inject_v2(xc_handle, XEN_MC_INJECT_TYPE_LMCE,
+                              cpumap, cpumap_size * 8);
+
+    free(cpumap);
+    return ret;
+}
+
 static uint64_t bank_addr(int bank, int type)
 {
     uint64_t addr;
@@ -330,8 +362,15 @@ static int inject(xc_interface *xc_handle, struct mce_info *mce,
                   uint32_t cpu_nr, uint32_t domain, uint64_t gaddr)
 {
     int ret = 0;
+    uint8_t mcg_status = mce->mcg_stat;
 
-    ret = inject_mcg_status(xc_handle, cpu_nr, mce->mcg_stat, domain);
+    if ( lmce )
+    {
+        if ( mce->cmci )
+            err(xc_handle, "No support to inject CMCI as LMCE");
+        mcg_status |= MCG_STATUS_LMCE;
+    }
+    ret = inject_mcg_status(xc_handle, cpu_nr, mcg_status, domain);
     if ( ret )
         err(xc_handle, "Failed to inject MCG_STATUS MSR");
 
@@ -354,6 +393,8 @@ static int inject(xc_interface *xc_handle, struct mce_info *mce,
         err(xc_handle, "Failed to inject MSR");
     if ( mce->cmci )
         ret = inject_cmci(xc_handle, cpu_nr);
+    else if ( lmce )
+        ret = inject_lmce(xc_handle, cpu_nr);
     else
         ret = inject_mce(xc_handle, cpu_nr);
     if ( ret )
@@ -393,6 +434,7 @@ static struct option opts[] = {
     {"dump", 0, 0, 'D'},
     {"help", 0, 0, 'h'},
     {"page", 0, 0, 'p'},
+    {"lmce", 0, 0, 'l'},
     {"", 0, 0, '\0'}
 };
 
@@ -409,6 +451,7 @@ static void help(void)
            "  -d, --domain=DOMID   target domain, the default is Xen itself\n"
            "  -h, --help           print this page\n"
            "  -p, --page=ADDR      physical address to report\n"
+           "  -l, --lmce           inject as LMCE (Intel only)\n"
            "  -t, --type=ERROR     error type\n");
 
     for ( i = 0; i < MCE_TABLE_SIZE; i++ )
@@ -438,7 +481,7 @@ int main(int argc, char *argv[])
     }
 
     while ( 1 ) {
-        c = getopt_long(argc, argv, "c:Dd:t:hp:", opts, &opt_index);
+        c = getopt_long(argc, argv, "c:Dd:t:hp:l", opts, &opt_index);
         if ( c == -1 )
             break;
         switch ( c ) {
@@ -463,6 +506,9 @@ int main(int argc, char *argv[])
         case 't':
             type = strtol(optarg, NULL, 0);
             break;
+        case 'l':
+            lmce = 1;
+            break;
         case 'h':
         default:
             help();
-- 
2.11.0


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Re: [PATCH v9 1/7] x86/domctl: generalize the restore of vMCE parameters

[Jan Beulich]

>>> Haozhong Zhang <haozhong.zhang@intel.com> 07/12/17 4:05 AM >>>
>+static int vcpu_set_vmce(struct vcpu *v,
>+                         const struct xen_domctl_ext_vcpucontext *evc)
>+{
>+    /*
>+     * Sizes of vMCE parameters used by the current and past versions
>+     * of Xen in descending order. If vMCE parameters are extended,
>+     * remember to add the old size to this array by VMCE_SIZE().
>+     */
>+#define VMCE_SIZE(field) \
>+    (offsetof(typeof(evc->vmce), field) + sizeof(evc->vmce.field))
>+
>+    static const unsigned int valid_sizes[] = {
>+        sizeof(evc->vmce),
>+        VMCE_SIZE(caps),
>+    };
>+#undef VMCE_SIZE
>+
>+    struct hvm_vmce_vcpu vmce = { };
>+    unsigned int evc_vmce_size =
>+        min(evc->size - offsetof(typeof(*evc), mcg_cap), sizeof(evc->vmce));

I should have noticed this earlier, and I'll try to remember to adjust this while
committing: Instead of mcg_cap we really should be using vmce here, as the
former is there solely for backward compatibility purposes (which this
expression doesn't relate to directly).

Jan


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Re: [PATCH v9 6/7] tools/libxc: add support of injecting MC# to specified CPUs

[Konrad Rzeszutek Wilk]

On Wed, Jul 12, 2017 at 10:04:39AM +0800, Haozhong Zhang wrote:
> Though XEN_MC_inject_v2 allows injecting MC# to specified CPUs, the
> current xc_mca_op() does not use this feature and not provide an
> interface to callers. This commit add a new xc_mca_op_inject_v2() that
> receives a cpumap providing the set of target CPUs.
> 
> Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
> Acked-by: Wei Liu <wei.liu2@citrix.com>
> ---
> Cc: Ian Jackson <ian.jackson@eu.citrix.com>
> Cc: Wei Liu <wei.liu2@citrix.com>
> ---
>  tools/libxc/include/xenctrl.h |  2 ++
>  tools/libxc/xc_misc.c         | 52 ++++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 53 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
> index c51bb3b448..552a4fd47d 100644
> --- a/tools/libxc/include/xenctrl.h
> +++ b/tools/libxc/include/xenctrl.h
> @@ -1809,6 +1809,8 @@ int xc_cpuid_apply_policy(xc_interface *xch,
>  void xc_cpuid_to_str(const unsigned int *regs,
>                       char **strs); /* some strs[] may be NULL if ENOMEM */
>  int xc_mca_op(xc_interface *xch, struct xen_mc *mc);
> +int xc_mca_op_inject_v2(xc_interface *xch, unsigned int flags,
> +                        xc_cpumap_t cpumap, unsigned int nr_cpus);
>  #endif
>  
>  struct xc_px_val {
> diff --git a/tools/libxc/xc_misc.c b/tools/libxc/xc_misc.c
> index 88084fde30..2303293c6c 100644
> --- a/tools/libxc/xc_misc.c
> +++ b/tools/libxc/xc_misc.c
> @@ -341,7 +341,57 @@ int xc_mca_op(xc_interface *xch, struct xen_mc *mc)
>      xc_hypercall_bounce_post(xch, mc);
>      return ret;
>  }
> -#endif
> +
> +int xc_mca_op_inject_v2(xc_interface *xch, unsigned int flags,
> +                        xc_cpumap_t cpumap, unsigned int nr_bits)
> +{
> +    int ret = -1;
> +    struct xen_mc mc_buf, *mc = &mc_buf;
> +    struct xen_mc_inject_v2 *inject = &mc->u.mc_inject_v2;
> +
> +    DECLARE_HYPERCALL_BOUNCE(cpumap, 0, XC_HYPERCALL_BUFFER_BOUNCE_IN);
> +    DECLARE_HYPERCALL_BOUNCE(mc, sizeof(*mc), XC_HYPERCALL_BUFFER_BOUNCE_BOTH);
> +
> +    memset(mc, 0, sizeof(*mc));
> +
> +    if ( cpumap )
> +    {
> +        if ( !nr_bits )
> +        {
> +            errno = EINVAL;
> +            goto out;
> +        }
> +
> +        HYPERCALL_BOUNCE_SET_SIZE(cpumap, (nr_bits + 7) / 8);

bitmap_size ?

> +        if ( xc_hypercall_bounce_pre(xch, cpumap) )
> +        {
> +            PERROR("Could not bounce cpumap memory buffer");
> +            goto out;
> +        }
> +        set_xen_guest_handle(inject->cpumap.bitmap, cpumap);
> +        inject->cpumap.nr_bits = nr_bits;
> +    }
> +
> +    inject->flags = flags;
> +    mc->cmd = XEN_MC_inject_v2;
> +    mc->interface_version = XEN_MCA_INTERFACE_VERSION;
> +
> +    if ( xc_hypercall_bounce_pre(xch, mc) )
> +    {
> +        PERROR("Could not bounce xen_mc memory buffer");
> +        goto out_free_cpumap;
> +    }
> +
> +    ret = xencall1(xch->xcall, __HYPERVISOR_mca, HYPERCALL_BUFFER_AS_ARG(mc));
> +
> +    xc_hypercall_bounce_post(xch, mc);
> +out_free_cpumap:
> +    if ( cpumap )
> +        xc_hypercall_bounce_post(xch, cpumap);
> +out:
> +    return ret;
> +}
> +#endif /* __i386__ || __x86_64__ */
>  
>  int xc_perfc_reset(xc_interface *xch)
>  {
> -- 
> 2.11.0
> 
> 
> _______________________________________________
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> https://lists.xen.org/xen-devel

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Re: [PATCH v9 7/7] tools/xen-mceinj: add support of injecting LMCE

[Konrad Rzeszutek Wilk]

On Wed, Jul 12, 2017 at 10:04:40AM +0800, Haozhong Zhang wrote:
> If option '-l' or '--lmce' is specified and the host supports LMCE,
> xen-mceinj will inject LMCE to CPU specified by '-c' (or CPU0 if '-c'
> is not present).
> 
> Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
> Acked-by: Wei Liu <wei.liu2@citrix.com>
> ---
> Cc: Ian Jackson <ian.jackson@eu.citrix.com>
> Cc: Wei Liu <wei.liu2@citrix.com>
> ---
>  tools/tests/mce-test/tools/xen-mceinj.c | 50 +++++++++++++++++++++++++++++++--
>  1 file changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/tests/mce-test/tools/xen-mceinj.c b/tools/tests/mce-test/tools/xen-mceinj.c
> index bae5a46eb5..380e42190c 100644
> --- a/tools/tests/mce-test/tools/xen-mceinj.c
> +++ b/tools/tests/mce-test/tools/xen-mceinj.c
> @@ -56,6 +56,8 @@
>  #define MSR_IA32_MC0_MISC        0x00000403
>  #define MSR_IA32_MC0_CTL2        0x00000280
>  
> +#define MCG_STATUS_LMCE          0x8
> +
>  struct mce_info {
>      const char *description;
>      uint8_t mcg_stat;
> @@ -113,6 +115,7 @@ static struct mce_info mce_table[] = {
>  #define LOGFILE stdout
>  
>  int dump;
> +int lmce;
>  struct xen_mc_msrinject msr_inj;
>  
>  static void Lprintf(const char *fmt, ...)
> @@ -212,6 +215,35 @@ static int inject_mce(xc_interface *xc_handle, int cpu_nr)
>      return xc_mca_op(xc_handle, &mc);
>  }
>  
> +static int inject_lmce(xc_interface *xc_handle, unsigned int cpu)
> +{
> +    uint8_t *cpumap = NULL;
> +    size_t cpumap_size, line, shift;
> +    unsigned int nr_cpus;
> +    int ret;
> +
> +    nr_cpus = mca_cpuinfo(xc_handle);
> +    if ( !nr_cpus )
> +        err(xc_handle, "Failed to get mca_cpuinfo");
> +    if ( cpu >= nr_cpus )
> +        err(xc_handle, "-c %u is larger than %u", cpu, nr_cpus - 1);
> +
> +    cpumap_size = (nr_cpus + 7) / 8;

bitmap_size

> +    cpumap = malloc(cpumap_size);

bitmap_alloc ?
> +    if ( !cpumap )
> +        err(xc_handle, "Failed to allocate cpumap\n");
> +    memset(cpumap, 0, cpumap_size);

bitmap_clear?

> +    line = cpu / 8;

BITMAP_ENTRY?
> +    shift = cpu % 8;

BITMAP_SHIFT?
> +    memset(cpumap + line, 1 << shift, 1);
> +
> +    ret = xc_mca_op_inject_v2(xc_handle, XEN_MC_INJECT_TYPE_LMCE,
> +                              cpumap, cpumap_size * 8);
> +
> +    free(cpumap);
> +    return ret;
> +}
> +
>  static uint64_t bank_addr(int bank, int type)
>  {
>      uint64_t addr;
> @@ -330,8 +362,15 @@ static int inject(xc_interface *xc_handle, struct mce_info *mce,
>                    uint32_t cpu_nr, uint32_t domain, uint64_t gaddr)
>  {
>      int ret = 0;
> +    uint8_t mcg_status = mce->mcg_stat;
>  
> -    ret = inject_mcg_status(xc_handle, cpu_nr, mce->mcg_stat, domain);
> +    if ( lmce )
> +    {
> +        if ( mce->cmci )
> +            err(xc_handle, "No support to inject CMCI as LMCE");
> +        mcg_status |= MCG_STATUS_LMCE;
> +    }
> +    ret = inject_mcg_status(xc_handle, cpu_nr, mcg_status, domain);
>      if ( ret )
>          err(xc_handle, "Failed to inject MCG_STATUS MSR");
>  
> @@ -354,6 +393,8 @@ static int inject(xc_interface *xc_handle, struct mce_info *mce,
>          err(xc_handle, "Failed to inject MSR");
>      if ( mce->cmci )
>          ret = inject_cmci(xc_handle, cpu_nr);
> +    else if ( lmce )
> +        ret = inject_lmce(xc_handle, cpu_nr);
>      else
>          ret = inject_mce(xc_handle, cpu_nr);
>      if ( ret )
> @@ -393,6 +434,7 @@ static struct option opts[] = {
>      {"dump", 0, 0, 'D'},
>      {"help", 0, 0, 'h'},
>      {"page", 0, 0, 'p'},
> +    {"lmce", 0, 0, 'l'},
>      {"", 0, 0, '\0'}
>  };
>  
> @@ -409,6 +451,7 @@ static void help(void)
>             "  -d, --domain=DOMID   target domain, the default is Xen itself\n"
>             "  -h, --help           print this page\n"
>             "  -p, --page=ADDR      physical address to report\n"
> +           "  -l, --lmce           inject as LMCE (Intel only)\n"
>             "  -t, --type=ERROR     error type\n");
>  
>      for ( i = 0; i < MCE_TABLE_SIZE; i++ )
> @@ -438,7 +481,7 @@ int main(int argc, char *argv[])
>      }
>  
>      while ( 1 ) {
> -        c = getopt_long(argc, argv, "c:Dd:t:hp:", opts, &opt_index);
> +        c = getopt_long(argc, argv, "c:Dd:t:hp:l", opts, &opt_index);
>          if ( c == -1 )
>              break;
>          switch ( c ) {
> @@ -463,6 +506,9 @@ int main(int argc, char *argv[])
>          case 't':
>              type = strtol(optarg, NULL, 0);
>              break;
> +        case 'l':
> +            lmce = 1;
> +            break;
>          case 'h':
>          default:
>              help();
> -- 
> 2.11.0
> 
> 
> _______________________________________________
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> Xen-devel@lists.xen.org
> https://lists.xen.org/xen-devel

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Re: [PATCH v9 7/7] tools/xen-mceinj: add support of injecting LMCE

[Haozhong Zhang]

On 07/12/17 09:26 -0400, Konrad Rzeszutek Wilk wrote:
> On Wed, Jul 12, 2017 at 10:04:40AM +0800, Haozhong Zhang wrote:
> > If option '-l' or '--lmce' is specified and the host supports LMCE,
> > xen-mceinj will inject LMCE to CPU specified by '-c' (or CPU0 if '-c'
> > is not present).
> > 
> > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
> > Acked-by: Wei Liu <wei.liu2@citrix.com>
> > ---
> > Cc: Ian Jackson <ian.jackson@eu.citrix.com>
> > Cc: Wei Liu <wei.liu2@citrix.com>
> > ---
> >  tools/tests/mce-test/tools/xen-mceinj.c | 50 +++++++++++++++++++++++++++++++--
> >  1 file changed, 48 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tools/tests/mce-test/tools/xen-mceinj.c b/tools/tests/mce-test/tools/xen-mceinj.c
> > index bae5a46eb5..380e42190c 100644
> > --- a/tools/tests/mce-test/tools/xen-mceinj.c
> > +++ b/tools/tests/mce-test/tools/xen-mceinj.c
[..]
> >  
> > +static int inject_lmce(xc_interface *xc_handle, unsigned int cpu)
> > +{
> > +    uint8_t *cpumap = NULL;
> > +    size_t cpumap_size, line, shift;
> > +    unsigned int nr_cpus;
> > +    int ret;
> > +
> > +    nr_cpus = mca_cpuinfo(xc_handle);
> > +    if ( !nr_cpus )
> > +        err(xc_handle, "Failed to get mca_cpuinfo");
> > +    if ( cpu >= nr_cpus )
> > +        err(xc_handle, "-c %u is larger than %u", cpu, nr_cpus - 1);
> > +
> > +    cpumap_size = (nr_cpus + 7) / 8;
> 
> bitmap_size
>

IIUC, these bitmap_* functions/macros are libxc internals and should
not be used here.

Haozhong

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Re: [PATCH v9 6/7] tools/libxc: add support of injecting MC# to specified CPUs

[Haozhong Zhang]

On 07/12/17 09:25 -0400, Konrad Rzeszutek Wilk wrote:
> On Wed, Jul 12, 2017 at 10:04:39AM +0800, Haozhong Zhang wrote:
> > Though XEN_MC_inject_v2 allows injecting MC# to specified CPUs, the
> > current xc_mca_op() does not use this feature and not provide an
> > interface to callers. This commit add a new xc_mca_op_inject_v2() that
> > receives a cpumap providing the set of target CPUs.
> > 
> > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
> > Acked-by: Wei Liu <wei.liu2@citrix.com>
> > ---
> > Cc: Ian Jackson <ian.jackson@eu.citrix.com>
> > Cc: Wei Liu <wei.liu2@citrix.com>
> > ---
> >  tools/libxc/include/xenctrl.h |  2 ++
> >  tools/libxc/xc_misc.c         | 52 ++++++++++++++++++++++++++++++++++++++++++-
> >  2 files changed, 53 insertions(+), 1 deletion(-)
> > 
> > diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
> > index c51bb3b448..552a4fd47d 100644
> > --- a/tools/libxc/include/xenctrl.h
> > +++ b/tools/libxc/include/xenctrl.h
> > @@ -1809,6 +1809,8 @@ int xc_cpuid_apply_policy(xc_interface *xch,
> >  void xc_cpuid_to_str(const unsigned int *regs,
> >                       char **strs); /* some strs[] may be NULL if ENOMEM */
> >  int xc_mca_op(xc_interface *xch, struct xen_mc *mc);
> > +int xc_mca_op_inject_v2(xc_interface *xch, unsigned int flags,
> > +                        xc_cpumap_t cpumap, unsigned int nr_cpus);
> >  #endif
> >  
> >  struct xc_px_val {
> > diff --git a/tools/libxc/xc_misc.c b/tools/libxc/xc_misc.c
> > index 88084fde30..2303293c6c 100644
> > --- a/tools/libxc/xc_misc.c
> > +++ b/tools/libxc/xc_misc.c
> > @@ -341,7 +341,57 @@ int xc_mca_op(xc_interface *xch, struct xen_mc *mc)
> >      xc_hypercall_bounce_post(xch, mc);
> >      return ret;
> >  }
> > -#endif
> > +
> > +int xc_mca_op_inject_v2(xc_interface *xch, unsigned int flags,
> > +                        xc_cpumap_t cpumap, unsigned int nr_bits)
> > +{
> > +    int ret = -1;
> > +    struct xen_mc mc_buf, *mc = &mc_buf;
> > +    struct xen_mc_inject_v2 *inject = &mc->u.mc_inject_v2;
> > +
> > +    DECLARE_HYPERCALL_BOUNCE(cpumap, 0, XC_HYPERCALL_BUFFER_BOUNCE_IN);
> > +    DECLARE_HYPERCALL_BOUNCE(mc, sizeof(*mc), XC_HYPERCALL_BUFFER_BOUNCE_BOTH);
> > +
> > +    memset(mc, 0, sizeof(*mc));
> > +
> > +    if ( cpumap )
> > +    {
> > +        if ( !nr_bits )
> > +        {
> > +            errno = EINVAL;
> > +            goto out;
> > +        }
> > +
> > +        HYPERCALL_BOUNCE_SET_SIZE(cpumap, (nr_bits + 7) / 8);
> 
> bitmap_size ?

nr_bits is of type unsigned int, while bitmap_size() requires a signed
int argument, though the number of CPUs passed via nr_bits in practice
can be represented by a signed int.

Haozhong

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Re: [PATCH v9 0/7] Add LMCE support

[Jan Beulich]

>>> On 12.07.17 at 04:04, <haozhong.zhang@intel.com> wrote:
> Changes in v9:
>  * Minor updates in patch 1 per Jan's comments.
>  * Collect Jan's R-b in patch 2.
> 
> Haozhong Zhang (7):
>   [M   ] x86/domctl: generalize the restore of vMCE parameters
>   [  R ] x86/vmce: emulate MSR_IA32_MCG_EXT_CTL
>   [  R ] x86/vmce: enable injecting LMCE to guest on Intel host
>   [  RA] x86/vmce, tools/libxl: expose LMCE capability in guest MSR_IA32_MCG_CAP
>   [  R ] xen/mce: add support of vLMCE injection to XEN_MC_inject_v2

I've committed these, but ...

>   [   A] tools/libxc: add support of injecting MC# to specified CPUs
>   [   A] tools/xen-mceinj: add support of injecting LMCE

... I've left out these, due to Konrad's (late) comments which I'm
not sure are being expected to be addressed in another round.

Jan


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Re: [PATCH v9 7/7] tools/xen-mceinj: add support of injecting LMCE

[Wei Liu]

On Thu, Jul 13, 2017 at 10:10:05AM +0800, Haozhong Zhang wrote:
> On 07/12/17 09:26 -0400, Konrad Rzeszutek Wilk wrote:
> > On Wed, Jul 12, 2017 at 10:04:40AM +0800, Haozhong Zhang wrote:
> > > If option '-l' or '--lmce' is specified and the host supports LMCE,
> > > xen-mceinj will inject LMCE to CPU specified by '-c' (or CPU0 if '-c'
> > > is not present).
> > > 
> > > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
> > > Acked-by: Wei Liu <wei.liu2@citrix.com>
> > > ---
> > > Cc: Ian Jackson <ian.jackson@eu.citrix.com>
> > > Cc: Wei Liu <wei.liu2@citrix.com>
> > > ---
> > >  tools/tests/mce-test/tools/xen-mceinj.c | 50 +++++++++++++++++++++++++++++++--
> > >  1 file changed, 48 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/tools/tests/mce-test/tools/xen-mceinj.c b/tools/tests/mce-test/tools/xen-mceinj.c
> > > index bae5a46eb5..380e42190c 100644
> > > --- a/tools/tests/mce-test/tools/xen-mceinj.c
> > > +++ b/tools/tests/mce-test/tools/xen-mceinj.c
> [..]
> > >  
> > > +static int inject_lmce(xc_interface *xc_handle, unsigned int cpu)
> > > +{
> > > +    uint8_t *cpumap = NULL;
> > > +    size_t cpumap_size, line, shift;
> > > +    unsigned int nr_cpus;
> > > +    int ret;
> > > +
> > > +    nr_cpus = mca_cpuinfo(xc_handle);
> > > +    if ( !nr_cpus )
> > > +        err(xc_handle, "Failed to get mca_cpuinfo");
> > > +    if ( cpu >= nr_cpus )
> > > +        err(xc_handle, "-c %u is larger than %u", cpu, nr_cpus - 1);
> > > +
> > > +    cpumap_size = (nr_cpus + 7) / 8;
> > 
> > bitmap_size
> >
> 
> IIUC, these bitmap_* functions/macros are libxc internals and should
> not be used here.
> 

Correct. Those aren't available to external users. If we want to export
those we would need to add libxc_ prefix.

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Re: [PATCH v9 7/7] tools/xen-mceinj: add support of injecting LMCE

[Wei Liu]

On Mon, Jul 17, 2017 at 11:05:24AM +0100, Wei Liu wrote:
> On Thu, Jul 13, 2017 at 10:10:05AM +0800, Haozhong Zhang wrote:
> > On 07/12/17 09:26 -0400, Konrad Rzeszutek Wilk wrote:
> > > On Wed, Jul 12, 2017 at 10:04:40AM +0800, Haozhong Zhang wrote:
> > > > If option '-l' or '--lmce' is specified and the host supports LMCE,
> > > > xen-mceinj will inject LMCE to CPU specified by '-c' (or CPU0 if '-c'
> > > > is not present).
> > > > 
> > > > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
> > > > Acked-by: Wei Liu <wei.liu2@citrix.com>
> > > > ---
> > > > Cc: Ian Jackson <ian.jackson@eu.citrix.com>
> > > > Cc: Wei Liu <wei.liu2@citrix.com>
> > > > ---
> > > >  tools/tests/mce-test/tools/xen-mceinj.c | 50 +++++++++++++++++++++++++++++++--
> > > >  1 file changed, 48 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/tools/tests/mce-test/tools/xen-mceinj.c b/tools/tests/mce-test/tools/xen-mceinj.c
> > > > index bae5a46eb5..380e42190c 100644
> > > > --- a/tools/tests/mce-test/tools/xen-mceinj.c
> > > > +++ b/tools/tests/mce-test/tools/xen-mceinj.c
> > [..]
> > > >  
> > > > +static int inject_lmce(xc_interface *xc_handle, unsigned int cpu)
> > > > +{
> > > > +    uint8_t *cpumap = NULL;
> > > > +    size_t cpumap_size, line, shift;
> > > > +    unsigned int nr_cpus;
> > > > +    int ret;
> > > > +
> > > > +    nr_cpus = mca_cpuinfo(xc_handle);
> > > > +    if ( !nr_cpus )
> > > > +        err(xc_handle, "Failed to get mca_cpuinfo");
> > > > +    if ( cpu >= nr_cpus )
> > > > +        err(xc_handle, "-c %u is larger than %u", cpu, nr_cpus - 1);
> > > > +
> > > > +    cpumap_size = (nr_cpus + 7) / 8;
> > > 
> > > bitmap_size
> > >
> > 
> > IIUC, these bitmap_* functions/macros are libxc internals and should
> > not be used here.
> > 
> 
> Correct. Those aren't available to external users. If we want to export
> those we would need to add libxc_ prefix.

FAOD I think bitmap_* aren't appropriate to use here for the reason
stated above. That also makes the suggestion on previous patch moot. If
I hear no objection by tomorrow I will just commit these two remaining
patches.

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Re: [PATCH v9 7/7] tools/xen-mceinj: add support of injecting LMCE

[Wei Liu]

On Wed, Jul 12, 2017 at 10:04:40AM +0800, Haozhong Zhang wrote:
>  
> +static int inject_lmce(xc_interface *xc_handle, unsigned int cpu)
> +{
> +    uint8_t *cpumap = NULL;
> +    size_t cpumap_size, line, shift;
> +    unsigned int nr_cpus;
> +    int ret;
> +
> +    nr_cpus = mca_cpuinfo(xc_handle);
> +    if ( !nr_cpus )
> +        err(xc_handle, "Failed to get mca_cpuinfo");
> +    if ( cpu >= nr_cpus )
> +        err(xc_handle, "-c %u is larger than %u", cpu, nr_cpus - 1);
> +
> +    cpumap_size = (nr_cpus + 7) / 8;
> +    cpumap = malloc(cpumap_size);
> +    if ( !cpumap )
> +        err(xc_handle, "Failed to allocate cpumap\n");
> +    memset(cpumap, 0, cpumap_size);
> +    line = cpu / 8;
> +    shift = cpu % 8;
> +    memset(cpumap + line, 1 << shift, 1);
> +
> +    ret = xc_mca_op_inject_v2(xc_handle, XEN_MC_INJECT_TYPE_LMCE,
> +                              cpumap, cpumap_size * 8);

This doesn't compile because XEN_MC_INJECT_TYPE_LMCE is not defined.

Please rework this patch and make sure it compiles before submitting.

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Re: [PATCH v9 7/7] tools/xen-mceinj: add support of injecting LMCE

[Wei Liu]

On Tue, Jul 18, 2017 at 11:33:04AM +0100, Wei Liu wrote:
> On Wed, Jul 12, 2017 at 10:04:40AM +0800, Haozhong Zhang wrote:
> >  
> > +static int inject_lmce(xc_interface *xc_handle, unsigned int cpu)
> > +{
> > +    uint8_t *cpumap = NULL;
> > +    size_t cpumap_size, line, shift;
> > +    unsigned int nr_cpus;
> > +    int ret;
> > +
> > +    nr_cpus = mca_cpuinfo(xc_handle);
> > +    if ( !nr_cpus )
> > +        err(xc_handle, "Failed to get mca_cpuinfo");
> > +    if ( cpu >= nr_cpus )
> > +        err(xc_handle, "-c %u is larger than %u", cpu, nr_cpus - 1);
> > +
> > +    cpumap_size = (nr_cpus + 7) / 8;
> > +    cpumap = malloc(cpumap_size);
> > +    if ( !cpumap )
> > +        err(xc_handle, "Failed to allocate cpumap\n");
> > +    memset(cpumap, 0, cpumap_size);
> > +    line = cpu / 8;
> > +    shift = cpu % 8;
> > +    memset(cpumap + line, 1 << shift, 1);
> > +
> > +    ret = xc_mca_op_inject_v2(xc_handle, XEN_MC_INJECT_TYPE_LMCE,
> > +                              cpumap, cpumap_size * 8);
> 
> This doesn't compile because XEN_MC_INJECT_TYPE_LMCE is not defined.
> 
> Please rework this patch and make sure it compiles before submitting.

Oh, actually that's my fault. I forgot to pull in your hypervisor
patches.

Sorry for the noise.

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