[PATCH v3] clk: fractional-divider: fix up the fractional clk's jitter

[PATCH v3] clk: fractional-divider: fix up the fractional clk's jitter

[Elaine Zhang]

Fractional dividers may have special requirements concerning numerator
and denominator selection that differ from just getting the best
approximation.

For example on Rockchip socs the denominator must be at least 20 times
larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions,
approx = rockchip_fractional_special_approx;
but approx = NULL in the default case.

RK document description:
3.1.9  Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
fractional divider. Generally you must set that denominator is 20 times
larger than numerator to generate precise clock frequency. So the
fractional divider applies only to generate low frequency clock like
I2S, UART.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/clk-fractional-divider.c |  4 ++++
 drivers/clk/rockchip/clk.c           | 20 ++++++++++++++++++++
 include/linux/clk-provider.h         |  3 +++
 3 files changed, 27 insertions(+)

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index aab904618eb6..ab2bc229ef2f 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -60,6 +60,9 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
 	if (!rate || rate >= *parent_rate)
 		return *parent_rate;
 
+	if (fd->approx)
+		fd->approx(hw, rate, parent_rate);
+
 	/*
 	 * Get rate closer to *parent_rate to guarantee there is no overflow
 	 * for m and n. In the result it will be the nearest rate left shifted
@@ -145,6 +148,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
 	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
 	fd->flags = clk_divider_flags;
 	fd->lock = lock;
+	fd->approx = NULL;
 	fd->hw.init = &init;
 
 	hw = &fd->hw;
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fe1d393cf678..8b21c5b19107 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -164,6 +164,25 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 	return notifier_from_errno(ret);
 }
 
+/**
+ * fractional divider must set that denominator is 20 times larger than
+ * numerator to generate precise clock frequency.
+ */
+void rockchip_fractional_special_approx(struct clk_hw *hw,
+					unsigned long rate,
+					unsigned long *parent_rate)
+{
+	struct clk_hw *p_parent;
+	unsigned long p_rate, p_parent_rate;
+
+	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
+	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
+		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
+		p_parent_rate = clk_hw_get_rate(p_parent);
+		*parent_rate = p_parent_rate;
+	}
+}
+
 static struct clk *rockchip_clk_register_frac_branch(
 		struct rockchip_clk_provider *ctx, const char *name,
 		const char *const *parent_names, u8 num_parents,
@@ -210,6 +229,7 @@ static struct clk *rockchip_clk_register_frac_branch(
 	div->nwidth = 16;
 	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
 	div->lock = lock;
+	div->approx = rockchip_fractional_special_approx;
 	div_ops = &clk_fractional_divider_ops;
 
 	clk = clk_register_composite(NULL, name, parent_names, num_parents,
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index a428aec36ace..807262375292 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -564,6 +564,9 @@ struct clk_fractional_divider {
 	u8		nwidth;
 	u32		nmask;
 	u8		flags;
+	void            (*approx)(struct clk_hw *hw,
+				  unsigned long rate,
+				  unsigned long *parent_rate);
 	spinlock_t	*lock;
 };
 
-- 
1.9.1

[PATCH v3] clk: fractional-divider: fix up the fractional clk's jitter

[Elaine Zhang]

Fractional dividers may have special requirements concerning numerator
and denominator selection that differ from just getting the best
approximation.

For example on Rockchip socs the denominator must be at least 20 times
larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions,
approx = rockchip_fractional_special_approx;
but approx = NULL in the default case.

RK document description:
3.1.9  Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
fractional divider. Generally you must set that denominator is 20 times
larger than numerator to generate precise clock frequency. So the
fractional divider applies only to generate low frequency clock like
I2S, UART.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/clk-fractional-divider.c |  4 ++++
 drivers/clk/rockchip/clk.c           | 20 ++++++++++++++++++++
 include/linux/clk-provider.h         |  3 +++
 3 files changed, 27 insertions(+)

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index aab904618eb6..ab2bc229ef2f 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -60,6 +60,9 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
 	if (!rate || rate >= *parent_rate)
 		return *parent_rate;
 
+	if (fd->approx)
+		fd->approx(hw, rate, parent_rate);
+
 	/*
 	 * Get rate closer to *parent_rate to guarantee there is no overflow
 	 * for m and n. In the result it will be the nearest rate left shifted
@@ -145,6 +148,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
 	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
 	fd->flags = clk_divider_flags;
 	fd->lock = lock;
+	fd->approx = NULL;
 	fd->hw.init = &init;
 
 	hw = &fd->hw;
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fe1d393cf678..8b21c5b19107 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -164,6 +164,25 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 	return notifier_from_errno(ret);
 }
 
+/**
+ * fractional divider must set that denominator is 20 times larger than
+ * numerator to generate precise clock frequency.
+ */
+void rockchip_fractional_special_approx(struct clk_hw *hw,
+					unsigned long rate,
+					unsigned long *parent_rate)
+{
+	struct clk_hw *p_parent;
+	unsigned long p_rate, p_parent_rate;
+
+	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
+	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
+		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
+		p_parent_rate = clk_hw_get_rate(p_parent);
+		*parent_rate = p_parent_rate;
+	}
+}
+
 static struct clk *rockchip_clk_register_frac_branch(
 		struct rockchip_clk_provider *ctx, const char *name,
 		const char *const *parent_names, u8 num_parents,
@@ -210,6 +229,7 @@ static struct clk *rockchip_clk_register_frac_branch(
 	div->nwidth = 16;
 	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
 	div->lock = lock;
+	div->approx = rockchip_fractional_special_approx;
 	div_ops = &clk_fractional_divider_ops;
 
 	clk = clk_register_composite(NULL, name, parent_names, num_parents,
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index a428aec36ace..807262375292 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -564,6 +564,9 @@ struct clk_fractional_divider {
 	u8		nwidth;
 	u32		nmask;
 	u8		flags;
+	void            (*approx)(struct clk_hw *hw,
+				  unsigned long rate,
+				  unsigned long *parent_rate);
 	spinlock_t	*lock;
 };
 
-- 
1.9.1

Re: [PATCH v3] clk: fractional-divider: fix up the fractional clk's jitter

[Heiko Stuebner]

Hi Elaine,

sorry this took a bit longer, but I didn't manage to find the time to
respond properly until now.

Am Freitag, 21. Juli 2017, 16:03:07 CEST schrieb Elaine Zhang:
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
> 
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
> 
> Therefore add the ability to provide custom approximation functions,
> approx = rockchip_fractional_special_approx;
> but approx = NULL in the default case.
> 
> RK document description:
> 3.1.9  Fractional divider usage
> To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
> fractional divider. Generally you must set that denominator is 20 times
> larger than numerator to generate precise clock frequency. So the
> fractional divider applies only to generate low frequency clock like
> I2S, UART.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>  drivers/clk/clk-fractional-divider.c |  4 ++++
>  drivers/clk/rockchip/clk.c           | 20 ++++++++++++++++++++
>  include/linux/clk-provider.h         |  3 +++
>  3 files changed, 27 insertions(+)

The code below does go into the right direction, but I'd really like to
have the full approximation  overrideable. The reason is that while on
Rockchip SoCs it's enough to increase the parent rate, other socs might
have completely different requirements when determining numerator
and denominator.

So I've taken the time and modified your patch into 2 that look like I
would envision it - compile-tested only, so please test :-)
But essentially it only moves some things around but should be
functionally equivalent to your patch.

I'll add the patches as replies to this mail.


Two more things to keep in mind for the future below:

> @@ -145,6 +148,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
>  	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
>  	fd->flags = clk_divider_flags;
>  	fd->lock = lock;
> +	fd->approx = NULL;

not needed, as fd is allocated via kzalloc, so this is already NULL.
Also it is nicer to spell approximation full (which I've done in my rework)

[...]

> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index a428aec36ace..807262375292 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -564,6 +564,9 @@ struct clk_fractional_divider {
>  	u8		nwidth;
>  	u32		nmask;
>  	u8		flags;
> +	void            (*approx)(struct clk_hw *hw,

Please keep the spacing in line with other elements. Somehow
here spaces instead of a tab slipped in between void and (*appro...


Heiko

Re: [PATCH v3] clk: fractional-divider: fix up the fractional clk's jitter

[Heiko Stuebner]

Hi Elaine,

sorry this took a bit longer, but I didn't manage to find the time to
respond properly until now.

Am Freitag, 21. Juli 2017, 16:03:07 CEST schrieb Elaine Zhang:
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
> 
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
> 
> Therefore add the ability to provide custom approximation functions,
> approx = rockchip_fractional_special_approx;
> but approx = NULL in the default case.
> 
> RK document description:
> 3.1.9  Fractional divider usage
> To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
> fractional divider. Generally you must set that denominator is 20 times
> larger than numerator to generate precise clock frequency. So the
> fractional divider applies only to generate low frequency clock like
> I2S, UART.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>  drivers/clk/clk-fractional-divider.c |  4 ++++
>  drivers/clk/rockchip/clk.c           | 20 ++++++++++++++++++++
>  include/linux/clk-provider.h         |  3 +++
>  3 files changed, 27 insertions(+)

The code below does go into the right direction, but I'd really like to
have the full approximation  overrideable. The reason is that while on
Rockchip SoCs it's enough to increase the parent rate, other socs might
have completely different requirements when determining numerator
and denominator.

So I've taken the time and modified your patch into 2 that look like I
would envision it - compile-tested only, so please test :-)
But essentially it only moves some things around but should be
functionally equivalent to your patch.

I'll add the patches as replies to this mail.


Two more things to keep in mind for the future below:

> @@ -145,6 +148,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
>  	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
>  	fd->flags = clk_divider_flags;
>  	fd->lock = lock;
> +	fd->approx = NULL;

not needed, as fd is allocated via kzalloc, so this is already NULL.
Also it is nicer to spell approximation full (which I've done in my rework)

[...]

> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index a428aec36ace..807262375292 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -564,6 +564,9 @@ struct clk_fractional_divider {
>  	u8		nwidth;
>  	u32		nmask;
>  	u8		flags;
> +	void            (*approx)(struct clk_hw *hw,

Please keep the spacing in line with other elements. Somehow
here spaces instead of a tab slipped in between void and (*appro...


Heiko

[PATCH v3] clk: fractional-divider: fix up the fractional clk's jitter

[Heiko Stuebner]

Hi Elaine,

sorry this took a bit longer, but I didn't manage to find the time to
respond properly until now.

Am Freitag, 21. Juli 2017, 16:03:07 CEST schrieb Elaine Zhang:
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
> 
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
> 
> Therefore add the ability to provide custom approximation functions,
> approx = rockchip_fractional_special_approx;
> but approx = NULL in the default case.
> 
> RK document description:
> 3.1.9  Fractional divider usage
> To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
> fractional divider. Generally you must set that denominator is 20 times
> larger than numerator to generate precise clock frequency. So the
> fractional divider applies only to generate low frequency clock like
> I2S, UART.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>  drivers/clk/clk-fractional-divider.c |  4 ++++
>  drivers/clk/rockchip/clk.c           | 20 ++++++++++++++++++++
>  include/linux/clk-provider.h         |  3 +++
>  3 files changed, 27 insertions(+)

The code below does go into the right direction, but I'd really like to
have the full approximation  overrideable. The reason is that while on
Rockchip SoCs it's enough to increase the parent rate, other socs might
have completely different requirements when determining numerator
and denominator.

So I've taken the time and modified your patch into 2 that look like I
would envision it - compile-tested only, so please test :-)
But essentially it only moves some things around but should be
functionally equivalent to your patch.

I'll add the patches as replies to this mail.


Two more things to keep in mind for the future below:

> @@ -145,6 +148,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
>  	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
>  	fd->flags = clk_divider_flags;
>  	fd->lock = lock;
> +	fd->approx = NULL;

not needed, as fd is allocated via kzalloc, so this is already NULL.
Also it is nicer to spell approximation full (which I've done in my rework)

[...]

> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index a428aec36ace..807262375292 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -564,6 +564,9 @@ struct clk_fractional_divider {
>  	u8		nwidth;
>  	u32		nmask;
>  	u8		flags;
> +	void            (*approx)(struct clk_hw *hw,

Please keep the spacing in line with other elements. Somehow
here spaces instead of a tab slipped in between void and (*appro...


Heiko

[PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Heiko Stuebner]

From: Elaine Zhang <zhangqing@rock-chips.com>

Fractional dividers may have special requirements concerning numerator
and denominator selection that differ from just getting the best
approximation.

For example on Rockchip socs the denominator must be at least 20 times
larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/clk-fractional-divider.c | 28 ++++++++++++++++++++--------
 include/linux/clk-provider.h         |  3 +++
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index aab904618eb6..fdf625fb10fa 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
 	return ret;
 }
 
-static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
-			      unsigned long *parent_rate)
+static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
+					 unsigned long *parent_rate,
+					 unsigned long *m, unsigned long *n)
 {
 	struct clk_fractional_divider *fd = to_clk_fd(hw);
 	unsigned long scale;
-	unsigned long m, n;
-	u64 ret;
-
-	if (!rate || rate >= *parent_rate)
-		return *parent_rate;
 
 	/*
 	 * Get rate closer to *parent_rate to guarantee there is no overflow
@@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
 
 	rational_best_approximation(rate, *parent_rate,
 			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
-			&m, &n);
+			m, n);
+}
+
+static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *parent_rate)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long m, n;
+	u64 ret;
+
+	if (!rate || rate >= *parent_rate)
+		return *parent_rate;
+
+	if (fd->approximation)
+		fd->approximation(hw, rate, parent_rate, &m, &n);
+	else
+		clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
 
 	ret = (u64)*parent_rate * m;
 	do_div(ret, n);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c59c62571e4f..1fc113fbf955 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -565,6 +565,9 @@ struct clk_fractional_divider {
 	u8		nwidth;
 	u32		nmask;
 	u8		flags;
+	void		(*approximation)(struct clk_hw *hw,
+				unsigned long rate, unsigned long *parent_rate,
+				unsigned long *m, unsigned long *n);
 	spinlock_t	*lock;
 };
 
-- 
2.11.0

[PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Heiko Stuebner]

From: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Fractional dividers may have special requirements concerning numerator
and denominator selection that differ from just getting the best
approximation.

For example on Rockchip socs the denominator must be at least 20 times
larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions.

Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
 drivers/clk/clk-fractional-divider.c | 28 ++++++++++++++++++++--------
 include/linux/clk-provider.h         |  3 +++
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index aab904618eb6..fdf625fb10fa 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
 	return ret;
 }
 
-static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
-			      unsigned long *parent_rate)
+static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
+					 unsigned long *parent_rate,
+					 unsigned long *m, unsigned long *n)
 {
 	struct clk_fractional_divider *fd = to_clk_fd(hw);
 	unsigned long scale;
-	unsigned long m, n;
-	u64 ret;
-
-	if (!rate || rate >= *parent_rate)
-		return *parent_rate;
 
 	/*
 	 * Get rate closer to *parent_rate to guarantee there is no overflow
@@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
 
 	rational_best_approximation(rate, *parent_rate,
 			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
-			&m, &n);
+			m, n);
+}
+
+static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *parent_rate)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long m, n;
+	u64 ret;
+
+	if (!rate || rate >= *parent_rate)
+		return *parent_rate;
+
+	if (fd->approximation)
+		fd->approximation(hw, rate, parent_rate, &m, &n);
+	else
+		clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
 
 	ret = (u64)*parent_rate * m;
 	do_div(ret, n);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c59c62571e4f..1fc113fbf955 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -565,6 +565,9 @@ struct clk_fractional_divider {
 	u8		nwidth;
 	u32		nmask;
 	u8		flags;
+	void		(*approximation)(struct clk_hw *hw,
+				unsigned long rate, unsigned long *parent_rate,
+				unsigned long *m, unsigned long *n);
 	spinlock_t	*lock;
 };
 
-- 
2.11.0

[PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Heiko Stuebner]

From: Elaine Zhang <zhangqing@rock-chips.com>

Fractional dividers may have special requirements concerning numerator
and denominator selection that differ from just getting the best
approximation.

For example on Rockchip socs the denominator must be at least 20 times
larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/clk-fractional-divider.c | 28 ++++++++++++++++++++--------
 include/linux/clk-provider.h         |  3 +++
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index aab904618eb6..fdf625fb10fa 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
 	return ret;
 }
 
-static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
-			      unsigned long *parent_rate)
+static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
+					 unsigned long *parent_rate,
+					 unsigned long *m, unsigned long *n)
 {
 	struct clk_fractional_divider *fd = to_clk_fd(hw);
 	unsigned long scale;
-	unsigned long m, n;
-	u64 ret;
-
-	if (!rate || rate >= *parent_rate)
-		return *parent_rate;
 
 	/*
 	 * Get rate closer to *parent_rate to guarantee there is no overflow
@@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
 
 	rational_best_approximation(rate, *parent_rate,
 			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
-			&m, &n);
+			m, n);
+}
+
+static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *parent_rate)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long m, n;
+	u64 ret;
+
+	if (!rate || rate >= *parent_rate)
+		return *parent_rate;
+
+	if (fd->approximation)
+		fd->approximation(hw, rate, parent_rate, &m, &n);
+	else
+		clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
 
 	ret = (u64)*parent_rate * m;
 	do_div(ret, n);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c59c62571e4f..1fc113fbf955 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -565,6 +565,9 @@ struct clk_fractional_divider {
 	u8		nwidth;
 	u32		nmask;
 	u8		flags;
+	void		(*approximation)(struct clk_hw *hw,
+				unsigned long rate, unsigned long *parent_rate,
+				unsigned long *m, unsigned long *n);
 	spinlock_t	*lock;
 };
 
-- 
2.11.0

[PATCH 2/2] clk: rockchip: add special approximation to fix up fractional clk's jitter

[Heiko Stuebner]

From: Elaine Zhang <zhangqing@rock-chips.com>

>From Rockchips fractional divider description:
  3.1.9  Fractional divider usage
  To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
  fractional divider. Generally you must set that denominator is 20 times
  larger than numerator to generate precise clock frequency. So the
  fractional divider applies only to generate low frequency clock like
  I2S, UART.

Therefore add a special approximation function that handles this
special requirement.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fe1d393cf678..b6db79a00602 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -29,6 +29,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/reboot.h>
+#include <linux/rational.h>
 #include "clk.h"
 
 /**
@@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 	return notifier_from_errno(ret);
 }
 
+/**
+ * fractional divider must set that denominator is 20 times larger than
+ * numerator to generate precise clock frequency.
+ */
+void rockchip_fractional_approximation(struct clk_hw *hw,
+		unsigned long rate, unsigned long *parent_rate,
+		unsigned long *m, unsigned long *n)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long p_rate, p_parent_rate;
+	struct clk_hw *p_parent;
+	unsigned long scale;
+
+	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
+	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
+		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
+		p_parent_rate = clk_hw_get_rate(p_parent);
+		*parent_rate = p_parent_rate;
+	}
+
+	/*
+	 * Get rate closer to *parent_rate to guarantee there is no overflow
+	 * for m and n. In the result it will be the nearest rate left shifted
+	 * by (scale - fd->nwidth) bits.
+	 */
+	scale = fls_long(*parent_rate / rate - 1);
+	if (scale > fd->nwidth)
+		rate <<= scale - fd->nwidth;
+
+	rational_best_approximation(rate, *parent_rate,
+			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
+			m, n);
+}
+
 static struct clk *rockchip_clk_register_frac_branch(
 		struct rockchip_clk_provider *ctx, const char *name,
 		const char *const *parent_names, u8 num_parents,
@@ -210,6 +245,7 @@ static struct clk *rockchip_clk_register_frac_branch(
 	div->nwidth = 16;
 	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
 	div->lock = lock;
+	div->approximation = rockchip_fractional_approximation;
 	div_ops = &clk_fractional_divider_ops;
 
 	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-- 
2.11.0

[PATCH 2/2] clk: rockchip: add special approximation to fix up fractional clk's jitter

[Heiko Stuebner]

From: Elaine Zhang <zhangqing@rock-chips.com>

From Rockchips fractional divider description:
  3.1.9  Fractional divider usage
  To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
  fractional divider. Generally you must set that denominator is 20 times
  larger than numerator to generate precise clock frequency. So the
  fractional divider applies only to generate low frequency clock like
  I2S, UART.

Therefore add a special approximation function that handles this
special requirement.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fe1d393cf678..b6db79a00602 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -29,6 +29,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/reboot.h>
+#include <linux/rational.h>
 #include "clk.h"
 
 /**
@@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 	return notifier_from_errno(ret);
 }
 
+/**
+ * fractional divider must set that denominator is 20 times larger than
+ * numerator to generate precise clock frequency.
+ */
+void rockchip_fractional_approximation(struct clk_hw *hw,
+		unsigned long rate, unsigned long *parent_rate,
+		unsigned long *m, unsigned long *n)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long p_rate, p_parent_rate;
+	struct clk_hw *p_parent;
+	unsigned long scale;
+
+	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
+	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
+		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
+		p_parent_rate = clk_hw_get_rate(p_parent);
+		*parent_rate = p_parent_rate;
+	}
+
+	/*
+	 * Get rate closer to *parent_rate to guarantee there is no overflow
+	 * for m and n. In the result it will be the nearest rate left shifted
+	 * by (scale - fd->nwidth) bits.
+	 */
+	scale = fls_long(*parent_rate / rate - 1);
+	if (scale > fd->nwidth)
+		rate <<= scale - fd->nwidth;
+
+	rational_best_approximation(rate, *parent_rate,
+			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
+			m, n);
+}
+
 static struct clk *rockchip_clk_register_frac_branch(
 		struct rockchip_clk_provider *ctx, const char *name,
 		const char *const *parent_names, u8 num_parents,
@@ -210,6 +245,7 @@ static struct clk *rockchip_clk_register_frac_branch(
 	div->nwidth = 16;
 	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
 	div->lock = lock;
+	div->approximation = rockchip_fractional_approximation;
 	div_ops = &clk_fractional_divider_ops;
 
 	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-- 
2.11.0

[PATCH 2/2] clk: rockchip: add special approximation to fix up fractional clk's jitter

[Heiko Stuebner]

From: Elaine Zhang <zhangqing@rock-chips.com>

>From Rockchips fractional divider description:
  3.1.9  Fractional divider usage
  To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
  fractional divider. Generally you must set that denominator is 20 times
  larger than numerator to generate precise clock frequency. So the
  fractional divider applies only to generate low frequency clock like
  I2S, UART.

Therefore add a special approximation function that handles this
special requirement.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fe1d393cf678..b6db79a00602 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -29,6 +29,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/reboot.h>
+#include <linux/rational.h>
 #include "clk.h"
 
 /**
@@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 	return notifier_from_errno(ret);
 }
 
+/**
+ * fractional divider must set that denominator is 20 times larger than
+ * numerator to generate precise clock frequency.
+ */
+void rockchip_fractional_approximation(struct clk_hw *hw,
+		unsigned long rate, unsigned long *parent_rate,
+		unsigned long *m, unsigned long *n)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long p_rate, p_parent_rate;
+	struct clk_hw *p_parent;
+	unsigned long scale;
+
+	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
+	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
+		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
+		p_parent_rate = clk_hw_get_rate(p_parent);
+		*parent_rate = p_parent_rate;
+	}
+
+	/*
+	 * Get rate closer to *parent_rate to guarantee there is no overflow
+	 * for m and n. In the result it will be the nearest rate left shifted
+	 * by (scale - fd->nwidth) bits.
+	 */
+	scale = fls_long(*parent_rate / rate - 1);
+	if (scale > fd->nwidth)
+		rate <<= scale - fd->nwidth;
+
+	rational_best_approximation(rate, *parent_rate,
+			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
+			m, n);
+}
+
 static struct clk *rockchip_clk_register_frac_branch(
 		struct rockchip_clk_provider *ctx, const char *name,
 		const char *const *parent_names, u8 num_parents,
@@ -210,6 +245,7 @@ static struct clk *rockchip_clk_register_frac_branch(
 	div->nwidth = 16;
 	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
 	div->lock = lock;
+	div->approximation = rockchip_fractional_approximation;
 	div_ops = &clk_fractional_divider_ops;
 
 	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-- 
2.11.0

Re: [PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Elaine Zhang]

hi,heiko:

This a good solution.And I tested it on RK SOCs.It's work well.

On 08/02/2017 12:21 AM, Heiko Stuebner wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
>
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
>
> Therefore add the ability to provide custom approximation functions.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/clk-fractional-divider.c | 28 ++++++++++++++++++++--------
>   include/linux/clk-provider.h         |  3 +++
>   2 files changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
> index aab904618eb6..fdf625fb10fa 100644
> --- a/drivers/clk/clk-fractional-divider.c
> +++ b/drivers/clk/clk-fractional-divider.c
> @@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
>   	return ret;
>   }
>
> -static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
> -			      unsigned long *parent_rate)
> +static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
> +					 unsigned long *parent_rate,
> +					 unsigned long *m, unsigned long *n)
>   {
>   	struct clk_fractional_divider *fd = to_clk_fd(hw);
>   	unsigned long scale;
> -	unsigned long m, n;
> -	u64 ret;
> -
> -	if (!rate || rate >= *parent_rate)
> -		return *parent_rate;
>
>   	/*
>   	 * Get rate closer to *parent_rate to guarantee there is no overflow
> @@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
>
>   	rational_best_approximation(rate, *parent_rate,
>   			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
> -			&m, &n);
> +			m, n);
> +}
> +
> +static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
> +			      unsigned long *parent_rate)
> +{
> +	struct clk_fractional_divider *fd = to_clk_fd(hw);
> +	unsigned long m, n;
> +	u64 ret;
> +
> +	if (!rate || rate >= *parent_rate)
> +		return *parent_rate;
> +
> +	if (fd->approximation)
> +		fd->approximation(hw, rate, parent_rate, &m, &n);
> +	else
> +		clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
>
>   	ret = (u64)*parent_rate * m;
>   	do_div(ret, n);
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index c59c62571e4f..1fc113fbf955 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -565,6 +565,9 @@ struct clk_fractional_divider {
>   	u8		nwidth;
>   	u32		nmask;
>   	u8		flags;
> +	void		(*approximation)(struct clk_hw *hw,
> +				unsigned long rate, unsigned long *parent_rate,
> +				unsigned long *m, unsigned long *n);
>   	spinlock_t	*lock;
>   };
>
>
Tested-by: Elaine Zhang <zhangqing@rock-chips.com>

[PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Elaine Zhang]

hi,heiko:

This a good solution.And I tested it on RK SOCs.It's work well.

On 08/02/2017 12:21 AM, Heiko Stuebner wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
>
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
>
> Therefore add the ability to provide custom approximation functions.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/clk-fractional-divider.c | 28 ++++++++++++++++++++--------
>   include/linux/clk-provider.h         |  3 +++
>   2 files changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
> index aab904618eb6..fdf625fb10fa 100644
> --- a/drivers/clk/clk-fractional-divider.c
> +++ b/drivers/clk/clk-fractional-divider.c
> @@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
>   	return ret;
>   }
>
> -static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
> -			      unsigned long *parent_rate)
> +static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
> +					 unsigned long *parent_rate,
> +					 unsigned long *m, unsigned long *n)
>   {
>   	struct clk_fractional_divider *fd = to_clk_fd(hw);
>   	unsigned long scale;
> -	unsigned long m, n;
> -	u64 ret;
> -
> -	if (!rate || rate >= *parent_rate)
> -		return *parent_rate;
>
>   	/*
>   	 * Get rate closer to *parent_rate to guarantee there is no overflow
> @@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
>
>   	rational_best_approximation(rate, *parent_rate,
>   			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
> -			&m, &n);
> +			m, n);
> +}
> +
> +static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
> +			      unsigned long *parent_rate)
> +{
> +	struct clk_fractional_divider *fd = to_clk_fd(hw);
> +	unsigned long m, n;
> +	u64 ret;
> +
> +	if (!rate || rate >= *parent_rate)
> +		return *parent_rate;
> +
> +	if (fd->approximation)
> +		fd->approximation(hw, rate, parent_rate, &m, &n);
> +	else
> +		clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
>
>   	ret = (u64)*parent_rate * m;
>   	do_div(ret, n);
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index c59c62571e4f..1fc113fbf955 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -565,6 +565,9 @@ struct clk_fractional_divider {
>   	u8		nwidth;
>   	u32		nmask;
>   	u8		flags;
> +	void		(*approximation)(struct clk_hw *hw,
> +				unsigned long rate, unsigned long *parent_rate,
> +				unsigned long *m, unsigned long *n);
>   	spinlock_t	*lock;
>   };
>
>
Tested-by: Elaine Zhang <zhangqing@rock-chips.com>

Re: [PATCH 2/2] clk: rockchip: add special approximation to fix up fractional clk's jitter

[Elaine Zhang]

On 08/02/2017 12:22 AM, Heiko Stuebner wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
>>From Rockchips fractional divider description:
>    3.1.9  Fractional divider usage
>    To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
>    fractional divider. Generally you must set that denominator is 20 times
>    larger than numerator to generate precise clock frequency. So the
>    fractional divider applies only to generate low frequency clock like
>    I2S, UART.
>
> Therefore add a special approximation function that handles this
> special requirement.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 36 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index fe1d393cf678..b6db79a00602 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -29,6 +29,7 @@
>   #include <linux/mfd/syscon.h>
>   #include <linux/regmap.h>
>   #include <linux/reboot.h>
> +#include <linux/rational.h>
>   #include "clk.h"
>
>   /**
> @@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
>   	return notifier_from_errno(ret);
>   }
>
> +/**
> + * fractional divider must set that denominator is 20 times larger than
> + * numerator to generate precise clock frequency.
> + */
> +void rockchip_fractional_approximation(struct clk_hw *hw,
> +		unsigned long rate, unsigned long *parent_rate,
> +		unsigned long *m, unsigned long *n)
> +{
> +	struct clk_fractional_divider *fd = to_clk_fd(hw);
> +	unsigned long p_rate, p_parent_rate;
> +	struct clk_hw *p_parent;
> +	unsigned long scale;
> +
> +	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
> +	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
> +		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
> +		p_parent_rate = clk_hw_get_rate(p_parent);
> +		*parent_rate = p_parent_rate;
> +	}
> +
> +	/*
> +	 * Get rate closer to *parent_rate to guarantee there is no overflow
> +	 * for m and n. In the result it will be the nearest rate left shifted
> +	 * by (scale - fd->nwidth) bits.
> +	 */
> +	scale = fls_long(*parent_rate / rate - 1);
> +	if (scale > fd->nwidth)
> +		rate <<= scale - fd->nwidth;
> +
> +	rational_best_approximation(rate, *parent_rate,
> +			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
> +			m, n);
> +}
> +
>   static struct clk *rockchip_clk_register_frac_branch(
>   		struct rockchip_clk_provider *ctx, const char *name,
>   		const char *const *parent_names, u8 num_parents,
> @@ -210,6 +245,7 @@ static struct clk *rockchip_clk_register_frac_branch(
>   	div->nwidth = 16;
>   	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
>   	div->lock = lock;
> +	div->approximation = rockchip_fractional_approximation;
>   	div_ops = &clk_fractional_divider_ops;
>
>   	clk = clk_register_composite(NULL, name, parent_names, num_parents,
>
Tested-by: Elaine Zhang <zhangqing@rock-chips.com>

[PATCH 2/2] clk: rockchip: add special approximation to fix up fractional clk's jitter

[Elaine Zhang]

On 08/02/2017 12:22 AM, Heiko Stuebner wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
>>From Rockchips fractional divider description:
>    3.1.9  Fractional divider usage
>    To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
>    fractional divider. Generally you must set that denominator is 20 times
>    larger than numerator to generate precise clock frequency. So the
>    fractional divider applies only to generate low frequency clock like
>    I2S, UART.
>
> Therefore add a special approximation function that handles this
> special requirement.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 36 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index fe1d393cf678..b6db79a00602 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -29,6 +29,7 @@
>   #include <linux/mfd/syscon.h>
>   #include <linux/regmap.h>
>   #include <linux/reboot.h>
> +#include <linux/rational.h>
>   #include "clk.h"
>
>   /**
> @@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
>   	return notifier_from_errno(ret);
>   }
>
> +/**
> + * fractional divider must set that denominator is 20 times larger than
> + * numerator to generate precise clock frequency.
> + */
> +void rockchip_fractional_approximation(struct clk_hw *hw,
> +		unsigned long rate, unsigned long *parent_rate,
> +		unsigned long *m, unsigned long *n)
> +{
> +	struct clk_fractional_divider *fd = to_clk_fd(hw);
> +	unsigned long p_rate, p_parent_rate;
> +	struct clk_hw *p_parent;
> +	unsigned long scale;
> +
> +	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
> +	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
> +		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
> +		p_parent_rate = clk_hw_get_rate(p_parent);
> +		*parent_rate = p_parent_rate;
> +	}
> +
> +	/*
> +	 * Get rate closer to *parent_rate to guarantee there is no overflow
> +	 * for m and n. In the result it will be the nearest rate left shifted
> +	 * by (scale - fd->nwidth) bits.
> +	 */
> +	scale = fls_long(*parent_rate / rate - 1);
> +	if (scale > fd->nwidth)
> +		rate <<= scale - fd->nwidth;
> +
> +	rational_best_approximation(rate, *parent_rate,
> +			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
> +			m, n);
> +}
> +
>   static struct clk *rockchip_clk_register_frac_branch(
>   		struct rockchip_clk_provider *ctx, const char *name,
>   		const char *const *parent_names, u8 num_parents,
> @@ -210,6 +245,7 @@ static struct clk *rockchip_clk_register_frac_branch(
>   	div->nwidth = 16;
>   	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
>   	div->lock = lock;
> +	div->approximation = rockchip_fractional_approximation;
>   	div_ops = &clk_fractional_divider_ops;
>
>   	clk = clk_register_composite(NULL, name, parent_names, num_parents,
>
Tested-by: Elaine Zhang <zhangqing@rock-chips.com>

Re: [PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Stephen Boyd]

On 08/01, Heiko Stuebner wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
> 
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
> 
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
> 
> Therefore add the ability to provide custom approximation functions.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Stephen Boyd]

On 08/01, Heiko Stuebner wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
> 
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
> 
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
> 
> Therefore add the ability to provide custom approximation functions.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Heiko Stuebner]

Am Dienstag, 1. August 2017, 18:21:22 CEST schrieb Heiko Stuebner:
> From: Elaine Zhang <zhangqing@rock-chips.com>
> 
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
> 
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
> 
> Therefore add the ability to provide custom approximation functions.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied for 4.14 with Stephen's Ack


Heiko

[PATCH 1/2] clk: fractional-divider: allow overriding of approximation

[Heiko Stuebner]

Am Dienstag, 1. August 2017, 18:21:22 CEST schrieb Heiko Stuebner:
> From: Elaine Zhang <zhangqing@rock-chips.com>
> 
> Fractional dividers may have special requirements concerning numerator
> and denominator selection that differ from just getting the best
> approximation.
> 
> For example on Rockchip socs the denominator must be at least 20 times
> larger than the numerator to generate precise clock frequencies.
> 
> Therefore add the ability to provide custom approximation functions.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied for 4.14 with Stephen's Ack


Heiko

Re: [PATCH 2/2] clk: rockchip: add special approximation to fix up fractional clk's jitter

[Heiko Stuebner]

Am Dienstag, 1. August 2017, 18:22:24 CEST schrieb Heiko Stuebner:
> From: Elaine Zhang <zhangqing@rock-chips.com>
> 
> From Rockchips fractional divider description:
>   3.1.9  Fractional divider usage
>   To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
>   fractional divider. Generally you must set that denominator is 20 times
>   larger than numerator to generate precise clock frequency. So the
>   fractional divider applies only to generate low frequency clock like
>   I2S, UART.
> 
> Therefore add a special approximation function that handles this
> special requirement.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied for 4.14


Heiko

[PATCH 2/2] clk: rockchip: add special approximation to fix up fractional clk's jitter

[Heiko Stuebner]

Am Dienstag, 1. August 2017, 18:22:24 CEST schrieb Heiko Stuebner:
> From: Elaine Zhang <zhangqing@rock-chips.com>
> 
> From Rockchips fractional divider description:
>   3.1.9  Fractional divider usage
>   To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
>   fractional divider. Generally you must set that denominator is 20 times
>   larger than numerator to generate precise clock frequency. So the
>   fractional divider applies only to generate low frequency clock like
>   I2S, UART.
> 
> Therefore add a special approximation function that handles this
> special requirement.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied for 4.14


Heiko