* [PATCH] target/riscv: Check the correct exception cause in vector GDB stub
@ 2022-09-18 8:32 frank.chang
2022-09-19 10:48 ` LIU Zhiwei
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: frank.chang @ 2022-09-18 8:32 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Frank Chang, Jim Shu, Tommy Wu, Palmer Dabbelt,
Alistair Francis, Bin Meng
From: Frank Chang <frank.chang@sifive.com>
After RISCVException enum is introduced, riscv_csrrw_debug() returns
RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
should check the result against RISCV_EXCP_NONE instead of value 0.
Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
when using "info reg vector" GDB command.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Tommy Wu <tommy.wu@sifive.com>
---
target/riscv/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 9ed049c29e..118bd40f10 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -211,7 +211,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
target_ulong val = 0;
int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
- if (result == 0) {
+ if (result == RISCV_EXCP_NONE) {
return gdb_get_regl(buf, val);
}
@@ -238,7 +238,7 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
target_ulong val = ldtul_p(mem_buf);
int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
- if (result == 0) {
+ if (result == RISCV_EXCP_NONE) {
return sizeof(target_ulong);
}
--
2.36.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub
2022-09-18 8:32 [PATCH] target/riscv: Check the correct exception cause in vector GDB stub frank.chang
@ 2022-09-19 10:48 ` LIU Zhiwei
2022-09-19 23:35 ` Alistair Francis
2022-09-19 23:53 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: LIU Zhiwei @ 2022-09-19 10:48 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: qemu-riscv, Jim Shu, Tommy Wu, Palmer Dabbelt, Alistair Francis,
Bin Meng
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
On 2022/9/18 16:32, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> After RISCVException enum is introduced, riscv_csrrw_debug() returns
> RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
> should check the result against RISCV_EXCP_NONE instead of value 0.
> Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
> when using "info reg vector" GDB command.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Tommy Wu <tommy.wu@sifive.com>
> ---
> target/riscv/gdbstub.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 9ed049c29e..118bd40f10 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -211,7 +211,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
> target_ulong val = 0;
> int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
>
> - if (result == 0) {
> + if (result == RISCV_EXCP_NONE) {
> return gdb_get_regl(buf, val);
> }
>
> @@ -238,7 +238,7 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
> target_ulong val = ldtul_p(mem_buf);
> int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
>
> - if (result == 0) {
> + if (result == RISCV_EXCP_NONE) {
> return sizeof(target_ulong);
> }
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub
2022-09-18 8:32 [PATCH] target/riscv: Check the correct exception cause in vector GDB stub frank.chang
2022-09-19 10:48 ` LIU Zhiwei
@ 2022-09-19 23:35 ` Alistair Francis
2022-09-19 23:53 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-09-19 23:35 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Jim Shu,
Tommy Wu, Palmer Dabbelt, Alistair Francis, Bin Meng
On Sun, Sep 18, 2022 at 6:29 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> After RISCVException enum is introduced, riscv_csrrw_debug() returns
> RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
> should check the result against RISCV_EXCP_NONE instead of value 0.
> Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
> when using "info reg vector" GDB command.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/gdbstub.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 9ed049c29e..118bd40f10 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -211,7 +211,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
> target_ulong val = 0;
> int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
>
> - if (result == 0) {
> + if (result == RISCV_EXCP_NONE) {
> return gdb_get_regl(buf, val);
> }
>
> @@ -238,7 +238,7 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
> target_ulong val = ldtul_p(mem_buf);
> int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
>
> - if (result == 0) {
> + if (result == RISCV_EXCP_NONE) {
> return sizeof(target_ulong);
> }
>
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub
2022-09-18 8:32 [PATCH] target/riscv: Check the correct exception cause in vector GDB stub frank.chang
2022-09-19 10:48 ` LIU Zhiwei
2022-09-19 23:35 ` Alistair Francis
@ 2022-09-19 23:53 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-09-19 23:53 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Jim Shu,
Tommy Wu, Palmer Dabbelt, Alistair Francis, Bin Meng
On Sun, Sep 18, 2022 at 6:29 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> After RISCVException enum is introduced, riscv_csrrw_debug() returns
> RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
> should check the result against RISCV_EXCP_NONE instead of value 0.
> Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
> when using "info reg vector" GDB command.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Tommy Wu <tommy.wu@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/gdbstub.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 9ed049c29e..118bd40f10 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -211,7 +211,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
> target_ulong val = 0;
> int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
>
> - if (result == 0) {
> + if (result == RISCV_EXCP_NONE) {
> return gdb_get_regl(buf, val);
> }
>
> @@ -238,7 +238,7 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
> target_ulong val = ldtul_p(mem_buf);
> int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
>
> - if (result == 0) {
> + if (result == RISCV_EXCP_NONE) {
> return sizeof(target_ulong);
> }
>
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-09-19 23:54 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-09-18 8:32 [PATCH] target/riscv: Check the correct exception cause in vector GDB stub frank.chang
2022-09-19 10:48 ` LIU Zhiwei
2022-09-19 23:35 ` Alistair Francis
2022-09-19 23:53 ` Alistair Francis
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