* [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
@ 2020-05-08 20:39 Jim Mattson
2020-05-09 13:26 ` Paolo Bonzini
2020-10-10 8:42 ` Nadav Amit
0 siblings, 2 replies; 12+ messages in thread
From: Jim Mattson @ 2020-05-08 20:39 UTC (permalink / raw)
To: kvm, Paolo Bonzini; +Cc: Jim Mattson, Peter Shier
When the VMX-preemption timer is activated, code executing in VMX
non-root operation should never be able to record a TSC value beyond
the deadline imposed by adding the scaled VMX-preemption timer value
to the first TSC value observed by the guest after VM-entry.
Signed-off-by: Jim Mattson <jmattson@google.com>
Reviewed-by: Peter Shier <pshier@google.com>
---
lib/x86/processor.h | 23 +++++++++++++
x86/vmx.h | 21 ++++++++++++
x86/vmx_tests.c | 81 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 125 insertions(+)
diff --git a/lib/x86/processor.h b/lib/x86/processor.h
index 804673b..cf3acf6 100644
--- a/lib/x86/processor.h
+++ b/lib/x86/processor.h
@@ -479,6 +479,29 @@ static inline unsigned long long rdtsc(void)
return r;
}
+/*
+ * Per the advice in the SDM, volume 2, the sequence "mfence; lfence"
+ * executed immediately before rdtsc ensures that rdtsc will be
+ * executed only after all previous instructions have executed and all
+ * previous loads and stores are globally visible. In addition, the
+ * lfence immediately after rdtsc ensures that rdtsc will be executed
+ * prior to the execution of any subsequent instruction.
+ */
+static inline unsigned long long fenced_rdtsc(void)
+{
+ unsigned long long tsc;
+
+#ifdef __x86_64__
+ unsigned int eax, edx;
+
+ asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
+ tsc = eax | ((unsigned long long)edx << 32);
+#else
+ asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc));
+#endif
+ return tsc;
+}
+
static inline unsigned long long rdtscp(u32 *aux)
{
long long r;
diff --git a/x86/vmx.h b/x86/vmx.h
index 08b354d..71fdaa0 100644
--- a/x86/vmx.h
+++ b/x86/vmx.h
@@ -118,6 +118,27 @@ union vmx_ctrl_msr {
};
};
+union vmx_misc {
+ u64 val;
+ struct {
+ u32 pt_bit:5,
+ stores_lma:1,
+ act_hlt:1,
+ act_shutdown:1,
+ act_wfsipi:1,
+ :5,
+ vmx_pt:1,
+ smm_smbase:1,
+ cr3_targets:9,
+ msr_list_size:3,
+ smm_mon_ctl:1,
+ vmwrite_any:1,
+ inject_len0:1,
+ :1;
+ u32 mseg_revision;
+ };
+};
+
union vmx_ept_vpid {
u64 val;
struct {
diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c
index 0909adb..991c317 100644
--- a/x86/vmx_tests.c
+++ b/x86/vmx_tests.c
@@ -8555,6 +8555,86 @@ static void vmx_preemption_timer_tf_test(void)
handle_exception(DB_VECTOR, old_db);
}
+#define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000
+
+static u64 vmx_preemption_timer_expiry_start;
+static u64 vmx_preemption_timer_expiry_finish;
+
+static void vmx_preemption_timer_expiry_test_guest(void)
+{
+ vmcall();
+ vmx_preemption_timer_expiry_start = fenced_rdtsc();
+
+ while (vmx_get_test_stage() == 0)
+ vmx_preemption_timer_expiry_finish = fenced_rdtsc();
+}
+
+/*
+ * Test that the VMX-preemption timer is not excessively delayed.
+ *
+ * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer
+ * with the unsigned value in the VMX-preemption timer-value field,
+ * and the VMX-preemption timer counts down by 1 every time bit X in
+ * the TSC changes due to a TSC increment (where X is
+ * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state
+ * other than the wait-for-SIPI state, the logical processor
+ * transitions to the C0 C-state and causes a VM-exit.
+ *
+ * The guest code above reads the starting TSC after VM-entry. At this
+ * point, the VMX-preemption timer has already been activated. Next,
+ * the guest code reads the current TSC in a loop, storing the value
+ * read to memory.
+ *
+ * If the RDTSC in the loop reads a value past the VMX-preemption
+ * timer deadline, then the VMX-preemption timer VM-exit must be
+ * delivered before the next instruction retires. Even if a higher
+ * priority SMI is delivered first, the VMX-preemption timer VM-exit
+ * must be delivered before the next instruction retires. Hence, a TSC
+ * value past the VMX-preemption timer deadline might be read, but it
+ * cannot be stored. If a TSC value past the deadline *is* stored,
+ * then the architectural specification has been violated.
+ */
+static void vmx_preemption_timer_expiry_test(void)
+{
+ u32 preemption_timer_value;
+ union vmx_misc misc;
+ u64 tsc_deadline;
+ u32 reason;
+
+ if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) {
+ report_skip("'Activate VMX-preemption timer' not supported");
+ return;
+ }
+
+ test_set_guest(vmx_preemption_timer_expiry_test_guest);
+
+ enter_guest();
+ skip_exit_vmcall();
+
+ misc.val = rdmsr(MSR_IA32_VMX_MISC);
+ preemption_timer_value =
+ VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit;
+
+ vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT);
+ vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value);
+ vmx_set_test_stage(0);
+
+ enter_guest();
+ reason = (u32)vmcs_read(EXI_REASON);
+ TEST_ASSERT(reason == VMX_PREEMPT);
+
+ vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT);
+ vmx_set_test_stage(1);
+ enter_guest();
+
+ tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) <<
+ misc.pt_bit) + (preemption_timer_value << misc.pt_bit);
+
+ report(vmx_preemption_timer_expiry_finish < tsc_deadline,
+ "Last stored guest TSC (%lu) < TSC deadline (%lu)",
+ vmx_preemption_timer_expiry_finish, tsc_deadline);
+}
+
static void vmx_db_test_guest(void)
{
/*
@@ -9861,6 +9941,7 @@ struct vmx_test vmx_tests[] = {
TEST(vmx_store_tsc_test),
TEST(vmx_preemption_timer_zero_test),
TEST(vmx_preemption_timer_tf_test),
+ TEST(vmx_preemption_timer_expiry_test),
/* EPT access tests. */
TEST(ept_access_test_not_present),
TEST(ept_access_test_read_only),
--
2.26.2.526.g744177e7f7-goog
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-05-08 20:39 [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test Jim Mattson
@ 2020-05-09 13:26 ` Paolo Bonzini
2020-10-10 8:42 ` Nadav Amit
1 sibling, 0 replies; 12+ messages in thread
From: Paolo Bonzini @ 2020-05-09 13:26 UTC (permalink / raw)
To: Jim Mattson, kvm; +Cc: Peter Shier
On 08/05/20 22:39, Jim Mattson wrote:
> When the VMX-preemption timer is activated, code executing in VMX
> non-root operation should never be able to record a TSC value beyond
> the deadline imposed by adding the scaled VMX-preemption timer value
> to the first TSC value observed by the guest after VM-entry.
>
> Signed-off-by: Jim Mattson <jmattson@google.com>
> Reviewed-by: Peter Shier <pshier@google.com>
> ---
> lib/x86/processor.h | 23 +++++++++++++
> x86/vmx.h | 21 ++++++++++++
> x86/vmx_tests.c | 81 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 125 insertions(+)
>
> diff --git a/lib/x86/processor.h b/lib/x86/processor.h
> index 804673b..cf3acf6 100644
> --- a/lib/x86/processor.h
> +++ b/lib/x86/processor.h
> @@ -479,6 +479,29 @@ static inline unsigned long long rdtsc(void)
> return r;
> }
>
> +/*
> + * Per the advice in the SDM, volume 2, the sequence "mfence; lfence"
> + * executed immediately before rdtsc ensures that rdtsc will be
> + * executed only after all previous instructions have executed and all
> + * previous loads and stores are globally visible. In addition, the
> + * lfence immediately after rdtsc ensures that rdtsc will be executed
> + * prior to the execution of any subsequent instruction.
> + */
> +static inline unsigned long long fenced_rdtsc(void)
> +{
> + unsigned long long tsc;
> +
> +#ifdef __x86_64__
> + unsigned int eax, edx;
> +
> + asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
> + tsc = eax | ((unsigned long long)edx << 32);
> +#else
> + asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc));
> +#endif
> + return tsc;
> +}
> +
> static inline unsigned long long rdtscp(u32 *aux)
> {
> long long r;
> diff --git a/x86/vmx.h b/x86/vmx.h
> index 08b354d..71fdaa0 100644
> --- a/x86/vmx.h
> +++ b/x86/vmx.h
> @@ -118,6 +118,27 @@ union vmx_ctrl_msr {
> };
> };
>
> +union vmx_misc {
> + u64 val;
> + struct {
> + u32 pt_bit:5,
> + stores_lma:1,
> + act_hlt:1,
> + act_shutdown:1,
> + act_wfsipi:1,
> + :5,
> + vmx_pt:1,
> + smm_smbase:1,
> + cr3_targets:9,
> + msr_list_size:3,
> + smm_mon_ctl:1,
> + vmwrite_any:1,
> + inject_len0:1,
> + :1;
> + u32 mseg_revision;
> + };
> +};
> +
> union vmx_ept_vpid {
> u64 val;
> struct {
> diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c
> index 0909adb..991c317 100644
> --- a/x86/vmx_tests.c
> +++ b/x86/vmx_tests.c
> @@ -8555,6 +8555,86 @@ static void vmx_preemption_timer_tf_test(void)
> handle_exception(DB_VECTOR, old_db);
> }
>
> +#define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000
> +
> +static u64 vmx_preemption_timer_expiry_start;
> +static u64 vmx_preemption_timer_expiry_finish;
> +
> +static void vmx_preemption_timer_expiry_test_guest(void)
> +{
> + vmcall();
> + vmx_preemption_timer_expiry_start = fenced_rdtsc();
> +
> + while (vmx_get_test_stage() == 0)
> + vmx_preemption_timer_expiry_finish = fenced_rdtsc();
> +}
> +
> +/*
> + * Test that the VMX-preemption timer is not excessively delayed.
> + *
> + * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer
> + * with the unsigned value in the VMX-preemption timer-value field,
> + * and the VMX-preemption timer counts down by 1 every time bit X in
> + * the TSC changes due to a TSC increment (where X is
> + * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state
> + * other than the wait-for-SIPI state, the logical processor
> + * transitions to the C0 C-state and causes a VM-exit.
> + *
> + * The guest code above reads the starting TSC after VM-entry. At this
> + * point, the VMX-preemption timer has already been activated. Next,
> + * the guest code reads the current TSC in a loop, storing the value
> + * read to memory.
> + *
> + * If the RDTSC in the loop reads a value past the VMX-preemption
> + * timer deadline, then the VMX-preemption timer VM-exit must be
> + * delivered before the next instruction retires. Even if a higher
> + * priority SMI is delivered first, the VMX-preemption timer VM-exit
> + * must be delivered before the next instruction retires. Hence, a TSC
> + * value past the VMX-preemption timer deadline might be read, but it
> + * cannot be stored. If a TSC value past the deadline *is* stored,
> + * then the architectural specification has been violated.
> + */
> +static void vmx_preemption_timer_expiry_test(void)
> +{
> + u32 preemption_timer_value;
> + union vmx_misc misc;
> + u64 tsc_deadline;
> + u32 reason;
> +
> + if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) {
> + report_skip("'Activate VMX-preemption timer' not supported");
> + return;
> + }
> +
> + test_set_guest(vmx_preemption_timer_expiry_test_guest);
> +
> + enter_guest();
> + skip_exit_vmcall();
> +
> + misc.val = rdmsr(MSR_IA32_VMX_MISC);
> + preemption_timer_value =
> + VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit;
> +
> + vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT);
> + vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value);
> + vmx_set_test_stage(0);
> +
> + enter_guest();
> + reason = (u32)vmcs_read(EXI_REASON);
> + TEST_ASSERT(reason == VMX_PREEMPT);
> +
> + vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT);
> + vmx_set_test_stage(1);
> + enter_guest();
> +
> + tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) <<
> + misc.pt_bit) + (preemption_timer_value << misc.pt_bit);
> +
> + report(vmx_preemption_timer_expiry_finish < tsc_deadline,
> + "Last stored guest TSC (%lu) < TSC deadline (%lu)",
> + vmx_preemption_timer_expiry_finish, tsc_deadline);
> +}
> +
> static void vmx_db_test_guest(void)
> {
> /*
> @@ -9861,6 +9941,7 @@ struct vmx_test vmx_tests[] = {
> TEST(vmx_store_tsc_test),
> TEST(vmx_preemption_timer_zero_test),
> TEST(vmx_preemption_timer_tf_test),
> + TEST(vmx_preemption_timer_expiry_test),
> /* EPT access tests. */
> TEST(ept_access_test_not_present),
> TEST(ept_access_test_read_only),
>
Queued, thanks.
Paolo
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-05-08 20:39 [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test Jim Mattson
2020-05-09 13:26 ` Paolo Bonzini
@ 2020-10-10 8:42 ` Nadav Amit
2020-10-12 16:32 ` Sean Christopherson
1 sibling, 1 reply; 12+ messages in thread
From: Nadav Amit @ 2020-10-10 8:42 UTC (permalink / raw)
To: Jim Mattson; +Cc: kvm, Paolo Bonzini, Peter Shier
>
> On May 8, 2020, at 1:39 PM, Jim Mattson <jmattson@google.com> wrote:
>
> When the VMX-preemption timer is activated, code executing in VMX
> non-root operation should never be able to record a TSC value beyond
> the deadline imposed by adding the scaled VMX-preemption timer value
> to the first TSC value observed by the guest after VM-entry.
>
> Signed-off-by: Jim Mattson <jmattson@google.com>
> Reviewed-by: Peter Shier <pshier@google.com>
This test failed on my bare-metal machine (Broadwell):
Test suite: vmx_preemption_timer_expiry_test
FAIL: Last stored guest TSC (44435478250637180) < TSC deadline (44435478250419552)
Any hints why, perhaps based on the motivation for the test?
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-10 8:42 ` Nadav Amit
@ 2020-10-12 16:32 ` Sean Christopherson
2020-10-12 16:47 ` Nadav Amit
0 siblings, 1 reply; 12+ messages in thread
From: Sean Christopherson @ 2020-10-12 16:32 UTC (permalink / raw)
To: Nadav Amit; +Cc: Jim Mattson, kvm, Paolo Bonzini, Peter Shier
On Sat, Oct 10, 2020 at 01:42:26AM -0700, Nadav Amit wrote:
> >
> > On May 8, 2020, at 1:39 PM, Jim Mattson <jmattson@google.com> wrote:
> >
> > When the VMX-preemption timer is activated, code executing in VMX
> > non-root operation should never be able to record a TSC value beyond
> > the deadline imposed by adding the scaled VMX-preemption timer value
> > to the first TSC value observed by the guest after VM-entry.
> >
> > Signed-off-by: Jim Mattson <jmattson@google.com>
> > Reviewed-by: Peter Shier <pshier@google.com>
>
> This test failed on my bare-metal machine (Broadwell):
>
> Test suite: vmx_preemption_timer_expiry_test
> FAIL: Last stored guest TSC (44435478250637180) < TSC deadline (44435478250419552)
>
> Any hints why, perhaps based on the motivation for the test?
This test also fails intermittently on my Haswell and Coffee Lake systems when
running on KVM. I haven't done any "debug" beyond a quick glance at the test.
The intent of the test is to verify that KVM injects preemption timer VM-Exits
without violating the architectural guarantees of the timer, e.g. that the exit
isn't delayed by something else happening in the system.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-12 16:32 ` Sean Christopherson
@ 2020-10-12 16:47 ` Nadav Amit
2020-10-12 17:55 ` Jim Mattson
0 siblings, 1 reply; 12+ messages in thread
From: Nadav Amit @ 2020-10-12 16:47 UTC (permalink / raw)
To: Sean Christopherson; +Cc: Jim Mattson, KVM, Paolo Bonzini, Peter Shier
> On Oct 12, 2020, at 9:32 AM, Sean Christopherson <sean.j.christopherson@intel.com> wrote:
>
> On Sat, Oct 10, 2020 at 01:42:26AM -0700, Nadav Amit wrote:
>>> On May 8, 2020, at 1:39 PM, Jim Mattson <jmattson@google.com> wrote:
>>>
>>> When the VMX-preemption timer is activated, code executing in VMX
>>> non-root operation should never be able to record a TSC value beyond
>>> the deadline imposed by adding the scaled VMX-preemption timer value
>>> to the first TSC value observed by the guest after VM-entry.
>>>
>>> Signed-off-by: Jim Mattson <jmattson@google.com>
>>> Reviewed-by: Peter Shier <pshier@google.com>
>>
>> This test failed on my bare-metal machine (Broadwell):
>>
>> Test suite: vmx_preemption_timer_expiry_test
>> FAIL: Last stored guest TSC (44435478250637180) < TSC deadline (44435478250419552)
>>
>> Any hints why, perhaps based on the motivation for the test?
>
> This test also fails intermittently on my Haswell and Coffee Lake systems when
> running on KVM. I haven't done any "debug" beyond a quick glance at the test.
>
> The intent of the test is to verify that KVM injects preemption timer VM-Exits
> without violating the architectural guarantees of the timer, e.g. that the exit
> isn't delayed by something else happening in the system.
Thanks for testing it. I was wondering how come KVM does not experience such
failures.
I figured the basic motivation of the patch, but I was wondering whether
there is some errata that the test is supposed to check.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-12 16:47 ` Nadav Amit
@ 2020-10-12 17:55 ` Jim Mattson
2020-10-12 18:17 ` Nadav Amit
0 siblings, 1 reply; 12+ messages in thread
From: Jim Mattson @ 2020-10-12 17:55 UTC (permalink / raw)
To: Nadav Amit; +Cc: Sean Christopherson, KVM, Paolo Bonzini, Peter Shier
I don't know of any relevant hardware errata. The test verifies that
the implementation adheres to the architectural specification.
KVM clearly doesn't adhere to the architectural specification. I don't
know what is wrong with your Broadwell machine.
On Mon, Oct 12, 2020 at 9:47 AM Nadav Amit <nadav.amit@gmail.com> wrote:
>
> > On Oct 12, 2020, at 9:32 AM, Sean Christopherson <sean.j.christopherson@intel.com> wrote:
> >
> > On Sat, Oct 10, 2020 at 01:42:26AM -0700, Nadav Amit wrote:
> >>> On May 8, 2020, at 1:39 PM, Jim Mattson <jmattson@google.com> wrote:
> >>>
> >>> When the VMX-preemption timer is activated, code executing in VMX
> >>> non-root operation should never be able to record a TSC value beyond
> >>> the deadline imposed by adding the scaled VMX-preemption timer value
> >>> to the first TSC value observed by the guest after VM-entry.
> >>>
> >>> Signed-off-by: Jim Mattson <jmattson@google.com>
> >>> Reviewed-by: Peter Shier <pshier@google.com>
> >>
> >> This test failed on my bare-metal machine (Broadwell):
> >>
> >> Test suite: vmx_preemption_timer_expiry_test
> >> FAIL: Last stored guest TSC (44435478250637180) < TSC deadline (44435478250419552)
> >>
> >> Any hints why, perhaps based on the motivation for the test?
> >
> > This test also fails intermittently on my Haswell and Coffee Lake systems when
> > running on KVM. I haven't done any "debug" beyond a quick glance at the test.
> >
> > The intent of the test is to verify that KVM injects preemption timer VM-Exits
> > without violating the architectural guarantees of the timer, e.g. that the exit
> > isn't delayed by something else happening in the system.
>
> Thanks for testing it. I was wondering how come KVM does not experience such
> failures.
>
> I figured the basic motivation of the patch, but I was wondering whether
> there is some errata that the test is supposed to check.
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-12 17:55 ` Jim Mattson
@ 2020-10-12 18:17 ` Nadav Amit
2020-10-12 18:29 ` Paolo Bonzini
0 siblings, 1 reply; 12+ messages in thread
From: Nadav Amit @ 2020-10-12 18:17 UTC (permalink / raw)
To: Jim Mattson; +Cc: Sean Christopherson, KVM, Paolo Bonzini, Peter Shier
> On Oct 12, 2020, at 10:55 AM, Jim Mattson <jmattson@google.com> wrote:
>
> I don't know of any relevant hardware errata. The test verifies that
> the implementation adheres to the architectural specification.
>
> KVM clearly doesn't adhere to the architectural specification. I don't
> know what is wrong with your Broadwell machine.
Are you saying that the test is expected to fail on KVM? And that Sean’s
failures are expected?
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-12 18:17 ` Nadav Amit
@ 2020-10-12 18:29 ` Paolo Bonzini
2020-10-12 18:31 ` Nadav Amit
2020-10-12 18:34 ` Jim Mattson
0 siblings, 2 replies; 12+ messages in thread
From: Paolo Bonzini @ 2020-10-12 18:29 UTC (permalink / raw)
To: Nadav Amit, Jim Mattson; +Cc: Sean Christopherson, KVM, Peter Shier
On 12/10/20 20:17, Nadav Amit wrote:
>>
>> KVM clearly doesn't adhere to the architectural specification. I don't
>> know what is wrong with your Broadwell machine.
> Are you saying that the test is expected to fail on KVM? And that Sean’s
> failures are expected?
>
It's not expected to fail, but it's apparently broken.
Paolo
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-12 18:29 ` Paolo Bonzini
@ 2020-10-12 18:31 ` Nadav Amit
2020-10-12 18:46 ` Jim Mattson
2020-10-12 18:34 ` Jim Mattson
1 sibling, 1 reply; 12+ messages in thread
From: Nadav Amit @ 2020-10-12 18:31 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Jim Mattson, Sean Christopherson, KVM, Peter Shier
> On Oct 12, 2020, at 11:29 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 12/10/20 20:17, Nadav Amit wrote:
>>> KVM clearly doesn't adhere to the architectural specification. I don't
>>> know what is wrong with your Broadwell machine.
>> Are you saying that the test is expected to fail on KVM? And that Sean’s
>> failures are expected?
>
> It's not expected to fail, but it's apparently broken.
Hm… Based on my results on bare-metal, it might be an architectural issue or
a test issue, and not a KVM issue.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-12 18:29 ` Paolo Bonzini
2020-10-12 18:31 ` Nadav Amit
@ 2020-10-12 18:34 ` Jim Mattson
1 sibling, 0 replies; 12+ messages in thread
From: Jim Mattson @ 2020-10-12 18:34 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Nadav Amit, Sean Christopherson, KVM, Peter Shier
On Mon, Oct 12, 2020 at 11:29 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 12/10/20 20:17, Nadav Amit wrote:
> >>
> >> KVM clearly doesn't adhere to the architectural specification. I don't
> >> know what is wrong with your Broadwell machine.
> > Are you saying that the test is expected to fail on KVM? And that Sean’s
> > failures are expected?
> >
>
> It's not expected to fail, but it's apparently broken.
KVM uses a sloppy hrtimer to deliver the interrupt that emulates the
VMX-preemption timer, so it can't possibly work all of the time. Much
of the time, though, it gets lucky.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-12 18:31 ` Nadav Amit
@ 2020-10-12 18:46 ` Jim Mattson
2020-10-12 20:21 ` Nadav Amit
0 siblings, 1 reply; 12+ messages in thread
From: Jim Mattson @ 2020-10-12 18:46 UTC (permalink / raw)
To: Nadav Amit; +Cc: Paolo Bonzini, Sean Christopherson, KVM, Peter Shier
On Mon, Oct 12, 2020 at 11:31 AM Nadav Amit <nadav.amit@gmail.com> wrote:
>
> > On Oct 12, 2020, at 11:29 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> >
> > On 12/10/20 20:17, Nadav Amit wrote:
> >>> KVM clearly doesn't adhere to the architectural specification. I don't
> >>> know what is wrong with your Broadwell machine.
> >> Are you saying that the test is expected to fail on KVM? And that Sean’s
> >> failures are expected?
> >
> > It's not expected to fail, but it's apparently broken.
>
> Hm… Based on my results on bare-metal, it might be an architectural issue or
> a test issue, and not a KVM issue.
From section 25.5.1 of the SDM, volume 3:
If the last VM entry was performed with the 1-setting of “activate
VMX-preemption timer” VM-execution control,
the VMX-preemption timer counts down (from the value loaded by VM
entry; see Section 26.7.4) in VMX non-
root operation. When the timer counts down to zero, it stops counting
down and a VM exit occurs (see Section
25.2).
The test is actually quite lax, in that it doesn't start tracking VMX
non-root operation time until actually in the guest. Hardware is free
to start tracking VMX non-root operation time during VM-entry.
If the test can both observe a TSC value after the VMX-preemption
timer deadline *and* store that value to memory, then the store
instruction must have started executing after the VMX-preemption timer
has counted down to zero. Per the SDM, a VM-exit should have occurred
before the store could retire.
Of course, there could be a test bug.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test
2020-10-12 18:46 ` Jim Mattson
@ 2020-10-12 20:21 ` Nadav Amit
0 siblings, 0 replies; 12+ messages in thread
From: Nadav Amit @ 2020-10-12 20:21 UTC (permalink / raw)
To: Jim Mattson; +Cc: Paolo Bonzini, Sean Christopherson, KVM, Peter Shier
> On Oct 12, 2020, at 11:46 AM, Jim Mattson <jmattson@google.com> wrote:
>
> On Mon, Oct 12, 2020 at 11:31 AM Nadav Amit <nadav.amit@gmail.com> wrote:
>>> On Oct 12, 2020, at 11:29 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>>>
>>> On 12/10/20 20:17, Nadav Amit wrote:
>>>>> KVM clearly doesn't adhere to the architectural specification. I don't
>>>>> know what is wrong with your Broadwell machine.
>>>> Are you saying that the test is expected to fail on KVM? And that Sean’s
>>>> failures are expected?
>>>
>>> It's not expected to fail, but it's apparently broken.
>>
>> Hm… Based on my results on bare-metal, it might be an architectural issue or
>> a test issue, and not a KVM issue.
>
> From section 25.5.1 of the SDM, volume 3:
>
> If the last VM entry was performed with the 1-setting of “activate
> VMX-preemption timer” VM-execution control,
> the VMX-preemption timer counts down (from the value loaded by VM
> entry; see Section 26.7.4) in VMX non-
> root operation. When the timer counts down to zero, it stops counting
> down and a VM exit occurs (see Section
> 25.2).
>
> The test is actually quite lax, in that it doesn't start tracking VMX
> non-root operation time until actually in the guest. Hardware is free
> to start tracking VMX non-root operation time during VM-entry.
>
> If the test can both observe a TSC value after the VMX-preemption
> timer deadline *and* store that value to memory, then the store
> instruction must have started executing after the VMX-preemption timer
> has counted down to zero. Per the SDM, a VM-exit should have occurred
> before the store could retire.
>
> Of course, there could be a test bug.
My guess was that TSC_OFFSET is left set by one of the previous tests. But
unfortunately, I do not manage to reproduce the failure.
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-10-12 20:21 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-08 20:39 [kvm-unit-tests PATCH] x86: VMX: Add a VMX-preemption timer expiration test Jim Mattson
2020-05-09 13:26 ` Paolo Bonzini
2020-10-10 8:42 ` Nadav Amit
2020-10-12 16:32 ` Sean Christopherson
2020-10-12 16:47 ` Nadav Amit
2020-10-12 17:55 ` Jim Mattson
2020-10-12 18:17 ` Nadav Amit
2020-10-12 18:29 ` Paolo Bonzini
2020-10-12 18:31 ` Nadav Amit
2020-10-12 18:46 ` Jim Mattson
2020-10-12 20:21 ` Nadav Amit
2020-10-12 18:34 ` Jim Mattson
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