* [PATCHv4 0/14] dmtimer adaptation to platform_driver
@ 2010-11-20 2:39 Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes Tarun Kanti DebBarma
0 siblings, 1 reply; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap
dmtimer adaptation to platform_driver.
This patch series is adaptation of dmtimer code to platform driver
using omap_device and omap_hwmod abstraction.
v4:
(1) clock aliases are renamed as "32k_ck", "sys_ck" and "alt_ck"
(2) incorporate missing clk_put() for corresponding clk_get()
(3) modified clk_get()/clk_put() to be called once once in platform driver.
(4) consistent header for new files
(5) check return value of omap_hwmod_for_each_by_class() in device init
routines.
(6) remove is_abe_timer field in dmtimer_platform_data structure. this is
no longer needed with new input clock source aliasing.
(7) proper splitting of patch series
(8) remove register map from hwmod database.
(9) remove clock source strings array from hwmod database and associated
structure declaration from plat/dmtimer.h. this is no longer needed.
(10) remove dev_attr from hwmod database. this is no longer needed.
(11) use register offsets to identify OMAP 4 registers instead of register map.
(12) remove clock source name strings from hwmod database.
(13) introduce new mechanism for getting struct clk associated with clock source
names. this is achieved by adding clock alisases for all supported clock sources.
(14) remove clock setup functions in mach-omap2 for populating struct clk
associated with all input clock sources because this is no longer needed with
above implementation.
(15) device names changed from dmtimer to omap-timer
(16) device index starts from 1 instead of 0
(17) remove .init_name from hwmod database. this is not needed.
(18) introduce separate functions for reading/writing interrupt registers instead of
doing all operations within a single function.
TODO:
(1) off mode support
v3:
(1) multi-line comment error correction
(2) provision to allow any of the available dmtimers as early timers
instead of restricting them to millisecond timers only.
(3) in 'struct omap_dmtimer{}' is_initialized flag is redundant and
so must be removed. if the element is found in the list it is already
initialized.
(4) remove 'found' flag in omap_dm_timer_request() and
omap_dm_timer_request_specific() functions.
this is not needed with alternate implementation.
(5) use .init_name to initialize device names so that it can be identified
during early boot as well. This is to avoid duplicate functions for clock
manipulations during early boot and later.
(6) remove redundant functions from mach-omap2 which are created just to
call pm functions like: pm_runtime_get_sync(),pm_runtime_put_sync(),..
and instead call them directly from plat-omap function api's.
(7) timer clock source names made part of hwmod database. source_clock[]
of type 'struct clk' is made part of platform data.
(8) clockactivity field initialized in hwmod database to preserve fclk
during idle. code which manipulate OCP config removed since they are
already taken care by hwmod framework.
(9) omap2_dm_timer_set_src() is optimized. Clock enable/disbale routines
moved to plat-omap layer and simplfied to the level so as not to sacrifice
intended functionality.
NOTE: During early boot clock management was requested to be placed upon
client drivers responsibility. this has not been done keeping in mind
that it would entail (i) multiple modifications of client drivers (ii) it
would violate the purpose of having a framework (open to debate).
(10) dmtimer register maps moved to hwmod database
v2:
(1) removed dedicated functions for early timer clock access.
instead, now we have common functions for early and normal timers.
(2) removed usage of clock source strings for reading corresponding
struct clks. this is now achieved through clock aliases introduced
for each input clock sources.
(3) IP revision to distinguish new IP standard and the rest and then
initialize dmtimer interrupt and functional offsets.
(4) provision to initialize all dmtimers as early timers.
(5) remove dm_timer_setup() function because this is no longer needed.
(6) modify the device index to start from 1 instead of 0.
(7) device name changed from dmtimer to omap-timer
(8) extract device ids' from hwmod name and same used for device build.
(9) additional resource allocation checks and free
(10) early timer variable initialization
(11) initialize timer_ip_type and register offsets in platform data structure.
(12) some more comments/logs
Baseline:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git
origin/master
Tarun Kanti DebBarma (14):
OMAP2+: dmtimer: add device names to flck nodes
OMAP: dmtimer: infrastructure to support hwmod
OMAP2420: dmtimer: add hwmod database
OMAP2430: dmtimer: add hwmod database
OMAP3: dmtimer: add hwmod database
OMAP4: dmtimer: add hwmod database
OMAP: dmtimer: use list instead of static array
OMAP: dmtimer: platform driver
OMAP1: dmtimer: conversion to platform devices
OMAP: dmtimer: access routines to interrupt registers
OMAP2+: dmtimer: convert to platform devices
OMAP: dmtimer: switch-over to platform device driver
OMAP: dmtimer: remove reset function
OMAP: dmtimer: pm_runtime support
arch/arm/mach-omap1/Makefile | 2 +-
arch/arm/mach-omap1/dmtimer.c | 174 +++++++
arch/arm/mach-omap2/Makefile | 2 +-
arch/arm/mach-omap2/clock2420_data.c | 60 ++-
arch/arm/mach-omap2/clock2430_data.c | 60 ++-
arch/arm/mach-omap2/clock3xxx_data.c | 48 ++-
arch/arm/mach-omap2/clock44xx_data.c | 44 ++-
arch/arm/mach-omap2/dmtimer.c | 296 ++++++++++++
arch/arm/mach-omap2/dmtimer.h | 32 ++
arch/arm/mach-omap2/io.c | 2 +
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 633 ++++++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 632 ++++++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 674 ++++++++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 622 +++++++++++++++++++++++++
arch/arm/mach-omap2/timer-gp.c | 1 -
arch/arm/plat-omap/dmtimer.c | 581 +++++++++++++-----------
arch/arm/plat-omap/include/plat/dmtimer.h | 19 +
17 files changed, 3559 insertions(+), 323 deletions(-)
create mode 100644 arch/arm/mach-omap1/dmtimer.c
create mode 100644 arch/arm/mach-omap2/dmtimer.c
create mode 100644 arch/arm/mach-omap2/dmtimer.h
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes
2010-11-20 2:39 [PATCHv4 0/14] dmtimer adaptation to platform_driver Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Tarun Kanti DebBarma
2010-11-22 17:32 ` [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes Cousson, Benoit
0 siblings, 2 replies; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Thara Gopinath, Tarun Kanti DebBarma
From: Thara Gopinath <thara@ti.com>
Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can be
retrieved by doing a clk_get with the corresponding device pointers or
device names.
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/mach-omap2/clock2420_data.c | 58 +++++++++++++++++++++++++++------
arch/arm/mach-omap2/clock2430_data.c | 58 +++++++++++++++++++++++++++------
arch/arm/mach-omap2/clock3xxx_data.c | 46 ++++++++++++++++++++------
arch/arm/mach-omap2/clock44xx_data.c | 42 ++++++++++++++++++------
4 files changed, 161 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 21f8562..d2e90ae 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1803,27 +1803,27 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
- CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
+ CLK("omap-timer.2", "fck", &gpt2_fck, CK_242X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
- CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
+ CLK("omap-timer.3", "fck", &gpt3_fck, CK_242X),
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
- CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
+ CLK("omap-timer.4", "fck", &gpt4_fck, CK_242X),
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
- CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
+ CLK("omap-timer.5", "fck", &gpt5_fck, CK_242X),
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
- CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
+ CLK("omap-timer.6", "fck", &gpt6_fck, CK_242X),
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
- CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
+ CLK("omap-timer.7", "fck", &gpt7_fck, CK_242X),
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
- CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
+ CLK("omap-timer.8", "fck", &gpt8_fck, CK_242X),
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
- CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
+ CLK("omap-timer.9", "fck", &gpt9_fck, CK_242X),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
- CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
+ CLK("omap-timer.10", "fck", &gpt10_fck, CK_242X),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
- CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
+ CLK("omap-timer.11", "fck", &gpt11_fck, CK_242X),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
- CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
+ CLK("omap-timer.12", "fck", &gpt12_fck, CK_242X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
@@ -1878,6 +1878,42 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
CLK("musb_hdrc", "fck", &osc_ck, CK_242X),
+ CLK("omap-timer.1", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.2", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.3", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.4", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.5", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.6", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.7", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.8", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.9", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.10", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.11", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.12", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.1", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.2", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.3", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.4", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.5", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.6", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.7", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.8", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.9", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.10", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.11", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.12", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.1", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.2", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.3", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.4", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.5", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.6", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.7", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.8", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.9", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.10", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.11", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.12", "alt_ck", &alt_ck, CK_243X),
};
/*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index e32afcb..7861bf4 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1907,27 +1907,27 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
- CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
+ CLK("omap-timer.2", "fck", &gpt2_fck, CK_243X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
- CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
+ CLK("omap-timer.3", "fck", &gpt3_fck, CK_243X),
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
- CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
+ CLK("omap-timer.4", "fck", &gpt4_fck, CK_243X),
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
- CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
+ CLK("omap-timer.5", "fck", &gpt5_fck, CK_243X),
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
- CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
+ CLK("omap-timer.6", "fck", &gpt6_fck, CK_243X),
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
- CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
+ CLK("omap-timer.7", "fck", &gpt7_fck, CK_243X),
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
- CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
+ CLK("omap-timer.8", "fck", &gpt8_fck, CK_243X),
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
- CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
+ CLK("omap-timer.9", "fck", &gpt9_fck, CK_243X),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
- CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
+ CLK("omap-timer.10", "fck", &gpt10_fck, CK_243X),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
- CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
+ CLK("omap-timer.11", "fck", &gpt11_fck, CK_243X),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
- CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
+ CLK("omap-timer.12", "fck", &gpt12_fck, CK_243X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
@@ -1993,6 +1993,42 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
+ CLK("omap-timer.1", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.2", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.3", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.4", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.5", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.6", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.7", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.8", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.9", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.10", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.11", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.12", "32k_ck", &func_32k_ck, CK_243X),
+ CLK("omap-timer.1", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.2", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.3", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.4", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.5", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.6", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.7", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.8", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.9", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.10", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.11", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.12", "sys_ck", &sys_ck, CK_243X),
+ CLK("omap-timer.1", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.2", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.3", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.4", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.5", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.6", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.7", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.8", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.9", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.10", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.11", "alt_ck", &alt_ck, CK_243X),
+ CLK("omap-timer.12", "alt_ck", &alt_ck, CK_243X),
};
/*
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index d85ecd5..41685be 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3273,8 +3273,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "modem_fck", &modem_fck, CK_343X),
CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
- CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
- CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
+ CLK("omap-timer.10", "fck", &gpt10_fck, CK_3XXX),
+ CLK("omap-timer.11", "fck", &gpt11_fck, CK_3XXX),
CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
@@ -3380,14 +3380,14 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
- CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
- CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
- CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
- CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
- CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
- CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
- CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
- CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
+ CLK("omap-timer.2", "fck", &gpt2_fck, CK_3XXX),
+ CLK("omap-timer.3", "fck", &gpt3_fck, CK_3XXX),
+ CLK("omap-timer.4", "fck", &gpt4_fck, CK_3XXX),
+ CLK("omap-timer.5", "fck", &gpt5_fck, CK_3XXX),
+ CLK("omap-timer.6", "fck", &gpt6_fck, CK_3XXX),
+ CLK("omap-timer.7", "fck", &gpt7_fck, CK_3XXX),
+ CLK("omap-timer.8", "fck", &gpt8_fck, CK_3XXX),
+ CLK("omap-timer.9", "fck", &gpt9_fck, CK_3XXX),
CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
@@ -3428,7 +3428,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
- CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
+ CLK("omap-timer.12", "fck", &gpt12_fck, CK_3XXX),
CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
@@ -3441,6 +3441,30 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
+ CLK("omap-timer.1", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.2", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.4", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.5", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.6", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.7", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.8", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.9", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.10", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.11", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.12", "32k_ck", &omap_32k_fck, CK_3XXX),
+ CLK("omap-timer.1", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.2", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.3", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.4", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.5", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.6", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.7", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.8", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.9", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.10", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.11", "sys_ck", &sys_ck, CK_3XXX),
+ CLK("omap-timer.12", "sys_ck", &sys_ck, CK_3XXX),
};
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 1599836..d081c10 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -2922,16 +2922,16 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
- CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
- CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
- CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
- CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
- CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
- CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
- CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
- CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
- CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
- CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
+ CLK("omap-timer.10", "fck", &timer10_fck, CK_443X),
+ CLK("omap-timer.11", "fck", &timer11_fck, CK_443X),
+ CLK("omap-timer.2", "fck", &timer2_fck, CK_443X),
+ CLK("omap-timer.3", "fck", &timer3_fck, CK_443X),
+ CLK("omap-timer.4", "fck", &timer4_fck, CK_443X),
+ CLK("omap-timer.5", "fck", &timer5_fck, CK_443X),
+ CLK("omap-timer.6", "fck", &timer6_fck, CK_443X),
+ CLK("omap-timer.7", "fck", &timer7_fck, CK_443X),
+ CLK("omap-timer.8", "fck", &timer8_fck, CK_443X),
+ CLK("omap-timer.9", "fck", &timer9_fck, CK_443X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
@@ -2997,6 +2997,28 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
+ CLK("omap-timer.1", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.2", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.3", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.4", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.5", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.6", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.7", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.8", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.9", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.10", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.11", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap-timer.1", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap-timer.2", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap-timer.3", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap-timer.4", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap-timer.9", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap-timer.10", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap-timer.11", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap-timer.5", "sys_ck", &syc_clk_div_ck, CK_443X),
+ CLK("omap-timer.6", "sys_ck", &syc_clk_div_ck, CK_443X),
+ CLK("omap-timer.7", "sys_ck", &syc_clk_div_ck, CK_443X),
+ CLK("omap-timer.8", "sys_ck", &syc_clk_div_ck, CK_443X),
};
int __init omap4xxx_clk_init(void)
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod
2010-11-20 2:39 ` [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 3/14] OMAP2420: dmtimer: add hwmod database Tarun Kanti DebBarma
2010-11-23 14:48 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Cousson, Benoit
2010-11-22 17:32 ` [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes Cousson, Benoit
1 sibling, 2 replies; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Tarun Kanti DebBarma, Thara Gopinath
(1) Add new fields and data structures to support dmtimer conversion
to platform driver.
(2) Constants to identify IP revision so that Highlander IP in OMAP 4
can be distinguished.
(3) field to identify OMAP4 abe timers.
(4) Interface function to support early boot.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Thara Gopinath <thara@ti.com>
---
arch/arm/mach-omap2/dmtimer.h | 32 +++++++++++++++++++++++++++++
arch/arm/plat-omap/dmtimer.c | 8 +++++++
arch/arm/plat-omap/include/plat/dmtimer.h | 19 +++++++++++++++++
3 files changed, 59 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/dmtimer.h
diff --git a/arch/arm/mach-omap2/dmtimer.h b/arch/arm/mach-omap2/dmtimer.h
new file mode 100644
index 0000000..4d4493b
--- /dev/null
+++ b/arch/arm/mach-omap2/dmtimer.h
@@ -0,0 +1,32 @@
+/**
+ * OMAP Dual-Mode Timers - early initialization interface
+ *
+ * function interface called first to start dmtimer early initialization.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_DMTIMER_H
+#define __ASM_ARCH_DMTIMER_H
+
+/*
+ * dmtimer is required during early part of boot sequence even before
+ * device model and pm_runtime if fully up and running. this function
+ * provides hook to omap2_init_common_hw() which is triggered from
+ * start_kernel()->init_irq() of kernel initialization sequence.
+ */
+void __init omap2_dm_timer_early_init(void);
+
+#endif
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 1d706cf..10daa9d 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -3,6 +3,12 @@
*
* OMAP Dual-Mode Timers
*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Thara Gopinath <thara@ti.com>
+ *
* Copyright (C) 2005 Nokia Corporation
* OMAP2 support by Juha Yrjola
* API improvements and OMAP2 clock framework support by Timo Teras
@@ -151,6 +157,7 @@
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
struct omap_dm_timer {
+ int id;
unsigned long phys_base;
int irq;
#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -160,6 +167,7 @@ struct omap_dm_timer {
unsigned reserved:1;
unsigned enabled:1;
unsigned posted:1;
+ struct platform_device *pdev;
};
static int dm_timer_count;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index dfa3aff..2bb837e 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -3,6 +3,11 @@
*
* OMAP Dual-Mode Timers
*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ * Platform device conversion and hwmod support.
+ *
* Copyright (C) 2005 Nokia Corporation
* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
* PWM and clock framwork support by Timo Teras.
@@ -29,6 +34,8 @@
#ifndef __ASM_ARCH_DMTIMER_H
#define __ASM_ARCH_DMTIMER_H
+#include <linux/platform_device.h>
+
/* clock sources */
#define OMAP_TIMER_SRC_SYS_CLK 0x00
#define OMAP_TIMER_SRC_32_KHZ 0x01
@@ -44,11 +51,23 @@
#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
+/* timer ip constants */
+#define OMAP_TIMER_IP_VERSION_1 0x1
+#define OMAP_TIMER_IP_VERSION_2 0x2
+
struct omap_dm_timer;
extern struct omap_dm_timer *gptimer_wakeup;
extern struct sys_timer omap_timer;
struct clk;
+struct dmtimer_platform_data {
+ int (*set_timer_src) (struct platform_device *pdev, int source);
+ int timer_ip_type;
+ u8 func_offst;
+ u8 intr_offst;
+ u32 is_early_init:1;
+};
+
int omap_dm_timer_init(void);
struct omap_dm_timer *omap_dm_timer_request(void);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 3/14] OMAP2420: dmtimer: add hwmod database
2010-11-20 2:39 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 4/14] OMAP2430: " Tarun Kanti DebBarma
2010-11-23 14:48 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Cousson, Benoit
1 sibling, 1 reply; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Thara Gopinath, Tarun Kanti DebBarma
From: Thara Gopinath <thara@ti.com>
Add hwmod database for OMAP2420.
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 633 ++++++++++++++++++++++++++++
1 files changed, 633 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a1a3dd6..2babe70 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -18,6 +18,7 @@
#include <plat/serial.h>
#include <plat/i2c.h>
#include <plat/omap24xx.h>
+#include <plat/dmtimer.h>
#include "omap_hwmod_common_data.h"
@@ -273,6 +274,626 @@ static struct omap_hwmod omap2420_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .clockact = 0x2,
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap2420_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2420_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER1, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+ {
+ .pa_start = 0x48028000,
+ .pa_end = 0x48028000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+ .master = &omap2420_l4_wkup_hwmod,
+ .slave = &omap2420_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap2420_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
+ &omap2420_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2420_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = omap2420_timer1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT1_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2420_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER2, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
+ {
+ .pa_start = 0x4802a000,
+ .pa_end = 0x4802a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer2 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = omap2420_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
+ &omap2420_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2420_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = omap2420_timer2_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT2_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer3 */
+static struct omap_hwmod omap2420_timer3_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER3, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
+ {
+ .pa_start = 0x48078000,
+ .pa_end = 0x48078000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer3 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = omap2420_timer3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
+ &omap2420_l4_core__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap2420_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = omap2420_timer3_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT3_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer4 */
+static struct omap_hwmod omap2420_timer4_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER4, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
+ {
+ .pa_start = 0x4807a000,
+ .pa_end = 0x4807a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer4 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = omap2420_timer4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
+ &omap2420_l4_core__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap2420_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = omap2420_timer4_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT4_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer5 */
+static struct omap_hwmod omap2420_timer5_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER5, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
+ {
+ .pa_start = 0x4807c000,
+ .pa_end = 0x4807c000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer5 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = omap2420_timer5_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
+ &omap2420_l4_core__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap2420_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = omap2420_timer5_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT5_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+
+/* timer6 */
+static struct omap_hwmod omap2420_timer6_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER6, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
+ {
+ .pa_start = 0x4807e000,
+ .pa_end = 0x4807e000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer6 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = omap2420_timer6_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
+ &omap2420_l4_core__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap2420_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = omap2420_timer6_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT6_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer7 */
+static struct omap_hwmod omap2420_timer7_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER7, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
+ {
+ .pa_start = 0x48080000,
+ .pa_end = 0x48080000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer7 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = omap2420_timer7_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
+ &omap2420_l4_core__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap2420_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = omap2420_timer7_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT7_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer7_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer8 */
+static struct omap_hwmod omap2420_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER8, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
+ {
+ .pa_start = 0x48082000,
+ .pa_end = 0x48082000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer8 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer8_hwmod,
+ .clk = "gpt8_ick",
+ .addr = omap2420_timer8_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
+ &omap2420_l4_core__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap2420_timer8_hwmod = {
+ .name = "timer8",
+ .mpu_irqs = omap2420_timer8_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT8_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer8_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer9 */
+static struct omap_hwmod omap2420_timer9_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER9, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
+ {
+ .pa_start = 0x48084000,
+ .pa_end = 0x48084000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer9 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer9_hwmod,
+ .clk = "gpt9_ick",
+ .addr = omap2420_timer9_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
+ &omap2420_l4_core__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap2420_timer9_hwmod = {
+ .name = "timer9",
+ .mpu_irqs = omap2420_timer9_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT9_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer9_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer10 */
+static struct omap_hwmod omap2420_timer10_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER10, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x48086000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer10_hwmod,
+ .clk = "gpt10_ick",
+ .addr = omap2420_timer10_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
+ &omap2420_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap2420_timer10_hwmod = {
+ .name = "timer10",
+ .mpu_irqs = omap2420_timer10_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT10_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer10_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer11 */
+static struct omap_hwmod omap2420_timer11_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER11, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x48088000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer11_hwmod,
+ .clk = "gpt11_ick",
+ .addr = omap2420_timer11_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
+ &omap2420_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap2420_timer11_hwmod = {
+ .name = "timer11",
+ .mpu_irqs = omap2420_timer11_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT11_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer11_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer12 */
+static struct omap_hwmod omap2420_timer12_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER12, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
+ {
+ .pa_start = 0x4808a000,
+ .pa_end = 0x4808a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_timer12_hwmod,
+ .clk = "gpt12_ick",
+ .addr = omap2420_timer12_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
+ &omap2420_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap2420_timer12_hwmod = {
+ .name = "timer12",
+ .mpu_irqs = omap2420_timer12_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
+ .main_clk = "gpt12_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT12_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer12_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
+ .class = &omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
{
@@ -563,6 +1184,18 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
&omap2420_l4_wkup_hwmod,
&omap2420_mpu_hwmod,
&omap2420_iva_hwmod,
+ &omap2420_timer1_hwmod,
+ &omap2420_timer2_hwmod,
+ &omap2420_timer3_hwmod,
+ &omap2420_timer4_hwmod,
+ &omap2420_timer5_hwmod,
+ &omap2420_timer6_hwmod,
+ &omap2420_timer7_hwmod,
+ &omap2420_timer8_hwmod,
+ &omap2420_timer9_hwmod,
+ &omap2420_timer10_hwmod,
+ &omap2420_timer11_hwmod,
+ &omap2420_timer12_hwmod,
&omap2420_wd_timer2_hwmod,
&omap2420_uart1_hwmod,
&omap2420_uart2_hwmod,
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 4/14] OMAP2430: dmtimer: add hwmod database
2010-11-20 2:39 ` [PATCHv4 3/14] OMAP2420: dmtimer: add hwmod database Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 5/14] OMAP3: " Tarun Kanti DebBarma
0 siblings, 1 reply; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Thara Gopinath, Tarun Kanti DebBarma
From: Thara Gopinath <thara@ti.com>
Add hwmod database for OMAP2430.
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 632 ++++++++++++++++++++++++++++
1 files changed, 632 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 7cf0d3a..214111a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,6 +18,7 @@
#include <plat/serial.h>
#include <plat/i2c.h>
#include <plat/omap24xx.h>
+#include <plat/dmtimer.h>
#include "omap_hwmod_common_data.h"
@@ -271,6 +272,625 @@ static struct omap_hwmod omap2430_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .clockact = 0x2,
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap2430_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2430_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER1, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+ {
+ .pa_start = 0x49018000,
+ .pa_end = 0x49018000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+ .master = &omap2430_l4_wkup_hwmod,
+ .slave = &omap2430_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap2430_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
+ &omap2430_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2430_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = omap2430_timer1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT1_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2430_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER2, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
+ {
+ .pa_start = 0x4802a000,
+ .pa_end = 0x4802a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = omap2430_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
+ &omap2430_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2430_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = omap2430_timer2_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT2_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer3 */
+static struct omap_hwmod omap2430_timer3_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER3, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
+ {
+ .pa_start = 0x48078000,
+ .pa_end = 0x48078000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = omap2430_timer3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
+ &omap2430_l4_core__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap2430_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = omap2430_timer3_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT3_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer4 */
+static struct omap_hwmod omap2430_timer4_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER4, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
+ {
+ .pa_start = 0x4807a000,
+ .pa_end = 0x4807a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = omap2430_timer4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
+ &omap2430_l4_core__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap2430_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = omap2430_timer4_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT4_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer5 */
+static struct omap_hwmod omap2430_timer5_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER5, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
+ {
+ .pa_start = 0x4807c000,
+ .pa_end = 0x4807c000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = omap2430_timer5_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
+ &omap2430_l4_core__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap2430_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = omap2430_timer5_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT5_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer6 */
+static struct omap_hwmod omap2430_timer6_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER6, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
+ {
+ .pa_start = 0x4807e000,
+ .pa_end = 0x4807e000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer6 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = omap2430_timer6_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
+ &omap2430_l4_core__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap2430_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = omap2430_timer6_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT6_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer7 */
+static struct omap_hwmod omap2430_timer7_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER7, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
+ {
+ .pa_start = 0x48080000,
+ .pa_end = 0x48080000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer7 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = omap2430_timer7_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
+ &omap2430_l4_core__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap2430_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = omap2430_timer7_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT7_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer7_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer8 */
+static struct omap_hwmod omap2430_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER8, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
+ {
+ .pa_start = 0x48082000,
+ .pa_end = 0x48082000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer8 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer8_hwmod,
+ .clk = "gpt8_ick",
+ .addr = omap2430_timer8_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
+ &omap2430_l4_core__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap2430_timer8_hwmod = {
+ .name = "timer8",
+ .mpu_irqs = omap2430_timer8_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT8_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer8_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer9 */
+static struct omap_hwmod omap2430_timer9_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER9, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
+ {
+ .pa_start = 0x48084000,
+ .pa_end = 0x48084000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer9 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer9_hwmod,
+ .clk = "gpt9_ick",
+ .addr = omap2430_timer9_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
+ &omap2430_l4_core__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap2430_timer9_hwmod = {
+ .name = "timer9",
+ .mpu_irqs = omap2430_timer9_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT9_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer9_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer10 */
+static struct omap_hwmod omap2430_timer10_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER10, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x48086000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer10_hwmod,
+ .clk = "gpt10_ick",
+ .addr = omap2430_timer10_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
+ &omap2430_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap2430_timer10_hwmod = {
+ .name = "timer10",
+ .mpu_irqs = omap2430_timer10_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT10_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer10_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer11 */
+static struct omap_hwmod omap2430_timer11_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER11, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x48088000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer11_hwmod,
+ .clk = "gpt11_ick",
+ .addr = omap2430_timer11_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
+ &omap2430_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap2430_timer11_hwmod = {
+ .name = "timer11",
+ .mpu_irqs = omap2430_timer11_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT11_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer11_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer12 */
+static struct omap_hwmod omap2430_timer12_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER12, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
+ {
+ .pa_start = 0x4808a000,
+ .pa_end = 0x4808a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_timer12_hwmod,
+ .clk = "gpt12_ick",
+ .addr = omap2430_timer12_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
+ &omap2430_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap2430_timer12_hwmod = {
+ .name = "timer12",
+ .mpu_irqs = omap2430_timer12_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
+ .main_clk = "gpt12_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT12_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer12_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
+ .class = &omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
{
@@ -575,6 +1195,18 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
&omap2430_l4_wkup_hwmod,
&omap2430_mpu_hwmod,
&omap2430_iva_hwmod,
+ &omap2430_timer1_hwmod,
+ &omap2430_timer2_hwmod,
+ &omap2430_timer3_hwmod,
+ &omap2430_timer4_hwmod,
+ &omap2430_timer5_hwmod,
+ &omap2430_timer6_hwmod,
+ &omap2430_timer7_hwmod,
+ &omap2430_timer8_hwmod,
+ &omap2430_timer9_hwmod,
+ &omap2430_timer10_hwmod,
+ &omap2430_timer11_hwmod,
+ &omap2430_timer12_hwmod,
&omap2430_wd_timer2_hwmod,
&omap2430_uart1_hwmod,
&omap2430_uart2_hwmod,
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 5/14] OMAP3: dmtimer: add hwmod database
2010-11-20 2:39 ` [PATCHv4 4/14] OMAP2430: " Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 6/14] OMAP4: " Tarun Kanti DebBarma
0 siblings, 1 reply; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Thara Gopinath, Tarun Kanti DebBarma
From: Thara Gopinath <thara@ti.com>
Add hwmod database for OMAP3.
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 674 ++++++++++++++++++++++++++++
1 files changed, 674 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index a8bed84..20e4c9d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -21,6 +21,7 @@
#include <plat/l4_3xxx.h>
#include <plat/i2c.h>
#include <plat/omap34xx.h>
+#include <plat/dmtimer.h>
#include "omap_hwmod_common_data.h"
@@ -367,6 +368,668 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
+/* timer class */
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .clockact = 0x2,
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap3xxx_timer_1ms_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap3xxx_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap3xxx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER1, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+ {
+ .pa_start = 0x48318000,
+ .pa_end = 0x48318000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+ .master = &omap3xxx_l4_wkup_hwmod,
+ .slave = &omap3xxx_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap3xxx_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer1_masters[] = {
+ &omap3xxx_l4_wkup__timer1,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
+ &omap3xxx_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap3xxx_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = omap3xxx_timer1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT1_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer1_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer1_masters),
+ .slaves = omap3xxx_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
+ .class = &omap3xxx_timer_1ms_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap3xxx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER2, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+ {
+ .pa_start = 0x49032000,
+ .pa_end = 0x49032000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = omap3xxx_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer2_masters[] = {
+ &omap3xxx_l4_per__timer2,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
+ &omap3xxx_l4_per__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap3xxx_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = omap3xxx_timer2_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT2_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT2_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer2_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer2_masters),
+ .slaves = omap3xxx_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
+ .class = &omap3xxx_timer_1ms_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer3 */
+static struct omap_hwmod omap3xxx_timer3_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER3, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+ {
+ .pa_start = 0x49034000,
+ .pa_end = 0x49034000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = omap3xxx_timer3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer3_masters[] = {
+ &omap3xxx_l4_per__timer3,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
+ &omap3xxx_l4_per__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap3xxx_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = omap3xxx_timer3_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT3_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT3_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer3_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer3_masters),
+ .slaves = omap3xxx_timer3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
+ .class = &omap3xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer4 */
+static struct omap_hwmod omap3xxx_timer4_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER4, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+ {
+ .pa_start = 0x49036000,
+ .pa_end = 0x49036000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = omap3xxx_timer4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer4_masters[] = {
+ &omap3xxx_l4_per__timer4,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
+ &omap3xxx_l4_per__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap3xxx_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = omap3xxx_timer4_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT4_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT4_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer4_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer4_masters),
+ .slaves = omap3xxx_timer4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
+ .class = &omap3xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer5 */
+static struct omap_hwmod omap3xxx_timer5_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER5, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+ {
+ .pa_start = 0x49038000,
+ .pa_end = 0x49038000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = omap3xxx_timer5_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer5_masters[] = {
+ &omap3xxx_l4_per__timer5,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
+ &omap3xxx_l4_per__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap3xxx_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = omap3xxx_timer5_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT5_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT5_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer5_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer5_masters),
+ .slaves = omap3xxx_timer5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
+ .class = &omap3xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer6 */
+static struct omap_hwmod omap3xxx_timer6_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER6, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+ {
+ .pa_start = 0x4903A000,
+ .pa_end = 0x4903A000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer6 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = omap3xxx_timer6_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer6_masters[] = {
+ &omap3xxx_l4_per__timer6,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
+ &omap3xxx_l4_per__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap3xxx_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = omap3xxx_timer6_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT6_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT6_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer6_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer6_masters),
+ .slaves = omap3xxx_timer6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
+ .class = &omap3xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer7 */
+static struct omap_hwmod omap3xxx_timer7_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER7, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+ {
+ .pa_start = 0x4903C000,
+ .pa_end = 0x4903C000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer7 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = omap3xxx_timer7_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer7_masters[] = {
+ &omap3xxx_l4_per__timer7,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
+ &omap3xxx_l4_per__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap3xxx_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = omap3xxx_timer7_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT7_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT7_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer7_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer7_masters),
+ .slaves = omap3xxx_timer7_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
+ .class = &omap3xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer8 */
+static struct omap_hwmod omap3xxx_timer8_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER8, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+ {
+ .pa_start = 0x4903E000,
+ .pa_end = 0x4903E000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer8 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer8_hwmod,
+ .clk = "gpt8_ick",
+ .addr = omap3xxx_timer8_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer8_masters[] = {
+ &omap3xxx_l4_per__timer8,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
+ &omap3xxx_l4_per__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap3xxx_timer8_hwmod = {
+ .name = "timer8",
+ .mpu_irqs = omap3xxx_timer8_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT8_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT8_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer8_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer8_masters),
+ .slaves = omap3xxx_timer8_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
+ .class = &omap3xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer9 */
+static struct omap_hwmod omap3xxx_timer9_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER9, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+ {
+ .pa_start = 0x49040000,
+ .pa_end = 0x49040000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer9_hwmod,
+ .clk = "gpt9_ick",
+ .addr = omap3xxx_timer9_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer9_masters[] = {
+ &omap3xxx_l4_per__timer9,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
+ &omap3xxx_l4_per__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap3xxx_timer9_hwmod = {
+ .name = "timer9",
+ .mpu_irqs = omap3xxx_timer9_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT9_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_GPT9_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer9_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer9_masters),
+ .slaves = omap3xxx_timer9_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
+ .class = &omap3xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer10 */
+static struct omap_hwmod omap3xxx_timer10_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER10, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x48086000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_timer10_hwmod,
+ .clk = "gpt10_ick",
+ .addr = omap3xxx_timer10_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer10_masters[] = {
+ &omap3xxx_l4_core__timer10,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
+ &omap3xxx_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap3xxx_timer10_hwmod = {
+ .name = "timer10",
+ .mpu_irqs = omap3xxx_timer10_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT10_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer10_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer10_masters),
+ .slaves = omap3xxx_timer10_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
+ .class = &omap3xxx_timer_1ms_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer11 */
+static struct omap_hwmod omap3xxx_timer11_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
+ { .irq = INT_24XX_GPTIMER11, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x48088000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_timer11_hwmod,
+ .clk = "gpt11_ick",
+ .addr = omap3xxx_timer11_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer11_masters[] = {
+ &omap3xxx_l4_core__timer11,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
+ &omap3xxx_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap3xxx_timer11_hwmod = {
+ .name = "timer11",
+ .mpu_irqs = omap3xxx_timer11_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_GPT11_SHIFT,
+ },
+ },
+ .masters = omap3xxx_timer11_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_timer11_masters),
+ .slaves = omap3xxx_timer11_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
+ .class = &omap3xxx_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
{
@@ -746,6 +1409,17 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_l4_wkup_hwmod,
&omap3xxx_mpu_hwmod,
&omap3xxx_iva_hwmod,
+ &omap3xxx_timer1_hwmod,
+ &omap3xxx_timer2_hwmod,
+ &omap3xxx_timer3_hwmod,
+ &omap3xxx_timer4_hwmod,
+ &omap3xxx_timer5_hwmod,
+ &omap3xxx_timer6_hwmod,
+ &omap3xxx_timer7_hwmod,
+ &omap3xxx_timer8_hwmod,
+ &omap3xxx_timer9_hwmod,
+ &omap3xxx_timer10_hwmod,
+ &omap3xxx_timer11_hwmod,
&omap3xxx_wd_timer2_hwmod,
&omap3xxx_uart1_hwmod,
&omap3xxx_uart2_hwmod,
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 6/14] OMAP4: dmtimer: add hwmod database
2010-11-20 2:39 ` [PATCHv4 5/14] OMAP3: " Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Tarun Kanti DebBarma
2010-11-22 6:02 ` [PATCHv4 6/14] OMAP4: dmtimer: add hwmod database Varadarajan, Charulatha
0 siblings, 2 replies; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Cousson, Benoit, Tarun Kanti DebBarma
From: Cousson, Benoit <b-cousson@ti.com>
Add hwmod database for OMAP4.
Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 622 ++++++++++++++++++++++++++++
1 files changed, 622 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0d5c6eb..2845cec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,6 +22,7 @@
#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
+#include <plat/dmtimer.h>
#include "omap_hwmod_common_data.h"
@@ -685,6 +686,615 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
};
/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .clockact = 0x2,
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap44xx_timer_1ms_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap44xx_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_2,
+};
+
+/* timer1 */
+static struct omap_hwmod omap44xx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
+ { .irq = 37 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+ {
+ .pa_start = 0x4a318000,
+ .pa_end = 0x4a31807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_timer1_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+ &omap44xx_l4_wkup__timer1,
+};
+
+static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
+ .main_clk = "timer1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer2 */
+static struct omap_hwmod omap44xx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
+ { .irq = 38 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+ {
+ .pa_start = 0x48032000,
+ .pa_end = 0x4803207f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
+ &omap44xx_l4_per__timer2,
+};
+
+static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer3 */
+static struct omap_hwmod omap44xx_timer3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
+ { .irq = 39 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+ {
+ .pa_start = 0x48034000,
+ .pa_end = 0x4803407f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
+ &omap44xx_l4_per__timer3,
+};
+
+static struct omap_hwmod omap44xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer3_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
+ .main_clk = "timer3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer4 */
+static struct omap_hwmod omap44xx_timer4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
+ { .irq = 40 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+ {
+ .pa_start = 0x48036000,
+ .pa_end = 0x4803607f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
+ &omap44xx_l4_per__timer4,
+};
+
+static struct omap_hwmod omap44xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer4_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer5 */
+static struct omap_hwmod omap44xx_timer5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
+ { .irq = 41 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+ {
+ .pa_start = 0x40138000,
+ .pa_end = 0x4013807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer5_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer5_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
+ {
+ .pa_start = 0x49038000,
+ .pa_end = 0x4903807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer5 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer5_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer5_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+/* timer5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
+ &omap44xx_l4_abe__timer5,
+ &omap44xx_l4_abe__timer5_dma,
+};
+
+static struct omap_hwmod omap44xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer5_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer6 */
+static struct omap_hwmod omap44xx_timer6_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
+ { .irq = 42 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+ {
+ .pa_start = 0x4013a000,
+ .pa_end = 0x4013a07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer6_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer6_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
+ {
+ .pa_start = 0x4903a000,
+ .pa_end = 0x4903a07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer6 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer6_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer6_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+/* timer6 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
+ &omap44xx_l4_abe__timer6,
+ &omap44xx_l4_abe__timer6_dma,
+};
+
+static struct omap_hwmod omap44xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer6_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer7 */
+static struct omap_hwmod omap44xx_timer7_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
+ { .irq = 43 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+ {
+ .pa_start = 0x4013c000,
+ .pa_end = 0x4013c07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer7_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer7_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
+ {
+ .pa_start = 0x4903c000,
+ .pa_end = 0x4903c07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer7 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer7_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer7_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+/* timer7 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
+ &omap44xx_l4_abe__timer7,
+ &omap44xx_l4_abe__timer7_dma,
+};
+
+static struct omap_hwmod omap44xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer7_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer7_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer8 */
+static struct omap_hwmod omap44xx_timer8_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
+ { .irq = 44 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+ {
+ .pa_start = 0x4013e000,
+ .pa_end = 0x4013e07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer8_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer8_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
+ {
+ .pa_start = 0x4903e000,
+ .pa_end = 0x4903e07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer8 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer8_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer8_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+/* timer8 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
+ &omap44xx_l4_abe__timer8,
+ &omap44xx_l4_abe__timer8_dma,
+};
+
+static struct omap_hwmod omap44xx_timer8_hwmod = {
+ .name = "timer8",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer8_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
+ .main_clk = "timer8_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer8_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer9 */
+static struct omap_hwmod omap44xx_timer9_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
+ { .irq = 45 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+ {
+ .pa_start = 0x4803e000,
+ .pa_end = 0x4803e07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer9_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer9_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
+ &omap44xx_l4_per__timer9,
+};
+
+static struct omap_hwmod omap44xx_timer9_hwmod = {
+ .name = "timer9",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer9_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
+ .main_clk = "timer9_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer9_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer10 */
+static struct omap_hwmod omap44xx_timer10_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
+ { .irq = 46 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x4808607f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer10_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer10_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
+ &omap44xx_l4_per__timer10,
+};
+
+static struct omap_hwmod omap44xx_timer10_hwmod = {
+ .name = "timer10",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer10_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
+ .main_clk = "timer10_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer10_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer11 */
+static struct omap_hwmod omap44xx_timer11_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
+ { .irq = 47 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x4808807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer11_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer11_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
+ &omap44xx_l4_per__timer11,
+};
+
+static struct omap_hwmod omap44xx_timer11_hwmod = {
+ .name = "timer11",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer11_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
+ .main_clk = "timer11_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer11_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
@@ -1068,6 +1678,18 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* mpu class */
&omap44xx_mpu_hwmod,
+ /* timer class */
+ &omap44xx_timer1_hwmod,
+ &omap44xx_timer2_hwmod,
+ &omap44xx_timer3_hwmod,
+ &omap44xx_timer4_hwmod,
+ &omap44xx_timer5_hwmod,
+ &omap44xx_timer6_hwmod,
+ &omap44xx_timer7_hwmod,
+ &omap44xx_timer8_hwmod,
+ &omap44xx_timer9_hwmod,
+ &omap44xx_timer10_hwmod,
+ &omap44xx_timer11_hwmod,
/* wd_timer class */
&omap44xx_wd_timer2_hwmod,
&omap44xx_wd_timer3_hwmod,
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array
2010-11-20 2:39 ` [PATCHv4 6/14] OMAP4: " Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Tarun Kanti DebBarma
2010-11-23 15:22 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Cousson, Benoit
2010-11-22 6:02 ` [PATCHv4 6/14] OMAP4: dmtimer: add hwmod database Varadarajan, Charulatha
1 sibling, 2 replies; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Tarun Kanti DebBarma
Convert dmtimers static array in functions into list structure.
Please note that the static arrays will be completely removed
in subsequent patches when dmtimer is converted to platform driver.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/plat-omap/dmtimer.c | 67 +++++++++++++++++++++++-------------------
1 files changed, 37 insertions(+), 30 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 10daa9d..124fd21 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -168,6 +168,7 @@ struct omap_dm_timer {
unsigned enabled:1;
unsigned posted:1;
struct platform_device *pdev;
+ struct list_head node;
};
static int dm_timer_count;
@@ -290,7 +291,8 @@ static struct omap_dm_timer *dm_timers;
static const char **dm_source_names;
static struct clk **dm_source_clocks;
-static spinlock_t dm_timer_lock;
+static LIST_HEAD(omap_timer_list);
+static DEFINE_SPINLOCK(dm_timer_lock);
/*
* Reads timer registers in posted and non-posted mode. The posted mode bit
@@ -340,7 +342,7 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
{
u32 l;
- if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
+ if (!cpu_class_is_omap2() || timer->id != 1) {
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
omap_dm_timer_wait_for_reset(timer);
}
@@ -371,23 +373,24 @@ static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
struct omap_dm_timer *omap_dm_timer_request(void)
{
- struct omap_dm_timer *timer = NULL;
+ struct omap_dm_timer *timer = NULL, *t;
unsigned long flags;
- int i;
spin_lock_irqsave(&dm_timer_lock, flags);
- for (i = 0; i < dm_timer_count; i++) {
- if (dm_timers[i].reserved)
+ list_for_each_entry(t, &omap_timer_list, node) {
+ if (t->reserved)
continue;
- timer = &dm_timers[i];
+ timer = t;
timer->reserved = 1;
break;
}
spin_unlock_irqrestore(&dm_timer_lock, flags);
- if (timer != NULL)
+ if (timer)
omap_dm_timer_prepare(timer);
+ else
+ pr_debug("%s: free timer not available.\n", __func__);
return timer;
}
@@ -395,23 +398,23 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request);
struct omap_dm_timer *omap_dm_timer_request_specific(int id)
{
- struct omap_dm_timer *timer;
+ struct omap_dm_timer *timer = NULL, *t;
unsigned long flags;
spin_lock_irqsave(&dm_timer_lock, flags);
- if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
- spin_unlock_irqrestore(&dm_timer_lock, flags);
- printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
- __FILE__, __LINE__, __func__, id);
- dump_stack();
- return NULL;
+ list_for_each_entry(t, &omap_timer_list, node) {
+ if (t->id == id && !t->reserved) {
+ timer = t;
+ timer->reserved = 1;
+ break;
+ }
}
-
- timer = &dm_timers[id-1];
- timer->reserved = 1;
spin_unlock_irqrestore(&dm_timer_lock, flags);
- omap_dm_timer_prepare(timer);
+ if (timer)
+ omap_dm_timer_prepare(timer);
+ else
+ pr_debug("%s: timer%d not available.\n", __func__, id);
return timer;
}
@@ -474,24 +477,29 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
*/
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{
- int i;
+ int i = 0;
+ struct omap_dm_timer *timer = NULL;
+ unsigned long flags;
/* If ARMXOR cannot be idled this function call is unnecessary */
if (!(inputmask & (1 << 1)))
return inputmask;
/* If any active timer is using ARMXOR return modified mask */
- for (i = 0; i < dm_timer_count; i++) {
+ spin_lock_irqsave(&dm_timer_lock, flags);
+ list_for_each_entry(timer, &omap_timer_list, node) {
u32 l;
- l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
+ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (l & OMAP_TIMER_CTRL_ST) {
if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
inputmask &= ~(1 << 1);
else
inputmask &= ~(1 << 2);
}
+ i++;
}
+ spin_unlock_irqrestore(&dm_timer_lock, flags);
return inputmask;
}
@@ -722,13 +730,9 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
int omap_dm_timers_active(void)
{
- int i;
-
- for (i = 0; i < dm_timer_count; i++) {
- struct omap_dm_timer *timer;
-
- timer = &dm_timers[i];
+ struct omap_dm_timer *timer;
+ list_for_each_entry(timer, &omap_timer_list, node) {
if (!timer->enabled)
continue;
@@ -743,14 +747,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
int __init omap_dm_timer_init(void)
{
+ unsigned long flags;
struct omap_dm_timer *timer;
int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
return -ENODEV;
- spin_lock_init(&dm_timer_lock);
-
if (cpu_class_is_omap1()) {
dm_timers = omap1_dm_timers;
dm_timer_count = omap1_dm_timer_count;
@@ -795,6 +798,10 @@ int __init omap_dm_timer_init(void)
timer->fclk = clk_get(NULL, clk_name);
}
#endif
+ timer->id = i + 1; /* id starts from 1*/
+ spin_lock_irqsave(&dm_timer_lock, flags);
+ list_add_tail(&timer->node, &omap_timer_list);
+ spin_unlock_irqrestore(&dm_timer_lock, flags);
}
return 0;
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 8/14] OMAP: dmtimer: platform driver
2010-11-20 2:39 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 9/14] OMAP1: dmtimer: conversion to platform devices Tarun Kanti DebBarma
2010-11-22 7:13 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Varadarajan, Charulatha
2010-11-23 15:22 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Cousson, Benoit
1 sibling, 2 replies; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Thara Gopinath, Tarun Kanti DebBarma
From: Thara Gopinath <thara@ti.com>
Add dmtimer platform driver functions which include:
(1) platform driver initialization
(2) driver probe function
(3) driver remove function
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/plat-omap/dmtimer.c | 168 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 168 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 124fd21..3d7bd65 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,9 +43,11 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/slab.h>
#include <mach/hardware.h>
#include <plat/dmtimer.h>
#include <mach/irqs.h>
+#include <linux/err.h>
/* register offsets */
#define _OMAP_TIMER_ID_OFFSET 0x00
@@ -745,6 +747,172 @@ int omap_dm_timers_active(void)
}
EXPORT_SYMBOL_GPL(omap_dm_timers_active);
+/**
+ * omap_dm_timer_probe - probe function called for every registered device
+ * @pdev: pointer to current timer platform device
+ *
+ * called by driver framework at the end of device registration for all
+ * timer devices
+ */
+static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
+{
+ int ret;
+ unsigned long flags;
+ struct omap_dm_timer *timer;
+ struct resource *mem, *irq, *ioarea;
+ struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
+
+ dev_dbg(&pdev->dev, "%s:+\n", __func__);
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "%s: no platform data\n", __func__);
+ return -ENODEV;
+ }
+ /*
+ * early timers are already registered and in list.
+ * what we need to do during second phase of probe
+ * is to assign the newly allocated/configured pdev
+ * to already registered timer->pdev. we also call
+ * pm_runtime_enable() for each device because it
+ * could not be called during early boot because
+ * pm_runtime framework was not yet up and running.
+ */
+ spin_lock_irqsave(&dm_timer_lock, flags);
+ list_for_each_entry(timer, &omap_timer_list, node)
+ if (timer->id == pdev->id) {
+ timer->pdev = pdev;
+ spin_unlock_irqrestore(&dm_timer_lock, flags);
+ return 0;
+ }
+ spin_unlock_irqrestore(&dm_timer_lock, flags);
+
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (unlikely(!irq)) {
+ dev_err(&pdev->dev, "%s: no IRQ resource\n", __func__);
+ ret = -ENODEV;
+ goto err_free_pdev;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!mem)) {
+ dev_err(&pdev->dev, "%s: no memory resource\n", __func__);
+ ret = -ENODEV;
+ goto err_free_pdev;
+ }
+
+ ioarea = request_mem_region(mem->start, resource_size(mem),
+ pdev->name);
+ if (!ioarea) {
+ dev_err(&pdev->dev, "%s: region already claimed\n", __func__);
+ ret = -EBUSY;
+ goto err_free_pdev;
+ }
+
+ timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
+ if (!timer) {
+ dev_err(&pdev->dev, "%s: no memory for omap_dm_timer\n",
+ __func__);
+ ret = -ENOMEM;
+ goto err_release_ioregion;
+ }
+
+ timer->io_base = ioremap(mem->start, resource_size(mem));
+ if (!timer->io_base) {
+ dev_err(&pdev->dev, "%s: ioremap failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_mem;
+ }
+
+ timer->fclk = clk_get(&pdev->dev, "fck");
+ if (IS_ERR_OR_NULL(timer->fclk)) {
+ dev_dbg(&pdev->dev, "%s:%d: clk_get() FAILED\n",
+ __func__, __LINE__);
+ ret = -EINVAL;
+ goto err_free_mem;
+ }
+ timer->irq = irq->start;
+ timer->pdev = pdev;
+ timer->id = pdev->id;
+ timer->reserved = 0;
+
+ /* add the timer element to the list */
+ spin_lock_irqsave(&dm_timer_lock, flags);
+ list_add_tail(&timer->node, &omap_timer_list);
+ spin_unlock_irqrestore(&dm_timer_lock, flags);
+
+ dev_dbg(&pdev->dev, " bound to its driver\n");
+
+ return 0;
+
+err_free_mem:
+ kfree(timer);
+
+err_release_ioregion:
+ release_mem_region(mem->start, resource_size(mem));
+
+err_free_pdev:
+ platform_device_del(pdev);
+
+ return ret;
+}
+
+/**
+ * omap_dm_timer_remove - cleanup a registered timer device
+ * @pdev: pointer to current timer platform device
+ *
+ * called by driver framework whenever a timer device is unregistered.
+ * it addition to freeing platform resources it also deletes the timer
+ * entry from the local list.
+ */
+static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
+{
+ struct omap_dm_timer *timer, *tmp;
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ spin_lock_irqsave(&dm_timer_lock, flags);
+ list_for_each_entry_safe(timer, tmp, &omap_timer_list, node) {
+ if (timer->id == pdev->id) {
+ clk_put(timer->fclk);
+ platform_device_del(timer->pdev);
+ list_del(&timer->node);
+ kfree(timer);
+ ret = 0;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&dm_timer_lock, flags);
+
+ return ret;
+}
+
+static struct platform_driver omap_dmtimer_driver = {
+ .probe = omap_dm_timer_probe,
+ .remove = omap_dm_timer_remove,
+ .driver = {
+ .name = "omap-timer",
+ },
+};
+
+static int __init omap_dmtimer_driver_init(void)
+{
+ return platform_driver_register(&omap_dmtimer_driver);
+}
+
+static void __exit omap_dmtimer_driver_exit(void)
+{
+ platform_driver_unregister(&omap_dmtimer_driver);
+}
+
+early_platform_init("earlytimer", &omap_dmtimer_driver);
+module_init(omap_dmtimer_driver_init);
+module_exit(omap_dmtimer_driver_exit);
+
+MODULE_DESCRIPTION("OMAP DUAL MODE TIMER DRIVER");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
+
int __init omap_dm_timer_init(void)
{
unsigned long flags;
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 9/14] OMAP1: dmtimer: conversion to platform devices
2010-11-20 2:39 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 10/14] OMAP: dmtimer: access routines to interrupt registers Tarun Kanti DebBarma
2010-11-22 7:13 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Varadarajan, Charulatha
1 sibling, 1 reply; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Thara Gopinath, Tarun Kanti DebBarma
From: Thara Gopinath <thara@ti.com>
Convert OMAP1 dmtimers into a platform devices and then registers with
device model framework so that it can be bound to corresponding driver.
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/mach-omap1/Makefile | 2 +-
arch/arm/mach-omap1/dmtimer.c | 174 +++++++++++++++++++++++++++++++++++++++++
arch/arm/plat-omap/dmtimer.c | 44 +----------
3 files changed, 177 insertions(+), 43 deletions(-)
create mode 100644 arch/arm/mach-omap1/dmtimer.c
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index de3cc13..cb033ce 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -4,7 +4,7 @@
# Common support
obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o
-obj-y += clock.o clock_data.o opp_data.o
+obj-y += clock.o clock_data.o opp_data.o dmtimer.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap1/dmtimer.c b/arch/arm/mach-omap1/dmtimer.c
new file mode 100644
index 0000000..459c68e
--- /dev/null
+++ b/arch/arm/mach-omap1/dmtimer.c
@@ -0,0 +1,174 @@
+/**
+ * OMAP1 Dual-Mode Timers - platform device registration
+ *
+ * Contains first level initialization routines which internally
+ * generates timer device information and registers with linux
+ * device model. It also has low level function to chnage the timer
+ * input clock source.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#undef DEBUG
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <mach/irqs.h>
+#include <plat/dmtimer.h>
+#include <plat/omap_device.h>
+
+#define OMAP1610_GPTIMER1_BASE 0xfffb1400
+#define OMAP1610_GPTIMER2_BASE 0xfffb1c00
+#define OMAP1610_GPTIMER3_BASE 0xfffb2400
+#define OMAP1610_GPTIMER4_BASE 0xfffb2c00
+#define OMAP1610_GPTIMER5_BASE 0xfffb3400
+#define OMAP1610_GPTIMER6_BASE 0xfffb3c00
+#define OMAP1610_GPTIMER7_BASE 0xfffb7400
+#define OMAP1610_GPTIMER8_BASE 0xfffbd400
+
+#define OMAP1_DM_TIMER_COUNT 8
+
+static int omap1_dm_timer_set_src(struct platform_device *pdev,
+ int source)
+{
+ int n = (pdev->id) << 1;
+ u32 l;
+
+ l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
+ l |= source << n;
+ omap_writel(l, MOD_CONF_CTRL_1);
+
+ return 0;
+}
+
+int __init omap1_dmtimer_device_init(void)
+{
+ int i;
+ int ret;
+ struct dmtimer_platform_data *pdata;
+ struct platform_device *pdev;
+
+ pr_debug("%s:+\n", __func__);
+
+ if (!cpu_is_omap16xx())
+ return 0;
+
+ for (i = 1; i <= OMAP1_DM_TIMER_COUNT; i++) {
+ struct resource res[2];
+ u32 base, irq;
+
+ switch (i) {
+ case 1:
+ base = OMAP1610_GPTIMER1_BASE;
+ irq = INT_1610_GPTIMER1;
+ break;
+ case 2:
+ base = OMAP1610_GPTIMER2_BASE;
+ irq = INT_1610_GPTIMER2;
+ break;
+ case 3:
+ base = OMAP1610_GPTIMER3_BASE;
+ irq = INT_1610_GPTIMER3;
+ break;
+ case 4:
+ base = OMAP1610_GPTIMER4_BASE;
+ irq = INT_1610_GPTIMER4;
+ break;
+ case 5:
+ base = OMAP1610_GPTIMER5_BASE;
+ irq = INT_1610_GPTIMER5;
+ break;
+ case 6:
+ base = OMAP1610_GPTIMER6_BASE;
+ irq = INT_1610_GPTIMER6;
+ break;
+ case 7:
+ base = OMAP1610_GPTIMER7_BASE;
+ irq = INT_1610_GPTIMER7;
+ break;
+ case 8:
+ base = OMAP1610_GPTIMER8_BASE;
+ irq = INT_1610_GPTIMER8;
+ break;
+ default:
+ /* not supposd to reach here.
+ * this is to remove warning.
+ */
+ return -EINVAL;
+ }
+
+ pdev = platform_device_alloc("dmtimer", i);
+ if (!pdev) {
+ pr_err("%s: Unable to device alloc for dmtimer%d\n",
+ __func__, i);
+ return -ENOMEM;
+ }
+
+ memset(res, 0, 2 * sizeof(struct resource));
+ res[0].start = base;
+ res[0].end = base + 0xff;
+ res[0].flags = IORESOURCE_MEM;
+ res[1].start = res[1].end = irq;
+ res[1].flags = IORESOURCE_IRQ;
+ ret = platform_device_add_resources(pdev, res,
+ ARRAY_SIZE(res));
+ if (ret) {
+ pr_err("%s: Unable to add resources for %s.%d\n",
+ __func__, pdev->name, pdev->id);
+ goto err_free_pdev;
+ }
+
+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ pr_err("%s: Unable to allocate pdata for %s.%d\n",
+ __func__, pdev->name, pdev->id);
+ ret = -ENOMEM;
+ goto err_free_pdev;
+ }
+
+ pdata->set_timer_src = omap1_dm_timer_set_src;
+ pdata->is_early_init = 0;
+ pdata->timer_ip_type = OMAP_TIMER_IP_VERSION_1;
+ pdata->intr_reg_offset = 0;
+ pdata->func_reg_offset = 0;
+ ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+ if (ret) {
+ pr_err("%s: Unable to add platform data for %s.%d\n",
+ __func__, pdev->name, pdev->id);
+ goto err_free_pdata;
+ }
+ ret = platform_device_add(pdev);
+ if (ret) {
+ pr_err("%s: Unable to add platform device for %s.%d\n",
+ __func__, pdev->name, pdev->id);
+ goto err_free_pdata;
+ }
+
+ pr_info("%s.%d: registered\n", pdev->name, pdev->id);
+ }
+
+ return 0;
+
+err_free_pdata:
+ kfree(pdata);
+
+err_free_pdev:
+ platform_device_del(pdev);
+
+ return ret;
+}
+arch_initcall(omap1_dmtimer_device_init);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 3d7bd65..958acb8 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -175,25 +175,6 @@ struct omap_dm_timer {
static int dm_timer_count;
-#ifdef CONFIG_ARCH_OMAP1
-static struct omap_dm_timer omap1_dm_timers[] = {
- { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
- { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
- { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
- { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
- { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
- { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
- { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
- { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
-};
-
-static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
-
-#else
-#define omap1_dm_timers NULL
-#define omap1_dm_timer_count 0
-#endif /* CONFIG_ARCH_OMAP1 */
-
#ifdef CONFIG_ARCH_OMAP2
static struct omap_dm_timer omap2_dm_timers[] = {
{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
@@ -567,22 +548,6 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
}
EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
-#ifdef CONFIG_ARCH_OMAP1
-
-int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
-{
- int n = (timer - dm_timers) << 1;
- u32 l;
-
- l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
- l |= source << n;
- omap_writel(l, MOD_CONF_CTRL_1);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
-
-#else
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
{
@@ -605,7 +570,6 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
}
EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
-#endif
void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
unsigned int load)
@@ -919,14 +883,10 @@ int __init omap_dm_timer_init(void)
struct omap_dm_timer *timer;
int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
- if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
+ if (!cpu_class_is_omap2())
return -ENODEV;
- if (cpu_class_is_omap1()) {
- dm_timers = omap1_dm_timers;
- dm_timer_count = omap1_dm_timer_count;
- map_size = SZ_2K;
- } else if (cpu_is_omap24xx()) {
+ if (cpu_is_omap24xx()) {
dm_timers = omap2_dm_timers;
dm_timer_count = omap2_dm_timer_count;
dm_source_names = omap2_dm_source_names;
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 10/14] OMAP: dmtimer: access routines to interrupt registers
2010-11-20 2:39 ` [PATCHv4 9/14] OMAP1: dmtimer: conversion to platform devices Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Tarun Kanti DebBarma
0 siblings, 1 reply; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Tarun Kanti DebBarma, Partha Basak
Add low level read/write routines to access dmtimer interrupt
registers. These routines would be used later when we support
OMAP 4 new IP revision. When that happens the present read/write
routines would be used to access dmtimer functional registers
only.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Partha Basak <p-basak2@ti.com>
Reviewed-by: Cousson, Benoit <b-cousson@ti.com>
---
arch/arm/plat-omap/dmtimer.c | 51 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 958acb8..0479ab0 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -307,6 +307,57 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
writel(value, timer->io_base + (reg & 0xff));
}
+/**
+ * omap_dm_timer_read_intr_reg - read timer interrupt registers in posted
+ * and non-posted mode
+ * @timer: timer pointer over which read operation to perform
+ * @reg: lowest byte holds the register offset
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode write
+ * pending bit must be checked. Otherwise a read of a non completed write
+ * will produce an error.
+ */
+static inline
+u32 omap_dm_timer_read_intr_reg(struct omap_dm_timer *timer, u32 reg)
+{
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+
+ reg += pdata->intr_offst;
+ if (timer->posted)
+ while (readl(timer->io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
+ & 0xff)) & (reg >> WPSHIFT))
+ cpu_relax();
+ return readl(timer->io_base + (reg & 0xff));
+}
+
+/**
+ * omap_dm_timer_write_intr_reg - write timer interrupt registers in posted
+ * and non-posted mode
+ * @timer: timer pointer over which write operation is to perform
+ * @reg: lowest byte holds the register offset
+ * @value: data to write into the register
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode the write
+ * pending bit must be checked. Otherwise a write on a register which has a
+ * pending write will be lost.
+ */
+static inline
+void omap_dm_timer_write_intr_reg(struct omap_dm_timer *timer, u32 reg,
+ u32 value)
+{
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+
+ reg += pdata->intr_offst;
+ if (timer->posted)
+ while (readl(timer->io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
+ & 0xff)) & (reg >> WPSHIFT))
+ cpu_relax();
+ writel(value, timer->io_base + (reg & 0xff));
+}
+
+
static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
{
int c;
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
2010-11-20 2:39 ` [PATCHv4 10/14] OMAP: dmtimer: access routines to interrupt registers Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Tarun Kanti DebBarma
` (3 more replies)
0 siblings, 4 replies; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Thara Gopinath, Tarun Kanti DebBarma, Partha Basak
From: Thara Gopinath <thara@ti.com>
Add routines to converts dmtimers to platform devices. The device data
is obtained from hwmod database of respective platform and is registered
to device model after successful binding to driver. It also provides
provision to access timers during early boot when pm_runtime framework
is not completely up and running.
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[p-basak2@ti.com: pm_runtime logic]
Signed-off-by: Partha Basak <p-basak2@ti.com>
---
arch/arm/mach-omap2/Makefile | 2 +-
arch/arm/mach-omap2/dmtimer.c | 296 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 297 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/dmtimer.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ce7b1f0..148f4d7 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
- common.o
+ common.o dmtimer.o
omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
hwmod-common = omap_hwmod.o \
diff --git a/arch/arm/mach-omap2/dmtimer.c b/arch/arm/mach-omap2/dmtimer.c
new file mode 100644
index 0000000..b5951b1
--- /dev/null
+++ b/arch/arm/mach-omap2/dmtimer.c
@@ -0,0 +1,296 @@
+/**
+ * OMAP2PLUS Dual-Mode Timers - platform device registration
+ *
+ * Contains first level initialization routines which extracts timers
+ * information from hwmod database and registers with linux device model.
+ * It also has low level function to chnage the timer input clock source.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#undef DEBUG
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include <mach/irqs.h>
+#include <plat/dmtimer.h>
+#include <plat/powerdomain.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <linux/pm_runtime.h>
+
+static int early_timer_count __initdata = 1;
+
+/**
+ * omap2_dm_timer_set_src - change the timer input clock source
+ * @pdev: timer platform device pointer
+ * @timer_clk: current clock source
+ * @source: array index of parent clock source
+ */
+static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
+{
+ int ret;
+ struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
+ struct clk *fclk = clk_get(&pdev->dev, "fck");
+ struct clk *new_fclk;
+ char *fclk_name = "32k_ck"; /* default name */
+
+ switch(source) {
+ case OMAP_TIMER_SRC_SYS_CLK:
+ fclk_name = "sys_ck";
+ break;
+
+ case OMAP_TIMER_SRC_32_KHZ:
+ fclk_name = "32k_ck";
+ break;
+
+ case OMAP_TIMER_SRC_EXT_CLK:
+ if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_1) {
+ fclk_name = "alt_ck";
+ break;
+ }
+ dev_dbg(&pdev->dev, "%s:%d: invalid clk src.\n",
+ __func__, __LINE__);
+ return -EINVAL;
+ }
+
+
+ if (IS_ERR_OR_NULL(fclk)) {
+ dev_dbg(&pdev->dev, "%s:%d: clk_get() FAILED\n",
+ __func__, __LINE__);
+ return -EINVAL;
+ }
+
+ new_fclk = clk_get(&pdev->dev, fclk_name);
+ if (IS_ERR_OR_NULL(new_fclk)) {
+ dev_dbg(&pdev->dev, "%s:%d: clk_get() %s FAILED\n",
+ __func__, __LINE__, fclk_name);
+ clk_put(fclk);
+ return -EINVAL;
+ }
+
+ ret = clk_set_parent(fclk, new_fclk);
+ if (IS_ERR_VALUE(ret)) {
+ dev_dbg(&pdev->dev, "%s:clk_set_parent() to %s FAILED\n",
+ __func__, fclk_name);
+ ret = -EINVAL;
+ }
+
+ clk_put(new_fclk);
+ clk_put(fclk);
+
+ return ret;
+}
+
+struct omap_device_pm_latency omap2_dmtimer_latency[] = {
+ {
+ .deactivate_func = omap_device_idle_hwmods,
+ .activate_func = omap_device_enable_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+};
+
+/**
+ * omap_dm_timer_early_init - build and register early timer device
+ * with an associated timer hwmod
+ * @oh: timer hwmod pointer to be used to build timer device
+ * @user: parameter that can be passed from calling hwmod API
+ *
+ * early init is called in the last part of omap2_init_common_hw
+ * for each early timer class using omap_hwmod_for_each_by_class.
+ * it registers each of the timer devices present in the system.
+ * at the end of function call memory is allocated for omap_device
+ * and hwmod for early timer and the device is registered to the
+ * framework ready to be probed by the driver.
+ */
+static int __init omap2_timer_early_init(struct omap_hwmod *oh, void *user)
+{
+ int id;
+ int ret = 0;
+ char *name = "omap-timer";
+ struct dmtimer_platform_data *pdata;
+ struct omap_device *od;
+
+ pr_debug("%s:%s\n", __func__, oh->name);
+
+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ pr_err("%s: No memory for [%s]\n", __func__, oh->name);
+ return -ENOMEM;
+ }
+
+ pdata->is_early_init = 1;
+
+ /* hook clock set/get functions */
+ pdata->set_timer_src = omap2_dm_timer_set_src;
+
+ /* read timer ip version */
+ pdata->timer_ip_type = oh->class->rev;
+ if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
+ pdata->func_offst = 0x14;
+ pdata->intr_offst = 0x10;
+ } else {
+ pdata->func_offst = 0;
+ pdata->intr_offst = 0;
+ }
+
+ /*
+ * extract the id from name filed in hwmod database
+ * and use the same for constructing ids' for the
+ * timer devices. in a way, we are avoiding usage of
+ * static variable witin the function to do the same.
+ * CAUTION: we have to be careful and make sure the
+ * name in hwmod database does not change in which case
+ * we might either make corresponding change here or
+ * switch back static variable mechanism.
+ */
+ sscanf(oh->name, "timer%2d", &id);
+
+ od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
+ omap2_dmtimer_latency,
+ ARRAY_SIZE(omap2_dmtimer_latency), 1);
+
+ if (IS_ERR(od)) {
+ pr_err("%s: Cant build omap_device for %s:%s.\n",
+ __func__, name, oh->name);
+ ret = -EINVAL;
+ } else
+ early_timer_count++;
+ /*
+ * pdata can be freed because omap_device_build
+ * creates its own memory pool
+ */
+ kfree(pdata);
+
+ return ret;
+}
+
+/**
+ * omap2_dm_timer_init - build and register timer device with an
+ * associated timer hwmod
+ * @oh: timer hwmod pointer to be used to build timer device
+ * @user: parameter that can be passed from calling hwmod API
+ *
+ * called by omap_hwmod_for_each_by_class to register each of the timer
+ * devices present in the system. the number of timer devices is known
+ * by parsing through the hwmod database for a given class name. at the
+ * end of function call memory is allocated for omap_device and hwmod
+ * for timer and the device is registered to the framework ready to be
+ * proved by the driver.
+ */
+static int __init omap2_timer_init(struct omap_hwmod *oh, void *user)
+{
+ int id;
+ int ret = 0;
+ char *name = "omap-timer";
+ struct omap_device *od;
+ struct dmtimer_platform_data *pdata;
+
+ if (!oh) {
+ pr_err("%s:NULL hwmod pointer (oh)\n", __func__);
+ return -EINVAL;
+ }
+ pr_debug("%s:%s\n", __func__, oh->name);
+
+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ pr_err("%s:No memory for [%s]\n", __func__, oh->name);
+ return -ENOMEM;
+ }
+
+ pdata->is_early_init = 0;
+
+ /* hook clock set/get functions */
+ pdata->set_timer_src = omap2_dm_timer_set_src;
+
+ /* read timer ip version */
+ pdata->timer_ip_type = oh->class->rev;
+ if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
+ pdata->func_offst = 0x14;
+ pdata->intr_offst = 0x10;
+ } else {
+ pdata->func_offst = 0;
+ pdata->intr_offst = 0;
+ }
+
+ /*
+ * extract the id from name filed in hwmod database
+ * and use the same for constructing ids' for the
+ * timer devices. in a way, we are avoiding usage of
+ * static variable witin the function to do the same.
+ * CAUTION: we have to be careful and make sure the
+ * name in hwmod database does not change in which case
+ * we might either make corresponding change here or
+ * switch back static variable mechanism.
+ */
+ sscanf(oh->name, "timer%2d", &id);
+
+ od = omap_device_build(name, id, oh,
+ pdata, sizeof(*pdata),
+ omap2_dmtimer_latency,
+ ARRAY_SIZE(omap2_dmtimer_latency), 0);
+
+ if (IS_ERR(od)) {
+ pr_err("%s: Cant build omap_device for %s:%s.\n",
+ __func__, name, oh->name);
+ ret = -EINVAL;
+ }
+ /*
+ * pdata can be freed because omap_device_build
+ * creates its own memory pool
+ */
+ kfree(pdata);
+ return ret;
+}
+
+/**
+ * omap2_dm_timer_early_init - top level early timer initialization
+ * called in the last part of omap2_init_common_hw
+ *
+ * uses dedicated hwmod api to parse through hwmod database for
+ * given class name and then build and register the timer device.
+ * at the end driver is registered and early probe initiated.
+ */
+void __init omap2_dm_timer_early_init(void)
+{
+ if (omap_hwmod_for_each_by_class("timer",
+ omap2_timer_early_init, NULL)) {
+ pr_debug("%s: device registration FAILED\n", __func__);
+ return;
+ }
+ early_platform_driver_register_all("earlytimer");
+ early_platform_driver_probe("earlytimer", early_timer_count, 0);
+}
+
+/**
+ * omap_timer_init - top level timer device initialization
+ *
+ * uses dedicated hwmod api to parse through hwmod database for
+ * given class names and then build and register the timer device.
+ */
+static int __init omap2_dmtimer_device_init(void)
+{
+ int ret = omap_hwmod_for_each_by_class("timer", omap2_timer_init, NULL);
+
+ if (unlikely(ret))
+ pr_debug("%s: device registration FAILED\n", __func__);
+
+ return ret;
+}
+arch_initcall(omap2_dmtimer_device_init);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver
2010-11-20 2:39 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 13/14] OMAP: dmtimer: remove reset function Tarun Kanti DebBarma
2010-11-22 6:44 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Varadarajan, Charulatha
2010-11-22 6:33 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Varadarajan, Charulatha
` (2 subsequent siblings)
3 siblings, 2 replies; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Tarun Kanti DebBarma
switch-over to platform device driver through following changes:
(a) call to dmtimer initialization routine from timer-gp.c is
removed (b) initiate dmtimer early initialization from omap2_init_common_hw
in io.c (c) modify plat-omap/dmtimer routines to use new register map and
platform data.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Cousson, Benoit <b-cousson@ti.com>
---
arch/arm/mach-omap2/clock2420_data.c | 2 +-
arch/arm/mach-omap2/clock2430_data.c | 2 +-
arch/arm/mach-omap2/clock3xxx_data.c | 2 +-
arch/arm/mach-omap2/clock44xx_data.c | 2 +-
arch/arm/mach-omap2/io.c | 2 +
arch/arm/mach-omap2/timer-gp.c | 1 -
arch/arm/plat-omap/dmtimer.c | 242 +++++++---------------------------
7 files changed, 53 insertions(+), 200 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index d2e90ae..f88ad5d 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1801,7 +1801,7 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
- CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
+ CLK("omap-timer.1", "fck", &gpt1_fck, CK_242X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
CLK("omap-timer.2", "fck", &gpt2_fck, CK_242X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 7861bf4..e0ef1ea 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1905,7 +1905,7 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
- CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
+ CLK("omap-timer.1", "fck", &gpt1_fck, CK_243X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
CLK("omap-timer.2", "fck", &gpt2_fck, CK_243X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 41685be..cd50903 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3361,7 +3361,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
- CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
+ CLK("omap-timer.1", "fck", &gpt1_fck, CK_3XXX),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index d081c10..dd5f577 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -2921,7 +2921,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
- CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
+ CLK("omap-timer.1", "fck", &timer1_fck, CK_443X),
CLK("omap-timer.10", "fck", &timer10_fck, CK_443X),
CLK("omap-timer.11", "fck", &timer11_fck, CK_443X),
CLK("omap-timer.2", "fck", &timer2_fck, CK_443X),
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 40562dd..e6128b5 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -46,6 +46,7 @@
#include "clockdomains.h"
#include <plat/omap_hwmod.h>
+#include "dmtimer.h"
/*
* The machine specific code may provide the extra mapping besides the
@@ -352,4 +353,5 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
_omap2_init_reprogram_sdrc();
}
gpmc_init();
+ omap2_dm_timer_early_init();
}
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index e13c29e..54fafac 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -235,7 +235,6 @@ static void __init omap2_gp_timer_init(void)
BUG_ON(!twd_base);
}
#endif
- omap_dm_timer_init();
omap2_gp_clockevent_init();
omap2_gp_clocksource_init();
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 0479ab0..8950fcd 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -160,11 +160,8 @@
struct omap_dm_timer {
int id;
- unsigned long phys_base;
int irq;
-#ifdef CONFIG_ARCH_OMAP2PLUS
- struct clk *iclk, *fclk;
-#endif
+ struct clk *fclk;
void __iomem *io_base;
unsigned reserved:1;
unsigned enabled:1;
@@ -173,136 +170,55 @@ struct omap_dm_timer {
struct list_head node;
};
-static int dm_timer_count;
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct omap_dm_timer omap2_dm_timers[] = {
- { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
- { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
- { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
- { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
- { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
- { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
- { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
- { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
- { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
- { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
- { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
- { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
-};
-
-static const char *omap2_dm_source_names[] __initdata = {
- "sys_ck",
- "func_32k_ck",
- "alt_ck",
- NULL
-};
-
-static struct clk *omap2_dm_source_clocks[3];
-static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
-
-#else
-#define omap2_dm_timers NULL
-#define omap2_dm_timer_count 0
-#define omap2_dm_source_names NULL
-#define omap2_dm_source_clocks NULL
-#endif /* CONFIG_ARCH_OMAP2 */
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct omap_dm_timer omap3_dm_timers[] = {
- { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
- { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
- { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
- { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
- { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
- { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
- { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
- { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
- { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
- { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
- { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
- { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
-};
-
-static const char *omap3_dm_source_names[] __initdata = {
- "sys_ck",
- "omap_32k_fck",
- NULL
-};
-
-static struct clk *omap3_dm_source_clocks[2];
-static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
-
-#else
-#define omap3_dm_timers NULL
-#define omap3_dm_timer_count 0
-#define omap3_dm_source_names NULL
-#define omap3_dm_source_clocks NULL
-#endif /* CONFIG_ARCH_OMAP3 */
-
-#ifdef CONFIG_ARCH_OMAP4
-static struct omap_dm_timer omap4_dm_timers[] = {
- { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
- { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
- { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
- { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
- { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
- { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
- { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
- { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
- { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
- { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
- { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
- { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
-};
-static const char *omap4_dm_source_names[] __initdata = {
- "sys_clkin_ck",
- "sys_32k_ck",
- NULL
-};
-static struct clk *omap4_dm_source_clocks[2];
-static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
-
-#else
-#define omap4_dm_timers NULL
-#define omap4_dm_timer_count 0
-#define omap4_dm_source_names NULL
-#define omap4_dm_source_clocks NULL
-#endif /* CONFIG_ARCH_OMAP4 */
-
-static struct omap_dm_timer *dm_timers;
-static const char **dm_source_names;
-static struct clk **dm_source_clocks;
-
static LIST_HEAD(omap_timer_list);
static DEFINE_SPINLOCK(dm_timer_lock);
-/*
- * Reads timer registers in posted and non-posted mode. The posted mode bit
- * is encoded in reg. Note that in posted mode write pending bit must be
- * checked. Otherwise a read of a non completed write will produce an error.
+/**
+ * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
+ * @timer: timer pointer over which read operation to perform
+ * @reg: lowest byte holds the register offset
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode write
+ * pending bit must be checked. Otherwise a read of a non completed write
+ * will produce an error.
*/
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
{
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+
+ if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
+ reg += pdata->func_offst;
+
if (timer->posted)
- while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
- & (reg >> WPSHIFT))
+ while (readl(timer->io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
+ & 0xff)) & (reg >> WPSHIFT))
cpu_relax();
return readl(timer->io_base + (reg & 0xff));
}
-/*
- * Writes timer registers in posted and non-posted mode. The posted mode bit
- * is encoded in reg. Note that in posted mode the write pending bit must be
- * checked. Otherwise a write on a register which has a pending write will be
- * lost.
+/**
+ * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
+ * @timer: timer pointer over which write operation is to perform
+ * @reg: lowest byte holds the register offset
+ * @value: data to write into the register
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode the write
+ * pending bit must be checked. Otherwise a write on a register which has a
+ * pending write will be lost.
*/
static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
u32 value)
{
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+
+ if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
+ reg += pdata->func_offst;
+
if (timer->posted)
- while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
- & (reg >> WPSHIFT))
+ while (readl(timer->io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
+ & 0xff)) & (reg >> WPSHIFT))
cpu_relax();
writel(value, timer->io_base + (reg & 0xff));
}
@@ -470,12 +386,7 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer)
if (timer->enabled)
return;
-#ifdef CONFIG_ARCH_OMAP2PLUS
- if (cpu_class_is_omap2()) {
- clk_enable(timer->fclk);
- clk_enable(timer->iclk);
- }
-#endif
+ clk_enable(timer->fclk);
timer->enabled = 1;
}
@@ -486,12 +397,7 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer)
if (!timer->enabled)
return;
-#ifdef CONFIG_ARCH_OMAP2PLUS
- if (cpu_class_is_omap2()) {
- clk_disable(timer->iclk);
- clk_disable(timer->fclk);
- }
-#endif
+ clk_disable(timer->fclk);
timer->enabled = 0;
}
@@ -594,7 +500,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
#endif
}
/* Ack possibly pending interrupt */
- omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+ omap_dm_timer_write_intr_reg(timer, OMAP_TIMER_STAT_REG,
OMAP_TIMER_INT_OVERFLOW);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
@@ -603,13 +509,17 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
{
int ret = -EINVAL;
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
if (source < 0 || source >= 3)
return -EINVAL;
- clk_disable(timer->fclk);
- ret = clk_set_parent(timer->fclk, dm_source_clocks[source]);
- clk_enable(timer->fclk);
+ omap_dm_timer_disable(timer);
+
+ /* change the timer clock source */
+ ret = pdata->set_timer_src(timer->pdev, source);
+
+ omap_dm_timer_enable(timer);
/*
* When the functional clock disappears, too quick writes seem
@@ -708,7 +618,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
unsigned int value)
{
- omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
+ omap_dm_timer_write_intr_reg(timer, OMAP_TIMER_INT_EN_REG, value);
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
@@ -717,7 +627,7 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
{
unsigned int l;
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
+ l = omap_dm_timer_read_intr_reg(timer, OMAP_TIMER_STAT_REG);
return l;
}
@@ -725,7 +635,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
{
- omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
+ omap_dm_timer_write_intr_reg(timer, OMAP_TIMER_STAT_REG, value);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
@@ -927,61 +837,3 @@ MODULE_DESCRIPTION("OMAP DUAL MODE TIMER DRIVER");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_AUTHOR("Texas Instruments Inc");
-
-int __init omap_dm_timer_init(void)
-{
- unsigned long flags;
- struct omap_dm_timer *timer;
- int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
-
- if (!cpu_class_is_omap2())
- return -ENODEV;
-
- if (cpu_is_omap24xx()) {
- dm_timers = omap2_dm_timers;
- dm_timer_count = omap2_dm_timer_count;
- dm_source_names = omap2_dm_source_names;
- dm_source_clocks = omap2_dm_source_clocks;
- } else if (cpu_is_omap34xx()) {
- dm_timers = omap3_dm_timers;
- dm_timer_count = omap3_dm_timer_count;
- dm_source_names = omap3_dm_source_names;
- dm_source_clocks = omap3_dm_source_clocks;
- } else if (cpu_is_omap44xx()) {
- dm_timers = omap4_dm_timers;
- dm_timer_count = omap4_dm_timer_count;
- dm_source_names = omap4_dm_source_names;
- dm_source_clocks = omap4_dm_source_clocks;
- }
-
- if (cpu_class_is_omap2())
- for (i = 0; dm_source_names[i] != NULL; i++)
- dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
-
- if (cpu_is_omap243x())
- dm_timers[0].phys_base = 0x49018000;
-
- for (i = 0; i < dm_timer_count; i++) {
- timer = &dm_timers[i];
-
- /* Static mapping, never released */
- timer->io_base = ioremap(timer->phys_base, map_size);
- BUG_ON(!timer->io_base);
-
-#ifdef CONFIG_ARCH_OMAP2PLUS
- if (cpu_class_is_omap2()) {
- char clk_name[16];
- sprintf(clk_name, "gpt%d_ick", i + 1);
- timer->iclk = clk_get(NULL, clk_name);
- sprintf(clk_name, "gpt%d_fck", i + 1);
- timer->fclk = clk_get(NULL, clk_name);
- }
-#endif
- timer->id = i + 1; /* id starts from 1*/
- spin_lock_irqsave(&dm_timer_lock, flags);
- list_add_tail(&timer->node, &omap_timer_list);
- spin_unlock_irqrestore(&dm_timer_lock, flags);
- }
-
- return 0;
-}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 13/14] OMAP: dmtimer: remove reset function
2010-11-20 2:39 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 14/14] OMAP: dmtimer: pm_runtime support Tarun Kanti DebBarma
2010-11-22 6:44 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Varadarajan, Charulatha
1 sibling, 1 reply; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Tarun Kanti DebBarma
reset is handled by hwmod framework and so removing it
from the code.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Cousson, Benoit <b-cousson@ti.com>
---
arch/arm/plat-omap/dmtimer.c | 42 ++----------------------------------------
1 files changed, 2 insertions(+), 40 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 8950fcd..f9285b1 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -273,54 +273,18 @@ void omap_dm_timer_write_intr_reg(struct omap_dm_timer *timer, u32 reg,
writel(value, timer->io_base + (reg & 0xff));
}
-
-static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
-{
- int c;
-
- c = 0;
- while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
- c++;
- if (c > 100000) {
- printk(KERN_ERR "Timer failed to reset\n");
- return;
- }
- }
-}
-
-static void omap_dm_timer_reset(struct omap_dm_timer *timer)
+static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
- u32 l;
+ omap_dm_timer_enable(timer);
- if (!cpu_class_is_omap2() || timer->id != 1) {
- omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
- omap_dm_timer_wait_for_reset(timer);
- }
omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
- l |= 0x02 << 3; /* Set to smart-idle mode */
- l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
-
- /*
- * Enable wake-up on OMAP2 CPUs.
- */
- if (cpu_class_is_omap2())
- l |= 1 << 2;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
-
/* Match hardware reset default of posted mode */
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
OMAP_TIMER_CTRL_POSTED);
timer->posted = 1;
}
-static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
-{
- omap_dm_timer_enable(timer);
- omap_dm_timer_reset(timer);
-}
-
struct omap_dm_timer *omap_dm_timer_request(void)
{
struct omap_dm_timer *timer = NULL, *t;
@@ -372,8 +336,6 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
void omap_dm_timer_free(struct omap_dm_timer *timer)
{
- omap_dm_timer_enable(timer);
- omap_dm_timer_reset(timer);
omap_dm_timer_disable(timer);
WARN_ON(!timer->reserved);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCHv4 14/14] OMAP: dmtimer: pm_runtime support
2010-11-20 2:39 ` [PATCHv4 13/14] OMAP: dmtimer: remove reset function Tarun Kanti DebBarma
@ 2010-11-20 2:39 ` Tarun Kanti DebBarma
2010-11-22 7:04 ` Varadarajan, Charulatha
0 siblings, 1 reply; 42+ messages in thread
From: Tarun Kanti DebBarma @ 2010-11-20 2:39 UTC (permalink / raw)
To: linux-omap; +Cc: Tarun Kanti DebBarma, Partha Basak
Add pm_runtime support to dmtimer. Since dmtimer is used during
early boot before pm_runtime is initialized completely there are
provisions to enable/disable clocks directly in the code during
early boot.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[p-basak2@ti.com: added pm_runtime logic in probe()]
Signed-off-by: Partha Basak <p-basak2@ti.com>
---
arch/arm/plat-omap/dmtimer.c | 31 +++++++++++++++++++++++++++++--
1 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index f9285b1..83d0b66 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -45,6 +45,7 @@
#include <linux/module.h>
#include <linux/slab.h>
#include <mach/hardware.h>
+#include <linux/pm_runtime.h>
#include <plat/dmtimer.h>
#include <mach/irqs.h>
#include <linux/err.h>
@@ -345,10 +346,22 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_free);
void omap_dm_timer_enable(struct omap_dm_timer *timer)
{
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+
if (timer->enabled)
return;
- clk_enable(timer->fclk);
+ if (unlikely(pdata->is_early_init)) {
+ clk_enable(timer->fclk);
+ timer->enabled = 1;
+ return;
+ }
+
+ if (pm_runtime_get_sync(&timer->pdev->dev)) {
+ dev_dbg(&timer->pdev->dev, "%s:pm_runtime_get_sync() FAILED\n",
+ __func__);
+ return;
+ }
timer->enabled = 1;
}
@@ -356,10 +369,22 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
void omap_dm_timer_disable(struct omap_dm_timer *timer)
{
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+
if (!timer->enabled)
return;
- clk_disable(timer->fclk);
+ if (unlikely(pdata->is_early_init)) {
+ clk_disable(timer->fclk);
+ timer->enabled = 0;
+ return;
+ }
+
+ if (pm_runtime_put_sync(&timer->pdev->dev)) {
+ dev_dbg(&timer->pdev->dev, "%s:pm_runtime_put_sync() FAILED\n",
+ __func__);
+ return;
+ }
timer->enabled = 0;
}
@@ -669,6 +694,8 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
if (timer->id == pdev->id) {
timer->pdev = pdev;
spin_unlock_irqrestore(&dm_timer_lock, flags);
+ pm_runtime_enable(&pdev->dev);
+ dev_dbg(&pdev->dev, "pm_runtime ENABLED\n");
return 0;
}
spin_unlock_irqrestore(&dm_timer_lock, flags);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCHv4 6/14] OMAP4: dmtimer: add hwmod database
2010-11-20 2:39 ` [PATCHv4 6/14] OMAP4: " Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Tarun Kanti DebBarma
@ 2010-11-22 6:02 ` Varadarajan, Charulatha
2010-11-22 6:11 ` DebBarma, Tarun Kanti
1 sibling, 1 reply; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 6:02 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, Cousson, Benoit
These comments are from other hwmod reviews.
On Sat, Nov 20, 2010 at 08:09, Tarun Kanti DebBarma <tarun.kanti@ti.com> wrote:
> From: Cousson, Benoit <b-cousson@ti.com>
Subject should be something like: ( See [1] )
OMAP4: hwmod data: add dmtimer
Same is applicable to other hwmod DB patches for OMAP2420, OMAP2430
& OMAP3 to add dmtimer data
>
> Add hwmod database for OMAP4.
>
> Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 622 ++++++++++++++++++++++++++++
<<snip>>
> + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> +};
> +
> +/*
> * 'wd_timer' class
> * 32-bit watchdog upward counter that generates a pulse on the reset pin on
> * overflow condition
> @@ -1068,6 +1678,18 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
>
> /* mpu class */
> &omap44xx_mpu_hwmod,
> + /* timer class */
> + &omap44xx_timer1_hwmod,
> + &omap44xx_timer2_hwmod,
> + &omap44xx_timer3_hwmod,
> + &omap44xx_timer4_hwmod,
> + &omap44xx_timer5_hwmod,
> + &omap44xx_timer6_hwmod,
> + &omap44xx_timer7_hwmod,
> + &omap44xx_timer8_hwmod,
> + &omap44xx_timer9_hwmod,
> + &omap44xx_timer10_hwmod,
> + &omap44xx_timer11_hwmod,
Add a blank line between each class. See [2]
Same is applicable to other hwmod DB patches for OMAP2420, OMAP2430
& OMAP3 to add dmtimer data
[1] https://patchwork.kernel.org/patch/282472/
[2] https://patchwork.kernel.org/patch/308422/
> /* wd_timer class */
> &omap44xx_wd_timer2_hwmod,
> &omap44xx_wd_timer3_hwmod,
> --
> 1.6.0.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 6/14] OMAP4: dmtimer: add hwmod database
2010-11-22 6:02 ` [PATCHv4 6/14] OMAP4: dmtimer: add hwmod database Varadarajan, Charulatha
@ 2010-11-22 6:11 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-22 6:11 UTC (permalink / raw)
To: Varadarajan, Charulatha; +Cc: linux-omap, Cousson, Benoit
> -----Original Message-----
> From: Varadarajan, Charulatha
> Sent: Monday, November 22, 2010 11:32 AM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Cousson, Benoit
> Subject: Re: [PATCHv4 6/14] OMAP4: dmtimer: add hwmod database
>
> These comments are from other hwmod reviews.
>
> On Sat, Nov 20, 2010 at 08:09, Tarun Kanti DebBarma <tarun.kanti@ti.com>
> wrote:
> > From: Cousson, Benoit <b-cousson@ti.com>
>
> Subject should be something like: ( See [1] )
> OMAP4: hwmod data: add dmtimer
>
> Same is applicable to other hwmod DB patches for OMAP2420, OMAP2430
> & OMAP3 to add dmtimer data
Ok.
>
> >
> > Add hwmod database for OMAP4.
> >
> > Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > ---
> > arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 622
> ++++++++++++++++++++++++++++
>
> <<snip>>
>
> > + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
> > +};
> > +
> > +/*
> > * 'wd_timer' class
> > * 32-bit watchdog upward counter that generates a pulse on the reset
> pin on
> > * overflow condition
> > @@ -1068,6 +1678,18 @@ static __initdata struct omap_hwmod
> *omap44xx_hwmods[] = {
> >
> > /* mpu class */
> > &omap44xx_mpu_hwmod,
> > + /* timer class */
> > + &omap44xx_timer1_hwmod,
> > + &omap44xx_timer2_hwmod,
> > + &omap44xx_timer3_hwmod,
> > + &omap44xx_timer4_hwmod,
> > + &omap44xx_timer5_hwmod,
> > + &omap44xx_timer6_hwmod,
> > + &omap44xx_timer7_hwmod,
> > + &omap44xx_timer8_hwmod,
> > + &omap44xx_timer9_hwmod,
> > + &omap44xx_timer10_hwmod,
> > + &omap44xx_timer11_hwmod,
>
> Add a blank line between each class. See [2]
> Same is applicable to other hwmod DB patches for OMAP2420, OMAP2430
> & OMAP3 to add dmtimer data
Hmm... this is really funny! In fact in earlier patches I gave a blank line.
This time I saw other implementations which does not have blank lines like these and thought that I should remove the blank line:
/* dmm class */
&omap44xx_dmm_hwmod,
/* emif_fw class */
&omap44xx_emif_fw_hwmod,
/* l3 class */
&omap44xx_l3_instr_hwmod,
&omap44xx_l3_main_1_hwmod,
&omap44xx_l3_main_2_hwmod,
&omap44xx_l3_main_3_hwmod,
/* l4 class */
&omap44xx_l4_abe_hwmod,
&omap44xx_l4_cfg_hwmod,
&omap44xx_l4_per_hwmod,
&omap44xx_l4_wkup_hwmod,
Well, I can add blank lines with the hope that someone does not ask me to remove them again ;)
--
Tarun
>
> [1] https://patchwork.kernel.org/patch/282472/
> [2] https://patchwork.kernel.org/patch/308422/
>
> > /* wd_timer class */
> > &omap44xx_wd_timer2_hwmod,
> > &omap44xx_wd_timer3_hwmod,
> > --
> > 1.6.0.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> >
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
2010-11-20 2:39 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Tarun Kanti DebBarma
@ 2010-11-22 6:33 ` Varadarajan, Charulatha
2010-11-22 7:24 ` DebBarma, Tarun Kanti
2010-11-22 8:24 ` Varadarajan, Charulatha
2010-11-23 17:51 ` Cousson, Benoit
3 siblings, 1 reply; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 6:33 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, Thara Gopinath, Partha Basak
On Sat, Nov 20, 2010 at 08:09, Tarun Kanti DebBarma <tarun.kanti@ti.com> wrote:
> From: Thara Gopinath <thara@ti.com>
>
> Add routines to converts dmtimers to platform devices. The device data
> is obtained from hwmod database of respective platform and is registered
> to device model after successful binding to driver. It also provides
> provision to access timers during early boot when pm_runtime framework
> is not completely up and running.
>
> Signed-off-by: Thara Gopinath <thara@ti.com>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> [p-basak2@ti.com: pm_runtime logic]
Where is runtime logic in this patch? The patch description says "pm_runtime
framework is not completely up and running"
> Signed-off-by: Partha Basak <p-basak2@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 2 +-
> arch/arm/mach-omap2/dmtimer.c | 296 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 297 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-omap2/dmtimer.c
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index ce7b1f0..148f4d7 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -4,7 +4,7 @@
>
> # Common support
> obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
> - common.o
> + common.o dmtimer.o
>
> omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
> hwmod-common = omap_hwmod.o \
> diff --git a/arch/arm/mach-omap2/dmtimer.c b/arch/arm/mach-omap2/dmtimer.c
> new file mode 100644
> index 0000000..b5951b1
> --- /dev/null
> +++ b/arch/arm/mach-omap2/dmtimer.c
> @@ -0,0 +1,296 @@
> +/**
> + * OMAP2PLUS Dual-Mode Timers - platform device registration
> + *
> + * Contains first level initialization routines which extracts timers
> + * information from hwmod database and registers with linux device model.
> + * It also has low level function to chnage the timer input clock source.
> + *
> + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
> + * Tarun Kanti DebBarma <tarun.kanti@ti.com>
> + *
> + * Copyright (C) 2010 Texas Instruments Incorporated
> + * Thara Gopinath <thara@ti.com>
Don't repeat the same copyright information twice:
"Copyright (C) 2010 Texas Instruments Incorporated"
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#undef DEBUG
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/slab.h>
> +
> +#include <mach/irqs.h>
> +#include <plat/dmtimer.h>
> +#include <plat/powerdomain.h>
> +#include <plat/omap_hwmod.h>
> +#include <plat/omap_device.h>
> +#include <linux/pm_runtime.h>
Why is "linux/pm_runtime.h" required in this file? I don't find any use here.
Also check if "plat/powerdomain.h" is required.
> +
> +static int early_timer_count __initdata = 1;
> +
> +/**
> + * omap2_dm_timer_set_src - change the timer input clock source
> + * @pdev: timer platform device pointer
> + * @timer_clk: current clock source
> + * @source: array index of parent clock source
> + */
> +static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
> +{
> + int ret;
> + struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
> + struct clk *fclk = clk_get(&pdev->dev, "fck");
> + struct clk *new_fclk;
> + char *fclk_name = "32k_ck"; /* default name */
> +
> + switch(source) {
> + case OMAP_TIMER_SRC_SYS_CLK:
> + fclk_name = "sys_ck";
> + break;
> +
> + case OMAP_TIMER_SRC_32_KHZ:
> + fclk_name = "32k_ck";
> + break;
> +
> + case OMAP_TIMER_SRC_EXT_CLK:
> + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_1) {
> + fclk_name = "alt_ck";
> + break;
> + }
> + dev_dbg(&pdev->dev, "%s:%d: invalid clk src.\n",
> + __func__, __LINE__);
> + return -EINVAL;
> + }
> +
> +
> + if (IS_ERR_OR_NULL(fclk)) {
> + dev_dbg(&pdev->dev, "%s:%d: clk_get() FAILED\n",
> + __func__, __LINE__);
> + return -EINVAL;
> + }
> +
> + new_fclk = clk_get(&pdev->dev, fclk_name);
> + if (IS_ERR_OR_NULL(new_fclk)) {
> + dev_dbg(&pdev->dev, "%s:%d: clk_get() %s FAILED\n",
> + __func__, __LINE__, fclk_name);
> + clk_put(fclk);
> + return -EINVAL;
> + }
> +
> + ret = clk_set_parent(fclk, new_fclk);
> + if (IS_ERR_VALUE(ret)) {
> + dev_dbg(&pdev->dev, "%s:clk_set_parent() to %s FAILED\n",
> + __func__, fclk_name);
> + ret = -EINVAL;
> + }
> +
> + clk_put(new_fclk);
> + clk_put(fclk);
> +
> + return ret;
> +}
> +
> +struct omap_device_pm_latency omap2_dmtimer_latency[] = {
> + {
> + .deactivate_func = omap_device_idle_hwmods,
> + .activate_func = omap_device_enable_hwmods,
> + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
> + },
> +};
> +
> +/**
> + * omap_dm_timer_early_init - build and register early timer device
> + * with an associated timer hwmod
> + * @oh: timer hwmod pointer to be used to build timer device
> + * @user: parameter that can be passed from calling hwmod API
> + *
> + * early init is called in the last part of omap2_init_common_hw
> + * for each early timer class using omap_hwmod_for_each_by_class.
> + * it registers each of the timer devices present in the system.
> + * at the end of function call memory is allocated for omap_device
> + * and hwmod for early timer and the device is registered to the
> + * framework ready to be probed by the driver.
> + */
> +static int __init omap2_timer_early_init(struct omap_hwmod *oh, void *user)
Again a repeat comment from other hwmod reviews:
if "user" is not used, rename it as "unused"
> +{
> + int id;
> + int ret = 0;
> + char *name = "omap-timer";
> + struct dmtimer_platform_data *pdata;
> + struct omap_device *od;
> +
> + pr_debug("%s:%s\n", __func__, oh->name);
> +
> + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> + if (!pdata) {
> + pr_err("%s: No memory for [%s]\n", __func__, oh->name);
> + return -ENOMEM;
> + }
> +
> + pdata->is_early_init = 1;
> +
> + /* hook clock set/get functions */
> + pdata->set_timer_src = omap2_dm_timer_set_src;
> +
> + /* read timer ip version */
> + pdata->timer_ip_type = oh->class->rev;
> + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
> + pdata->func_offst = 0x14;
> + pdata->intr_offst = 0x10;
> + } else {
> + pdata->func_offst = 0;
> + pdata->intr_offst = 0;
> + }
> +
> + /*
> + * extract the id from name filed in hwmod database
> + * and use the same for constructing ids' for the
> + * timer devices. in a way, we are avoiding usage of
> + * static variable witin the function to do the same.
> + * CAUTION: we have to be careful and make sure the
> + * name in hwmod database does not change in which case
> + * we might either make corresponding change here or
> + * switch back static variable mechanism.
> + */
> + sscanf(oh->name, "timer%2d", &id);
> +
> + od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
> + omap2_dmtimer_latency,
> + ARRAY_SIZE(omap2_dmtimer_latency), 1);
> +
> + if (IS_ERR(od)) {
> + pr_err("%s: Cant build omap_device for %s:%s.\n",
> + __func__, name, oh->name);
> + ret = -EINVAL;
> + } else
> + early_timer_count++;
> + /*
> + * pdata can be freed because omap_device_build
> + * creates its own memory pool
> + */
No need to mention this.
> + kfree(pdata);
> +
> + return ret;
> +}
> +
> +/**
> + * omap2_dm_timer_init - build and register timer device with an
> + * associated timer hwmod
> + * @oh: timer hwmod pointer to be used to build timer device
> + * @user: parameter that can be passed from calling hwmod API
> + *
> + * called by omap_hwmod_for_each_by_class to register each of the timer
> + * devices present in the system. the number of timer devices is known
> + * by parsing through the hwmod database for a given class name. at the
> + * end of function call memory is allocated for omap_device and hwmod
> + * for timer and the device is registered to the framework ready to be
> + * proved by the driver.
> + */
> +static int __init omap2_timer_init(struct omap_hwmod *oh, void *user)
omap2_timer_init() and omap2_timer_early_init() looks similar except for
pdata->is_early_init value. Why not have a common function and call it
with appropriate pdata->is_early_init value?
> +{
> + int id;
> + int ret = 0;
> + char *name = "omap-timer";
> + struct omap_device *od;
> + struct dmtimer_platform_data *pdata;
> +
> + if (!oh) {
> + pr_err("%s:NULL hwmod pointer (oh)\n", __func__);
> + return -EINVAL;
> + }
> + pr_debug("%s:%s\n", __func__, oh->name);
> +
> + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> + if (!pdata) {
> + pr_err("%s:No memory for [%s]\n", __func__, oh->name);
> + return -ENOMEM;
> + }
> +
> + pdata->is_early_init = 0;
> +
> + /* hook clock set/get functions */
> + pdata->set_timer_src = omap2_dm_timer_set_src;
> +
> + /* read timer ip version */
> + pdata->timer_ip_type = oh->class->rev;
> + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
> + pdata->func_offst = 0x14;
> + pdata->intr_offst = 0x10;
> + } else {
> + pdata->func_offst = 0;
> + pdata->intr_offst = 0;
> + }
> +
> + /*
> + * extract the id from name filed in hwmod database
> + * and use the same for constructing ids' for the
> + * timer devices. in a way, we are avoiding usage of
> + * static variable witin the function to do the same.
> + * CAUTION: we have to be careful and make sure the
> + * name in hwmod database does not change in which case
> + * we might either make corresponding change here or
> + * switch back static variable mechanism.
> + */
> + sscanf(oh->name, "timer%2d", &id);
> +
> + od = omap_device_build(name, id, oh,
> + pdata, sizeof(*pdata),
> + omap2_dmtimer_latency,
> + ARRAY_SIZE(omap2_dmtimer_latency), 0);
> +
> + if (IS_ERR(od)) {
> + pr_err("%s: Cant build omap_device for %s:%s.\n",
> + __func__, name, oh->name);
> + ret = -EINVAL;
> + }
> + /*
> + * pdata can be freed because omap_device_build
> + * creates its own memory pool
> + */
Ditto.
> + kfree(pdata);
> + return ret;
> +}
> +
> +/**
> + * omap2_dm_timer_early_init - top level early timer initialization
> + * called in the last part of omap2_init_common_hw
> + *
> + * uses dedicated hwmod api to parse through hwmod database for
> + * given class name and then build and register the timer device.
> + * at the end driver is registered and early probe initiated.
> + */
> +void __init omap2_dm_timer_early_init(void)
> +{
> + if (omap_hwmod_for_each_by_class("timer",
> + omap2_timer_early_init, NULL)) {
> + pr_debug("%s: device registration FAILED\n", __func__);
> + return;
> + }
> + early_platform_driver_register_all("earlytimer");
> + early_platform_driver_probe("earlytimer", early_timer_count, 0);
> +}
> +
> +/**
> + * omap_timer_init - top level timer device initialization
> + *
> + * uses dedicated hwmod api to parse through hwmod database for
> + * given class names and then build and register the timer device.
> + */
> +static int __init omap2_dmtimer_device_init(void)
> +{
> + int ret = omap_hwmod_for_each_by_class("timer", omap2_timer_init, NULL);
> +
> + if (unlikely(ret))
> + pr_debug("%s: device registration FAILED\n", __func__);
> +
> + return ret;
> +}
> +arch_initcall(omap2_dmtimer_device_init);
> --
> 1.6.0.4
>
> --
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> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver
2010-11-20 2:39 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 13/14] OMAP: dmtimer: remove reset function Tarun Kanti DebBarma
@ 2010-11-22 6:44 ` Varadarajan, Charulatha
2010-11-22 9:14 ` DebBarma, Tarun Kanti
1 sibling, 1 reply; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 6:44 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap
<<snip>>
> -/*
> - * Reads timer registers in posted and non-posted mode. The posted mode bit
> - * is encoded in reg. Note that in posted mode write pending bit must be
> - * checked. Otherwise a read of a non completed write will produce an error.
> +/**
> + * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
> + * @timer: timer pointer over which read operation to perform
> + * @reg: lowest byte holds the register offset
> + *
> + * The posted mode bit is encoded in reg. Note that in posted mode write
> + * pending bit must be checked. Otherwise a read of a non completed write
> + * will produce an error.
> */
> static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
> {
> + struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
> +
> + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> + reg += pdata->func_offst;
> +
> if (timer->posted)
> - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
> - & (reg >> WPSHIFT))
> + while (readl(timer->io_base +
> + ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
> + & 0xff)) & (reg >> WPSHIFT))
You may add a timeout in this.
> cpu_relax();
> return readl(timer->io_base + (reg & 0xff));
> }
>
> -/*
> - * Writes timer registers in posted and non-posted mode. The posted mode bit
> - * is encoded in reg. Note that in posted mode the write pending bit must be
> - * checked. Otherwise a write on a register which has a pending write will be
> - * lost.
> +/**
> + * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
> + * @timer: timer pointer over which write operation is to perform
> + * @reg: lowest byte holds the register offset
> + * @value: data to write into the register
> + *
> + * The posted mode bit is encoded in reg. Note that in posted mode the write
> + * pending bit must be checked. Otherwise a write on a register which has a
> + * pending write will be lost.
> */
> static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
> u32 value)
> {
> + struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
> +
> + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> + reg += pdata->func_offst;
> +
> if (timer->posted)
> - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
> - & (reg >> WPSHIFT))
> + while (readl(timer->io_base +
> + ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
> + & 0xff)) & (reg >> WPSHIFT))
Ditto.
> cpu_relax();
> writel(value, timer->io_base + (reg & 0xff));
> }
<<snip>>
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 14/14] OMAP: dmtimer: pm_runtime support
2010-11-20 2:39 ` [PATCHv4 14/14] OMAP: dmtimer: pm_runtime support Tarun Kanti DebBarma
@ 2010-11-22 7:04 ` Varadarajan, Charulatha
2010-11-22 7:07 ` DebBarma, Tarun Kanti
0 siblings, 1 reply; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 7:04 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, Partha Basak
On Sat, Nov 20, 2010 at 08:09, Tarun Kanti DebBarma <tarun.kanti@ti.com> wrote:
> Add pm_runtime support to dmtimer. Since dmtimer is used during
> early boot before pm_runtime is initialized completely there are
> provisions to enable/disable clocks directly in the code during
> early boot.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> [p-basak2@ti.com: added pm_runtime logic in probe()]
> Signed-off-by: Partha Basak <p-basak2@ti.com>
> ---
> arch/arm/plat-omap/dmtimer.c | 31 +++++++++++++++++++++++++++++--
> 1 files changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> index f9285b1..83d0b66 100644
> --- a/arch/arm/plat-omap/dmtimer.c
> +++ b/arch/arm/plat-omap/dmtimer.c
> @@ -45,6 +45,7 @@
> #include <linux/module.h>
> #include <linux/slab.h>
> #include <mach/hardware.h>
> +#include <linux/pm_runtime.h>
> #include <plat/dmtimer.h>
> #include <mach/irqs.h>
> #include <linux/err.h>
> @@ -345,10 +346,22 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_free);
>
> void omap_dm_timer_enable(struct omap_dm_timer *timer)
> {
> + struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
> +
> if (timer->enabled)
> return;
>
> - clk_enable(timer->fclk);
> + if (unlikely(pdata->is_early_init)) {
> + clk_enable(timer->fclk);
> + timer->enabled = 1;
> + return;
> + }
If timer->fclk is not going to be used after "pdata->is_early_init" is
made zero,
you may do a clk_put( ) of the timer->fclk because pm_runtime_* APIs are
going to be used after pdata->is_early_init is made zero.
> +
> + if (pm_runtime_get_sync(&timer->pdev->dev)) {
> + dev_dbg(&timer->pdev->dev, "%s:pm_runtime_get_sync() FAILED\n",
> + __func__);
> + return;
> + }
>
> timer->enabled = 1;
> }
> @@ -356,10 +369,22 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
>
> void omap_dm_timer_disable(struct omap_dm_timer *timer)
> {
> + struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
> +
> if (!timer->enabled)
> return;
>
> - clk_disable(timer->fclk);
> + if (unlikely(pdata->is_early_init)) {
> + clk_disable(timer->fclk);
> + timer->enabled = 0;
Ditto
> + return;
> + }
> +
> + if (pm_runtime_put_sync(&timer->pdev->dev)) {
> + dev_dbg(&timer->pdev->dev, "%s:pm_runtime_put_sync() FAILED\n",
> + __func__);
> + return;
> + }
>
> timer->enabled = 0;
> }
<<snip>>
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^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 14/14] OMAP: dmtimer: pm_runtime support
2010-11-22 7:04 ` Varadarajan, Charulatha
@ 2010-11-22 7:07 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-22 7:07 UTC (permalink / raw)
To: Varadarajan, Charulatha; +Cc: linux-omap, Basak, Partha
> -----Original Message-----
> From: Varadarajan, Charulatha [mailto:charu@ti.com]
> Sent: Monday, November 22, 2010 12:34 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Basak, Partha
> Subject: Re: [PATCHv4 14/14] OMAP: dmtimer: pm_runtime support
>
> On Sat, Nov 20, 2010 at 08:09, Tarun Kanti DebBarma <tarun.kanti@ti.com>
> wrote:
> > Add pm_runtime support to dmtimer. Since dmtimer is used during
> > early boot before pm_runtime is initialized completely there are
> > provisions to enable/disable clocks directly in the code during
> > early boot.
> >
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > [p-basak2@ti.com: added pm_runtime logic in probe()]
> > Signed-off-by: Partha Basak <p-basak2@ti.com>
> > ---
> > arch/arm/plat-omap/dmtimer.c | 31 +++++++++++++++++++++++++++++--
> > 1 files changed, 29 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> > index f9285b1..83d0b66 100644
> > --- a/arch/arm/plat-omap/dmtimer.c
> > +++ b/arch/arm/plat-omap/dmtimer.c
> > @@ -45,6 +45,7 @@
> > #include <linux/module.h>
> > #include <linux/slab.h>
> > #include <mach/hardware.h>
> > +#include <linux/pm_runtime.h>
> > #include <plat/dmtimer.h>
> > #include <mach/irqs.h>
> > #include <linux/err.h>
> > @@ -345,10 +346,22 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_free);
> >
> > void omap_dm_timer_enable(struct omap_dm_timer *timer)
> > {
> > + struct dmtimer_platform_data *pdata = timer->pdev-
> >dev.platform_data;
> > +
> > if (timer->enabled)
> > return;
> >
> > - clk_enable(timer->fclk);
> > + if (unlikely(pdata->is_early_init)) {
> > + clk_enable(timer->fclk);
> > + timer->enabled = 1;
> > + return;
> > + }
>
> If timer->fclk is not going to be used after "pdata->is_early_init" is
> made zero,
> you may do a clk_put( ) of the timer->fclk because pm_runtime_* APIs are
> going to be used after pdata->is_early_init is made zero.
We need fclk throughout to be used by client driver for computing rate.
--
Tarun
>
> > +
> > + if (pm_runtime_get_sync(&timer->pdev->dev)) {
> > + dev_dbg(&timer->pdev->dev, "%s:pm_runtime_get_sync()
> FAILED\n",
> > + __func__);
> > + return;
> > + }
> >
> > timer->enabled = 1;
> > }
> > @@ -356,10 +369,22 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
> >
> > void omap_dm_timer_disable(struct omap_dm_timer *timer)
> > {
> > + struct dmtimer_platform_data *pdata = timer->pdev-
> >dev.platform_data;
> > +
> > if (!timer->enabled)
> > return;
> >
> > - clk_disable(timer->fclk);
> > + if (unlikely(pdata->is_early_init)) {
> > + clk_disable(timer->fclk);
> > + timer->enabled = 0;
>
> Ditto
>
> > + return;
> > + }
> > +
> > + if (pm_runtime_put_sync(&timer->pdev->dev)) {
> > + dev_dbg(&timer->pdev->dev, "%s:pm_runtime_put_sync()
> FAILED\n",
> > + __func__);
> > + return;
> > + }
> >
> > timer->enabled = 0;
> > }
>
> <<snip>>
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 8/14] OMAP: dmtimer: platform driver
2010-11-20 2:39 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 9/14] OMAP1: dmtimer: conversion to platform devices Tarun Kanti DebBarma
@ 2010-11-22 7:13 ` Varadarajan, Charulatha
2010-11-22 7:26 ` DebBarma, Tarun Kanti
1 sibling, 1 reply; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 7:13 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, Thara Gopinath
<<snip>>
> +static struct platform_driver omap_dmtimer_driver = {
> + .probe = omap_dm_timer_probe,
> + .remove = omap_dm_timer_remove,
> + .driver = {
> + .name = "omap-timer",
Comment from Benoit on omap devices name ( see [1] ):
"If possible, it will be better to use the "omap_" prefix in order to
start having some consitency in the omap devices name. "
[1] https://patchwork.kernel.org/patch/305082/
> + },
> +};
> +
<<snip>>
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^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
2010-11-22 6:33 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Varadarajan, Charulatha
@ 2010-11-22 7:24 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-22 7:24 UTC (permalink / raw)
To: Varadarajan, Charulatha; +Cc: linux-omap, Gopinath, Thara, Basak, Partha
> -----Original Message-----
> From: Varadarajan, Charulatha
> Sent: Monday, November 22, 2010 12:04 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Gopinath, Thara; Basak, Partha
> Subject: Re: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
>
> On Sat, Nov 20, 2010 at 08:09, Tarun Kanti DebBarma <tarun.kanti@ti.com>
> wrote:
> > From: Thara Gopinath <thara@ti.com>
> >
> > Add routines to converts dmtimers to platform devices. The device data
> > is obtained from hwmod database of respective platform and is registered
> > to device model after successful binding to driver. It also provides
> > provision to access timers during early boot when pm_runtime framework
> > is not completely up and running.
> >
> > Signed-off-by: Thara Gopinath <thara@ti.com>
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > [p-basak2@ti.com: pm_runtime logic]
>
> Where is runtime logic in this patch? The patch description says
> "pm_runtime
> framework is not completely up and running"
I have put in the wrong place.
>
> > Signed-off-by: Partha Basak <p-basak2@ti.com>
> > ---
> > arch/arm/mach-omap2/Makefile | 2 +-
> > arch/arm/mach-omap2/dmtimer.c | 296
> +++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 297 insertions(+), 1 deletions(-)
> > create mode 100644 arch/arm/mach-omap2/dmtimer.c
> >
> > diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> > index ce7b1f0..148f4d7 100644
> > --- a/arch/arm/mach-omap2/Makefile
> > +++ b/arch/arm/mach-omap2/Makefile
> > @@ -4,7 +4,7 @@
> >
> > # Common support
> > obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
> pm.o \
> > - common.o
> > + common.o dmtimer.o
> >
> > omap-2-3-common = irq.o sdrc.o
> prm2xxx_3xxx.o
> > hwmod-common = omap_hwmod.o \
> > diff --git a/arch/arm/mach-omap2/dmtimer.c b/arch/arm/mach-
> omap2/dmtimer.c
> > new file mode 100644
> > index 0000000..b5951b1
> > --- /dev/null
> > +++ b/arch/arm/mach-omap2/dmtimer.c
> > @@ -0,0 +1,296 @@
> > +/**
> > + * OMAP2PLUS Dual-Mode Timers - platform device registration
> > + *
> > + * Contains first level initialization routines which extracts timers
> > + * information from hwmod database and registers with linux device
> model.
> > + * It also has low level function to chnage the timer input clock
> source.
> > + *
> > + * Copyright (C) 2010 Texas Instruments Incorporated -
> http://www.ti.com/
> > + * Tarun Kanti DebBarma <tarun.kanti@ti.com>
> > + *
> > + * Copyright (C) 2010 Texas Instruments Incorporated
> > + * Thara Gopinath <thara@ti.com>
>
> Don't repeat the same copyright information twice:
> "Copyright (C) 2010 Texas Instruments Incorporated"
>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +#undef DEBUG
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/err.h>
> > +#include <linux/slab.h>
> > +
> > +#include <mach/irqs.h>
> > +#include <plat/dmtimer.h>
> > +#include <plat/powerdomain.h>
> > +#include <plat/omap_hwmod.h>
> > +#include <plat/omap_device.h>
> > +#include <linux/pm_runtime.h>
>
> Why is "linux/pm_runtime.h" required in this file? I don't find any use
> here.
> Also check if "plat/powerdomain.h" is required.
Thanks, this is a clean up problem. Lot of implementations were optimized.
But missed to cleanup the headers which include powerdomain.h, delay.h and
Irqs.h
>
> > +
> > +static int early_timer_count __initdata = 1;
> > +
> > +/**
> > + * omap2_dm_timer_set_src - change the timer input clock source
> > + * @pdev: timer platform device pointer
> > + * @timer_clk: current clock source
> > + * @source: array index of parent clock source
> > + */
> > +static int omap2_dm_timer_set_src(struct platform_device *pdev, int
> source)
> > +{
> > + int ret;
> > + struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
> > + struct clk *fclk = clk_get(&pdev->dev, "fck");
> > + struct clk *new_fclk;
> > + char *fclk_name = "32k_ck"; /* default name */
> > +
> > + switch(source) {
> > + case OMAP_TIMER_SRC_SYS_CLK:
> > + fclk_name = "sys_ck";
> > + break;
> > +
> > + case OMAP_TIMER_SRC_32_KHZ:
> > + fclk_name = "32k_ck";
> > + break;
> > +
> > + case OMAP_TIMER_SRC_EXT_CLK:
> > + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_1) {
> > + fclk_name = "alt_ck";
> > + break;
> > + }
> > + dev_dbg(&pdev->dev, "%s:%d: invalid clk src.\n",
> > + __func__, __LINE__);
> > + return -EINVAL;
> > + }
> > +
> > +
> > + if (IS_ERR_OR_NULL(fclk)) {
> > + dev_dbg(&pdev->dev, "%s:%d: clk_get() FAILED\n",
> > + __func__, __LINE__);
> > + return -EINVAL;
> > + }
> > +
> > + new_fclk = clk_get(&pdev->dev, fclk_name);
> > + if (IS_ERR_OR_NULL(new_fclk)) {
> > + dev_dbg(&pdev->dev, "%s:%d: clk_get() %s FAILED\n",
> > + __func__, __LINE__, fclk_name);
> > + clk_put(fclk);
> > + return -EINVAL;
> > + }
> > +
> > + ret = clk_set_parent(fclk, new_fclk);
> > + if (IS_ERR_VALUE(ret)) {
> > + dev_dbg(&pdev->dev, "%s:clk_set_parent() to %s
> FAILED\n",
> > + __func__, fclk_name);
> > + ret = -EINVAL;
> > + }
> > +
> > + clk_put(new_fclk);
> > + clk_put(fclk);
> > +
> > + return ret;
> > +}
> > +
> > +struct omap_device_pm_latency omap2_dmtimer_latency[] = {
> > + {
> > + .deactivate_func = omap_device_idle_hwmods,
> > + .activate_func = omap_device_enable_hwmods,
> > + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
> > + },
> > +};
> > +
> > +/**
> > + * omap_dm_timer_early_init - build and register early timer device
> > + * with an associated timer hwmod
> > + * @oh: timer hwmod pointer to be used to build timer device
> > + * @user: parameter that can be passed from calling hwmod API
> > + *
> > + * early init is called in the last part of omap2_init_common_hw
> > + * for each early timer class using omap_hwmod_for_each_by_class.
> > + * it registers each of the timer devices present in the system.
> > + * at the end of function call memory is allocated for omap_device
> > + * and hwmod for early timer and the device is registered to the
> > + * framework ready to be probed by the driver.
> > + */
> > +static int __init omap2_timer_early_init(struct omap_hwmod *oh, void
> *user)
>
> Again a repeat comment from other hwmod reviews:
> if "user" is not used, rename it as "unused"
Ok.
>
> > +{
> > + int id;
> > + int ret = 0;
> > + char *name = "omap-timer";
> > + struct dmtimer_platform_data *pdata;
> > + struct omap_device *od;
> > +
> > + pr_debug("%s:%s\n", __func__, oh->name);
> > +
> > + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> > + if (!pdata) {
> > + pr_err("%s: No memory for [%s]\n", __func__, oh->name);
> > + return -ENOMEM;
> > + }
> > +
> > + pdata->is_early_init = 1;
> > +
> > + /* hook clock set/get functions */
> > + pdata->set_timer_src = omap2_dm_timer_set_src;
> > +
> > + /* read timer ip version */
> > + pdata->timer_ip_type = oh->class->rev;
> > + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
> > + pdata->func_offst = 0x14;
> > + pdata->intr_offst = 0x10;
> > + } else {
> > + pdata->func_offst = 0;
> > + pdata->intr_offst = 0;
> > + }
> > +
> > + /*
> > + * extract the id from name filed in hwmod database
> > + * and use the same for constructing ids' for the
> > + * timer devices. in a way, we are avoiding usage of
> > + * static variable witin the function to do the same.
> > + * CAUTION: we have to be careful and make sure the
> > + * name in hwmod database does not change in which case
> > + * we might either make corresponding change here or
> > + * switch back static variable mechanism.
> > + */
> > + sscanf(oh->name, "timer%2d", &id);
> > +
> > + od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
> > + omap2_dmtimer_latency,
> > + ARRAY_SIZE(omap2_dmtimer_latency), 1);
> > +
> > + if (IS_ERR(od)) {
> > + pr_err("%s: Cant build omap_device for %s:%s.\n",
> > + __func__, name, oh->name);
> > + ret = -EINVAL;
> > + } else
> > + early_timer_count++;
> > + /*
> > + * pdata can be freed because omap_device_build
> > + * creates its own memory pool
> > + */
>
> No need to mention this.
OK, I will remove.
>
> > + kfree(pdata);
> > +
> > + return ret;
> > +}
> > +
> > +/**
> > + * omap2_dm_timer_init - build and register timer device with an
> > + * associated timer hwmod
> > + * @oh: timer hwmod pointer to be used to build timer device
> > + * @user: parameter that can be passed from calling hwmod API
> > + *
> > + * called by omap_hwmod_for_each_by_class to register each of the timer
> > + * devices present in the system. the number of timer devices is known
> > + * by parsing through the hwmod database for a given class name. at the
> > + * end of function call memory is allocated for omap_device and hwmod
> > + * for timer and the device is registered to the framework ready to be
> > + * proved by the driver.
> > + */
> > +static int __init omap2_timer_init(struct omap_hwmod *oh, void *user)
>
> omap2_timer_init() and omap2_timer_early_init() looks similar except for
> pdata->is_early_init value. Why not have a common function and call it
> with appropriate pdata->is_early_init value?
>
> > +{
> > + int id;
> > + int ret = 0;
> > + char *name = "omap-timer";
> > + struct omap_device *od;
> > + struct dmtimer_platform_data *pdata;
> > +
> > + if (!oh) {
> > + pr_err("%s:NULL hwmod pointer (oh)\n", __func__);
> > + return -EINVAL;
> > + }
> > + pr_debug("%s:%s\n", __func__, oh->name);
> > +
> > + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> > + if (!pdata) {
> > + pr_err("%s:No memory for [%s]\n", __func__, oh->name);
> > + return -ENOMEM;
> > + }
> > +
> > + pdata->is_early_init = 0;
> > +
> > + /* hook clock set/get functions */
> > + pdata->set_timer_src = omap2_dm_timer_set_src;
> > +
> > + /* read timer ip version */
> > + pdata->timer_ip_type = oh->class->rev;
> > + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
> > + pdata->func_offst = 0x14;
> > + pdata->intr_offst = 0x10;
> > + } else {
> > + pdata->func_offst = 0;
> > + pdata->intr_offst = 0;
> > + }
> > +
> > + /*
> > + * extract the id from name filed in hwmod database
> > + * and use the same for constructing ids' for the
> > + * timer devices. in a way, we are avoiding usage of
> > + * static variable witin the function to do the same.
> > + * CAUTION: we have to be careful and make sure the
> > + * name in hwmod database does not change in which case
> > + * we might either make corresponding change here or
> > + * switch back static variable mechanism.
> > + */
> > + sscanf(oh->name, "timer%2d", &id);
> > +
> > + od = omap_device_build(name, id, oh,
> > + pdata, sizeof(*pdata),
> > + omap2_dmtimer_latency,
> > + ARRAY_SIZE(omap2_dmtimer_latency), 0);
> > +
> > + if (IS_ERR(od)) {
> > + pr_err("%s: Cant build omap_device for %s:%s.\n",
> > + __func__, name, oh->name);
> > + ret = -EINVAL;
> > + }
> > + /*
> > + * pdata can be freed because omap_device_build
> > + * creates its own memory pool
> > + */
>
> Ditto.
OK.
>
> > + kfree(pdata);
> > + return ret;
> > +}
> > +
> > +/**
> > + * omap2_dm_timer_early_init - top level early timer initialization
> > + * called in the last part of omap2_init_common_hw
> > + *
> > + * uses dedicated hwmod api to parse through hwmod database for
> > + * given class name and then build and register the timer device.
> > + * at the end driver is registered and early probe initiated.
> > + */
> > +void __init omap2_dm_timer_early_init(void)
> > +{
> > + if (omap_hwmod_for_each_by_class("timer",
> > + omap2_timer_early_init, NULL)) {
> > + pr_debug("%s: device registration FAILED\n", __func__);
> > + return;
> > + }
> > + early_platform_driver_register_all("earlytimer");
> > + early_platform_driver_probe("earlytimer", early_timer_count, 0);
> > +}
> > +
> > +/**
> > + * omap_timer_init - top level timer device initialization
> > + *
> > + * uses dedicated hwmod api to parse through hwmod database for
> > + * given class names and then build and register the timer device.
> > + */
> > +static int __init omap2_dmtimer_device_init(void)
> > +{
> > + int ret = omap_hwmod_for_each_by_class("timer",
> omap2_timer_init, NULL);
> > +
> > + if (unlikely(ret))
> > + pr_debug("%s: device registration FAILED\n", __func__);
> > +
> > + return ret;
> > +}
> > +arch_initcall(omap2_dmtimer_device_init);
> > --
> > 1.6.0.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> >
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 8/14] OMAP: dmtimer: platform driver
2010-11-22 7:13 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Varadarajan, Charulatha
@ 2010-11-22 7:26 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-22 7:26 UTC (permalink / raw)
To: Varadarajan, Charulatha; +Cc: linux-omap, Gopinath, Thara
> -----Original Message-----
> From: Varadarajan, Charulatha [mailto:charu@ti.com]
> Sent: Monday, November 22, 2010 12:43 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Gopinath, Thara
> Subject: Re: [PATCHv4 8/14] OMAP: dmtimer: platform driver
>
> <<snip>>
>
> > +static struct platform_driver omap_dmtimer_driver = {
> > + .probe = omap_dm_timer_probe,
> > + .remove = omap_dm_timer_remove,
> > + .driver = {
> > + .name = "omap-timer",
>
> Comment from Benoit on omap devices name ( see [1] ):
>
> "If possible, it will be better to use the "omap_" prefix in order to
> start having some consitency in the omap devices name. "
I can change.
--
Tarun
>
> [1] https://patchwork.kernel.org/patch/305082/
>
> > + },
> > +};
> > +
>
> <<snip>>
--
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
2010-11-20 2:39 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Tarun Kanti DebBarma
2010-11-22 6:33 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Varadarajan, Charulatha
@ 2010-11-22 8:24 ` Varadarajan, Charulatha
2010-11-22 9:00 ` DebBarma, Tarun Kanti
2010-11-23 17:51 ` Cousson, Benoit
3 siblings, 1 reply; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 8:24 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, Thara Gopinath, Partha Basak
<<snip>>
> +/**
> + * omap_timer_init - top level timer device initialization
> + *
> + * uses dedicated hwmod api to parse through hwmod database for
> + * given class names and then build and register the timer device.
> + */
> +static int __init omap2_dmtimer_device_init(void)
> +{
> + int ret = omap_hwmod_for_each_by_class("timer", omap2_timer_init, NULL);
> +
> + if (unlikely(ret))
> + pr_debug("%s: device registration FAILED\n", __func__);
> +
> + return ret;
> +}
> +arch_initcall(omap2_dmtimer_device_init);
While introducing this, calls to omap_dm_timer_init() should be
removed. Else, the init
will happen twice for dmtimer devices
> --
> 1.6.0.4
>
--
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^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
2010-11-22 8:24 ` Varadarajan, Charulatha
@ 2010-11-22 9:00 ` DebBarma, Tarun Kanti
2010-11-22 9:03 ` Varadarajan, Charulatha
0 siblings, 1 reply; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-22 9:00 UTC (permalink / raw)
To: Varadarajan, Charulatha; +Cc: linux-omap, Gopinath, Thara, Basak, Partha
> -----Original Message-----
> From: Varadarajan, Charulatha
> Sent: Monday, November 22, 2010 1:55 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Gopinath, Thara; Basak, Partha
> Subject: Re: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
>
> <<snip>>
>
> > +/**
> > + * omap_timer_init - top level timer device initialization
> > + *
> > + * uses dedicated hwmod api to parse through hwmod database for
> > + * given class names and then build and register the timer device.
> > + */
> > +static int __init omap2_dmtimer_device_init(void)
> > +{
> > + int ret = omap_hwmod_for_each_by_class("timer",
> omap2_timer_init, NULL);
> > +
> > + if (unlikely(ret))
> > + pr_debug("%s: device registration FAILED\n", __func__);
> > +
> > + return ret;
> > +}
> > +arch_initcall(omap2_dmtimer_device_init);
>
> While introducing this, calls to omap_dm_timer_init() should be
> removed. Else, the init
> will happen twice for dmtimer devices
This function is called only when the switch-over takes place.
That is why you still see the omap_dm_timer_init().
So this is more to do with organizing the patch.
I could have introduced this init code as part of platform driver
Swith-over.
--
Tarun
>
> > --
> > 1.6.0.4
> >
--
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
2010-11-22 9:00 ` DebBarma, Tarun Kanti
@ 2010-11-22 9:03 ` Varadarajan, Charulatha
0 siblings, 0 replies; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 9:03 UTC (permalink / raw)
To: DebBarma, Tarun Kanti; +Cc: linux-omap, Gopinath, Thara, Basak, Partha
On Mon, Nov 22, 2010 at 14:30, DebBarma, Tarun Kanti <tarun.kanti@ti.com> wrote:
>> -----Original Message-----
>> From: Varadarajan, Charulatha
>> Sent: Monday, November 22, 2010 1:55 PM
>> To: DebBarma, Tarun Kanti
>> Cc: linux-omap@vger.kernel.org; Gopinath, Thara; Basak, Partha
>> Subject: Re: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
>>
>> <<snip>>
>>
>> > +/**
>> > + * omap_timer_init - top level timer device initialization
>> > + *
>> > + * uses dedicated hwmod api to parse through hwmod database for
>> > + * given class names and then build and register the timer device.
>> > + */
>> > +static int __init omap2_dmtimer_device_init(void)
>> > +{
>> > + int ret = omap_hwmod_for_each_by_class("timer",
>> omap2_timer_init, NULL);
>> > +
>> > + if (unlikely(ret))
>> > + pr_debug("%s: device registration FAILED\n", __func__);
>> > +
>> > + return ret;
>> > +}
>> > +arch_initcall(omap2_dmtimer_device_init);
>>
>> While introducing this, calls to omap_dm_timer_init() should be
>> removed. Else, the init
>> will happen twice for dmtimer devices
> This function is called only when the switch-over takes place.
> That is why you still see the omap_dm_timer_init().
> So this is more to do with organizing the patch.
Exactly. Please take care of this.
> I could have introduced this init code as part of platform driver
> Swith-over.
>
> --
> Tarun
>
>>
>> > --
>> > 1.6.0.4
>> >
>
--
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^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver
2010-11-22 6:44 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Varadarajan, Charulatha
@ 2010-11-22 9:14 ` DebBarma, Tarun Kanti
2010-11-22 12:00 ` Varadarajan, Charulatha
0 siblings, 1 reply; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-22 9:14 UTC (permalink / raw)
To: Varadarajan, Charulatha; +Cc: linux-omap
> -----Original Message-----
> From: Varadarajan, Charulatha
> Sent: Monday, November 22, 2010 12:15 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org
> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device
> driver
>
> <<snip>>
>
> > -/*
> > - * Reads timer registers in posted and non-posted mode. The posted mode
> bit
> > - * is encoded in reg. Note that in posted mode write pending bit must
> be
> > - * checked. Otherwise a read of a non completed write will produce an
> error.
> > +/**
> > + * omap_dm_timer_read_reg - read timer registers in posted and non-
> posted mode
> > + * @timer: timer pointer over which read operation to perform
> > + * @reg: lowest byte holds the register offset
> > + *
> > + * The posted mode bit is encoded in reg. Note that in posted mode
> write
> > + * pending bit must be checked. Otherwise a read of a non completed
> write
> > + * will produce an error.
> > */
> > static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer,
> u32 reg)
> > {
> > + struct dmtimer_platform_data *pdata = timer->pdev-
> >dev.platform_data;
> > +
> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> > + reg += pdata->func_offst;
> > +
> > if (timer->posted)
> > - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG
> & 0xff))
> > - & (reg >> WPSHIFT))
> > + while (readl(timer->io_base +
> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
> > + & 0xff)) & (reg >> WPSHIFT))
>
> You may add a timeout in this.
There are few reasons why I have not done:
(1) This was in this way from the beginning and I thought some analysis
Was done already for not adding timeout and so did not wish to alter that.
(2) wanted to keep low level functions as simple as possible by avoiding
As many checks as possible unless really needed.
(3) The client driver can take care of timeout. Even if timeout is
Introduced in this api, the client driver anyways have to check for the
Timeout.
--
Tarun
>
> > cpu_relax();
> > return readl(timer->io_base + (reg & 0xff));
> > }
> >
> > -/*
> > - * Writes timer registers in posted and non-posted mode. The posted
> mode bit
> > - * is encoded in reg. Note that in posted mode the write pending bit
> must be
> > - * checked. Otherwise a write on a register which has a pending write
> will be
> > - * lost.
> > +/**
> > + * omap_dm_timer_write_reg - write timer registers in posted and non-
> posted mode
> > + * @timer: timer pointer over which write operation is to perform
> > + * @reg: lowest byte holds the register offset
> > + * @value: data to write into the register
> > + *
> > + * The posted mode bit is encoded in reg. Note that in posted mode the
> write
> > + * pending bit must be checked. Otherwise a write on a register which
> has a
> > + * pending write will be lost.
> > */
> > static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32
> reg,
> > u32 value)
> > {
> > + struct dmtimer_platform_data *pdata = timer->pdev-
> >dev.platform_data;
> > +
> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> > + reg += pdata->func_offst;
> > +
> > if (timer->posted)
> > - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG
> & 0xff))
> > - & (reg >> WPSHIFT))
> > + while (readl(timer->io_base +
> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
> > + & 0xff)) & (reg >> WPSHIFT))
>
> Ditto.
>
> > cpu_relax();
> > writel(value, timer->io_base + (reg & 0xff));
> > }
>
>
> <<snip>>
--
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver
2010-11-22 9:14 ` DebBarma, Tarun Kanti
@ 2010-11-22 12:00 ` Varadarajan, Charulatha
2010-11-22 12:08 ` DebBarma, Tarun Kanti
0 siblings, 1 reply; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 12:00 UTC (permalink / raw)
To: DebBarma, Tarun Kanti; +Cc: linux-omap
On Mon, Nov 22, 2010 at 14:44, DebBarma, Tarun Kanti <tarun.kanti@ti.com> wrote:
>> -----Original Message-----
>> From: Varadarajan, Charulatha
>> Sent: Monday, November 22, 2010 12:15 PM
>> To: DebBarma, Tarun Kanti
>> Cc: linux-omap@vger.kernel.org
>> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device
>> driver
>>
>> <<snip>>
>>
>> > -/*
>> > - * Reads timer registers in posted and non-posted mode. The posted mode
>> bit
>> > - * is encoded in reg. Note that in posted mode write pending bit must
>> be
>> > - * checked. Otherwise a read of a non completed write will produce an
>> error.
>> > +/**
>> > + * omap_dm_timer_read_reg - read timer registers in posted and non-
>> posted mode
>> > + * @timer: timer pointer over which read operation to perform
>> > + * @reg: lowest byte holds the register offset
>> > + *
>> > + * The posted mode bit is encoded in reg. Note that in posted mode
>> write
>> > + * pending bit must be checked. Otherwise a read of a non completed
>> write
>> > + * will produce an error.
>> > */
>> > static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer,
>> u32 reg)
>> > {
>> > + struct dmtimer_platform_data *pdata = timer->pdev-
>> >dev.platform_data;
>> > +
>> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
>> > + reg += pdata->func_offst;
>> > +
>> > if (timer->posted)
>> > - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG
>> & 0xff))
>> > - & (reg >> WPSHIFT))
>> > + while (readl(timer->io_base +
>> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
>> > + & 0xff)) & (reg >> WPSHIFT))
>>
>> You may add a timeout in this.
> There are few reasons why I have not done:
> (1) This was in this way from the beginning and I thought some analysis
> Was done already for not adding timeout and so did not wish to alter that.
> (2) wanted to keep low level functions as simple as possible by avoiding
> As many checks as possible unless really needed.
> (3) The client driver can take care of timeout. Even if timeout is
> Introduced in this api, the client driver anyways have to check for the
> Timeout.
I don't think that client driver should take care of this. The client
driver should
check only for the return value. If timeout, return error.
In your case, one of the calls to omap_dm_timer_write_reg() is as given below:
omap2_gp_timer_init()
-> omap2_gp_clockevent_init()
-> omap_dm_timer_request_specific()
-> omap_dm_timer_prepare()
-> omap_dm_timer_write_reg()
Here timeout is not taken care.
>
> --
> Tarun
>>
>> > cpu_relax();
>> > return readl(timer->io_base + (reg & 0xff));
>> > }
>> >
>> > -/*
>> > - * Writes timer registers in posted and non-posted mode. The posted
>> mode bit
>> > - * is encoded in reg. Note that in posted mode the write pending bit
>> must be
>> > - * checked. Otherwise a write on a register which has a pending write
>> will be
>> > - * lost.
>> > +/**
>> > + * omap_dm_timer_write_reg - write timer registers in posted and non-
>> posted mode
>> > + * @timer: timer pointer over which write operation is to perform
>> > + * @reg: lowest byte holds the register offset
>> > + * @value: data to write into the register
>> > + *
>> > + * The posted mode bit is encoded in reg. Note that in posted mode the
>> write
>> > + * pending bit must be checked. Otherwise a write on a register which
>> has a
>> > + * pending write will be lost.
>> > */
>> > static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32
>> reg,
>> > u32 value)
>> > {
>> > + struct dmtimer_platform_data *pdata = timer->pdev-
>> >dev.platform_data;
>> > +
>> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
>> > + reg += pdata->func_offst;
>> > +
>> > if (timer->posted)
>> > - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG
>> & 0xff))
>> > - & (reg >> WPSHIFT))
>> > + while (readl(timer->io_base +
>> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
>> > + & 0xff)) & (reg >> WPSHIFT))
>>
>> Ditto.
>>
>> > cpu_relax();
>> > writel(value, timer->io_base + (reg & 0xff));
>> > }
>>
>>
>> <<snip>>
>
--
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^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver
2010-11-22 12:00 ` Varadarajan, Charulatha
@ 2010-11-22 12:08 ` DebBarma, Tarun Kanti
2010-11-22 12:35 ` Varadarajan, Charulatha
0 siblings, 1 reply; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-22 12:08 UTC (permalink / raw)
To: Varadarajan, Charulatha; +Cc: linux-omap
> -----Original Message-----
> From: Varadarajan, Charulatha
> Sent: Monday, November 22, 2010 5:30 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org
> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device
> driver
>
> On Mon, Nov 22, 2010 at 14:44, DebBarma, Tarun Kanti <tarun.kanti@ti.com>
> wrote:
> >> -----Original Message-----
> >> From: Varadarajan, Charulatha
> >> Sent: Monday, November 22, 2010 12:15 PM
> >> To: DebBarma, Tarun Kanti
> >> Cc: linux-omap@vger.kernel.org
> >> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform
> device
> >> driver
> >>
> >> <<snip>>
> >>
> >> > -/*
> >> > - * Reads timer registers in posted and non-posted mode. The posted
> mode
> >> bit
> >> > - * is encoded in reg. Note that in posted mode write pending bit
> must
> >> be
> >> > - * checked. Otherwise a read of a non completed write will produce
> an
> >> error.
> >> > +/**
> >> > + * omap_dm_timer_read_reg - read timer registers in posted and non-
> >> posted mode
> >> > + * @timer: timer pointer over which read operation to perform
> >> > + * @reg: lowest byte holds the register offset
> >> > + *
> >> > + * The posted mode bit is encoded in reg. Note that in posted mode
> >> write
> >> > + * pending bit must be checked. Otherwise a read of a non completed
> >> write
> >> > + * will produce an error.
> >> > */
> >> > static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer
> *timer,
> >> u32 reg)
> >> > {
> >> > + struct dmtimer_platform_data *pdata = timer->pdev-
> >> >dev.platform_data;
> >> > +
> >> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> >> > + reg += pdata->func_offst;
> >> > +
> >> > if (timer->posted)
> >> > - while (readl(timer->io_base +
> (OMAP_TIMER_WRITE_PEND_REG
> >> & 0xff))
> >> > - & (reg >> WPSHIFT))
> >> > + while (readl(timer->io_base +
> >> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata-
> >func_offst)
> >> > + & 0xff)) & (reg >> WPSHIFT))
> >>
> >> You may add a timeout in this.
> > There are few reasons why I have not done:
> > (1) This was in this way from the beginning and I thought some analysis
> > Was done already for not adding timeout and so did not wish to alter
> that.
> > (2) wanted to keep low level functions as simple as possible by avoiding
> > As many checks as possible unless really needed.
> > (3) The client driver can take care of timeout. Even if timeout is
> > Introduced in this api, the client driver anyways have to check for the
> > Timeout.
>
> I don't think that client driver should take care of this. The client
> driver should
> check only for the return value. If timeout, return error.
So what I am saying is it can add the timeout instead of checking for the
Return value. This would keep the low level function simple.
Please try to understand that this is a common function called by all the
Client drivers associated with all the timers. If you can reduce a check
The benefit is tremendous.
--
Tarun
>
> In your case, one of the calls to omap_dm_timer_write_reg() is as given
> below:
> omap2_gp_timer_init()
> -> omap2_gp_clockevent_init()
> -> omap_dm_timer_request_specific()
> -> omap_dm_timer_prepare()
> -> omap_dm_timer_write_reg()
>
> Here timeout is not taken care.
>
> >
> > --
> > Tarun
> >>
> >> > cpu_relax();
> >> > return readl(timer->io_base + (reg & 0xff));
> >> > }
> >> >
> >> > -/*
> >> > - * Writes timer registers in posted and non-posted mode. The posted
> >> mode bit
> >> > - * is encoded in reg. Note that in posted mode the write pending bit
> >> must be
> >> > - * checked. Otherwise a write on a register which has a pending
> write
> >> will be
> >> > - * lost.
> >> > +/**
> >> > + * omap_dm_timer_write_reg - write timer registers in posted and
> non-
> >> posted mode
> >> > + * @timer: timer pointer over which write operation is to
> perform
> >> > + * @reg: lowest byte holds the register offset
> >> > + * @value: data to write into the register
> >> > + *
> >> > + * The posted mode bit is encoded in reg. Note that in posted mode
> the
> >> write
> >> > + * pending bit must be checked. Otherwise a write on a register
> which
> >> has a
> >> > + * pending write will be lost.
> >> > */
> >> > static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32
> >> reg,
> >> > u32 value)
> >> > {
> >> > + struct dmtimer_platform_data *pdata = timer->pdev-
> >> >dev.platform_data;
> >> > +
> >> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> >> > + reg += pdata->func_offst;
> >> > +
> >> > if (timer->posted)
> >> > - while (readl(timer->io_base +
> (OMAP_TIMER_WRITE_PEND_REG
> >> & 0xff))
> >> > - & (reg >> WPSHIFT))
> >> > + while (readl(timer->io_base +
> >> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata-
> >func_offst)
> >> > + & 0xff)) & (reg >> WPSHIFT))
> >>
> >> Ditto.
> >>
> >> > cpu_relax();
> >> > writel(value, timer->io_base + (reg & 0xff));
> >> > }
> >>
> >>
> >> <<snip>>
> >
--
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver
2010-11-22 12:08 ` DebBarma, Tarun Kanti
@ 2010-11-22 12:35 ` Varadarajan, Charulatha
2010-11-22 12:55 ` DebBarma, Tarun Kanti
0 siblings, 1 reply; 42+ messages in thread
From: Varadarajan, Charulatha @ 2010-11-22 12:35 UTC (permalink / raw)
To: DebBarma, Tarun Kanti; +Cc: linux-omap
On Mon, Nov 22, 2010 at 17:38, DebBarma, Tarun Kanti <tarun.kanti@ti.com> wrote:
>
>> -----Original Message-----
>> From: Varadarajan, Charulatha
>> Sent: Monday, November 22, 2010 5:30 PM
>> To: DebBarma, Tarun Kanti
>> Cc: linux-omap@vger.kernel.org
>> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device
>> driver
>>
>> On Mon, Nov 22, 2010 at 14:44, DebBarma, Tarun Kanti <tarun.kanti@ti.com>
>> wrote:
>> >> -----Original Message-----
>> >> From: Varadarajan, Charulatha
>> >> Sent: Monday, November 22, 2010 12:15 PM
>> >> To: DebBarma, Tarun Kanti
>> >> Cc: linux-omap@vger.kernel.org
>> >> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform
>> device
>> >> driver
>> >>
>> >> <<snip>>
>> >>
>> >> > -/*
>> >> > - * Reads timer registers in posted and non-posted mode. The posted
>> mode
>> >> bit
>> >> > - * is encoded in reg. Note that in posted mode write pending bit
>> must
>> >> be
>> >> > - * checked. Otherwise a read of a non completed write will produce
>> an
>> >> error.
>> >> > +/**
>> >> > + * omap_dm_timer_read_reg - read timer registers in posted and non-
>> >> posted mode
>> >> > + * @timer: timer pointer over which read operation to perform
>> >> > + * @reg: lowest byte holds the register offset
>> >> > + *
>> >> > + * The posted mode bit is encoded in reg. Note that in posted mode
>> >> write
>> >> > + * pending bit must be checked. Otherwise a read of a non completed
>> >> write
>> >> > + * will produce an error.
>> >> > */
>> >> > static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer
>> *timer,
>> >> u32 reg)
>> >> > {
>> >> > + struct dmtimer_platform_data *pdata = timer->pdev-
>> >> >dev.platform_data;
>> >> > +
>> >> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
>> >> > + reg += pdata->func_offst;
>> >> > +
>> >> > if (timer->posted)
>> >> > - while (readl(timer->io_base +
>> (OMAP_TIMER_WRITE_PEND_REG
>> >> & 0xff))
>> >> > - & (reg >> WPSHIFT))
>> >> > + while (readl(timer->io_base +
>> >> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata-
>> >func_offst)
>> >> > + & 0xff)) & (reg >> WPSHIFT))
>> >>
>> >> You may add a timeout in this.
>> > There are few reasons why I have not done:
>> > (1) This was in this way from the beginning and I thought some analysis
>> > Was done already for not adding timeout and so did not wish to alter
>> that.
>> > (2) wanted to keep low level functions as simple as possible by avoiding
>> > As many checks as possible unless really needed.
>> > (3) The client driver can take care of timeout. Even if timeout is
>> > Introduced in this api, the client driver anyways have to check for the
>> > Timeout.
>>
>> I don't think that client driver should take care of this. The client
>> driver should
>> check only for the return value. If timeout, return error.
> So what I am saying is it can add the timeout instead of checking for the
> Return value. This would keep the low level function simple.
> Please try to understand that this is a common function called by all the
> Client drivers associated with all the timers. If you can reduce a check
> The benefit is tremendous.
I do not agree. If low level driver functions are using these common read/write
functions, there is a possibility of getting struck up in the while loop since
there is no timeout. If you think that there is no possibility of timeout when
called from low level driver functions, remove the while loop unless if it is
really required.
If these functions uses while loops, please have a timeout error. Otherwise,
analyze and remove the while loop from these functions.
>
> --
> Tarun
>
>>
>> In your case, one of the calls to omap_dm_timer_write_reg() is as given
>> below:
>> omap2_gp_timer_init()
>> -> omap2_gp_clockevent_init()
>> -> omap_dm_timer_request_specific()
>> -> omap_dm_timer_prepare()
>> -> omap_dm_timer_write_reg()
>>
>> Here timeout is not taken care.
>>
>> >
>> > --
>> > Tarun
>> >>
>> >> > cpu_relax();
>> >> > return readl(timer->io_base + (reg & 0xff));
>> >> > }
>> >> >
>> >> > -/*
>> >> > - * Writes timer registers in posted and non-posted mode. The posted
>> >> mode bit
>> >> > - * is encoded in reg. Note that in posted mode the write pending bit
>> >> must be
>> >> > - * checked. Otherwise a write on a register which has a pending
>> write
>> >> will be
>> >> > - * lost.
>> >> > +/**
>> >> > + * omap_dm_timer_write_reg - write timer registers in posted and
>> non-
>> >> posted mode
>> >> > + * @timer: timer pointer over which write operation is to
>> perform
>> >> > + * @reg: lowest byte holds the register offset
>> >> > + * @value: data to write into the register
>> >> > + *
>> >> > + * The posted mode bit is encoded in reg. Note that in posted mode
>> the
>> >> write
>> >> > + * pending bit must be checked. Otherwise a write on a register
>> which
>> >> has a
>> >> > + * pending write will be lost.
>> >> > */
>> >> > static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32
>> >> reg,
>> >> > u32 value)
>> >> > {
>> >> > + struct dmtimer_platform_data *pdata = timer->pdev-
>> >> >dev.platform_data;
>> >> > +
>> >> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
>> >> > + reg += pdata->func_offst;
>> >> > +
>> >> > if (timer->posted)
>> >> > - while (readl(timer->io_base +
>> (OMAP_TIMER_WRITE_PEND_REG
>> >> & 0xff))
>> >> > - & (reg >> WPSHIFT))
>> >> > + while (readl(timer->io_base +
>> >> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata-
>> >func_offst)
>> >> > + & 0xff)) & (reg >> WPSHIFT))
>> >>
>> >> Ditto.
>> >>
>> >> > cpu_relax();
>> >> > writel(value, timer->io_base + (reg & 0xff));
>> >> > }
>> >>
>> >>
>> >> <<snip>>
>> >
>
--
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the body of a message to majordomo@vger.kernel.org
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^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver
2010-11-22 12:35 ` Varadarajan, Charulatha
@ 2010-11-22 12:55 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-22 12:55 UTC (permalink / raw)
To: Varadarajan, Charulatha, Cousson, Benoit; +Cc: linux-omap
Charu and Benoit,
> -----Original Message-----
> From: Varadarajan, Charulatha
> Sent: Monday, November 22, 2010 6:05 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org
> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device
> driver
>
> On Mon, Nov 22, 2010 at 17:38, DebBarma, Tarun Kanti <tarun.kanti@ti.com>
> wrote:
> >
> >> -----Original Message-----
> >> From: Varadarajan, Charulatha
> >> Sent: Monday, November 22, 2010 5:30 PM
> >> To: DebBarma, Tarun Kanti
> >> Cc: linux-omap@vger.kernel.org
> >> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform
> device
> >> driver
> >>
> >> On Mon, Nov 22, 2010 at 14:44, DebBarma, Tarun Kanti
> <tarun.kanti@ti.com>
> >> wrote:
> >> >> -----Original Message-----
> >> >> From: Varadarajan, Charulatha
> >> >> Sent: Monday, November 22, 2010 12:15 PM
> >> >> To: DebBarma, Tarun Kanti
> >> >> Cc: linux-omap@vger.kernel.org
> >> >> Subject: Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform
> >> device
> >> >> driver
> >> >>
> >> >> <<snip>>
> >> >>
> >> >> > -/*
> >> >> > - * Reads timer registers in posted and non-posted mode. The
> posted
> >> mode
> >> >> bit
> >> >> > - * is encoded in reg. Note that in posted mode write pending bit
> >> must
> >> >> be
> >> >> > - * checked. Otherwise a read of a non completed write will
> produce
> >> an
> >> >> error.
> >> >> > +/**
> >> >> > + * omap_dm_timer_read_reg - read timer registers in posted and
> non-
> >> >> posted mode
> >> >> > + * @timer: timer pointer over which read operation to
> perform
> >> >> > + * @reg: lowest byte holds the register offset
> >> >> > + *
> >> >> > + * The posted mode bit is encoded in reg. Note that in posted
> mode
> >> >> write
> >> >> > + * pending bit must be checked. Otherwise a read of a non
> completed
> >> >> write
> >> >> > + * will produce an error.
> >> >> > */
> >> >> > static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer
> >> *timer,
> >> >> u32 reg)
> >> >> > {
> >> >> > + struct dmtimer_platform_data *pdata = timer->pdev-
> >> >> >dev.platform_data;
> >> >> > +
> >> >> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> >> >> > + reg += pdata->func_offst;
> >> >> > +
> >> >> > if (timer->posted)
> >> >> > - while (readl(timer->io_base +
> >> (OMAP_TIMER_WRITE_PEND_REG
> >> >> & 0xff))
> >> >> > - & (reg >> WPSHIFT))
> >> >> > + while (readl(timer->io_base +
> >> >> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata-
> >> >func_offst)
> >> >> > + & 0xff)) & (reg >> WPSHIFT))
> >> >>
> >> >> You may add a timeout in this.
> >> > There are few reasons why I have not done:
> >> > (1) This was in this way from the beginning and I thought some
> analysis
> >> > Was done already for not adding timeout and so did not wish to alter
> >> that.
> >> > (2) wanted to keep low level functions as simple as possible by
> avoiding
> >> > As many checks as possible unless really needed.
> >> > (3) The client driver can take care of timeout. Even if timeout is
> >> > Introduced in this api, the client driver anyways have to check for
> the
> >> > Timeout.
> >>
> >> I don't think that client driver should take care of this. The client
> >> driver should
> >> check only for the return value. If timeout, return error.
> > So what I am saying is it can add the timeout instead of checking for
> the
> > Return value. This would keep the low level function simple.
> > Please try to understand that this is a common function called by all
> the
> > Client drivers associated with all the timers. If you can reduce a check
> > The benefit is tremendous.
>
> I do not agree. If low level driver functions are using these common
> read/write
> functions, there is a possibility of getting struck up in the while loop
> since
> there is no timeout. If you think that there is no possibility of timeout
> when
> called from low level driver functions, remove the while loop unless if it
> is
> really required.
>
> If these functions uses while loops, please have a timeout error.
> Otherwise,
> analyze and remove the while loop from these functions.
As long as we use *posted* mode we need the while loop check.
So the timeout can be added inside the while loop.
Benoit,
Under this circumstance I am feeling no more value for having
Separate set of low level functions for accessing the interrupt
Registers, viz. omap_dm_timer_read_intr_reg() and
omap_dm_timer_write_intr_reg() which were added to keep the
low level functions simple.
So can I go ahead and merge them within omap_dm_timer_read_reg()
And omap_dm_timer_write_reg()?
--
Tarun
> >
> >>
> >> In your case, one of the calls to omap_dm_timer_write_reg() is as given
> >> below:
> >> omap2_gp_timer_init()
> >> -> omap2_gp_clockevent_init()
> >> -> omap_dm_timer_request_specific()
> >> -> omap_dm_timer_prepare()
> >> -> omap_dm_timer_write_reg()
> >>
> >> Here timeout is not taken care.
> >>
> >> >
> >> > --
> >> > Tarun
> >> >>
> >> >> > cpu_relax();
> >> >> > return readl(timer->io_base + (reg & 0xff));
> >> >> > }
> >> >> >
> >> >> > -/*
> >> >> > - * Writes timer registers in posted and non-posted mode. The
> posted
> >> >> mode bit
> >> >> > - * is encoded in reg. Note that in posted mode the write pending
> bit
> >> >> must be
> >> >> > - * checked. Otherwise a write on a register which has a pending
> >> write
> >> >> will be
> >> >> > - * lost.
> >> >> > +/**
> >> >> > + * omap_dm_timer_write_reg - write timer registers in posted and
> >> non-
> >> >> posted mode
> >> >> > + * @timer: timer pointer over which write operation is to
> >> perform
> >> >> > + * @reg: lowest byte holds the register offset
> >> >> > + * @value: data to write into the register
> >> >> > + *
> >> >> > + * The posted mode bit is encoded in reg. Note that in posted
> mode
> >> the
> >> >> write
> >> >> > + * pending bit must be checked. Otherwise a write on a register
> >> which
> >> >> has a
> >> >> > + * pending write will be lost.
> >> >> > */
> >> >> > static void omap_dm_timer_write_reg(struct omap_dm_timer *timer,
> u32
> >> >> reg,
> >> >> > u32 value)
> >> >> > {
> >> >> > + struct dmtimer_platform_data *pdata = timer->pdev-
> >> >> >dev.platform_data;
> >> >> > +
> >> >> > + if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> >> >> > + reg += pdata->func_offst;
> >> >> > +
> >> >> > if (timer->posted)
> >> >> > - while (readl(timer->io_base +
> >> (OMAP_TIMER_WRITE_PEND_REG
> >> >> & 0xff))
> >> >> > - & (reg >> WPSHIFT))
> >> >> > + while (readl(timer->io_base +
> >> >> > + ((OMAP_TIMER_WRITE_PEND_REG + pdata-
> >> >func_offst)
> >> >> > + & 0xff)) & (reg >> WPSHIFT))
> >> >>
> >> >> Ditto.
> >> >>
> >> >> > cpu_relax();
> >> >> > writel(value, timer->io_base + (reg & 0xff));
> >> >> > }
> >> >>
> >> >>
> >> >> <<snip>>
> >> >
> >
--
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes
2010-11-20 2:39 ` [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Tarun Kanti DebBarma
@ 2010-11-22 17:32 ` Cousson, Benoit
2010-11-23 8:36 ` DebBarma, Tarun Kanti
1 sibling, 1 reply; 42+ messages in thread
From: Cousson, Benoit @ 2010-11-22 17:32 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, Gopinath, Thara
Hi Tarun,
On 11/20/2010 3:39 AM, Tarun Kanti DebBarma wrote:
> From: Thara Gopinath<thara@ti.com>
>
> Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can be
> retrieved by doing a clk_get with the corresponding device pointers or
> device names.
>
> Signed-off-by: Thara Gopinath<thara@ti.com>
> Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> ---
> arch/arm/mach-omap2/clock2420_data.c | 58 +++++++++++++++++++++++++++------
> arch/arm/mach-omap2/clock2430_data.c | 58 +++++++++++++++++++++++++++------
> arch/arm/mach-omap2/clock3xxx_data.c | 46 ++++++++++++++++++++------
> arch/arm/mach-omap2/clock44xx_data.c | 42 ++++++++++++++++++------
> 4 files changed, 161 insertions(+), 43 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
> index 21f8562..d2e90ae 100644
> --- a/arch/arm/mach-omap2/clock2420_data.c
> +++ b/arch/arm/mach-omap2/clock2420_data.c
> @@ -1803,27 +1803,27 @@ static struct omap_clk omap2420_clks[] = {
> CLK(NULL, "gpt1_ick",&gpt1_ick, CK_242X),
> CLK(NULL, "gpt1_fck",&gpt1_fck, CK_242X),
Why is the timer1 not using a clockdev with device name?
+ CLK("omap-timer.1", "fck",&gpt1_fck, CK_242X),
It is the case for all the other platforms.
Thanks,
Benoit
> CLK(NULL, "gpt2_ick",&gpt2_ick, CK_242X),
> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_242X),
> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_242X),
> CLK(NULL, "gpt3_ick",&gpt3_ick, CK_242X),
> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_242X),
> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_242X),
> CLK(NULL, "gpt4_ick",&gpt4_ick, CK_242X),
> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_242X),
> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_242X),
> CLK(NULL, "gpt5_ick",&gpt5_ick, CK_242X),
> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_242X),
> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_242X),
> CLK(NULL, "gpt6_ick",&gpt6_ick, CK_242X),
> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_242X),
> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_242X),
> CLK(NULL, "gpt7_ick",&gpt7_ick, CK_242X),
> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_242X),
> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_242X),
> CLK(NULL, "gpt8_ick",&gpt8_ick, CK_242X),
> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_242X),
> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_242X),
> CLK(NULL, "gpt9_ick",&gpt9_ick, CK_242X),
> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_242X),
> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_242X),
> CLK(NULL, "gpt10_ick",&gpt10_ick, CK_242X),
> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_242X),
> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_242X),
> CLK(NULL, "gpt11_ick",&gpt11_ick, CK_242X),
> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_242X),
> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_242X),
> CLK(NULL, "gpt12_ick",&gpt12_ick, CK_242X),
> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_242X),
> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_242X),
> CLK("omap-mcbsp.1", "ick",&mcbsp1_ick, CK_242X),
> CLK("omap-mcbsp.1", "fck",&mcbsp1_fck, CK_242X),
> CLK("omap-mcbsp.2", "ick",&mcbsp2_ick, CK_242X),
> @@ -1878,6 +1878,42 @@ static struct omap_clk omap2420_clks[] = {
> CLK(NULL, "pka_ick",&pka_ick, CK_242X),
> CLK(NULL, "usb_fck",&usb_fck, CK_242X),
> CLK("musb_hdrc", "fck",&osc_ck, CK_242X),
> + CLK("omap-timer.1", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.2", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.3", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.4", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.5", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.6", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.7", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.8", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.9", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.10", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.11", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.12", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.1", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.2", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.3", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.4", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.5", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.6", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.7", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.8", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.9", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.10", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.11", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.12", "alt_ck",&alt_ck, CK_243X),
> };
>
> /*
> diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
> index e32afcb..7861bf4 100644
> --- a/arch/arm/mach-omap2/clock2430_data.c
> +++ b/arch/arm/mach-omap2/clock2430_data.c
> @@ -1907,27 +1907,27 @@ static struct omap_clk omap2430_clks[] = {
> CLK(NULL, "gpt1_ick",&gpt1_ick, CK_243X),
> CLK(NULL, "gpt1_fck",&gpt1_fck, CK_243X),
> CLK(NULL, "gpt2_ick",&gpt2_ick, CK_243X),
> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_243X),
> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_243X),
> CLK(NULL, "gpt3_ick",&gpt3_ick, CK_243X),
> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_243X),
> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_243X),
> CLK(NULL, "gpt4_ick",&gpt4_ick, CK_243X),
> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_243X),
> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_243X),
> CLK(NULL, "gpt5_ick",&gpt5_ick, CK_243X),
> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_243X),
> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_243X),
> CLK(NULL, "gpt6_ick",&gpt6_ick, CK_243X),
> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_243X),
> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_243X),
> CLK(NULL, "gpt7_ick",&gpt7_ick, CK_243X),
> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_243X),
> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_243X),
> CLK(NULL, "gpt8_ick",&gpt8_ick, CK_243X),
> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_243X),
> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_243X),
> CLK(NULL, "gpt9_ick",&gpt9_ick, CK_243X),
> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_243X),
> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_243X),
> CLK(NULL, "gpt10_ick",&gpt10_ick, CK_243X),
> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_243X),
> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_243X),
> CLK(NULL, "gpt11_ick",&gpt11_ick, CK_243X),
> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_243X),
> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_243X),
> CLK(NULL, "gpt12_ick",&gpt12_ick, CK_243X),
> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_243X),
> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_243X),
> CLK("omap-mcbsp.1", "ick",&mcbsp1_ick, CK_243X),
> CLK("omap-mcbsp.1", "fck",&mcbsp1_fck, CK_243X),
> CLK("omap-mcbsp.2", "ick",&mcbsp2_ick, CK_243X),
> @@ -1993,6 +1993,42 @@ static struct omap_clk omap2430_clks[] = {
> CLK(NULL, "mdm_intc_ick",&mdm_intc_ick, CK_243X),
> CLK("mmci-omap-hs.0", "mmchsdb_fck",&mmchsdb1_fck, CK_243X),
> CLK("mmci-omap-hs.1", "mmchsdb_fck",&mmchsdb2_fck, CK_243X),
> + CLK("omap-timer.1", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.2", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.3", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.4", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.5", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.6", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.7", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.8", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.9", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.10", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.11", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.12", "32k_ck",&func_32k_ck, CK_243X),
> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_243X),
> + CLK("omap-timer.1", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.2", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.3", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.4", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.5", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.6", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.7", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.8", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.9", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.10", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.11", "alt_ck",&alt_ck, CK_243X),
> + CLK("omap-timer.12", "alt_ck",&alt_ck, CK_243X),
> };
>
> /*
> diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
> index d85ecd5..41685be 100644
> --- a/arch/arm/mach-omap2/clock3xxx_data.c
> +++ b/arch/arm/mach-omap2/clock3xxx_data.c
> @@ -3273,8 +3273,8 @@ static struct omap_clk omap3xxx_clks[] = {
> CLK(NULL, "modem_fck",&modem_fck, CK_343X),
> CLK(NULL, "sad2d_ick",&sad2d_ick, CK_343X),
> CLK(NULL, "mad2d_ick",&mad2d_ick, CK_343X),
> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_3XXX),
> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_3XXX),
> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_3XXX),
> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_3XXX),
> CLK(NULL, "cpefuse_fck",&cpefuse_fck, CK_3430ES2 | CK_AM35XX),
> CLK(NULL, "ts_fck",&ts_fck, CK_3430ES2 | CK_AM35XX),
> CLK(NULL, "usbtll_fck",&usbtll_fck, CK_3430ES2 | CK_AM35XX),
> @@ -3380,14 +3380,14 @@ static struct omap_clk omap3xxx_clks[] = {
> CLK(NULL, "per_48m_fck",&per_48m_fck, CK_3XXX),
> CLK(NULL, "uart3_fck",&uart3_fck, CK_3XXX),
> CLK(NULL, "uart4_fck",&uart4_fck, CK_36XX),
> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_3XXX),
> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_3XXX),
> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_3XXX),
> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_3XXX),
> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_3XXX),
> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_3XXX),
> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_3XXX),
> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_3XXX),
> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_3XXX),
> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_3XXX),
> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_3XXX),
> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_3XXX),
> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_3XXX),
> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_3XXX),
> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_3XXX),
> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_3XXX),
> CLK(NULL, "per_32k_alwon_fck",&per_32k_alwon_fck, CK_3XXX),
> CLK(NULL, "gpio6_dbck",&gpio6_dbck, CK_3XXX),
> CLK(NULL, "gpio5_dbck",&gpio5_dbck, CK_3XXX),
> @@ -3428,7 +3428,7 @@ static struct omap_clk omap3xxx_clks[] = {
> CLK(NULL, "sr2_fck",&sr2_fck, CK_343X),
> CLK(NULL, "sr_l4_ick",&sr_l4_ick, CK_343X),
> CLK(NULL, "secure_32k_fck",&secure_32k_fck, CK_3XXX),
> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_3XXX),
> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_3XXX),
> CLK(NULL, "wdt1_fck",&wdt1_fck, CK_3XXX),
> CLK(NULL, "ipss_ick",&ipss_ick, CK_AM35XX),
> CLK(NULL, "rmii_ck",&rmii_ck, CK_AM35XX),
> @@ -3441,6 +3441,30 @@ static struct omap_clk omap3xxx_clks[] = {
> CLK("musb_hdrc", "fck",&hsotgusb_fck_am35xx, CK_AM35XX),
> CLK(NULL, "hecc_ck",&hecc_ck, CK_AM35XX),
> CLK(NULL, "uart4_ick",&uart4_ick_am35xx, CK_AM35XX),
> + CLK("omap-timer.1", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.2", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.3", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.4", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.5", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.6", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.7", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.8", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.9", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.10", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.11", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.12", "32k_ck",&omap_32k_fck, CK_3XXX),
> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_3XXX),
> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_3XXX),
> };
>
>
> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
> index 1599836..d081c10 100644
> --- a/arch/arm/mach-omap2/clock44xx_data.c
> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> @@ -2922,16 +2922,16 @@ static struct omap_clk omap44xx_clks[] = {
> CLK(NULL, "smartreflex_iva_fck",&smartreflex_iva_fck, CK_443X),
> CLK(NULL, "smartreflex_mpu_fck",&smartreflex_mpu_fck, CK_443X),
> CLK(NULL, "gpt1_fck",&timer1_fck, CK_443X),
> - CLK(NULL, "gpt10_fck",&timer10_fck, CK_443X),
> - CLK(NULL, "gpt11_fck",&timer11_fck, CK_443X),
> - CLK(NULL, "gpt2_fck",&timer2_fck, CK_443X),
> - CLK(NULL, "gpt3_fck",&timer3_fck, CK_443X),
> - CLK(NULL, "gpt4_fck",&timer4_fck, CK_443X),
> - CLK(NULL, "gpt5_fck",&timer5_fck, CK_443X),
> - CLK(NULL, "gpt6_fck",&timer6_fck, CK_443X),
> - CLK(NULL, "gpt7_fck",&timer7_fck, CK_443X),
> - CLK(NULL, "gpt8_fck",&timer8_fck, CK_443X),
> - CLK(NULL, "gpt9_fck",&timer9_fck, CK_443X),
> + CLK("omap-timer.10", "fck",&timer10_fck, CK_443X),
> + CLK("omap-timer.11", "fck",&timer11_fck, CK_443X),
> + CLK("omap-timer.2", "fck",&timer2_fck, CK_443X),
> + CLK("omap-timer.3", "fck",&timer3_fck, CK_443X),
> + CLK("omap-timer.4", "fck",&timer4_fck, CK_443X),
> + CLK("omap-timer.5", "fck",&timer5_fck, CK_443X),
> + CLK("omap-timer.6", "fck",&timer6_fck, CK_443X),
> + CLK("omap-timer.7", "fck",&timer7_fck, CK_443X),
> + CLK("omap-timer.8", "fck",&timer8_fck, CK_443X),
> + CLK("omap-timer.9", "fck",&timer9_fck, CK_443X),
> CLK(NULL, "uart1_fck",&uart1_fck, CK_443X),
> CLK(NULL, "uart2_fck",&uart2_fck, CK_443X),
> CLK(NULL, "uart3_fck",&uart3_fck, CK_443X),
> @@ -2997,6 +2997,28 @@ static struct omap_clk omap44xx_clks[] = {
> CLK(NULL, "uart3_ick",&dummy_ck, CK_443X),
> CLK(NULL, "uart4_ick",&dummy_ck, CK_443X),
> CLK("omap_wdt", "ick",&dummy_ck, CK_443X),
> + CLK("omap-timer.1", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.2", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.3", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.4", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.5", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.6", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.7", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.8", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.9", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.10", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.11", "32k_ck",&sys_32k_ck, CK_443X),
> + CLK("omap-timer.1", "sys_ck",&sys_clkin_ck, CK_443X),
> + CLK("omap-timer.2", "sys_ck",&sys_clkin_ck, CK_443X),
> + CLK("omap-timer.3", "sys_ck",&sys_clkin_ck, CK_443X),
> + CLK("omap-timer.4", "sys_ck",&sys_clkin_ck, CK_443X),
> + CLK("omap-timer.9", "sys_ck",&sys_clkin_ck, CK_443X),
> + CLK("omap-timer.10", "sys_ck",&sys_clkin_ck, CK_443X),
> + CLK("omap-timer.11", "sys_ck",&sys_clkin_ck, CK_443X),
> + CLK("omap-timer.5", "sys_ck",&syc_clk_div_ck, CK_443X),
> + CLK("omap-timer.6", "sys_ck",&syc_clk_div_ck, CK_443X),
> + CLK("omap-timer.7", "sys_ck",&syc_clk_div_ck, CK_443X),
> + CLK("omap-timer.8", "sys_ck",&syc_clk_div_ck, CK_443X),
> };
>
> int __init omap4xxx_clk_init(void)
> --
> 1.6.0.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes
2010-11-22 17:32 ` [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes Cousson, Benoit
@ 2010-11-23 8:36 ` DebBarma, Tarun Kanti
2010-11-23 8:40 ` Cousson, Benoit
0 siblings, 1 reply; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-23 8:36 UTC (permalink / raw)
To: Cousson, Benoit; +Cc: linux-omap, Gopinath, Thara
Benoit,
> -----Original Message-----
> From: Cousson, Benoit
> Sent: Monday, November 22, 2010 11:03 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Gopinath, Thara
> Subject: Re: [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck
> nodes
>
> Hi Tarun,
>
> On 11/20/2010 3:39 AM, Tarun Kanti DebBarma wrote:
> > From: Thara Gopinath<thara@ti.com>
> >
> > Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can
> be
> > retrieved by doing a clk_get with the corresponding device pointers or
> > device names.
> >
> > Signed-off-by: Thara Gopinath<thara@ti.com>
> > Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> > ---
> > arch/arm/mach-omap2/clock2420_data.c | 58
> +++++++++++++++++++++++++++------
> > arch/arm/mach-omap2/clock2430_data.c | 58
> +++++++++++++++++++++++++++------
> > arch/arm/mach-omap2/clock3xxx_data.c | 46 ++++++++++++++++++++------
> > arch/arm/mach-omap2/clock44xx_data.c | 42 ++++++++++++++++++------
> > 4 files changed, 161 insertions(+), 43 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-
> omap2/clock2420_data.c
> > index 21f8562..d2e90ae 100644
> > --- a/arch/arm/mach-omap2/clock2420_data.c
> > +++ b/arch/arm/mach-omap2/clock2420_data.c
> > @@ -1803,27 +1803,27 @@ static struct omap_clk omap2420_clks[] = {
> > CLK(NULL, "gpt1_ick",&gpt1_ick, CK_242X),
> > CLK(NULL, "gpt1_fck",&gpt1_fck, CK_242X),
>
> Why is the timer1 not using a clockdev with device name?
> + CLK("omap-timer.1", "fck",&gpt1_fck, CK_242X),
>
> It is the case for all the other platforms.
Ok, this is done at later patch when we switch to platform driver.
This is done in this way because gptimer driver would not recognize
Clock access using device name until the complete switch-over happens.
This is to keep each patch compiled and booting.
--
Tarun
>
> > CLK(NULL, "gpt2_ick",&gpt2_ick, CK_242X),
> > - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_242X),
> > + CLK("omap-timer.2", "fck",&gpt2_fck, CK_242X),
> > CLK(NULL, "gpt3_ick",&gpt3_ick, CK_242X),
> > - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_242X),
> > + CLK("omap-timer.3", "fck",&gpt3_fck, CK_242X),
> > CLK(NULL, "gpt4_ick",&gpt4_ick, CK_242X),
> > - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_242X),
> > + CLK("omap-timer.4", "fck",&gpt4_fck, CK_242X),
> > CLK(NULL, "gpt5_ick",&gpt5_ick, CK_242X),
> > - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_242X),
> > + CLK("omap-timer.5", "fck",&gpt5_fck, CK_242X),
> > CLK(NULL, "gpt6_ick",&gpt6_ick, CK_242X),
> > - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_242X),
> > + CLK("omap-timer.6", "fck",&gpt6_fck, CK_242X),
> > CLK(NULL, "gpt7_ick",&gpt7_ick, CK_242X),
> > - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_242X),
> > + CLK("omap-timer.7", "fck",&gpt7_fck, CK_242X),
> > CLK(NULL, "gpt8_ick",&gpt8_ick, CK_242X),
> > - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_242X),
> > + CLK("omap-timer.8", "fck",&gpt8_fck, CK_242X),
> > CLK(NULL, "gpt9_ick",&gpt9_ick, CK_242X),
> > - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_242X),
> > + CLK("omap-timer.9", "fck",&gpt9_fck, CK_242X),
> > CLK(NULL, "gpt10_ick",&gpt10_ick, CK_242X),
> > - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_242X),
> > + CLK("omap-timer.10", "fck",&gpt10_fck, CK_242X),
> > CLK(NULL, "gpt11_ick",&gpt11_ick, CK_242X),
> > - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_242X),
> > + CLK("omap-timer.11", "fck",&gpt11_fck, CK_242X),
> > CLK(NULL, "gpt12_ick",&gpt12_ick, CK_242X),
> > - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_242X),
> > + CLK("omap-timer.12", "fck",&gpt12_fck, CK_242X),
> > CLK("omap-mcbsp.1", "ick",&mcbsp1_ick, CK_242X),
> > CLK("omap-mcbsp.1", "fck",&mcbsp1_fck, CK_242X),
> > CLK("omap-mcbsp.2", "ick",&mcbsp2_ick, CK_242X),
> > @@ -1878,6 +1878,42 @@ static struct omap_clk omap2420_clks[] = {
> > CLK(NULL, "pka_ick",&pka_ick, CK_242X),
> > CLK(NULL, "usb_fck",&usb_fck, CK_242X),
> > CLK("musb_hdrc", "fck",&osc_ck, CK_242X),
> > + CLK("omap-timer.1", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.2", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.3", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.4", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.5", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.6", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.7", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.8", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.9", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.10", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.11", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.12", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.1", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.2", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.3", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.4", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.5", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.6", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.7", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.8", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.9", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.10", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.11", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.12", "alt_ck",&alt_ck, CK_243X),
> > };
> >
> > /*
> > diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-
> omap2/clock2430_data.c
> > index e32afcb..7861bf4 100644
> > --- a/arch/arm/mach-omap2/clock2430_data.c
> > +++ b/arch/arm/mach-omap2/clock2430_data.c
> > @@ -1907,27 +1907,27 @@ static struct omap_clk omap2430_clks[] = {
> > CLK(NULL, "gpt1_ick",&gpt1_ick, CK_243X),
> > CLK(NULL, "gpt1_fck",&gpt1_fck, CK_243X),
> > CLK(NULL, "gpt2_ick",&gpt2_ick, CK_243X),
> > - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_243X),
> > + CLK("omap-timer.2", "fck",&gpt2_fck, CK_243X),
> > CLK(NULL, "gpt3_ick",&gpt3_ick, CK_243X),
> > - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_243X),
> > + CLK("omap-timer.3", "fck",&gpt3_fck, CK_243X),
> > CLK(NULL, "gpt4_ick",&gpt4_ick, CK_243X),
> > - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_243X),
> > + CLK("omap-timer.4", "fck",&gpt4_fck, CK_243X),
> > CLK(NULL, "gpt5_ick",&gpt5_ick, CK_243X),
> > - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_243X),
> > + CLK("omap-timer.5", "fck",&gpt5_fck, CK_243X),
> > CLK(NULL, "gpt6_ick",&gpt6_ick, CK_243X),
> > - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_243X),
> > + CLK("omap-timer.6", "fck",&gpt6_fck, CK_243X),
> > CLK(NULL, "gpt7_ick",&gpt7_ick, CK_243X),
> > - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_243X),
> > + CLK("omap-timer.7", "fck",&gpt7_fck, CK_243X),
> > CLK(NULL, "gpt8_ick",&gpt8_ick, CK_243X),
> > - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_243X),
> > + CLK("omap-timer.8", "fck",&gpt8_fck, CK_243X),
> > CLK(NULL, "gpt9_ick",&gpt9_ick, CK_243X),
> > - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_243X),
> > + CLK("omap-timer.9", "fck",&gpt9_fck, CK_243X),
> > CLK(NULL, "gpt10_ick",&gpt10_ick, CK_243X),
> > - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_243X),
> > + CLK("omap-timer.10", "fck",&gpt10_fck, CK_243X),
> > CLK(NULL, "gpt11_ick",&gpt11_ick, CK_243X),
> > - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_243X),
> > + CLK("omap-timer.11", "fck",&gpt11_fck, CK_243X),
> > CLK(NULL, "gpt12_ick",&gpt12_ick, CK_243X),
> > - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_243X),
> > + CLK("omap-timer.12", "fck",&gpt12_fck, CK_243X),
> > CLK("omap-mcbsp.1", "ick",&mcbsp1_ick, CK_243X),
> > CLK("omap-mcbsp.1", "fck",&mcbsp1_fck, CK_243X),
> > CLK("omap-mcbsp.2", "ick",&mcbsp2_ick, CK_243X),
> > @@ -1993,6 +1993,42 @@ static struct omap_clk omap2430_clks[] = {
> > CLK(NULL, "mdm_intc_ick",&mdm_intc_ick, CK_243X),
> > CLK("mmci-omap-hs.0", "mmchsdb_fck",&mmchsdb1_fck, CK_243X),
> > CLK("mmci-omap-hs.1", "mmchsdb_fck",&mmchsdb2_fck, CK_243X),
> > + CLK("omap-timer.1", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.2", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.3", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.4", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.5", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.6", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.7", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.8", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.9", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.10", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.11", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.12", "32k_ck",&func_32k_ck, CK_243X),
> > + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_243X),
> > + CLK("omap-timer.1", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.2", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.3", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.4", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.5", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.6", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.7", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.8", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.9", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.10", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.11", "alt_ck",&alt_ck, CK_243X),
> > + CLK("omap-timer.12", "alt_ck",&alt_ck, CK_243X),
> > };
> >
> > /*
> > diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-
> omap2/clock3xxx_data.c
> > index d85ecd5..41685be 100644
> > --- a/arch/arm/mach-omap2/clock3xxx_data.c
> > +++ b/arch/arm/mach-omap2/clock3xxx_data.c
> > @@ -3273,8 +3273,8 @@ static struct omap_clk omap3xxx_clks[] = {
> > CLK(NULL, "modem_fck",&modem_fck, CK_343X),
> > CLK(NULL, "sad2d_ick",&sad2d_ick, CK_343X),
> > CLK(NULL, "mad2d_ick",&mad2d_ick, CK_343X),
> > - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_3XXX),
> > - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_3XXX),
> > + CLK("omap-timer.10", "fck",&gpt10_fck, CK_3XXX),
> > + CLK("omap-timer.11", "fck",&gpt11_fck, CK_3XXX),
> > CLK(NULL, "cpefuse_fck",&cpefuse_fck, CK_3430ES2 |
> CK_AM35XX),
> > CLK(NULL, "ts_fck",&ts_fck, CK_3430ES2 |
> CK_AM35XX),
> > CLK(NULL, "usbtll_fck",&usbtll_fck, CK_3430ES2 |
> CK_AM35XX),
> > @@ -3380,14 +3380,14 @@ static struct omap_clk omap3xxx_clks[] = {
> > CLK(NULL, "per_48m_fck",&per_48m_fck, CK_3XXX),
> > CLK(NULL, "uart3_fck",&uart3_fck, CK_3XXX),
> > CLK(NULL, "uart4_fck",&uart4_fck, CK_36XX),
> > - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_3XXX),
> > - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_3XXX),
> > - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_3XXX),
> > - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_3XXX),
> > - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_3XXX),
> > - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_3XXX),
> > - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_3XXX),
> > - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_3XXX),
> > + CLK("omap-timer.2", "fck",&gpt2_fck, CK_3XXX),
> > + CLK("omap-timer.3", "fck",&gpt3_fck, CK_3XXX),
> > + CLK("omap-timer.4", "fck",&gpt4_fck, CK_3XXX),
> > + CLK("omap-timer.5", "fck",&gpt5_fck, CK_3XXX),
> > + CLK("omap-timer.6", "fck",&gpt6_fck, CK_3XXX),
> > + CLK("omap-timer.7", "fck",&gpt7_fck, CK_3XXX),
> > + CLK("omap-timer.8", "fck",&gpt8_fck, CK_3XXX),
> > + CLK("omap-timer.9", "fck",&gpt9_fck, CK_3XXX),
> > CLK(NULL, "per_32k_alwon_fck",&per_32k_alwon_fck,
> CK_3XXX),
> > CLK(NULL, "gpio6_dbck",&gpio6_dbck, CK_3XXX),
> > CLK(NULL, "gpio5_dbck",&gpio5_dbck, CK_3XXX),
> > @@ -3428,7 +3428,7 @@ static struct omap_clk omap3xxx_clks[] = {
> > CLK(NULL, "sr2_fck",&sr2_fck, CK_343X),
> > CLK(NULL, "sr_l4_ick",&sr_l4_ick, CK_343X),
> > CLK(NULL, "secure_32k_fck",&secure_32k_fck, CK_3XXX),
> > - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_3XXX),
> > + CLK("omap-timer.12", "fck",&gpt12_fck, CK_3XXX),
> > CLK(NULL, "wdt1_fck",&wdt1_fck, CK_3XXX),
> > CLK(NULL, "ipss_ick",&ipss_ick, CK_AM35XX),
> > CLK(NULL, "rmii_ck",&rmii_ck, CK_AM35XX),
> > @@ -3441,6 +3441,30 @@ static struct omap_clk omap3xxx_clks[] = {
> > CLK("musb_hdrc", "fck",&hsotgusb_fck_am35xx,
> CK_AM35XX),
> > CLK(NULL, "hecc_ck",&hecc_ck, CK_AM35XX),
> > CLK(NULL, "uart4_ick",&uart4_ick_am35xx, CK_AM35XX),
> > + CLK("omap-timer.1", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.2", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.3", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.4", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.5", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.6", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.7", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.8", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.9", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.10", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.11", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.12", "32k_ck",&omap_32k_fck, CK_3XXX),
> > + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_3XXX),
> > + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_3XXX),
> > };
> >
> >
> > diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-
> omap2/clock44xx_data.c
> > index 1599836..d081c10 100644
> > --- a/arch/arm/mach-omap2/clock44xx_data.c
> > +++ b/arch/arm/mach-omap2/clock44xx_data.c
> > @@ -2922,16 +2922,16 @@ static struct omap_clk omap44xx_clks[] = {
> > CLK(NULL, "smartreflex_iva_fck",&smartreflex_iva_fck,
> CK_443X),
> > CLK(NULL, "smartreflex_mpu_fck",&smartreflex_mpu_fck,
> CK_443X),
> > CLK(NULL, "gpt1_fck",&timer1_fck, CK_443X),
> > - CLK(NULL, "gpt10_fck",&timer10_fck, CK_443X),
> > - CLK(NULL, "gpt11_fck",&timer11_fck, CK_443X),
> > - CLK(NULL, "gpt2_fck",&timer2_fck, CK_443X),
> > - CLK(NULL, "gpt3_fck",&timer3_fck, CK_443X),
> > - CLK(NULL, "gpt4_fck",&timer4_fck, CK_443X),
> > - CLK(NULL, "gpt5_fck",&timer5_fck, CK_443X),
> > - CLK(NULL, "gpt6_fck",&timer6_fck, CK_443X),
> > - CLK(NULL, "gpt7_fck",&timer7_fck, CK_443X),
> > - CLK(NULL, "gpt8_fck",&timer8_fck, CK_443X),
> > - CLK(NULL, "gpt9_fck",&timer9_fck, CK_443X),
> > + CLK("omap-timer.10", "fck",&timer10_fck, CK_443X),
> > + CLK("omap-timer.11", "fck",&timer11_fck, CK_443X),
> > + CLK("omap-timer.2", "fck",&timer2_fck, CK_443X),
> > + CLK("omap-timer.3", "fck",&timer3_fck, CK_443X),
> > + CLK("omap-timer.4", "fck",&timer4_fck, CK_443X),
> > + CLK("omap-timer.5", "fck",&timer5_fck, CK_443X),
> > + CLK("omap-timer.6", "fck",&timer6_fck, CK_443X),
> > + CLK("omap-timer.7", "fck",&timer7_fck, CK_443X),
> > + CLK("omap-timer.8", "fck",&timer8_fck, CK_443X),
> > + CLK("omap-timer.9", "fck",&timer9_fck, CK_443X),
> > CLK(NULL, "uart1_fck",&uart1_fck, CK_443X),
> > CLK(NULL, "uart2_fck",&uart2_fck, CK_443X),
> > CLK(NULL, "uart3_fck",&uart3_fck, CK_443X),
> > @@ -2997,6 +2997,28 @@ static struct omap_clk omap44xx_clks[] = {
> > CLK(NULL, "uart3_ick",&dummy_ck, CK_443X),
> > CLK(NULL, "uart4_ick",&dummy_ck, CK_443X),
> > CLK("omap_wdt", "ick",&dummy_ck, CK_443X),
> > + CLK("omap-timer.1", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.2", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.3", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.4", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.5", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.6", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.7", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.8", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.9", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.10", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.11", "32k_ck",&sys_32k_ck, CK_443X),
> > + CLK("omap-timer.1", "sys_ck",&sys_clkin_ck, CK_443X),
> > + CLK("omap-timer.2", "sys_ck",&sys_clkin_ck, CK_443X),
> > + CLK("omap-timer.3", "sys_ck",&sys_clkin_ck, CK_443X),
> > + CLK("omap-timer.4", "sys_ck",&sys_clkin_ck, CK_443X),
> > + CLK("omap-timer.9", "sys_ck",&sys_clkin_ck, CK_443X),
> > + CLK("omap-timer.10", "sys_ck",&sys_clkin_ck, CK_443X),
> > + CLK("omap-timer.11", "sys_ck",&sys_clkin_ck, CK_443X),
> > + CLK("omap-timer.5", "sys_ck",&syc_clk_div_ck,
> CK_443X),
> > + CLK("omap-timer.6", "sys_ck",&syc_clk_div_ck,
> CK_443X),
> > + CLK("omap-timer.7", "sys_ck",&syc_clk_div_ck,
> CK_443X),
> > + CLK("omap-timer.8", "sys_ck",&syc_clk_div_ck,
> CK_443X),
> > };
> >
> > int __init omap4xxx_clk_init(void)
> > --
> > 1.6.0.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes
2010-11-23 8:36 ` DebBarma, Tarun Kanti
@ 2010-11-23 8:40 ` Cousson, Benoit
2010-11-23 8:43 ` DebBarma, Tarun Kanti
0 siblings, 1 reply; 42+ messages in thread
From: Cousson, Benoit @ 2010-11-23 8:40 UTC (permalink / raw)
To: DebBarma, Tarun Kanti; +Cc: linux-omap, Gopinath, Thara
On 11/23/2010 9:36 AM, DebBarma, Tarun Kanti wrote:
> Benoit,
>> -----Original Message-----
>> From: Cousson, Benoit
>> Sent: Monday, November 22, 2010 11:03 PM
>> To: DebBarma, Tarun Kanti
>> Cc: linux-omap@vger.kernel.org; Gopinath, Thara
>> Subject: Re: [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck
>> nodes
>>
>> Hi Tarun,
>>
>> On 11/20/2010 3:39 AM, Tarun Kanti DebBarma wrote:
>>> From: Thara Gopinath<thara@ti.com>
>>>
>>> Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can
>> be
>>> retrieved by doing a clk_get with the corresponding device pointers or
>>> device names.
>>>
>>> Signed-off-by: Thara Gopinath<thara@ti.com>
>>> Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
>>> ---
>>> arch/arm/mach-omap2/clock2420_data.c | 58
>> +++++++++++++++++++++++++++------
>>> arch/arm/mach-omap2/clock2430_data.c | 58
>> +++++++++++++++++++++++++++------
>>> arch/arm/mach-omap2/clock3xxx_data.c | 46 ++++++++++++++++++++------
>>> arch/arm/mach-omap2/clock44xx_data.c | 42 ++++++++++++++++++------
>>> 4 files changed, 161 insertions(+), 43 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-
>> omap2/clock2420_data.c
>>> index 21f8562..d2e90ae 100644
>>> --- a/arch/arm/mach-omap2/clock2420_data.c
>>> +++ b/arch/arm/mach-omap2/clock2420_data.c
>>> @@ -1803,27 +1803,27 @@ static struct omap_clk omap2420_clks[] = {
>>> CLK(NULL, "gpt1_ick",&gpt1_ick, CK_242X),
>>> CLK(NULL, "gpt1_fck",&gpt1_fck, CK_242X),
>>
>> Why is the timer1 not using a clockdev with device name?
>> + CLK("omap-timer.1", "fck",&gpt1_fck, CK_242X),
>>
>> It is the case for all the other platforms.
> Ok, this is done at later patch when we switch to platform driver.
> This is done in this way because gptimer driver would not recognize
> Clock access using device name until the complete switch-over happens.
> This is to keep each patch compiled and booting.
OK, I've just the the patch (#12) where it happens. In that case, you
should just add some disclaimer in the changelog.
Benoit
> --
> Tarun
>
>>
>>> CLK(NULL, "gpt2_ick",&gpt2_ick, CK_242X),
>>> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_242X),
>>> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_242X),
>>> CLK(NULL, "gpt3_ick",&gpt3_ick, CK_242X),
>>> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_242X),
>>> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_242X),
>>> CLK(NULL, "gpt4_ick",&gpt4_ick, CK_242X),
>>> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_242X),
>>> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_242X),
>>> CLK(NULL, "gpt5_ick",&gpt5_ick, CK_242X),
>>> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_242X),
>>> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_242X),
>>> CLK(NULL, "gpt6_ick",&gpt6_ick, CK_242X),
>>> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_242X),
>>> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_242X),
>>> CLK(NULL, "gpt7_ick",&gpt7_ick, CK_242X),
>>> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_242X),
>>> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_242X),
>>> CLK(NULL, "gpt8_ick",&gpt8_ick, CK_242X),
>>> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_242X),
>>> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_242X),
>>> CLK(NULL, "gpt9_ick",&gpt9_ick, CK_242X),
>>> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_242X),
>>> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_242X),
>>> CLK(NULL, "gpt10_ick",&gpt10_ick, CK_242X),
>>> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_242X),
>>> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_242X),
>>> CLK(NULL, "gpt11_ick",&gpt11_ick, CK_242X),
>>> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_242X),
>>> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_242X),
>>> CLK(NULL, "gpt12_ick",&gpt12_ick, CK_242X),
>>> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_242X),
>>> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_242X),
>>> CLK("omap-mcbsp.1", "ick",&mcbsp1_ick, CK_242X),
>>> CLK("omap-mcbsp.1", "fck",&mcbsp1_fck, CK_242X),
>>> CLK("omap-mcbsp.2", "ick",&mcbsp2_ick, CK_242X),
>>> @@ -1878,6 +1878,42 @@ static struct omap_clk omap2420_clks[] = {
>>> CLK(NULL, "pka_ick",&pka_ick, CK_242X),
>>> CLK(NULL, "usb_fck",&usb_fck, CK_242X),
>>> CLK("musb_hdrc", "fck",&osc_ck, CK_242X),
>>> + CLK("omap-timer.1", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.2", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.3", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.4", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.5", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.6", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.7", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.8", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.9", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.10", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.11", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.12", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.1", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.2", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.3", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.4", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.5", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.6", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.7", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.8", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.9", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.10", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.11", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.12", "alt_ck",&alt_ck, CK_243X),
>>> };
>>>
>>> /*
>>> diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-
>> omap2/clock2430_data.c
>>> index e32afcb..7861bf4 100644
>>> --- a/arch/arm/mach-omap2/clock2430_data.c
>>> +++ b/arch/arm/mach-omap2/clock2430_data.c
>>> @@ -1907,27 +1907,27 @@ static struct omap_clk omap2430_clks[] = {
>>> CLK(NULL, "gpt1_ick",&gpt1_ick, CK_243X),
>>> CLK(NULL, "gpt1_fck",&gpt1_fck, CK_243X),
>>> CLK(NULL, "gpt2_ick",&gpt2_ick, CK_243X),
>>> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_243X),
>>> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_243X),
>>> CLK(NULL, "gpt3_ick",&gpt3_ick, CK_243X),
>>> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_243X),
>>> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_243X),
>>> CLK(NULL, "gpt4_ick",&gpt4_ick, CK_243X),
>>> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_243X),
>>> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_243X),
>>> CLK(NULL, "gpt5_ick",&gpt5_ick, CK_243X),
>>> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_243X),
>>> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_243X),
>>> CLK(NULL, "gpt6_ick",&gpt6_ick, CK_243X),
>>> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_243X),
>>> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_243X),
>>> CLK(NULL, "gpt7_ick",&gpt7_ick, CK_243X),
>>> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_243X),
>>> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_243X),
>>> CLK(NULL, "gpt8_ick",&gpt8_ick, CK_243X),
>>> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_243X),
>>> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_243X),
>>> CLK(NULL, "gpt9_ick",&gpt9_ick, CK_243X),
>>> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_243X),
>>> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_243X),
>>> CLK(NULL, "gpt10_ick",&gpt10_ick, CK_243X),
>>> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_243X),
>>> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_243X),
>>> CLK(NULL, "gpt11_ick",&gpt11_ick, CK_243X),
>>> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_243X),
>>> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_243X),
>>> CLK(NULL, "gpt12_ick",&gpt12_ick, CK_243X),
>>> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_243X),
>>> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_243X),
>>> CLK("omap-mcbsp.1", "ick",&mcbsp1_ick, CK_243X),
>>> CLK("omap-mcbsp.1", "fck",&mcbsp1_fck, CK_243X),
>>> CLK("omap-mcbsp.2", "ick",&mcbsp2_ick, CK_243X),
>>> @@ -1993,6 +1993,42 @@ static struct omap_clk omap2430_clks[] = {
>>> CLK(NULL, "mdm_intc_ick",&mdm_intc_ick, CK_243X),
>>> CLK("mmci-omap-hs.0", "mmchsdb_fck",&mmchsdb1_fck, CK_243X),
>>> CLK("mmci-omap-hs.1", "mmchsdb_fck",&mmchsdb2_fck, CK_243X),
>>> + CLK("omap-timer.1", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.2", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.3", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.4", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.5", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.6", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.7", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.8", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.9", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.10", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.11", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.12", "32k_ck",&func_32k_ck, CK_243X),
>>> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_243X),
>>> + CLK("omap-timer.1", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.2", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.3", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.4", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.5", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.6", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.7", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.8", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.9", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.10", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.11", "alt_ck",&alt_ck, CK_243X),
>>> + CLK("omap-timer.12", "alt_ck",&alt_ck, CK_243X),
>>> };
>>>
>>> /*
>>> diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-
>> omap2/clock3xxx_data.c
>>> index d85ecd5..41685be 100644
>>> --- a/arch/arm/mach-omap2/clock3xxx_data.c
>>> +++ b/arch/arm/mach-omap2/clock3xxx_data.c
>>> @@ -3273,8 +3273,8 @@ static struct omap_clk omap3xxx_clks[] = {
>>> CLK(NULL, "modem_fck",&modem_fck, CK_343X),
>>> CLK(NULL, "sad2d_ick",&sad2d_ick, CK_343X),
>>> CLK(NULL, "mad2d_ick",&mad2d_ick, CK_343X),
>>> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_3XXX),
>>> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_3XXX),
>>> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_3XXX),
>>> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_3XXX),
>>> CLK(NULL, "cpefuse_fck",&cpefuse_fck, CK_3430ES2 |
>> CK_AM35XX),
>>> CLK(NULL, "ts_fck",&ts_fck, CK_3430ES2 |
>> CK_AM35XX),
>>> CLK(NULL, "usbtll_fck",&usbtll_fck, CK_3430ES2 |
>> CK_AM35XX),
>>> @@ -3380,14 +3380,14 @@ static struct omap_clk omap3xxx_clks[] = {
>>> CLK(NULL, "per_48m_fck",&per_48m_fck, CK_3XXX),
>>> CLK(NULL, "uart3_fck",&uart3_fck, CK_3XXX),
>>> CLK(NULL, "uart4_fck",&uart4_fck, CK_36XX),
>>> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_3XXX),
>>> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_3XXX),
>>> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_3XXX),
>>> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_3XXX),
>>> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_3XXX),
>>> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_3XXX),
>>> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_3XXX),
>>> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_3XXX),
>>> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_3XXX),
>>> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_3XXX),
>>> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_3XXX),
>>> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_3XXX),
>>> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_3XXX),
>>> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_3XXX),
>>> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_3XXX),
>>> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_3XXX),
>>> CLK(NULL, "per_32k_alwon_fck",&per_32k_alwon_fck,
>> CK_3XXX),
>>> CLK(NULL, "gpio6_dbck",&gpio6_dbck, CK_3XXX),
>>> CLK(NULL, "gpio5_dbck",&gpio5_dbck, CK_3XXX),
>>> @@ -3428,7 +3428,7 @@ static struct omap_clk omap3xxx_clks[] = {
>>> CLK(NULL, "sr2_fck",&sr2_fck, CK_343X),
>>> CLK(NULL, "sr_l4_ick",&sr_l4_ick, CK_343X),
>>> CLK(NULL, "secure_32k_fck",&secure_32k_fck, CK_3XXX),
>>> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_3XXX),
>>> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_3XXX),
>>> CLK(NULL, "wdt1_fck",&wdt1_fck, CK_3XXX),
>>> CLK(NULL, "ipss_ick",&ipss_ick, CK_AM35XX),
>>> CLK(NULL, "rmii_ck",&rmii_ck, CK_AM35XX),
>>> @@ -3441,6 +3441,30 @@ static struct omap_clk omap3xxx_clks[] = {
>>> CLK("musb_hdrc", "fck",&hsotgusb_fck_am35xx,
>> CK_AM35XX),
>>> CLK(NULL, "hecc_ck",&hecc_ck, CK_AM35XX),
>>> CLK(NULL, "uart4_ick",&uart4_ick_am35xx, CK_AM35XX),
>>> + CLK("omap-timer.1", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.2", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.3", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.4", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.5", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.6", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.7", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.8", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.9", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.10", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.11", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.12", "32k_ck",&omap_32k_fck, CK_3XXX),
>>> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_3XXX),
>>> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_3XXX),
>>> };
>>>
>>>
>>> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-
>> omap2/clock44xx_data.c
>>> index 1599836..d081c10 100644
>>> --- a/arch/arm/mach-omap2/clock44xx_data.c
>>> +++ b/arch/arm/mach-omap2/clock44xx_data.c
>>> @@ -2922,16 +2922,16 @@ static struct omap_clk omap44xx_clks[] = {
>>> CLK(NULL, "smartreflex_iva_fck",&smartreflex_iva_fck,
>> CK_443X),
>>> CLK(NULL, "smartreflex_mpu_fck",&smartreflex_mpu_fck,
>> CK_443X),
>>> CLK(NULL, "gpt1_fck",&timer1_fck, CK_443X),
>>> - CLK(NULL, "gpt10_fck",&timer10_fck, CK_443X),
>>> - CLK(NULL, "gpt11_fck",&timer11_fck, CK_443X),
>>> - CLK(NULL, "gpt2_fck",&timer2_fck, CK_443X),
>>> - CLK(NULL, "gpt3_fck",&timer3_fck, CK_443X),
>>> - CLK(NULL, "gpt4_fck",&timer4_fck, CK_443X),
>>> - CLK(NULL, "gpt5_fck",&timer5_fck, CK_443X),
>>> - CLK(NULL, "gpt6_fck",&timer6_fck, CK_443X),
>>> - CLK(NULL, "gpt7_fck",&timer7_fck, CK_443X),
>>> - CLK(NULL, "gpt8_fck",&timer8_fck, CK_443X),
>>> - CLK(NULL, "gpt9_fck",&timer9_fck, CK_443X),
>>> + CLK("omap-timer.10", "fck",&timer10_fck, CK_443X),
>>> + CLK("omap-timer.11", "fck",&timer11_fck, CK_443X),
>>> + CLK("omap-timer.2", "fck",&timer2_fck, CK_443X),
>>> + CLK("omap-timer.3", "fck",&timer3_fck, CK_443X),
>>> + CLK("omap-timer.4", "fck",&timer4_fck, CK_443X),
>>> + CLK("omap-timer.5", "fck",&timer5_fck, CK_443X),
>>> + CLK("omap-timer.6", "fck",&timer6_fck, CK_443X),
>>> + CLK("omap-timer.7", "fck",&timer7_fck, CK_443X),
>>> + CLK("omap-timer.8", "fck",&timer8_fck, CK_443X),
>>> + CLK("omap-timer.9", "fck",&timer9_fck, CK_443X),
>>> CLK(NULL, "uart1_fck",&uart1_fck, CK_443X),
>>> CLK(NULL, "uart2_fck",&uart2_fck, CK_443X),
>>> CLK(NULL, "uart3_fck",&uart3_fck, CK_443X),
>>> @@ -2997,6 +2997,28 @@ static struct omap_clk omap44xx_clks[] = {
>>> CLK(NULL, "uart3_ick",&dummy_ck, CK_443X),
>>> CLK(NULL, "uart4_ick",&dummy_ck, CK_443X),
>>> CLK("omap_wdt", "ick",&dummy_ck, CK_443X),
>>> + CLK("omap-timer.1", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.2", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.3", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.4", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.5", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.6", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.7", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.8", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.9", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.10", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.11", "32k_ck",&sys_32k_ck, CK_443X),
>>> + CLK("omap-timer.1", "sys_ck",&sys_clkin_ck, CK_443X),
>>> + CLK("omap-timer.2", "sys_ck",&sys_clkin_ck, CK_443X),
>>> + CLK("omap-timer.3", "sys_ck",&sys_clkin_ck, CK_443X),
>>> + CLK("omap-timer.4", "sys_ck",&sys_clkin_ck, CK_443X),
>>> + CLK("omap-timer.9", "sys_ck",&sys_clkin_ck, CK_443X),
>>> + CLK("omap-timer.10", "sys_ck",&sys_clkin_ck, CK_443X),
>>> + CLK("omap-timer.11", "sys_ck",&sys_clkin_ck, CK_443X),
>>> + CLK("omap-timer.5", "sys_ck",&syc_clk_div_ck,
>> CK_443X),
>>> + CLK("omap-timer.6", "sys_ck",&syc_clk_div_ck,
>> CK_443X),
>>> + CLK("omap-timer.7", "sys_ck",&syc_clk_div_ck,
>> CK_443X),
>>> + CLK("omap-timer.8", "sys_ck",&syc_clk_div_ck,
>> CK_443X),
>>> };
>>>
>>> int __init omap4xxx_clk_init(void)
>>> --
>>> 1.6.0.4
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes
2010-11-23 8:40 ` Cousson, Benoit
@ 2010-11-23 8:43 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-23 8:43 UTC (permalink / raw)
To: Cousson, Benoit; +Cc: linux-omap, Gopinath, Thara
Benoit,
> -----Original Message-----
> From: Cousson, Benoit
> Sent: Tuesday, November 23, 2010 2:11 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Gopinath, Thara
> Subject: Re: [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck
> nodes
>
> On 11/23/2010 9:36 AM, DebBarma, Tarun Kanti wrote:
> > Benoit,
> >> -----Original Message-----
> >> From: Cousson, Benoit
> >> Sent: Monday, November 22, 2010 11:03 PM
> >> To: DebBarma, Tarun Kanti
> >> Cc: linux-omap@vger.kernel.org; Gopinath, Thara
> >> Subject: Re: [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck
> >> nodes
> >>
> >> Hi Tarun,
> >>
> >> On 11/20/2010 3:39 AM, Tarun Kanti DebBarma wrote:
> >>> From: Thara Gopinath<thara@ti.com>
> >>>
> >>> Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can
> >> be
> >>> retrieved by doing a clk_get with the corresponding device pointers or
> >>> device names.
> >>>
> >>> Signed-off-by: Thara Gopinath<thara@ti.com>
> >>> Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> >>> ---
> >>> arch/arm/mach-omap2/clock2420_data.c | 58
> >> +++++++++++++++++++++++++++------
> >>> arch/arm/mach-omap2/clock2430_data.c | 58
> >> +++++++++++++++++++++++++++------
> >>> arch/arm/mach-omap2/clock3xxx_data.c | 46 ++++++++++++++++++++---
> ---
> >>> arch/arm/mach-omap2/clock44xx_data.c | 42 ++++++++++++++++++-----
> -
> >>> 4 files changed, 161 insertions(+), 43 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-
> >> omap2/clock2420_data.c
> >>> index 21f8562..d2e90ae 100644
> >>> --- a/arch/arm/mach-omap2/clock2420_data.c
> >>> +++ b/arch/arm/mach-omap2/clock2420_data.c
> >>> @@ -1803,27 +1803,27 @@ static struct omap_clk omap2420_clks[] = {
> >>> CLK(NULL, "gpt1_ick",&gpt1_ick, CK_242X),
> >>> CLK(NULL, "gpt1_fck",&gpt1_fck, CK_242X),
> >>
> >> Why is the timer1 not using a clockdev with device name?
> >> + CLK("omap-timer.1", "fck",&gpt1_fck, CK_242X),
> >>
> >> It is the case for all the other platforms.
> > Ok, this is done at later patch when we switch to platform driver.
> > This is done in this way because gptimer driver would not recognize
> > Clock access using device name until the complete switch-over happens.
> > This is to keep each patch compiled and booting.
>
> OK, I've just the the patch (#12) where it happens. In that case, you
> should just add some disclaimer in the changelog.
OK, sure.
--
Tarun
> >
> >>
> >>> CLK(NULL, "gpt2_ick",&gpt2_ick, CK_242X),
> >>> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_242X),
> >>> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_242X),
> >>> CLK(NULL, "gpt3_ick",&gpt3_ick, CK_242X),
> >>> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_242X),
> >>> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_242X),
> >>> CLK(NULL, "gpt4_ick",&gpt4_ick, CK_242X),
> >>> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_242X),
> >>> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_242X),
> >>> CLK(NULL, "gpt5_ick",&gpt5_ick, CK_242X),
> >>> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_242X),
> >>> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_242X),
> >>> CLK(NULL, "gpt6_ick",&gpt6_ick, CK_242X),
> >>> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_242X),
> >>> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_242X),
> >>> CLK(NULL, "gpt7_ick",&gpt7_ick, CK_242X),
> >>> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_242X),
> >>> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_242X),
> >>> CLK(NULL, "gpt8_ick",&gpt8_ick, CK_242X),
> >>> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_242X),
> >>> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_242X),
> >>> CLK(NULL, "gpt9_ick",&gpt9_ick, CK_242X),
> >>> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_242X),
> >>> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_242X),
> >>> CLK(NULL, "gpt10_ick",&gpt10_ick, CK_242X),
> >>> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_242X),
> >>> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_242X),
> >>> CLK(NULL, "gpt11_ick",&gpt11_ick, CK_242X),
> >>> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_242X),
> >>> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_242X),
> >>> CLK(NULL, "gpt12_ick",&gpt12_ick, CK_242X),
> >>> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_242X),
> >>> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_242X),
> >>> CLK("omap-mcbsp.1", "ick",&mcbsp1_ick, CK_242X),
> >>> CLK("omap-mcbsp.1", "fck",&mcbsp1_fck, CK_242X),
> >>> CLK("omap-mcbsp.2", "ick",&mcbsp2_ick, CK_242X),
> >>> @@ -1878,6 +1878,42 @@ static struct omap_clk omap2420_clks[] = {
> >>> CLK(NULL, "pka_ick",&pka_ick, CK_242X),
> >>> CLK(NULL, "usb_fck",&usb_fck, CK_242X),
> >>> CLK("musb_hdrc", "fck",&osc_ck, CK_242X),
> >>> + CLK("omap-timer.1", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.2", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.3", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.4", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.5", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.6", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.7", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.8", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.9", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.10", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.11", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.12", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.1", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.2", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.3", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.4", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.5", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.6", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.7", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.8", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.9", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.10", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.11", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.12", "alt_ck",&alt_ck, CK_243X),
> >>> };
> >>>
> >>> /*
> >>> diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-
> >> omap2/clock2430_data.c
> >>> index e32afcb..7861bf4 100644
> >>> --- a/arch/arm/mach-omap2/clock2430_data.c
> >>> +++ b/arch/arm/mach-omap2/clock2430_data.c
> >>> @@ -1907,27 +1907,27 @@ static struct omap_clk omap2430_clks[] = {
> >>> CLK(NULL, "gpt1_ick",&gpt1_ick, CK_243X),
> >>> CLK(NULL, "gpt1_fck",&gpt1_fck, CK_243X),
> >>> CLK(NULL, "gpt2_ick",&gpt2_ick, CK_243X),
> >>> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_243X),
> >>> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_243X),
> >>> CLK(NULL, "gpt3_ick",&gpt3_ick, CK_243X),
> >>> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_243X),
> >>> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_243X),
> >>> CLK(NULL, "gpt4_ick",&gpt4_ick, CK_243X),
> >>> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_243X),
> >>> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_243X),
> >>> CLK(NULL, "gpt5_ick",&gpt5_ick, CK_243X),
> >>> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_243X),
> >>> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_243X),
> >>> CLK(NULL, "gpt6_ick",&gpt6_ick, CK_243X),
> >>> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_243X),
> >>> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_243X),
> >>> CLK(NULL, "gpt7_ick",&gpt7_ick, CK_243X),
> >>> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_243X),
> >>> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_243X),
> >>> CLK(NULL, "gpt8_ick",&gpt8_ick, CK_243X),
> >>> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_243X),
> >>> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_243X),
> >>> CLK(NULL, "gpt9_ick",&gpt9_ick, CK_243X),
> >>> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_243X),
> >>> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_243X),
> >>> CLK(NULL, "gpt10_ick",&gpt10_ick, CK_243X),
> >>> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_243X),
> >>> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_243X),
> >>> CLK(NULL, "gpt11_ick",&gpt11_ick, CK_243X),
> >>> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_243X),
> >>> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_243X),
> >>> CLK(NULL, "gpt12_ick",&gpt12_ick, CK_243X),
> >>> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_243X),
> >>> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_243X),
> >>> CLK("omap-mcbsp.1", "ick",&mcbsp1_ick, CK_243X),
> >>> CLK("omap-mcbsp.1", "fck",&mcbsp1_fck, CK_243X),
> >>> CLK("omap-mcbsp.2", "ick",&mcbsp2_ick, CK_243X),
> >>> @@ -1993,6 +1993,42 @@ static struct omap_clk omap2430_clks[] = {
> >>> CLK(NULL, "mdm_intc_ick",&mdm_intc_ick, CK_243X),
> >>> CLK("mmci-omap-hs.0", "mmchsdb_fck",&mmchsdb1_fck,
> CK_243X),
> >>> CLK("mmci-omap-hs.1", "mmchsdb_fck",&mmchsdb2_fck,
> CK_243X),
> >>> + CLK("omap-timer.1", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.2", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.3", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.4", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.5", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.6", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.7", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.8", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.9", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.10", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.11", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.12", "32k_ck",&func_32k_ck, CK_243X),
> >>> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_243X),
> >>> + CLK("omap-timer.1", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.2", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.3", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.4", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.5", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.6", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.7", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.8", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.9", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.10", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.11", "alt_ck",&alt_ck, CK_243X),
> >>> + CLK("omap-timer.12", "alt_ck",&alt_ck, CK_243X),
> >>> };
> >>>
> >>> /*
> >>> diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-
> >> omap2/clock3xxx_data.c
> >>> index d85ecd5..41685be 100644
> >>> --- a/arch/arm/mach-omap2/clock3xxx_data.c
> >>> +++ b/arch/arm/mach-omap2/clock3xxx_data.c
> >>> @@ -3273,8 +3273,8 @@ static struct omap_clk omap3xxx_clks[] = {
> >>> CLK(NULL, "modem_fck",&modem_fck, CK_343X),
> >>> CLK(NULL, "sad2d_ick",&sad2d_ick, CK_343X),
> >>> CLK(NULL, "mad2d_ick",&mad2d_ick, CK_343X),
> >>> - CLK(NULL, "gpt10_fck",&gpt10_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt11_fck",&gpt11_fck, CK_3XXX),
> >>> + CLK("omap-timer.10", "fck",&gpt10_fck, CK_3XXX),
> >>> + CLK("omap-timer.11", "fck",&gpt11_fck, CK_3XXX),
> >>> CLK(NULL, "cpefuse_fck",&cpefuse_fck, CK_3430ES2 |
> >> CK_AM35XX),
> >>> CLK(NULL, "ts_fck",&ts_fck, CK_3430ES2 |
> >> CK_AM35XX),
> >>> CLK(NULL, "usbtll_fck",&usbtll_fck, CK_3430ES2 |
> >> CK_AM35XX),
> >>> @@ -3380,14 +3380,14 @@ static struct omap_clk omap3xxx_clks[] = {
> >>> CLK(NULL, "per_48m_fck",&per_48m_fck, CK_3XXX),
> >>> CLK(NULL, "uart3_fck",&uart3_fck, CK_3XXX),
> >>> CLK(NULL, "uart4_fck",&uart4_fck, CK_36XX),
> >>> - CLK(NULL, "gpt2_fck",&gpt2_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt3_fck",&gpt3_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt4_fck",&gpt4_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt5_fck",&gpt5_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt6_fck",&gpt6_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt7_fck",&gpt7_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt8_fck",&gpt8_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt9_fck",&gpt9_fck, CK_3XXX),
> >>> + CLK("omap-timer.2", "fck",&gpt2_fck, CK_3XXX),
> >>> + CLK("omap-timer.3", "fck",&gpt3_fck, CK_3XXX),
> >>> + CLK("omap-timer.4", "fck",&gpt4_fck, CK_3XXX),
> >>> + CLK("omap-timer.5", "fck",&gpt5_fck, CK_3XXX),
> >>> + CLK("omap-timer.6", "fck",&gpt6_fck, CK_3XXX),
> >>> + CLK("omap-timer.7", "fck",&gpt7_fck, CK_3XXX),
> >>> + CLK("omap-timer.8", "fck",&gpt8_fck, CK_3XXX),
> >>> + CLK("omap-timer.9", "fck",&gpt9_fck, CK_3XXX),
> >>> CLK(NULL, "per_32k_alwon_fck",&per_32k_alwon_fck,
> >> CK_3XXX),
> >>> CLK(NULL, "gpio6_dbck",&gpio6_dbck, CK_3XXX),
> >>> CLK(NULL, "gpio5_dbck",&gpio5_dbck, CK_3XXX),
> >>> @@ -3428,7 +3428,7 @@ static struct omap_clk omap3xxx_clks[] = {
> >>> CLK(NULL, "sr2_fck",&sr2_fck, CK_343X),
> >>> CLK(NULL, "sr_l4_ick",&sr_l4_ick, CK_343X),
> >>> CLK(NULL, "secure_32k_fck",&secure_32k_fck, CK_3XXX),
> >>> - CLK(NULL, "gpt12_fck",&gpt12_fck, CK_3XXX),
> >>> + CLK("omap-timer.12", "fck",&gpt12_fck, CK_3XXX),
> >>> CLK(NULL, "wdt1_fck",&wdt1_fck, CK_3XXX),
> >>> CLK(NULL, "ipss_ick",&ipss_ick, CK_AM35XX),
> >>> CLK(NULL, "rmii_ck",&rmii_ck, CK_AM35XX),
> >>> @@ -3441,6 +3441,30 @@ static struct omap_clk omap3xxx_clks[] = {
> >>> CLK("musb_hdrc", "fck",&hsotgusb_fck_am35xx,
> >> CK_AM35XX),
> >>> CLK(NULL, "hecc_ck",&hecc_ck, CK_AM35XX),
> >>> CLK(NULL, "uart4_ick",&uart4_ick_am35xx,
> CK_AM35XX),
> >>> + CLK("omap-timer.1", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.2", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.3", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.4", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.5", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.6", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.7", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.8", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.9", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.10", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.11", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.12", "32k_ck",&omap_32k_fck, CK_3XXX),
> >>> + CLK("omap-timer.1", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.2", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.3", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.4", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.5", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.6", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.7", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.8", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.9", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.10", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.11", "sys_ck",&sys_ck, CK_3XXX),
> >>> + CLK("omap-timer.12", "sys_ck",&sys_ck, CK_3XXX),
> >>> };
> >>>
> >>>
> >>> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-
> >> omap2/clock44xx_data.c
> >>> index 1599836..d081c10 100644
> >>> --- a/arch/arm/mach-omap2/clock44xx_data.c
> >>> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> >>> @@ -2922,16 +2922,16 @@ static struct omap_clk omap44xx_clks[] = {
> >>> CLK(NULL, "smartreflex_iva_fck",&smartreflex_iva_fck,
> >> CK_443X),
> >>> CLK(NULL, "smartreflex_mpu_fck",&smartreflex_mpu_fck,
> >> CK_443X),
> >>> CLK(NULL, "gpt1_fck",&timer1_fck, CK_443X),
> >>> - CLK(NULL, "gpt10_fck",&timer10_fck, CK_443X),
> >>> - CLK(NULL, "gpt11_fck",&timer11_fck, CK_443X),
> >>> - CLK(NULL, "gpt2_fck",&timer2_fck, CK_443X),
> >>> - CLK(NULL, "gpt3_fck",&timer3_fck, CK_443X),
> >>> - CLK(NULL, "gpt4_fck",&timer4_fck, CK_443X),
> >>> - CLK(NULL, "gpt5_fck",&timer5_fck, CK_443X),
> >>> - CLK(NULL, "gpt6_fck",&timer6_fck, CK_443X),
> >>> - CLK(NULL, "gpt7_fck",&timer7_fck, CK_443X),
> >>> - CLK(NULL, "gpt8_fck",&timer8_fck, CK_443X),
> >>> - CLK(NULL, "gpt9_fck",&timer9_fck, CK_443X),
> >>> + CLK("omap-timer.10", "fck",&timer10_fck, CK_443X),
> >>> + CLK("omap-timer.11", "fck",&timer11_fck, CK_443X),
> >>> + CLK("omap-timer.2", "fck",&timer2_fck, CK_443X),
> >>> + CLK("omap-timer.3", "fck",&timer3_fck, CK_443X),
> >>> + CLK("omap-timer.4", "fck",&timer4_fck, CK_443X),
> >>> + CLK("omap-timer.5", "fck",&timer5_fck, CK_443X),
> >>> + CLK("omap-timer.6", "fck",&timer6_fck, CK_443X),
> >>> + CLK("omap-timer.7", "fck",&timer7_fck, CK_443X),
> >>> + CLK("omap-timer.8", "fck",&timer8_fck, CK_443X),
> >>> + CLK("omap-timer.9", "fck",&timer9_fck, CK_443X),
> >>> CLK(NULL, "uart1_fck",&uart1_fck, CK_443X),
> >>> CLK(NULL, "uart2_fck",&uart2_fck, CK_443X),
> >>> CLK(NULL, "uart3_fck",&uart3_fck, CK_443X),
> >>> @@ -2997,6 +2997,28 @@ static struct omap_clk omap44xx_clks[] = {
> >>> CLK(NULL, "uart3_ick",&dummy_ck, CK_443X),
> >>> CLK(NULL, "uart4_ick",&dummy_ck, CK_443X),
> >>> CLK("omap_wdt", "ick",&dummy_ck, CK_443X),
> >>> + CLK("omap-timer.1", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.2", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.3", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.4", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.5", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.6", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.7", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.8", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.9", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.10", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.11", "32k_ck",&sys_32k_ck, CK_443X),
> >>> + CLK("omap-timer.1", "sys_ck",&sys_clkin_ck, CK_443X),
> >>> + CLK("omap-timer.2", "sys_ck",&sys_clkin_ck, CK_443X),
> >>> + CLK("omap-timer.3", "sys_ck",&sys_clkin_ck, CK_443X),
> >>> + CLK("omap-timer.4", "sys_ck",&sys_clkin_ck, CK_443X),
> >>> + CLK("omap-timer.9", "sys_ck",&sys_clkin_ck, CK_443X),
> >>> + CLK("omap-timer.10", "sys_ck",&sys_clkin_ck, CK_443X),
> >>> + CLK("omap-timer.11", "sys_ck",&sys_clkin_ck, CK_443X),
> >>> + CLK("omap-timer.5", "sys_ck",&syc_clk_div_ck,
> >> CK_443X),
> >>> + CLK("omap-timer.6", "sys_ck",&syc_clk_div_ck,
> >> CK_443X),
> >>> + CLK("omap-timer.7", "sys_ck",&syc_clk_div_ck,
> >> CK_443X),
> >>> + CLK("omap-timer.8", "sys_ck",&syc_clk_div_ck,
> >> CK_443X),
> >>> };
> >>>
> >>> int __init omap4xxx_clk_init(void)
> >>> --
> >>> 1.6.0.4
> >>>
> >>> --
> >>> To unsubscribe from this list: send the line "unsubscribe linux-omap"
> in
> >>> the body of a message to majordomo@vger.kernel.org
> >>> More majordomo info at http://vger.kernel.org/majordomo-info.html
> >
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod
2010-11-20 2:39 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 3/14] OMAP2420: dmtimer: add hwmod database Tarun Kanti DebBarma
@ 2010-11-23 14:48 ` Cousson, Benoit
2010-11-24 6:53 ` DebBarma, Tarun Kanti
1 sibling, 1 reply; 42+ messages in thread
From: Cousson, Benoit @ 2010-11-23 14:48 UTC (permalink / raw)
To: DebBarma, Tarun Kanti; +Cc: linux-omap, Gopinath, Thara
On 11/20/2010 3:39 AM, DebBarma, Tarun Kanti wrote:
> (1) Add new fields and data structures to support dmtimer conversion
> to platform driver.
> (2) Constants to identify IP revision so that Highlander IP in OMAP 4
> can be distinguished.
> (3) field to identify OMAP4 abe timers.
> (4) Interface function to support early boot.
>
> Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> Signed-off-by: Thara Gopinath<thara@ti.com>
> ---
> arch/arm/mach-omap2/dmtimer.h | 32 +++++++++++++++++++++++++++++
> arch/arm/plat-omap/dmtimer.c | 8 +++++++
> arch/arm/plat-omap/include/plat/dmtimer.h | 19 +++++++++++++++++
> 3 files changed, 59 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-omap2/dmtimer.h
>
> diff --git a/arch/arm/mach-omap2/dmtimer.h b/arch/arm/mach-omap2/dmtimer.h
> new file mode 100644
> index 0000000..4d4493b
> --- /dev/null
> +++ b/arch/arm/mach-omap2/dmtimer.h
> @@ -0,0 +1,32 @@
> +/**
> + * OMAP Dual-Mode Timers - early initialization interface
> + *
> + * function interface called first to start dmtimer early initialization.
> + *
> + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
> + * Tarun Kanti DebBarma<tarun.kanti@ti.com>
> + *
> + * Copyright (C) 2010 Texas Instruments Incorporated
> + * Thara Gopinath<thara@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#ifndef __ASM_ARCH_DMTIMER_H
> +#define __ASM_ARCH_DMTIMER_H
> +
> +/*
> + * dmtimer is required during early part of boot sequence even before
> + * device model and pm_runtime if fully up and running. this function
> + * provides hook to omap2_init_common_hw() which is triggered from
> + * start_kernel()->init_irq() of kernel initialization sequence.
> + */
> +void __init omap2_dm_timer_early_init(void);
> +
> +#endif
> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> index 1d706cf..10daa9d 100644
> --- a/arch/arm/plat-omap/dmtimer.c
> +++ b/arch/arm/plat-omap/dmtimer.c
> @@ -3,6 +3,12 @@
> *
> * OMAP Dual-Mode Timers
> *
> + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
> + * Tarun Kanti DebBarma<tarun.kanti@ti.com>
> + *
> + * Copyright (C) 2010 Texas Instruments Incorporated
> + * Thara Gopinath<thara@ti.com>
You can remove the copyright and put Thara's name below yours.
It should be the case for other field as well.
> + *
> * Copyright (C) 2005 Nokia Corporation
> * OMAP2 support by Juha Yrjola
> * API improvements and OMAP2 clock framework support by Timo Teras
> @@ -151,6 +157,7 @@
> (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR<< WPSHIFT))
>
> struct omap_dm_timer {
> + int id;
> unsigned long phys_base;
> int irq;
> #ifdef CONFIG_ARCH_OMAP2PLUS
> @@ -160,6 +167,7 @@ struct omap_dm_timer {
> unsigned reserved:1;
> unsigned enabled:1;
> unsigned posted:1;
> + struct platform_device *pdev;
> };
What that structure is used for? Is it some legacy structure that will
be removed in next patches? It seems to be a wrapper on top of the
device that should not be used anymore after platform_driver migration.
>
> static int dm_timer_count;
> diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
> index dfa3aff..2bb837e 100644
> --- a/arch/arm/plat-omap/include/plat/dmtimer.h
> +++ b/arch/arm/plat-omap/include/plat/dmtimer.h
> @@ -3,6 +3,11 @@
> *
> * OMAP Dual-Mode Timers
> *
> + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
> + * Tarun Kanti DebBarma<tarun.kanti@ti.com>
> + * Thara Gopinath<thara@ti.com>
Add a blank line here.
> + * Platform device conversion and hwmod support.
> + *
> * Copyright (C) 2005 Nokia Corporation
> * Author: Lauri Leukkunen<lauri.leukkunen@nokia.com>
> * PWM and clock framwork support by Timo Teras.
> @@ -29,6 +34,8 @@
> #ifndef __ASM_ARCH_DMTIMER_H
> #define __ASM_ARCH_DMTIMER_H
>
> +#include<linux/platform_device.h>
> +
> /* clock sources */
> #define OMAP_TIMER_SRC_SYS_CLK 0x00
> #define OMAP_TIMER_SRC_32_KHZ 0x01
> @@ -44,11 +51,23 @@
> #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
> #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPAR 0x02
>
> +/* timer ip constants */
Maybe you should have a better comment here?
Something closer to your changelog: IP revision identifier so that
Highlander IP in OMAP 4 can be distinguished.
> +#define OMAP_TIMER_IP_VERSION_1 0x1
> +#define OMAP_TIMER_IP_VERSION_2 0x2
> +
> struct omap_dm_timer;
> extern struct omap_dm_timer *gptimer_wakeup;
> extern struct sys_timer omap_timer;
> struct clk;
>
> +struct dmtimer_platform_data {
> + int (*set_timer_src) (struct platform_device *pdev, int source);
> + int timer_ip_type;
> + u8 func_offst;
> + u8 intr_offst;
You can probably keep "offset" since you save only one character...
Regards,
Benoit
> + u32 is_early_init:1;
> +};
> +
> int omap_dm_timer_init(void);
>
> struct omap_dm_timer *omap_dm_timer_request(void);
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array
2010-11-20 2:39 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Tarun Kanti DebBarma
@ 2010-11-23 15:22 ` Cousson, Benoit
2010-11-24 7:01 ` DebBarma, Tarun Kanti
1 sibling, 1 reply; 42+ messages in thread
From: Cousson, Benoit @ 2010-11-23 15:22 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap
On 11/20/2010 3:39 AM, Tarun Kanti DebBarma wrote:
> Convert dmtimers static array in functions into list structure.
> Please note that the static arrays will be completely removed
> in subsequent patches when dmtimer is converted to platform driver.
Why do you still need to keep your own list of timers?
The driver already contains a list of devices.
You even have some iterator available in the kernel:
driver_for_each_device or driver_find_device.
You could probably get rid of all that stuff for my point of view.
Benoit
>
> Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> ---
> arch/arm/plat-omap/dmtimer.c | 67 +++++++++++++++++++++++-------------------
> 1 files changed, 37 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> index 10daa9d..124fd21 100644
> --- a/arch/arm/plat-omap/dmtimer.c
> +++ b/arch/arm/plat-omap/dmtimer.c
> @@ -168,6 +168,7 @@ struct omap_dm_timer {
> unsigned enabled:1;
> unsigned posted:1;
> struct platform_device *pdev;
> + struct list_head node;
> };
>
> static int dm_timer_count;
> @@ -290,7 +291,8 @@ static struct omap_dm_timer *dm_timers;
> static const char **dm_source_names;
> static struct clk **dm_source_clocks;
>
> -static spinlock_t dm_timer_lock;
> +static LIST_HEAD(omap_timer_list);
> +static DEFINE_SPINLOCK(dm_timer_lock);
>
> /*
> * Reads timer registers in posted and non-posted mode. The posted mode bit
> @@ -340,7 +342,7 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
> {
> u32 l;
>
> - if (!cpu_class_is_omap2() || timer !=&dm_timers[0]) {
> + if (!cpu_class_is_omap2() || timer->id != 1) {
> omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
> omap_dm_timer_wait_for_reset(timer);
> }
> @@ -371,23 +373,24 @@ static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
>
> struct omap_dm_timer *omap_dm_timer_request(void)
> {
> - struct omap_dm_timer *timer = NULL;
> + struct omap_dm_timer *timer = NULL, *t;
> unsigned long flags;
> - int i;
>
> spin_lock_irqsave(&dm_timer_lock, flags);
> - for (i = 0; i< dm_timer_count; i++) {
> - if (dm_timers[i].reserved)
> + list_for_each_entry(t,&omap_timer_list, node) {
> + if (t->reserved)
> continue;
>
> - timer =&dm_timers[i];
> + timer = t;
> timer->reserved = 1;
> break;
> }
> spin_unlock_irqrestore(&dm_timer_lock, flags);
>
> - if (timer != NULL)
> + if (timer)
> omap_dm_timer_prepare(timer);
> + else
> + pr_debug("%s: free timer not available.\n", __func__);
>
> return timer;
> }
> @@ -395,23 +398,23 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request);
>
> struct omap_dm_timer *omap_dm_timer_request_specific(int id)
> {
> - struct omap_dm_timer *timer;
> + struct omap_dm_timer *timer = NULL, *t;
> unsigned long flags;
>
> spin_lock_irqsave(&dm_timer_lock, flags);
> - if (id<= 0 || id> dm_timer_count || dm_timers[id-1].reserved) {
> - spin_unlock_irqrestore(&dm_timer_lock, flags);
> - printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
> - __FILE__, __LINE__, __func__, id);
> - dump_stack();
> - return NULL;
> + list_for_each_entry(t,&omap_timer_list, node) {
> + if (t->id == id&& !t->reserved) {
> + timer = t;
> + timer->reserved = 1;
> + break;
> + }
> }
> -
> - timer =&dm_timers[id-1];
> - timer->reserved = 1;
> spin_unlock_irqrestore(&dm_timer_lock, flags);
>
> - omap_dm_timer_prepare(timer);
> + if (timer)
> + omap_dm_timer_prepare(timer);
> + else
> + pr_debug("%s: timer%d not available.\n", __func__, id);
>
> return timer;
> }
> @@ -474,24 +477,29 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
> */
> __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
> {
> - int i;
> + int i = 0;
> + struct omap_dm_timer *timer = NULL;
> + unsigned long flags;
>
> /* If ARMXOR cannot be idled this function call is unnecessary */
> if (!(inputmask& (1<< 1)))
> return inputmask;
>
> /* If any active timer is using ARMXOR return modified mask */
> - for (i = 0; i< dm_timer_count; i++) {
> + spin_lock_irqsave(&dm_timer_lock, flags);
> + list_for_each_entry(timer,&omap_timer_list, node) {
> u32 l;
>
> - l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
> + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
> if (l& OMAP_TIMER_CTRL_ST) {
> if (((omap_readl(MOD_CONF_CTRL_1)>> (i * 2))& 0x03) == 0)
> inputmask&= ~(1<< 1);
> else
> inputmask&= ~(1<< 2);
> }
> + i++;
> }
> + spin_unlock_irqrestore(&dm_timer_lock, flags);
>
> return inputmask;
> }
> @@ -722,13 +730,9 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
>
> int omap_dm_timers_active(void)
> {
> - int i;
> -
> - for (i = 0; i< dm_timer_count; i++) {
> - struct omap_dm_timer *timer;
> -
> - timer =&dm_timers[i];
> + struct omap_dm_timer *timer;
>
> + list_for_each_entry(timer,&omap_timer_list, node) {
> if (!timer->enabled)
> continue;
>
> @@ -743,14 +747,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
>
> int __init omap_dm_timer_init(void)
> {
> + unsigned long flags;
> struct omap_dm_timer *timer;
> int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
>
> if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
> return -ENODEV;
>
> - spin_lock_init(&dm_timer_lock);
> -
> if (cpu_class_is_omap1()) {
> dm_timers = omap1_dm_timers;
> dm_timer_count = omap1_dm_timer_count;
> @@ -795,6 +798,10 @@ int __init omap_dm_timer_init(void)
> timer->fclk = clk_get(NULL, clk_name);
> }
> #endif
> + timer->id = i + 1; /* id starts from 1*/
> + spin_lock_irqsave(&dm_timer_lock, flags);
> + list_add_tail(&timer->node,&omap_timer_list);
> + spin_unlock_irqrestore(&dm_timer_lock, flags);
> }
>
> return 0;
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
2010-11-20 2:39 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Tarun Kanti DebBarma
` (2 preceding siblings ...)
2010-11-22 8:24 ` Varadarajan, Charulatha
@ 2010-11-23 17:51 ` Cousson, Benoit
2010-11-24 7:30 ` DebBarma, Tarun Kanti
3 siblings, 1 reply; 42+ messages in thread
From: Cousson, Benoit @ 2010-11-23 17:51 UTC (permalink / raw)
To: Tarun Kanti DebBarma; +Cc: linux-omap, Gopinath, Thara, Basak, Partha
On 11/20/2010 3:39 AM, Tarun Kanti DebBarma wrote:
> From: Thara Gopinath<thara@ti.com>
>
> Add routines to converts dmtimers to platform devices. The device data
> is obtained from hwmod database of respective platform and is registered
> to device model after successful binding to driver. It also provides
> provision to access timers during early boot when pm_runtime framework
> is not completely up and running.
>
> Signed-off-by: Thara Gopinath<thara@ti.com>
> Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> [p-basak2@ti.com: pm_runtime logic]
> Signed-off-by: Partha Basak<p-basak2@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 2 +-
> arch/arm/mach-omap2/dmtimer.c | 296 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 297 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-omap2/dmtimer.c
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index ce7b1f0..148f4d7 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -4,7 +4,7 @@
>
> # Common support
> obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
> - common.o
> + common.o dmtimer.o
>
> omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
> hwmod-common = omap_hwmod.o \
> diff --git a/arch/arm/mach-omap2/dmtimer.c b/arch/arm/mach-omap2/dmtimer.c
> new file mode 100644
> index 0000000..b5951b1
> --- /dev/null
> +++ b/arch/arm/mach-omap2/dmtimer.c
> @@ -0,0 +1,296 @@
> +/**
> + * OMAP2PLUS Dual-Mode Timers - platform device registration
> + *
> + * Contains first level initialization routines which extracts timers
> + * information from hwmod database and registers with linux device model.
> + * It also has low level function to chnage the timer input clock source.
typo.
> + *
> + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
> + * Tarun Kanti DebBarma<tarun.kanti@ti.com>
> + *
> + * Copyright (C) 2010 Texas Instruments Incorporated
> + * Thara Gopinath<thara@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#undef DEBUG
I guess, that undef should not be there?
> +
> +#include<linux/clk.h>
> +#include<linux/delay.h>
> +#include<linux/io.h>
> +#include<linux/err.h>
> +#include<linux/slab.h>
> +
> +#include<mach/irqs.h>
Do you still need that?
> +#include<plat/dmtimer.h>
> +#include<plat/powerdomain.h>
Why do you need powerdomain in that file?
> +#include<plat/omap_hwmod.h>
> +#include<plat/omap_device.h>
> +#include<linux/pm_runtime.h>
> +
> +static int early_timer_count __initdata = 1;
> +
> +/**
> + * omap2_dm_timer_set_src - change the timer input clock source
> + * @pdev: timer platform device pointer
> + * @timer_clk: current clock source
> + * @source: array index of parent clock source
> + */
> +static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
> +{
> + int ret;
> + struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
> + struct clk *fclk = clk_get(&pdev->dev, "fck");
> + struct clk *new_fclk;
> + char *fclk_name = "32k_ck"; /* default name */
> +
> + switch(source) {
> + case OMAP_TIMER_SRC_SYS_CLK:
> + fclk_name = "sys_ck";
> + break;
> +
> + case OMAP_TIMER_SRC_32_KHZ:
> + fclk_name = "32k_ck";
> + break;
> +
> + case OMAP_TIMER_SRC_EXT_CLK:
> + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_1) {
> + fclk_name = "alt_ck";
> + break;
> + }
> + dev_dbg(&pdev->dev, "%s:%d: invalid clk src.\n",
> + __func__, __LINE__);
> + return -EINVAL;
> + }
Do you really have to maintain the source enum? Cannot you just pass the
char* to this API?
It will avoid that code, and make that API much more flexible if we have
to add extra clock source in the future.
If the clock does not exist in a particular Soc, the clk_get will fail
and that's all you have to know.
> +
> +
> + if (IS_ERR_OR_NULL(fclk)) {
> + dev_dbg(&pdev->dev, "%s:%d: clk_get() FAILED\n",
> + __func__, __LINE__);
> + return -EINVAL;
> + }
> +
> + new_fclk = clk_get(&pdev->dev, fclk_name);
> + if (IS_ERR_OR_NULL(new_fclk)) {
> + dev_dbg(&pdev->dev, "%s:%d: clk_get() %s FAILED\n",
> + __func__, __LINE__, fclk_name);
> + clk_put(fclk);
> + return -EINVAL;
> + }
> +
> + ret = clk_set_parent(fclk, new_fclk);
> + if (IS_ERR_VALUE(ret)) {
> + dev_dbg(&pdev->dev, "%s:clk_set_parent() to %s FAILED\n",
> + __func__, fclk_name);
> + ret = -EINVAL;
> + }
> +
> + clk_put(new_fclk);
> + clk_put(fclk);
> +
> + return ret;
> +}
> +
> +struct omap_device_pm_latency omap2_dmtimer_latency[] = {
> + {
> + .deactivate_func = omap_device_idle_hwmods,
> + .activate_func = omap_device_enable_hwmods,
> + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
> + },
> +};
> +
> +/**
> + * omap_dm_timer_early_init - build and register early timer device
> + * with an associated timer hwmod
> + * @oh: timer hwmod pointer to be used to build timer device
> + * @user: parameter that can be passed from calling hwmod API
> + *
> + * early init is called in the last part of omap2_init_common_hw
> + * for each early timer class using omap_hwmod_for_each_by_class.
> + * it registers each of the timer devices present in the system.
typo: It
> + * at the end of function call memory is allocated for omap_device
Typo: At... There are tons of typo like that in your patches, so I'm not
going to highlight them all. You should do a check of the whole series.
> + * and hwmod for early timer and the device is registered to the
> + * framework ready to be probed by the driver.
> + */
> +static int __init omap2_timer_early_init(struct omap_hwmod *oh, void *user)
> +{
> + int id;
> + int ret = 0;
> + char *name = "omap-timer";
Please use "omap_timer" instead in order to be consistent with other
omap devices.
> + struct dmtimer_platform_data *pdata;
> + struct omap_device *od;
> +
> + pr_debug("%s:%s\n", __func__, oh->name);
> +
> + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> + if (!pdata) {
> + pr_err("%s: No memory for [%s]\n", __func__, oh->name);
> + return -ENOMEM;
> + }
> +
> + pdata->is_early_init = 1;
> +
> + /* hook clock set/get functions */
> + pdata->set_timer_src = omap2_dm_timer_set_src;
> +
> + /* read timer ip version */
> + pdata->timer_ip_type = oh->class->rev;
> + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
> + pdata->func_offst = 0x14;
> + pdata->intr_offst = 0x10;
You should use the defines here instead of the hard coded values.
XXX_TIOCP_CFG, XXX_IRQSTATUS_RAW - XXX_TIOCP_CFG...
> + } else {
> + pdata->func_offst = 0;
> + pdata->intr_offst = 0;
> + }
> +
> + /*
> + * extract the id from name filed in hwmod database
> + * and use the same for constructing ids' for the
> + * timer devices. in a way, we are avoiding usage of
> + * static variable witin the function to do the same.
> + * CAUTION: we have to be careful and make sure the
> + * name in hwmod database does not change in which case
> + * we might either make corresponding change here or
> + * switch back static variable mechanism.
> + */
> + sscanf(oh->name, "timer%2d",&id);
> +
> + od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
> + omap2_dmtimer_latency,
> + ARRAY_SIZE(omap2_dmtimer_latency), 1);
> +
> + if (IS_ERR(od)) {
> + pr_err("%s: Cant build omap_device for %s:%s.\n",
> + __func__, name, oh->name);
> + ret = -EINVAL;
> + } else
> + early_timer_count++;
Blank line here.
> + /*
> + * pdata can be freed because omap_device_build
> + * creates its own memory pool
> + */
> + kfree(pdata);
> +
> + return ret;
> +}
> +
> +/**
> + * omap2_dm_timer_init - build and register timer device with an
> + * associated timer hwmod
> + * @oh: timer hwmod pointer to be used to build timer device
> + * @user: parameter that can be passed from calling hwmod API
> + *
> + * called by omap_hwmod_for_each_by_class to register each of the timer
> + * devices present in the system. the number of timer devices is known
> + * by parsing through the hwmod database for a given class name. at the
> + * end of function call memory is allocated for omap_device and hwmod
> + * for timer and the device is registered to the framework ready to be
> + * proved by the driver.
> + */
> +static int __init omap2_timer_init(struct omap_hwmod *oh, void *user)
> +{
> + int id;
> + int ret = 0;
> + char *name = "omap-timer";
> + struct omap_device *od;
> + struct dmtimer_platform_data *pdata;
> +
> + if (!oh) {
> + pr_err("%s:NULL hwmod pointer (oh)\n", __func__);
> + return -EINVAL;
> + }
> + pr_debug("%s:%s\n", __func__, oh->name);
> +
> + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> + if (!pdata) {
> + pr_err("%s:No memory for [%s]\n", __func__, oh->name);
> + return -ENOMEM;
> + }
> +
> + pdata->is_early_init = 0;
> +
> + /* hook clock set/get functions */
> + pdata->set_timer_src = omap2_dm_timer_set_src;
> +
> + /* read timer ip version */
> + pdata->timer_ip_type = oh->class->rev;
> + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
> + pdata->func_offst = 0x14;
> + pdata->intr_offst = 0x10;
> + } else {
> + pdata->func_offst = 0;
> + pdata->intr_offst = 0;
> + }
> +
> + /*
> + * extract the id from name filed in hwmod database
> + * and use the same for constructing ids' for the
> + * timer devices. in a way, we are avoiding usage of
> + * static variable witin the function to do the same.
typo: within
> + * CAUTION: we have to be careful and make sure the
> + * name in hwmod database does not change in which case
> + * we might either make corresponding change here or
> + * switch back static variable mechanism.
> + */
> + sscanf(oh->name, "timer%2d",&id);
> +
> + od = omap_device_build(name, id, oh,
> + pdata, sizeof(*pdata),
> + omap2_dmtimer_latency,
> + ARRAY_SIZE(omap2_dmtimer_latency), 0);
> +
> + if (IS_ERR(od)) {
> + pr_err("%s: Cant build omap_device for %s:%s.\n",
typo: can't
> + __func__, name, oh->name);
> + ret = -EINVAL;
> + }
Blank line here.
> + /*
> + * pdata can be freed because omap_device_build
> + * creates its own memory pool
> + */
> + kfree(pdata);
> + return ret;
> +}
That function is a pure duplication of the omap2_timer_early_init one.
You can probably use the "user" extra parameters to handle the small
differences between them (is_early_init).
> +
> +/**
> + * omap2_dm_timer_early_init - top level early timer initialization
> + * called in the last part of omap2_init_common_hw
> + *
> + * uses dedicated hwmod api to parse through hwmod database for
> + * given class name and then build and register the timer device.
> + * at the end driver is registered and early probe initiated.
> + */
> +void __init omap2_dm_timer_early_init(void)
> +{
> + if (omap_hwmod_for_each_by_class("timer",
> + omap2_timer_early_init, NULL)) {
For better readability, you'd better not call that function directly in
the if statement.
> + pr_debug("%s: device registration FAILED\n", __func__);
> + return;
> + }
Blank line here.
> + early_platform_driver_register_all("earlytimer");
> + early_platform_driver_probe("earlytimer", early_timer_count, 0);
> +}
> +
> +/**
> + * omap_timer_init - top level timer device initialization
> + *
> + * uses dedicated hwmod api to parse through hwmod database for
> + * given class names and then build and register the timer device.
> + */
> +static int __init omap2_dmtimer_device_init(void)
Most of the functions here are using _dm_timer_. You should align this
name too.
Benoit
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod
2010-11-23 14:48 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Cousson, Benoit
@ 2010-11-24 6:53 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-24 6:53 UTC (permalink / raw)
To: Cousson, Benoit; +Cc: linux-omap, Gopinath, Thara
> -----Original Message-----
> From: Cousson, Benoit
> Sent: Tuesday, November 23, 2010 8:19 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Gopinath, Thara
> Subject: Re: [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod
>
> On 11/20/2010 3:39 AM, DebBarma, Tarun Kanti wrote:
> > (1) Add new fields and data structures to support dmtimer conversion
> > to platform driver.
> > (2) Constants to identify IP revision so that Highlander IP in OMAP 4
> > can be distinguished.
> > (3) field to identify OMAP4 abe timers.
> > (4) Interface function to support early boot.
> >
> > Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> > Signed-off-by: Thara Gopinath<thara@ti.com>
> > ---
> > arch/arm/mach-omap2/dmtimer.h | 32
> +++++++++++++++++++++++++++++
> > arch/arm/plat-omap/dmtimer.c | 8 +++++++
> > arch/arm/plat-omap/include/plat/dmtimer.h | 19 +++++++++++++++++
> > 3 files changed, 59 insertions(+), 0 deletions(-)
> > create mode 100644 arch/arm/mach-omap2/dmtimer.h
> >
> > diff --git a/arch/arm/mach-omap2/dmtimer.h b/arch/arm/mach-
> omap2/dmtimer.h
> > new file mode 100644
> > index 0000000..4d4493b
> > --- /dev/null
> > +++ b/arch/arm/mach-omap2/dmtimer.h
> > @@ -0,0 +1,32 @@
> > +/**
> > + * OMAP Dual-Mode Timers - early initialization interface
> > + *
> > + * function interface called first to start dmtimer early
> initialization.
> > + *
> > + * Copyright (C) 2010 Texas Instruments Incorporated -
> http://www.ti.com/
> > + * Tarun Kanti DebBarma<tarun.kanti@ti.com>
> > + *
> > + * Copyright (C) 2010 Texas Instruments Incorporated
> > + * Thara Gopinath<thara@ti.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +#ifndef __ASM_ARCH_DMTIMER_H
> > +#define __ASM_ARCH_DMTIMER_H
> > +
> > +/*
> > + * dmtimer is required during early part of boot sequence even before
> > + * device model and pm_runtime if fully up and running. this function
> > + * provides hook to omap2_init_common_hw() which is triggered from
> > + * start_kernel()->init_irq() of kernel initialization sequence.
> > + */
> > +void __init omap2_dm_timer_early_init(void);
> > +
> > +#endif
> > diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> > index 1d706cf..10daa9d 100644
> > --- a/arch/arm/plat-omap/dmtimer.c
> > +++ b/arch/arm/plat-omap/dmtimer.c
> > @@ -3,6 +3,12 @@
> > *
> > * OMAP Dual-Mode Timers
> > *
> > + * Copyright (C) 2010 Texas Instruments Incorporated -
> http://www.ti.com/
> > + * Tarun Kanti DebBarma<tarun.kanti@ti.com>
> > + *
> > + * Copyright (C) 2010 Texas Instruments Incorporated
> > + * Thara Gopinath<thara@ti.com>
>
> You can remove the copyright and put Thara's name below yours.
> It should be the case for other field as well.
Ok.
>
> > + *
> > * Copyright (C) 2005 Nokia Corporation
> > * OMAP2 support by Juha Yrjola
> > * API improvements and OMAP2 clock framework support by Timo Teras
> > @@ -151,6 +157,7 @@
> > (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR<< WPSHIFT))
> >
> > struct omap_dm_timer {
> > + int id;
> > unsigned long phys_base;
> > int irq;
> > #ifdef CONFIG_ARCH_OMAP2PLUS
> > @@ -160,6 +167,7 @@ struct omap_dm_timer {
> > unsigned reserved:1;
> > unsigned enabled:1;
> > unsigned posted:1;
> > + struct platform_device *pdev;
> > };
>
> What that structure is used for? Is it some legacy structure that will
> be removed in next patches? It seems to be a wrapper on top of the
> device that should not be used anymore after platform_driver migration.
No, this structure is used to maintain list of some dynamically manipulated
Information to indicate if the timer is reserved or free, enabled or
Disabled, fclk and so on. It also has static information like irq, base
Address. If we are not allowed to have sort of list in the driver then
There are we have to modify the export APIs which assume this structure.
In that case it would be better to incorporate in separate patch series.
Another point is that I need to figure out how to get pointer to
platform_device for a given device name. If you know the answer please
let me know.
>
> >
> > static int dm_timer_count;
> > diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-
> omap/include/plat/dmtimer.h
> > index dfa3aff..2bb837e 100644
> > --- a/arch/arm/plat-omap/include/plat/dmtimer.h
> > +++ b/arch/arm/plat-omap/include/plat/dmtimer.h
> > @@ -3,6 +3,11 @@
> > *
> > * OMAP Dual-Mode Timers
> > *
> > + * Copyright (C) 2010 Texas Instruments Incorporated -
> http://www.ti.com/
> > + * Tarun Kanti DebBarma<tarun.kanti@ti.com>
> > + * Thara Gopinath<thara@ti.com>
>
> Add a blank line here.
>
> > + * Platform device conversion and hwmod support.
> > + *
> > * Copyright (C) 2005 Nokia Corporation
> > * Author: Lauri Leukkunen<lauri.leukkunen@nokia.com>
> > * PWM and clock framwork support by Timo Teras.
> > @@ -29,6 +34,8 @@
> > #ifndef __ASM_ARCH_DMTIMER_H
> > #define __ASM_ARCH_DMTIMER_H
> >
> > +#include<linux/platform_device.h>
> > +
> > /* clock sources */
> > #define OMAP_TIMER_SRC_SYS_CLK 0x00
> > #define OMAP_TIMER_SRC_32_KHZ 0x01
> > @@ -44,11 +51,23 @@
> > #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
> > #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPAR 0x02
> >
> > +/* timer ip constants */
>
> Maybe you should have a better comment here?
> Something closer to your changelog: IP revision identifier so that
> Highlander IP in OMAP 4 can be distinguished.
OK.
>
> > +#define OMAP_TIMER_IP_VERSION_1 0x1
> > +#define OMAP_TIMER_IP_VERSION_2 0x2
> > +
> > struct omap_dm_timer;
> > extern struct omap_dm_timer *gptimer_wakeup;
> > extern struct sys_timer omap_timer;
> > struct clk;
> >
> > +struct dmtimer_platform_data {
> > + int (*set_timer_src) (struct platform_device *pdev, int source);
> > + int timer_ip_type;
> > + u8 func_offst;
> > + u8 intr_offst;
>
> You can probably keep "offset" since you save only one character...
OK.
--
Tarun
>
> > + u32 is_early_init:1;
> > +};
> > +
> > int omap_dm_timer_init(void);
> >
> > struct omap_dm_timer *omap_dm_timer_request(void);
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array
2010-11-23 15:22 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Cousson, Benoit
@ 2010-11-24 7:01 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-24 7:01 UTC (permalink / raw)
To: Cousson, Benoit; +Cc: linux-omap
> -----Original Message-----
> From: Cousson, Benoit
> Sent: Tuesday, November 23, 2010 8:52 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org
> Subject: Re: [PATCHv4 7/14] OMAP: dmtimer: use list instead of static
> array
>
> On 11/20/2010 3:39 AM, Tarun Kanti DebBarma wrote:
> > Convert dmtimers static array in functions into list structure.
> > Please note that the static arrays will be completely removed
> > in subsequent patches when dmtimer is converted to platform driver.
>
> Why do you still need to keep your own list of timers?
> The driver already contains a list of devices.
> You even have some iterator available in the kernel:
> driver_for_each_device or driver_find_device.
>
> You could probably get rid of all that stuff for my point of view.
Ok, this partially answers my previous email.
As I said this would involve change of exported APIs.
I will try making the change to avoid this if possible.
Thanks.
--
Tarun
>
> >
> > Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> > ---
> > arch/arm/plat-omap/dmtimer.c | 67 +++++++++++++++++++++++-----------
> --------
> > 1 files changed, 37 insertions(+), 30 deletions(-)
> >
> > diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> > index 10daa9d..124fd21 100644
> > --- a/arch/arm/plat-omap/dmtimer.c
> > +++ b/arch/arm/plat-omap/dmtimer.c
> > @@ -168,6 +168,7 @@ struct omap_dm_timer {
> > unsigned enabled:1;
> > unsigned posted:1;
> > struct platform_device *pdev;
> > + struct list_head node;
> > };
> >
> > static int dm_timer_count;
> > @@ -290,7 +291,8 @@ static struct omap_dm_timer *dm_timers;
> > static const char **dm_source_names;
> > static struct clk **dm_source_clocks;
> >
> > -static spinlock_t dm_timer_lock;
> > +static LIST_HEAD(omap_timer_list);
> > +static DEFINE_SPINLOCK(dm_timer_lock);
> >
> > /*
> > * Reads timer registers in posted and non-posted mode. The posted
> mode bit
> > @@ -340,7 +342,7 @@ static void omap_dm_timer_reset(struct omap_dm_timer
> *timer)
> > {
> > u32 l;
> >
> > - if (!cpu_class_is_omap2() || timer !=&dm_timers[0]) {
> > + if (!cpu_class_is_omap2() || timer->id != 1) {
> > omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
> > omap_dm_timer_wait_for_reset(timer);
> > }
> > @@ -371,23 +373,24 @@ static void omap_dm_timer_prepare(struct
> omap_dm_timer *timer)
> >
> > struct omap_dm_timer *omap_dm_timer_request(void)
> > {
> > - struct omap_dm_timer *timer = NULL;
> > + struct omap_dm_timer *timer = NULL, *t;
> > unsigned long flags;
> > - int i;
> >
> > spin_lock_irqsave(&dm_timer_lock, flags);
> > - for (i = 0; i< dm_timer_count; i++) {
> > - if (dm_timers[i].reserved)
> > + list_for_each_entry(t,&omap_timer_list, node) {
> > + if (t->reserved)
> > continue;
> >
> > - timer =&dm_timers[i];
> > + timer = t;
> > timer->reserved = 1;
> > break;
> > }
> > spin_unlock_irqrestore(&dm_timer_lock, flags);
> >
> > - if (timer != NULL)
> > + if (timer)
> > omap_dm_timer_prepare(timer);
> > + else
> > + pr_debug("%s: free timer not available.\n", __func__);
> >
> > return timer;
> > }
> > @@ -395,23 +398,23 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request);
> >
> > struct omap_dm_timer *omap_dm_timer_request_specific(int id)
> > {
> > - struct omap_dm_timer *timer;
> > + struct omap_dm_timer *timer = NULL, *t;
> > unsigned long flags;
> >
> > spin_lock_irqsave(&dm_timer_lock, flags);
> > - if (id<= 0 || id> dm_timer_count || dm_timers[id-1].reserved) {
> > - spin_unlock_irqrestore(&dm_timer_lock, flags);
> > - printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
> > - __FILE__, __LINE__, __func__, id);
> > - dump_stack();
> > - return NULL;
> > + list_for_each_entry(t,&omap_timer_list, node) {
> > + if (t->id == id&& !t->reserved) {
> > + timer = t;
> > + timer->reserved = 1;
> > + break;
> > + }
> > }
> > -
> > - timer =&dm_timers[id-1];
> > - timer->reserved = 1;
> > spin_unlock_irqrestore(&dm_timer_lock, flags);
> >
> > - omap_dm_timer_prepare(timer);
> > + if (timer)
> > + omap_dm_timer_prepare(timer);
> > + else
> > + pr_debug("%s: timer%d not available.\n", __func__, id);
> >
> > return timer;
> > }
> > @@ -474,24 +477,29 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
> > */
> > __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
> > {
> > - int i;
> > + int i = 0;
> > + struct omap_dm_timer *timer = NULL;
> > + unsigned long flags;
> >
> > /* If ARMXOR cannot be idled this function call is unnecessary */
> > if (!(inputmask& (1<< 1)))
> > return inputmask;
> >
> > /* If any active timer is using ARMXOR return modified mask */
> > - for (i = 0; i< dm_timer_count; i++) {
> > + spin_lock_irqsave(&dm_timer_lock, flags);
> > + list_for_each_entry(timer,&omap_timer_list, node) {
> > u32 l;
> >
> > - l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
> > + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
> > if (l& OMAP_TIMER_CTRL_ST) {
> > if (((omap_readl(MOD_CONF_CTRL_1)>> (i * 2))& 0x03) == 0)
> > inputmask&= ~(1<< 1);
> > else
> > inputmask&= ~(1<< 2);
> > }
> > + i++;
> > }
> > + spin_unlock_irqrestore(&dm_timer_lock, flags);
> >
> > return inputmask;
> > }
> > @@ -722,13 +730,9 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
> >
> > int omap_dm_timers_active(void)
> > {
> > - int i;
> > -
> > - for (i = 0; i< dm_timer_count; i++) {
> > - struct omap_dm_timer *timer;
> > -
> > - timer =&dm_timers[i];
> > + struct omap_dm_timer *timer;
> >
> > + list_for_each_entry(timer,&omap_timer_list, node) {
> > if (!timer->enabled)
> > continue;
> >
> > @@ -743,14 +747,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
> >
> > int __init omap_dm_timer_init(void)
> > {
> > + unsigned long flags;
> > struct omap_dm_timer *timer;
> > int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
> >
> > if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
> > return -ENODEV;
> >
> > - spin_lock_init(&dm_timer_lock);
> > -
> > if (cpu_class_is_omap1()) {
> > dm_timers = omap1_dm_timers;
> > dm_timer_count = omap1_dm_timer_count;
> > @@ -795,6 +798,10 @@ int __init omap_dm_timer_init(void)
> > timer->fclk = clk_get(NULL, clk_name);
> > }
> > #endif
> > + timer->id = i + 1; /* id starts from 1*/
> > + spin_lock_irqsave(&dm_timer_lock, flags);
> > + list_add_tail(&timer->node,&omap_timer_list);
> > + spin_unlock_irqrestore(&dm_timer_lock, flags);
> > }
> >
> > return 0;
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
2010-11-23 17:51 ` Cousson, Benoit
@ 2010-11-24 7:30 ` DebBarma, Tarun Kanti
0 siblings, 0 replies; 42+ messages in thread
From: DebBarma, Tarun Kanti @ 2010-11-24 7:30 UTC (permalink / raw)
To: Cousson, Benoit; +Cc: linux-omap, Gopinath, Thara, Basak, Partha
> -----Original Message-----
> From: Cousson, Benoit
> Sent: Tuesday, November 23, 2010 11:21 PM
> To: DebBarma, Tarun Kanti
> Cc: linux-omap@vger.kernel.org; Gopinath, Thara; Basak, Partha
> Subject: Re: [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices
>
> On 11/20/2010 3:39 AM, Tarun Kanti DebBarma wrote:
> > From: Thara Gopinath<thara@ti.com>
> >
> > Add routines to converts dmtimers to platform devices. The device data
> > is obtained from hwmod database of respective platform and is registered
> > to device model after successful binding to driver. It also provides
> > provision to access timers during early boot when pm_runtime framework
> > is not completely up and running.
> >
> > Signed-off-by: Thara Gopinath<thara@ti.com>
> > Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> > [p-basak2@ti.com: pm_runtime logic]
> > Signed-off-by: Partha Basak<p-basak2@ti.com>
> > ---
> > arch/arm/mach-omap2/Makefile | 2 +-
> > arch/arm/mach-omap2/dmtimer.c | 296
> +++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 297 insertions(+), 1 deletions(-)
> > create mode 100644 arch/arm/mach-omap2/dmtimer.c
> >
> > diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> > index ce7b1f0..148f4d7 100644
> > --- a/arch/arm/mach-omap2/Makefile
> > +++ b/arch/arm/mach-omap2/Makefile
> > @@ -4,7 +4,7 @@
> >
> > # Common support
> > obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-
> gp.o pm.o \
> > - common.o
> > + common.o dmtimer.o
> >
> > omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
> > hwmod-common = omap_hwmod.o \
> > diff --git a/arch/arm/mach-omap2/dmtimer.c b/arch/arm/mach-
> omap2/dmtimer.c
> > new file mode 100644
> > index 0000000..b5951b1
> > --- /dev/null
> > +++ b/arch/arm/mach-omap2/dmtimer.c
> > @@ -0,0 +1,296 @@
> > +/**
> > + * OMAP2PLUS Dual-Mode Timers - platform device registration
> > + *
> > + * Contains first level initialization routines which extracts timers
> > + * information from hwmod database and registers with linux device
> model.
> > + * It also has low level function to chnage the timer input clock
> source.
>
> typo.
Will change.
>
> > + *
> > + * Copyright (C) 2010 Texas Instruments Incorporated -
> http://www.ti.com/
> > + * Tarun Kanti DebBarma<tarun.kanti@ti.com>
> > + *
> > + * Copyright (C) 2010 Texas Instruments Incorporated
> > + * Thara Gopinath<thara@ti.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +#undef DEBUG
>
> I guess, that undef should not be there?
Will remove.
>
> > +
> > +#include<linux/clk.h>
> > +#include<linux/delay.h>
> > +#include<linux/io.h>
> > +#include<linux/err.h>
> > +#include<linux/slab.h>
> > +
> > +#include<mach/irqs.h>
>
> Do you still need that?
It have been already removed. Thanks.
>
> > +#include<plat/dmtimer.h>
> > +#include<plat/powerdomain.h>
>
> Why do you need powerdomain in that file?
This is also removed. After code optimization and cleanup this got missed.
>
> > +#include<plat/omap_hwmod.h>
> > +#include<plat/omap_device.h>
> > +#include<linux/pm_runtime.h>
> > +
> > +static int early_timer_count __initdata = 1;
> > +
> > +/**
> > + * omap2_dm_timer_set_src - change the timer input clock source
> > + * @pdev: timer platform device pointer
> > + * @timer_clk: current clock source
> > + * @source: array index of parent clock source
> > + */
> > +static int omap2_dm_timer_set_src(struct platform_device *pdev, int
> source)
> > +{
> > + int ret;
> > + struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
> > + struct clk *fclk = clk_get(&pdev->dev, "fck");
> > + struct clk *new_fclk;
> > + char *fclk_name = "32k_ck"; /* default name */
> > +
> > + switch(source) {
> > + case OMAP_TIMER_SRC_SYS_CLK:
> > + fclk_name = "sys_ck";
> > + break;
> > +
> > + case OMAP_TIMER_SRC_32_KHZ:
> > + fclk_name = "32k_ck";
> > + break;
> > +
> > + case OMAP_TIMER_SRC_EXT_CLK:
> > + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_1) {
> > + fclk_name = "alt_ck";
> > + break;
> > + }
> > + dev_dbg(&pdev->dev, "%s:%d: invalid clk src.\n",
> > + __func__, __LINE__);
> > + return -EINVAL;
> > + }
>
> Do you really have to maintain the source enum? Cannot you just pass the
> char* to this API?
> It will avoid that code, and make that API much more flexible if we have
> to add extra clock source in the future.
> If the clock does not exist in a particular Soc, the clk_get will fail
> and that's all you have to know.
Right now the exported APIs use integer constants to identify different
Sources. So this can not be changed without wider implications.
Besides I have seen Paul Walmsley implementing in this way.
So you can suggest and I am OK.
>
> > +
> > +
> > + if (IS_ERR_OR_NULL(fclk)) {
> > + dev_dbg(&pdev->dev, "%s:%d: clk_get() FAILED\n",
> > + __func__, __LINE__);
> > + return -EINVAL;
> > + }
> > +
> > + new_fclk = clk_get(&pdev->dev, fclk_name);
> > + if (IS_ERR_OR_NULL(new_fclk)) {
> > + dev_dbg(&pdev->dev, "%s:%d: clk_get() %s FAILED\n",
> > + __func__, __LINE__, fclk_name);
> > + clk_put(fclk);
> > + return -EINVAL;
> > + }
> > +
> > + ret = clk_set_parent(fclk, new_fclk);
> > + if (IS_ERR_VALUE(ret)) {
> > + dev_dbg(&pdev->dev, "%s:clk_set_parent() to %s FAILED\n",
> > + __func__, fclk_name);
> > + ret = -EINVAL;
> > + }
> > +
> > + clk_put(new_fclk);
> > + clk_put(fclk);
> > +
> > + return ret;
> > +}
> > +
> > +struct omap_device_pm_latency omap2_dmtimer_latency[] = {
> > + {
> > + .deactivate_func = omap_device_idle_hwmods,
> > + .activate_func = omap_device_enable_hwmods,
> > + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
> > + },
> > +};
> > +
> > +/**
> > + * omap_dm_timer_early_init - build and register early timer device
> > + * with an associated timer hwmod
> > + * @oh: timer hwmod pointer to be used to build timer device
> > + * @user: parameter that can be passed from calling hwmod API
> > + *
> > + * early init is called in the last part of omap2_init_common_hw
> > + * for each early timer class using omap_hwmod_for_each_by_class.
> > + * it registers each of the timer devices present in the system.
>
> typo: It
>
> > + * at the end of function call memory is allocated for omap_device
>
> Typo: At... There are tons of typo like that in your patches, so I'm not
> going to highlight them all. You should do a check of the whole series.
Yes, I will make the correction.
>
> > + * and hwmod for early timer and the device is registered to the
> > + * framework ready to be probed by the driver.
> > + */
> > +static int __init omap2_timer_early_init(struct omap_hwmod *oh, void
> *user)
> > +{
> > + int id;
> > + int ret = 0;
> > + char *name = "omap-timer";
>
> Please use "omap_timer" instead in order to be consistent with other
> omap devices.
Yes, I have already made the change.
>
> > + struct dmtimer_platform_data *pdata;
> > + struct omap_device *od;
> > +
> > + pr_debug("%s:%s\n", __func__, oh->name);
> > +
> > + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> > + if (!pdata) {
> > + pr_err("%s: No memory for [%s]\n", __func__, oh->name);
> > + return -ENOMEM;
> > + }
> > +
> > + pdata->is_early_init = 1;
> > +
> > + /* hook clock set/get functions */
> > + pdata->set_timer_src = omap2_dm_timer_set_src;
> > +
> > + /* read timer ip version */
> > + pdata->timer_ip_type = oh->class->rev;
> > + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
> > + pdata->func_offst = 0x14;
> > + pdata->intr_offst = 0x10;
>
> You should use the defines here instead of the hard coded values.
> XXX_TIOCP_CFG, XXX_IRQSTATUS_RAW - XXX_TIOCP_CFG...
Ok.
>
> > + } else {
> > + pdata->func_offst = 0;
> > + pdata->intr_offst = 0;
> > + }
> > +
> > + /*
> > + * extract the id from name filed in hwmod database
> > + * and use the same for constructing ids' for the
> > + * timer devices. in a way, we are avoiding usage of
> > + * static variable witin the function to do the same.
> > + * CAUTION: we have to be careful and make sure the
> > + * name in hwmod database does not change in which case
> > + * we might either make corresponding change here or
> > + * switch back static variable mechanism.
> > + */
> > + sscanf(oh->name, "timer%2d",&id);
> > +
> > + od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
> > + omap2_dmtimer_latency,
> > + ARRAY_SIZE(omap2_dmtimer_latency), 1);
> > +
> > + if (IS_ERR(od)) {
> > + pr_err("%s: Cant build omap_device for %s:%s.\n",
> > + __func__, name, oh->name);
> > + ret = -EINVAL;
> > + } else
> > + early_timer_count++;
>
> Blank line here.
Ok.
>
> > + /*
> > + * pdata can be freed because omap_device_build
> > + * creates its own memory pool
> > + */
> > + kfree(pdata);
> > +
> > + return ret;
> > +}
> > +
> > +/**
> > + * omap2_dm_timer_init - build and register timer device with an
> > + * associated timer hwmod
> > + * @oh: timer hwmod pointer to be used to build timer device
> > + * @user: parameter that can be passed from calling hwmod API
> > + *
> > + * called by omap_hwmod_for_each_by_class to register each of the timer
> > + * devices present in the system. the number of timer devices is known
> > + * by parsing through the hwmod database for a given class name. at the
> > + * end of function call memory is allocated for omap_device and hwmod
> > + * for timer and the device is registered to the framework ready to be
> > + * proved by the driver.
> > + */
> > +static int __init omap2_timer_init(struct omap_hwmod *oh, void *user)
> > +{
> > + int id;
> > + int ret = 0;
> > + char *name = "omap-timer";
> > + struct omap_device *od;
> > + struct dmtimer_platform_data *pdata;
> > +
> > + if (!oh) {
> > + pr_err("%s:NULL hwmod pointer (oh)\n", __func__);
> > + return -EINVAL;
> > + }
> > + pr_debug("%s:%s\n", __func__, oh->name);
> > +
> > + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> > + if (!pdata) {
> > + pr_err("%s:No memory for [%s]\n", __func__, oh->name);
> > + return -ENOMEM;
> > + }
> > +
> > + pdata->is_early_init = 0;
> > +
> > + /* hook clock set/get functions */
> > + pdata->set_timer_src = omap2_dm_timer_set_src;
> > +
> > + /* read timer ip version */
> > + pdata->timer_ip_type = oh->class->rev;
> > + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
> > + pdata->func_offst = 0x14;
> > + pdata->intr_offst = 0x10;
> > + } else {
> > + pdata->func_offst = 0;
> > + pdata->intr_offst = 0;
> > + }
> > +
> > + /*
> > + * extract the id from name filed in hwmod database
> > + * and use the same for constructing ids' for the
> > + * timer devices. in a way, we are avoiding usage of
> > + * static variable witin the function to do the same.
>
> typo: within
Ok.
>
> > + * CAUTION: we have to be careful and make sure the
> > + * name in hwmod database does not change in which case
> > + * we might either make corresponding change here or
> > + * switch back static variable mechanism.
> > + */
> > + sscanf(oh->name, "timer%2d",&id);
> > +
> > + od = omap_device_build(name, id, oh,
> > + pdata, sizeof(*pdata),
> > + omap2_dmtimer_latency,
> > + ARRAY_SIZE(omap2_dmtimer_latency), 0);
> > +
> > + if (IS_ERR(od)) {
> > + pr_err("%s: Cant build omap_device for %s:%s.\n",
>
> typo: can't
Ok.
>
> > + __func__, name, oh->name);
> > + ret = -EINVAL;
> > + }
>
> Blank line here.
Ok.
>
> > + /*
> > + * pdata can be freed because omap_device_build
> > + * creates its own memory pool
> > + */
> > + kfree(pdata);
> > + return ret;
> > +}
>
> That function is a pure duplication of the omap2_timer_early_init one.
> You can probably use the "user" extra parameters to handle the small
> differences between them (is_early_init).
Sounds good! I will try.
>
> > +
> > +/**
> > + * omap2_dm_timer_early_init - top level early timer initialization
> > + * called in the last part of omap2_init_common_hw
> > + *
> > + * uses dedicated hwmod api to parse through hwmod database for
> > + * given class name and then build and register the timer device.
> > + * at the end driver is registered and early probe initiated.
> > + */
> > +void __init omap2_dm_timer_early_init(void)
> > +{
> > + if (omap_hwmod_for_each_by_class("timer",
> > + omap2_timer_early_init, NULL)) {
>
> For better readability, you'd better not call that function directly in
> the if statement.
Ok.
>
> > + pr_debug("%s: device registration FAILED\n", __func__);
> > + return;
> > + }
>
> Blank line here.
Ok.
>
> > + early_platform_driver_register_all("earlytimer");
> > + early_platform_driver_probe("earlytimer", early_timer_count, 0);
> > +}
> > +
> > +/**
> > + * omap_timer_init - top level timer device initialization
> > + *
> > + * uses dedicated hwmod api to parse through hwmod database for
> > + * given class names and then build and register the timer device.
> > + */
> > +static int __init omap2_dmtimer_device_init(void)
>
> Most of the functions here are using _dm_timer_. You should align this
> name too.
Ok, thanks.
--
Tarun
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2010-11-24 7:30 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-11-20 2:39 [PATCHv4 0/14] dmtimer adaptation to platform_driver Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 3/14] OMAP2420: dmtimer: add hwmod database Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 4/14] OMAP2430: " Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 5/14] OMAP3: " Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 6/14] OMAP4: " Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 9/14] OMAP1: dmtimer: conversion to platform devices Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 10/14] OMAP: dmtimer: access routines to interrupt registers Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 13/14] OMAP: dmtimer: remove reset function Tarun Kanti DebBarma
2010-11-20 2:39 ` [PATCHv4 14/14] OMAP: dmtimer: pm_runtime support Tarun Kanti DebBarma
2010-11-22 7:04 ` Varadarajan, Charulatha
2010-11-22 7:07 ` DebBarma, Tarun Kanti
2010-11-22 6:44 ` [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver Varadarajan, Charulatha
2010-11-22 9:14 ` DebBarma, Tarun Kanti
2010-11-22 12:00 ` Varadarajan, Charulatha
2010-11-22 12:08 ` DebBarma, Tarun Kanti
2010-11-22 12:35 ` Varadarajan, Charulatha
2010-11-22 12:55 ` DebBarma, Tarun Kanti
2010-11-22 6:33 ` [PATCHv4 11/14] OMAP2+: dmtimer: convert to platform devices Varadarajan, Charulatha
2010-11-22 7:24 ` DebBarma, Tarun Kanti
2010-11-22 8:24 ` Varadarajan, Charulatha
2010-11-22 9:00 ` DebBarma, Tarun Kanti
2010-11-22 9:03 ` Varadarajan, Charulatha
2010-11-23 17:51 ` Cousson, Benoit
2010-11-24 7:30 ` DebBarma, Tarun Kanti
2010-11-22 7:13 ` [PATCHv4 8/14] OMAP: dmtimer: platform driver Varadarajan, Charulatha
2010-11-22 7:26 ` DebBarma, Tarun Kanti
2010-11-23 15:22 ` [PATCHv4 7/14] OMAP: dmtimer: use list instead of static array Cousson, Benoit
2010-11-24 7:01 ` DebBarma, Tarun Kanti
2010-11-22 6:02 ` [PATCHv4 6/14] OMAP4: dmtimer: add hwmod database Varadarajan, Charulatha
2010-11-22 6:11 ` DebBarma, Tarun Kanti
2010-11-23 14:48 ` [PATCHv4 2/14] OMAP: dmtimer: infrastructure to support hwmod Cousson, Benoit
2010-11-24 6:53 ` DebBarma, Tarun Kanti
2010-11-22 17:32 ` [PATCHv4 1/14] OMAP2+: dmtimer: add device names to flck nodes Cousson, Benoit
2010-11-23 8:36 ` DebBarma, Tarun Kanti
2010-11-23 8:40 ` Cousson, Benoit
2010-11-23 8:43 ` DebBarma, Tarun Kanti
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