[PATCH] x86: use alternatives for FS/GS base accesses

[PATCH] x86: use alternatives for FS/GS base accesses

[Jan Beulich]

Eliminates a couple of branches in particular from the context switch
path.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/include/asm-x86/msr.h
+++ b/xen/include/asm-x86/msr.h
@@ -11,6 +11,7 @@
 
 #include <xen/lib/x86/msr.h>
 
+#include <asm/alternative.h>
 #include <asm/asm_defns.h>
 #include <asm/cpufeature.h>
 #include <asm/processor.h>
@@ -154,10 +155,15 @@ static inline unsigned long rdfsbase(voi
 {
     unsigned long base;
 
-    if ( cpu_has_fsgsbase )
-        return __rdfsbase();
-
-    rdmsrl(MSR_FS_BASE, base);
+    alternative_io("mov %[msr], %%ecx\n\t"
+                   "rdmsr\n\t"
+                   "shl $32, %%rdx\n\t"
+                   "or %%rdx, %[res]",
+                   /* rdfsbase rax */
+                   ".byte 0xf3, 0x48, 0x0f, 0xae, 0xc0",
+                   X86_FEATURE_FSGSBASE,
+                   [res] "=&a" (base),
+                   [msr] "i" (MSR_FS_BASE) : "rcx", "rdx");
 
     return base;
 }
@@ -166,10 +172,15 @@ static inline unsigned long rdgsbase(voi
 {
     unsigned long base;
 
-    if ( cpu_has_fsgsbase )
-        return __rdgsbase();
-
-    rdmsrl(MSR_GS_BASE, base);
+    alternative_io("mov %[msr], %%ecx\n\t"
+                   "rdmsr\n\t"
+                   "shl $32, %%rdx\n\t"
+                   "or %%rdx, %[res]",
+                   /* rdgsbase rax */
+                   ".byte 0xf3, 0x48, 0x0f, 0xae, 0xc8",
+                   X86_FEATURE_FSGSBASE,
+                   [res] "=&a" (base),
+                   [msr] "i" (MSR_GS_BASE) : "rcx", "rdx");
 
     return base;
 }
@@ -178,59 +189,58 @@ static inline unsigned long rdgsshadow(v
 {
     unsigned long base;
 
-    if ( cpu_has_fsgsbase )
-    {
-        asm volatile ( "swapgs" );
-        base = __rdgsbase();
-        asm volatile ( "swapgs" );
-    }
-    else
-        rdmsrl(MSR_SHADOW_GS_BASE, base);
+    alternative_io("mov %[msr], %%ecx\n\t"
+                   "rdmsr\n\t"
+                   "shl $32, %%rdx\n\t"
+                   "or %%rdx, %[res]",
+                   /* Wrapping RDGSBASE in a pair of SWAPGS. */
+                   "swapgs\n\t"
+                   ".byte 0xf3, 0x48, 0x0f, 0xae, 0xc8\n\t" /* rdgsbase rax */
+                   "swapgs",
+                   X86_FEATURE_FSGSBASE,
+                   [res] "=&a" (base),
+                   [msr] "i" (MSR_SHADOW_GS_BASE) : "rcx", "rdx");
 
     return base;
 }
 
 static inline void wrfsbase(unsigned long base)
 {
-    if ( cpu_has_fsgsbase )
-#ifdef HAVE_AS_FSGSBASE
-        asm volatile ( "wrfsbase %0" :: "r" (base) );
-#else
-        asm volatile ( ".byte 0xf3, 0x48, 0x0f, 0xae, 0xd0" :: "a" (base) );
-#endif
-    else
-        wrmsrl(MSR_FS_BASE, base);
+    alternative_input("mov %[msr], %%ecx\n\t"
+                      "mov %[val], %%rdx\n\t"
+                      "shr $32, %%rdx\n\t"
+                      "wrmsr",
+                      /* wrfsbase rax */
+                      ".byte 0xf3, 0x48, 0x0f, 0xae, 0xd0",
+                      X86_FEATURE_FSGSBASE,
+                      [val] "a" (base), [msr] "i" (MSR_FS_BASE) : "rcx", "rdx");
 }
 
 static inline void wrgsbase(unsigned long base)
 {
-    if ( cpu_has_fsgsbase )
-#ifdef HAVE_AS_FSGSBASE
-        asm volatile ( "wrgsbase %0" :: "r" (base) );
-#else
-        asm volatile ( ".byte 0xf3, 0x48, 0x0f, 0xae, 0xd8" :: "a" (base) );
-#endif
-    else
-        wrmsrl(MSR_GS_BASE, base);
+    alternative_input("mov %[msr], %%ecx\n\t"
+                      "mov %[val], %%rdx\n\t"
+                      "shr $32, %%rdx\n\t"
+                      "wrmsr",
+                      /* wrgsbase rax */
+                      ".byte 0xf3, 0x48, 0x0f, 0xae, 0xd8",
+                      X86_FEATURE_FSGSBASE,
+                      [val] "a" (base), [msr] "i" (MSR_GS_BASE) : "rcx", "rdx");
 }
 
 static inline void wrgsshadow(unsigned long base)
 {
-    if ( cpu_has_fsgsbase )
-    {
-        asm volatile ( "swapgs\n\t"
-#ifdef HAVE_AS_FSGSBASE
-                       "wrgsbase %0\n\t"
-                       "swapgs"
-                       :: "r" (base) );
-#else
-                       ".byte 0xf3, 0x48, 0x0f, 0xae, 0xd8\n\t"
-                       "swapgs"
-                       :: "a" (base) );
-#endif
-    }
-    else
-        wrmsrl(MSR_SHADOW_GS_BASE, base);
+    alternative_input("mov %[msr], %%ecx\n\t"
+                      "mov %[val], %%rdx\n\t"
+                      "shr $32, %%rdx\n\t"
+                      "wrmsr",
+                      /* Wrapping WRGSBASE in a pair of SWAPGS. */
+                      "swapgs\n\t"
+                      ".byte 0xf3, 0x48, 0x0f, 0xae, 0xd8\n\t" /* wrgsbase rax */
+                      "swapgs",
+                      X86_FEATURE_FSGSBASE,
+                      [val] "a" (base),
+                      [msr] "i" (MSR_SHADOW_GS_BASE) : "rcx", "rdx");
 }
 
 DECLARE_PER_CPU(uint64_t, efer);




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Re: [PATCH] x86: use alternatives for FS/GS base accesses

[Wei Liu]

On Wed, Aug 29, 2018 at 10:03:01AM -0600, Jan Beulich wrote:
> Eliminates a couple of branches in particular from the context switch
> path.
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Wei Liu <wei.liu2@citrix.com>

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Ping: [PATCH] x86: use alternatives for FS/GS base accesses

[Jan Beulich]

>>> On 30.08.18 at 10:13, <wei.liu2@citrix.com> wrote:
> On Wed, Aug 29, 2018 at 10:03:01AM -0600, Jan Beulich wrote:
>> Eliminates a couple of branches in particular from the context switch
>> path.
>> 
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> 
> Reviewed-by: Wei Liu <wei.liu2@citrix.com>

Andrew?

Jan



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Ping: [PATCH] x86: use alternatives for FS/GS base accesses

[Jan Beulich]

>>> On 30.08.18 at 10:13, <wei.liu2@citrix.com> wrote:
> On Wed, Aug 29, 2018 at 10:03:01AM -0600, Jan Beulich wrote:
>> Eliminates a couple of branches in particular from the context switch
>> path.
>> 
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> 
> Reviewed-by: Wei Liu <wei.liu2@citrix.com>

Andrew?

Thanks, Jan



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Re: [PATCH] x86: use alternatives for FS/GS base accesses

[Andrew Cooper]

On 29/08/18 17:03, Jan Beulich wrote:
> Eliminates a couple of branches in particular from the context switch
> path.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

I've already expressed a dis-inclination to this patch, because it looks
like a micro-optimisation which won't actually affect measureable
performance.  (And as said before, I could be wrong, but I don't think I
am...)

Have you done some perf analysis since you last posted it?

~Andrew

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Re: [PATCH] x86: use alternatives for FS/GS base accesses

[Jan Beulich]

>>> On 25.09.18 at 18:52, <andrew.cooper3@citrix.com> wrote:
> On 29/08/18 17:03, Jan Beulich wrote:
>> Eliminates a couple of branches in particular from the context switch
>> path.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> 
> I've already expressed a dis-inclination to this patch, because it looks
> like a micro-optimisation which won't actually affect measureable
> performance.  (And as said before, I could be wrong, but I don't think I
> am...)

Iirc you had indicated you first of all don't like the mix of some constructs
using alternatives and some not. Eliminating conditional branches is
always a Good Thing (tm), it seems to me. And that's not just for
performance (inside Xen we can't assume at all that any code path,
even the context switch one, is hot enough to have any BTB entries
allocated), but also for ease of looking at the assembly, should there
be a need to do so. Overall I think we ought to make much heavier use
of alternatives patching, so I view this only as a first step towards this.

Otherwise, btw, why did you not object to e.g. clac() / stac() using
alternatives patching? As with so  many other things, I very much think
we should settle on a fundamental approach, and then write all code
consistently. If we followed what you say, we'd have to limit patching
to cases where conditionals can't (reasonably) express what we want.

> Have you done some perf analysis since you last posted it?

I don't view this as a worthwhile use of my time, to be honest. Even
a non-measurable improvement is an improvement. I'd understand
your objection if there was a fair reason to be afraid of worse
performance as a result of this change.

Jan



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Re: [PATCH] x86: use alternatives for FS/GS base accesses

[Andrew Cooper]

On 26/09/18 07:43, Jan Beulich wrote:
>>>> On 25.09.18 at 18:52, <andrew.cooper3@citrix.com> wrote:
>> On 29/08/18 17:03, Jan Beulich wrote:
>>> Eliminates a couple of branches in particular from the context switch
>>> path.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>> I've already expressed a dis-inclination to this patch, because it looks
>> like a micro-optimisation which won't actually affect measureable
>> performance.  (And as said before, I could be wrong, but I don't think I
>> am...)
> Iirc you had indicated you first of all don't like the mix of some constructs
> using alternatives and some not.

Correct.  Consistency (one way or the other) is better overall here.

> Eliminating conditional branches is always a Good Thing (tm), it seems to me.

By this reasoning, we should compile Xen with movfuscator, which really
will get rid of every branch.

Doing so would be utter nonsense, ergo this claim is false.

> And that's not just for
> performance (inside Xen we can't assume at all that any code path,
> even the context switch one, is hot enough to have any BTB entries
> allocated), 

This is a valid argument, for why the proposed change might plausibly be
an improvement.

It is by no means a guarantee that making the change will result in
improved performance.

> but also for ease of looking at the assembly, should there
> be a need to do so.

Using alternatives actively obfuscates the logic in the disassembly.  It
is almost impossible to distinguish the individual fragments, and you
rejected my suggestion of rectifying this by putting symbols into the
.altinstructions section.  It also results in harder to read C, and
poorer surrounded code generation, as the compiler has to cope with the
union of entry/exit requirements for the blocks.

So no - this claim is also false.

> Overall I think we ought to make much heavier use
> of alternatives patching, so I view this only as a first step towards this.
> Otherwise, btw, why did you not object to e.g. clac() / stac() using
> alternatives patching? As with so  many other things, I very much think
> we should settle on a fundamental approach, and then write all code
> consistently. If we followed what you say, we'd have to limit patching
> to cases where conditionals can't (reasonably) express what we want.

I never said that we shouldn't patch conditionals.

There is a cost to every use of alternative, and the decision to use a
alternatives needs to be justified on their merits outweighing their
cost.  I'm not currently convinced of the merit/cost tradeoff in this case.

>> Have you done some perf analysis since you last posted it?
> I don't view this as a worthwhile use of my time, to be honest. Even
> a non-measurable improvement is an improvement. I'd understand
> your objection if there was a fair reason to be afraid of worse
> performance as a result of this change.

So you're submitting a performance patch (which you admit might have no
measurable improvement) based on logic which I've called into question,
and furthermore, you expect me to ack it based on your untested opinion
that "its an improvement"?

Do you think that repeating myself is a worthwhile use of my time?

I'm afraid that I'm going to be very blunt now.

What matters, performance wise, is net performance in common workloads,
and avoiding catastrophic corner cases.  This is a macro problem, not a
micro problem, and in my opinion, you are demonstrating repeated poor
judgement in this regard.  In particular, it is simply not true that
improving the micro-performance of a block increases the overall
performance.

To cover some examples so far this year...

This patch still hasn't addressed the concerns about sh[lr]d, and the
resulting competition for execution resource on AMD Fam15/16h systems.

"x86: enable interrupts earlier with XPTI disabled" was objected to by
me on the basis of the increased complexity of following the code,
rather than any performance consideration.  A contributory factor was
that I couldn't see any reason why it would make any performance
difference.  When Juergen eventually measured it, the results said the
performance was worse.  (It might be interesting to work out why it was
worse overall, because its definitely not obvious, but I suspect we all
have more important work to do).

"x86/xsave: prefer eager clearing of state over eager restoring" is
basic statistics.  In this case, worrying about the theoretical longterm
trend is having a material performance impact (in Intel's case, 8%) on
current users, and I do intend to make Xen fully eager (benefiting all
hardware) when I've confirmed what I suspect to be true on the AMD side
of things.  When all the major OS and hypervisors are fully eager, and
when most hardware you can buy today is specifically optimised for this
configuration, Xen being the different hurts only ourselves.

"x86: use PDEP/PEXT for maddr/direct-map-offset conversion when
available​" neglects the cache bloat of having 255 copies of the stub,
and the pipeline stall from mixing legacy and VEX SSE instructions. 
Both of these (irrespective of other aspects) have a very real chance of
making the overall performance worse rather than better.


All of these are very real potential problem, which may or may not be an
issue in practice.  You're certainly not going to know without testing
your patch, so no - I'm not going to simply accept patches on your blind
assertion that it is better in one way or another - I'd be failing in my
responsibility as a maintainer if I were to do so.

~Andrew

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Re: [PATCH] x86: use alternatives for FS/GS base accesses

[Jan Beulich]

>>> On 26.09.18 at 20:13, <andrew.cooper3@citrix.com> wrote:
> On 26/09/18 07:43, Jan Beulich wrote:
>> Eliminating conditional branches is always a Good Thing (tm), it seems to 
> me.
> 
> By this reasoning, we should compile Xen with movfuscator, which really
> will get rid of every branch.
> 
> Doing so would be utter nonsense, ergo this claim is false.

Please take the use of "always" here with a grain of salt: Of course
I'm not suggesting to eliminate all conditionals. But conditionals which
are there sole to select between different insns achieving the same
thing are a pretty good target for replacement by alternatives.

>> And that's not just for
>> performance (inside Xen we can't assume at all that any code path,
>> even the context switch one, is hot enough to have any BTB entries
>> allocated), 
> 
> This is a valid argument, for why the proposed change might plausibly be
> an improvement.
> 
> It is by no means a guarantee that making the change will result in
> improved performance.

As I've said before - if improved code clarity is accompanied by no
drop in performance, that would already be good enough imo. And
I see no reason to believe that streamlining code by eliminating
conditional branches has any meaningful risk of impacting
performance, without the need to do any measurements (and I
say this despite realizing that at times actual behavior can be
surprising).

>> but also for ease of looking at the assembly, should there
>> be a need to do so.
> 
> Using alternatives actively obfuscates the logic in the disassembly.  It
> is almost impossible to distinguish the individual fragments, and you
> rejected my suggestion of rectifying this by putting symbols into the
> .altinstructions section.

I could be talked into this, provided they don't make it into the
"kallsyms"-like symbol table.

>  It also results in harder to read C, and

This may or may not be the case, depending on which part of
the code you look at. Especially if there are conditionals in
mainline code, their elimination helps readability imo. But yes,
there's _some_ price to pay.

> poorer surrounded code generation, as the compiler has to cope with the
> union of entry/exit requirements for the blocks.

Interesting - you now use an argument the inverse of which you
use on the PDEP/PEXT patch series.

Furthermore I question this argument in the context here: In
order to satisfy the WRMSR constraints, the compiler is left with
basically no choice of register allocation already anyway. The
replacement insns then simply use these same registers. It's
certainly possible that without alternatives the non-WRMSR
part of the conditional uses different register allocation, but
according to my (general, not specific to this case here)
observations gcc at least is often producing more redundancy
than would be possible to go with, in order to use different
registers in cases like this.

> This patch still hasn't addressed the concerns about sh[lr]d, and the
> resulting competition for execution resource on AMD Fam15/16h systems.

Excuse me? Where did you see any SH[LR]D left in the patch?

> "x86: enable interrupts earlier with XPTI disabled" was objected to by
> me on the basis of the increased complexity of following the code,
> rather than any performance consideration.  A contributory factor was
> that I couldn't see any reason why it would make any performance
> difference.  When Juergen eventually measured it, the results said the
> performance was worse.  (It might be interesting to work out why it was
> worse overall, because its definitely not obvious, but I suspect we all
> have more important work to do).

And I've accepted your arguments (without fully buying them, with
latency in mind) and dropped the patch.

> "x86: use PDEP/PEXT for maddr/direct-map-offset conversion when
> available​" neglects the cache bloat of having 255 copies of the stub,
> and the pipeline stall from mixing legacy and VEX SSE instructions. 

I've responded to both of these before. I'm not going to repeat any
of that here.

Jan


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