* [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-10 14:33 ` Li Qiang
0 siblings, 0 replies; 10+ messages in thread
From: Li Qiang @ 2019-04-10 14:33 UTC (permalink / raw)
To: pbonzini, mst; +Cc: qemu-devel, liq3ea
Hi all,
I see the link device ‘_PRS’ uses irq line 5, 10, 11 in ‘build_link_dev’ function.
But I never see the 5 lines uses in the guest, just uses 10 and 11.
Why this happen? Maybe related with the guest?
Thanks,
Li Qiang
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-10 14:33 ` Li Qiang
0 siblings, 0 replies; 10+ messages in thread
From: Li Qiang @ 2019-04-10 14:33 UTC (permalink / raw)
To: pbonzini, mst; +Cc: liq3ea, qemu-devel
Hi all,
I see the link device ‘_PRS’ uses irq line 5, 10, 11 in ‘build_link_dev’ function.
But I never see the 5 lines uses in the guest, just uses 10 and 11.
Why this happen? Maybe related with the guest?
Thanks,
Li Qiang
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-10 15:55 ` Paolo Bonzini
0 siblings, 0 replies; 10+ messages in thread
From: Paolo Bonzini @ 2019-04-10 15:55 UTC (permalink / raw)
To: Li Qiang, mst; +Cc: qemu-devel, liq3ea
On 10/04/19 16:33, Li Qiang wrote:
> Hi all,
>
>
>
> I see the link device ‘_PRS’ uses irq line 5, 10, 11 in
> ‘build_link_dev’ function.
>
> But I never see the 5 lines uses in the guest, just uses 10 and 11.
>
> Why this happen? Maybe related with the guest?
Because the MADT table tells the guest to only use lines 10 and 11. The
BIOS configures the chipset that way.
Paolo
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-10 15:55 ` Paolo Bonzini
0 siblings, 0 replies; 10+ messages in thread
From: Paolo Bonzini @ 2019-04-10 15:55 UTC (permalink / raw)
To: Li Qiang, mst; +Cc: liq3ea, qemu-devel
On 10/04/19 16:33, Li Qiang wrote:
> Hi all,
>
>
>
> I see the link device ‘_PRS’ uses irq line 5, 10, 11 in
> ‘build_link_dev’ function.
>
> But I never see the 5 lines uses in the guest, just uses 10 and 11.
>
> Why this happen? Maybe related with the guest?
Because the MADT table tells the guest to only use lines 10 and 11. The
BIOS configures the chipset that way.
Paolo
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-11 0:57 ` Li Qiang
0 siblings, 0 replies; 10+ messages in thread
From: Li Qiang @ 2019-04-11 0:57 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Li Qiang, mst, qemu-devel, liq3ea
Paolo Bonzini <pbonzini@redhat.com> 于2019年4月10日周三 下午11:55写道:
> On 10/04/19 16:33, Li Qiang wrote:
> > Hi all,
> >
> >
> >
> > I see the link device ‘_PRS’ uses irq line 5, 10, 11 in
> > ‘build_link_dev’ function.
> >
> > But I never see the 5 lines uses in the guest, just uses 10 and 11.
> >
> > Why this happen? Maybe related with the guest?
>
> Because the MADT table tells the guest to only use lines 10 and 11. The
> BIOS configures the chipset that way.
>
>
Hi Paolo,
I read the MADT spec, and found that it may related with 'Entry Type 2 :
Interrupt Source Override'.
However, in build_madt function, I found following code when fill interrupt
source overide.
#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
/* No need for a INT source override structure. */
continue;
}
Seems the madt doesn't play a role?
Also in the seabios code, I see the pci interrupt linking device is routed
hard-coded by pci_irqs.
So this means the seabios doesn't use the madt/dsdt table to configure PCI
interrupt routing?
Thanks,
Li Qiang
const u8 pci_irqs[4] = {
10, 10, 11, 11
};
static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
{
int i, irq;
u8 elcr[2];
elcr[0] = 0x00;
elcr[1] = 0x00;
for (i = 0; i < 4; i++) {
irq = pci_irqs[i];
/* set to trigger level */
elcr[irq >> 3] |= (1 << (irq & 7));
/* activate irq remapping in PIIX */
pci_config_writeb(pci->bdf, 0x60 + i, irq);
}
outb(elcr[0], PIIX_PORT_ELCR1);
outb(elcr[1], PIIX_PORT_ELCR2);
dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
}
Paolo
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-11 0:57 ` Li Qiang
0 siblings, 0 replies; 10+ messages in thread
From: Li Qiang @ 2019-04-11 0:57 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: liq3ea, Li Qiang, qemu-devel, mst
Paolo Bonzini <pbonzini@redhat.com> 于2019年4月10日周三 下午11:55写道:
> On 10/04/19 16:33, Li Qiang wrote:
> > Hi all,
> >
> >
> >
> > I see the link device ‘_PRS’ uses irq line 5, 10, 11 in
> > ‘build_link_dev’ function.
> >
> > But I never see the 5 lines uses in the guest, just uses 10 and 11.
> >
> > Why this happen? Maybe related with the guest?
>
> Because the MADT table tells the guest to only use lines 10 and 11. The
> BIOS configures the chipset that way.
>
>
Hi Paolo,
I read the MADT spec, and found that it may related with 'Entry Type 2 :
Interrupt Source Override'.
However, in build_madt function, I found following code when fill interrupt
source overide.
#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
/* No need for a INT source override structure. */
continue;
}
Seems the madt doesn't play a role?
Also in the seabios code, I see the pci interrupt linking device is routed
hard-coded by pci_irqs.
So this means the seabios doesn't use the madt/dsdt table to configure PCI
interrupt routing?
Thanks,
Li Qiang
const u8 pci_irqs[4] = {
10, 10, 11, 11
};
static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
{
int i, irq;
u8 elcr[2];
elcr[0] = 0x00;
elcr[1] = 0x00;
for (i = 0; i < 4; i++) {
irq = pci_irqs[i];
/* set to trigger level */
elcr[irq >> 3] |= (1 << (irq & 7));
/* activate irq remapping in PIIX */
pci_config_writeb(pci->bdf, 0x60 + i, irq);
}
outb(elcr[0], PIIX_PORT_ELCR1);
outb(elcr[1], PIIX_PORT_ELCR2);
dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
}
Paolo
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-11 7:44 ` Paolo Bonzini
0 siblings, 0 replies; 10+ messages in thread
From: Paolo Bonzini @ 2019-04-11 7:44 UTC (permalink / raw)
To: Li Qiang; +Cc: Li Qiang, mst, qemu-devel
On 11/04/19 02:57, Li Qiang wrote:
>
>
> Paolo Bonzini <pbonzini@redhat.com <mailto:pbonzini@redhat.com>> 于2019
> 年4月10日周三 下午11:55写道:
>
> On 10/04/19 16:33, Li Qiang wrote:
> > Hi all,
> >
> >
> >
> > I see the link device ‘_PRS’ uses irq line 5, 10, 11 in
> > ‘build_link_dev’ function.
> >
> > But I never see the 5 lines uses in the guest, just uses 10 and 11.
> >
> > Why this happen? Maybe related with the guest?
>
> Because the MADT table tells the guest to only use lines 10 and 11. The
> BIOS configures the chipset that way.
>
>
> Hi Paolo,
>
> I read the MADT spec, and found that it may related with 'Entry Type 2 :
> Interrupt Source Override'.
> However, in build_madt function, I found following code when fill
> interrupt source overide.
>
> #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
> if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
> /* No need for a INT source override structure. */
> continue;
> }
>
> Seems the madt doesn't play a role?
>
> Also in the seabios code, I see the pci interrupt linking device is
> routed hard-coded by pci_irqs.
> So this means the seabios doesn't use the madt/dsdt table to configure
> PCI interrupt routing?
Yeah, the MADT doesn't matter, I got confused. It's just the firmware's
definition of pci_irqs that affects the behavior you're seeing.
Paolo
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-11 7:44 ` Paolo Bonzini
0 siblings, 0 replies; 10+ messages in thread
From: Paolo Bonzini @ 2019-04-11 7:44 UTC (permalink / raw)
To: Li Qiang; +Cc: Li Qiang, qemu-devel, mst
On 11/04/19 02:57, Li Qiang wrote:
>
>
> Paolo Bonzini <pbonzini@redhat.com <mailto:pbonzini@redhat.com>> 于2019
> 年4月10日周三 下午11:55写道:
>
> On 10/04/19 16:33, Li Qiang wrote:
> > Hi all,
> >
> >
> >
> > I see the link device ‘_PRS’ uses irq line 5, 10, 11 in
> > ‘build_link_dev’ function.
> >
> > But I never see the 5 lines uses in the guest, just uses 10 and 11.
> >
> > Why this happen? Maybe related with the guest?
>
> Because the MADT table tells the guest to only use lines 10 and 11. The
> BIOS configures the chipset that way.
>
>
> Hi Paolo,
>
> I read the MADT spec, and found that it may related with 'Entry Type 2 :
> Interrupt Source Override'.
> However, in build_madt function, I found following code when fill
> interrupt source overide.
>
> #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
> if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
> /* No need for a INT source override structure. */
> continue;
> }
>
> Seems the madt doesn't play a role?
>
> Also in the seabios code, I see the pci interrupt linking device is
> routed hard-coded by pci_irqs.
> So this means the seabios doesn't use the madt/dsdt table to configure
> PCI interrupt routing?
Yeah, the MADT doesn't matter, I got confused. It's just the firmware's
definition of pci_irqs that affects the behavior you're seeing.
Paolo
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-11 7:52 ` Li Qiang
0 siblings, 0 replies; 10+ messages in thread
From: Li Qiang @ 2019-04-11 7:52 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Li Qiang, mst, qemu-devel
Paolo Bonzini <pbonzini@redhat.com> 于2019年4月11日周四 下午3:44写道:
> On 11/04/19 02:57, Li Qiang wrote:
> >
> >
> > Paolo Bonzini <pbonzini@redhat.com <mailto:pbonzini@redhat.com>> 于2019
> > 年4月10日周三 下午11:55写道:
> >
> > On 10/04/19 16:33, Li Qiang wrote:
> > > Hi all,
> > >
> > >
> > >
> > > I see the link device ‘_PRS’ uses irq line 5, 10, 11 in
> > > ‘build_link_dev’ function.
> > >
> > > But I never see the 5 lines uses in the guest, just uses 10 and 11.
> > >
> > > Why this happen? Maybe related with the guest?
> >
> > Because the MADT table tells the guest to only use lines 10 and 11.
> The
> > BIOS configures the chipset that way.
> >
> >
> > Hi Paolo,
> >
> > I read the MADT spec, and found that it may related with 'Entry Type 2 :
> > Interrupt Source Override'.
> > However, in build_madt function, I found following code when fill
> > interrupt source overide.
> >
> > #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
> > if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
> > /* No need for a INT source override structure. */
> > continue;
> > }
> >
> > Seems the madt doesn't play a role?
> >
> > Also in the seabios code, I see the pci interrupt linking device is
> > routed hard-coded by pci_irqs.
> > So this means the seabios doesn't use the madt/dsdt table to configure
> > PCI interrupt routing?
>
> Yeah, the MADT doesn't matter, I got confused. It's just the firmware's
> definition of pci_irqs that affects the behavior you're seeing.
>
>
Hello Paolo,
Thanks so much for your confirmation! I appreciate it.
I'm confused by the massive acpi table/concepts recently.
Thanks,
Li Qiang
> Paolo
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field
@ 2019-04-11 7:52 ` Li Qiang
0 siblings, 0 replies; 10+ messages in thread
From: Li Qiang @ 2019-04-11 7:52 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Li Qiang, qemu-devel, mst
Paolo Bonzini <pbonzini@redhat.com> 于2019年4月11日周四 下午3:44写道:
> On 11/04/19 02:57, Li Qiang wrote:
> >
> >
> > Paolo Bonzini <pbonzini@redhat.com <mailto:pbonzini@redhat.com>> 于2019
> > 年4月10日周三 下午11:55写道:
> >
> > On 10/04/19 16:33, Li Qiang wrote:
> > > Hi all,
> > >
> > >
> > >
> > > I see the link device ‘_PRS’ uses irq line 5, 10, 11 in
> > > ‘build_link_dev’ function.
> > >
> > > But I never see the 5 lines uses in the guest, just uses 10 and 11.
> > >
> > > Why this happen? Maybe related with the guest?
> >
> > Because the MADT table tells the guest to only use lines 10 and 11.
> The
> > BIOS configures the chipset that way.
> >
> >
> > Hi Paolo,
> >
> > I read the MADT spec, and found that it may related with 'Entry Type 2 :
> > Interrupt Source Override'.
> > However, in build_madt function, I found following code when fill
> > interrupt source overide.
> >
> > #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
> > if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
> > /* No need for a INT source override structure. */
> > continue;
> > }
> >
> > Seems the madt doesn't play a role?
> >
> > Also in the seabios code, I see the pci interrupt linking device is
> > routed hard-coded by pci_irqs.
> > So this means the seabios doesn't use the madt/dsdt table to configure
> > PCI interrupt routing?
>
> Yeah, the MADT doesn't matter, I got confused. It's just the firmware's
> definition of pci_irqs that affects the behavior you're seeing.
>
>
Hello Paolo,
Thanks so much for your confirmation! I appreciate it.
I'm confused by the massive acpi table/concepts recently.
Thanks,
Li Qiang
> Paolo
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-04-11 7:53 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-10 14:33 [Qemu-devel] Questions about acpi interrupt link device's ‘_PRS' field Li Qiang
2019-04-10 14:33 ` Li Qiang
2019-04-10 15:55 ` Paolo Bonzini
2019-04-10 15:55 ` Paolo Bonzini
2019-04-11 0:57 ` Li Qiang
2019-04-11 0:57 ` Li Qiang
2019-04-11 7:44 ` Paolo Bonzini
2019-04-11 7:44 ` Paolo Bonzini
2019-04-11 7:52 ` Li Qiang
2019-04-11 7:52 ` Li Qiang
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