From: Aradhya Bhatia <a-bhatia1@ti.com> To: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Cc: Darren Etheridge <detheridge@ti.com>, Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>, Rahul T R <r-ravikumar@ti.com>, Krunal Bhargav <k-bhargav@ti.com>, Devarsh Thakkar <devarsht@ti.com>, DRI Development List <dri-devel@lists.freedesktop.org>, Devicetree List <devicetree@vger.kernel.org>, Linux Kernel List <linux-kernel@vger.kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>, Jyri Sarha <jyri.sarha@iki.fi> Subject: Re: [PATCH 7/8] drm/tidss: Fix clock request value for OLDI videoports Date: Fri, 29 Jul 2022 09:26:49 +0530 [thread overview] Message-ID: <5abdc690-3b0d-0763-2a8a-30d1516c8ab0@ti.com> (raw) In-Reply-To: <03c77b33-271c-5cb3-fe00-cda7ff21102b@ideasonboard.com> On 28-Jul-22 15:35, Tomi Valkeinen wrote: > On 19/07/2022 11:08, Aradhya Bhatia wrote: >> The OLDI TX(es) require a serial clock which is 7 times the pixel clock >> of the display panel. When the OLDI is enabled in DSS, the pixel clock >> input of the corresponding videoport gets a divided-by 7 value of the >> requested clock. >> >> For the am625-dss, the requested clock needs to be 7 times the value. >> >> Update the clock frequency by requesting 7 times the value. >> >> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> >> --- >> drivers/gpu/drm/tidss/tidss_dispc.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c >> b/drivers/gpu/drm/tidss/tidss_dispc.c >> index c4a5f808648f..0b9689453ee8 100644 >> --- a/drivers/gpu/drm/tidss/tidss_dispc.c >> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c >> @@ -1326,6 +1326,16 @@ int dispc_vp_set_clk_rate(struct dispc_device >> *dispc, u32 hw_videoport, >> int r; >> unsigned long new_rate; >> + /* >> + * For AM625 OLDI video ports, the requested pixel clock needs to >> take into account the >> + * serial clock required for the serialization of DPI signals >> into LVDS signals. The >> + * incoming pixel clock on the OLDI video port gets divided by 7 >> whenever OLDI enable bit >> + * gets set. >> + */ >> + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI && >> + dispc->feat->subrev == DISPC_AM625) >> + rate *= 7; >> + >> r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); >> if (r) { >> dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", > > The AM625 TRM seems to be missing the "DSS integration" section, even if > it's referred to in three places in the TRM. Supposedly that has details > about the clocking. > > Shouldn't the source clock be 3.5x when dual-link mode is used? There should not be. Whenever OLDI is enabled, the clock generated from the PLL is 7 times the required pixel clock. For the OLDI TXes, the clock passes through a /2 divider. This divider only gets activated when the dual mode has been enabled in the OLDI configuration. Thus the OLDI TXes get 3.5x the pixel clock in dual mode. When the OLDI has been configured for a single mode, the PLL clock passes through the /2 divider without any change. > > While I don't know the details, this doesn't feel correct. We're > supposed to be setting the VP pixel clock here, and the serial clock > would be derived from that as it's done on AM65x. Is the DT clock tree > wrong for AM625? Ideally, yes, its the pixel frequency that we are supposed to set here. The same PLL clock (7 times the pixel frequency) passes through a /7 clock divider. This clock divider only gets active when OLDI is enabled. Thus, the DSS VP clock input, only gets the actual pixel frequency that it needs. Since, the /7 divider is controlled by a signal from the DSS, the driver needs to request 7 times more the pixel clock to accommodate for the divider. In AM65X, the system FW is able to model the 7 times requirement because the divider is not controlled by the DSS signal. DSS signal controls a multiplexer which receives both PLL Clock and PLL / 7 clock. Regards Aradhya
WARNING: multiple messages have this Message-ID (diff)
From: Aradhya Bhatia <a-bhatia1@ti.com> To: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Cc: Nishanth Menon <nm@ti.com>, Devicetree List <devicetree@vger.kernel.org>, Vignesh Raghavendra <vigneshr@ti.com>, Devarsh Thakkar <devarsht@ti.com>, David Airlie <airlied@linux.ie>, Linux Kernel List <linux-kernel@vger.kernel.org>, DRI Development List <dri-devel@lists.freedesktop.org>, Darren Etheridge <detheridge@ti.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Jyri Sarha <jyri.sarha@iki.fi>, Rahul T R <r-ravikumar@ti.com>, Krunal Bhargav <k-bhargav@ti.com> Subject: Re: [PATCH 7/8] drm/tidss: Fix clock request value for OLDI videoports Date: Fri, 29 Jul 2022 09:26:49 +0530 [thread overview] Message-ID: <5abdc690-3b0d-0763-2a8a-30d1516c8ab0@ti.com> (raw) In-Reply-To: <03c77b33-271c-5cb3-fe00-cda7ff21102b@ideasonboard.com> On 28-Jul-22 15:35, Tomi Valkeinen wrote: > On 19/07/2022 11:08, Aradhya Bhatia wrote: >> The OLDI TX(es) require a serial clock which is 7 times the pixel clock >> of the display panel. When the OLDI is enabled in DSS, the pixel clock >> input of the corresponding videoport gets a divided-by 7 value of the >> requested clock. >> >> For the am625-dss, the requested clock needs to be 7 times the value. >> >> Update the clock frequency by requesting 7 times the value. >> >> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> >> --- >> drivers/gpu/drm/tidss/tidss_dispc.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c >> b/drivers/gpu/drm/tidss/tidss_dispc.c >> index c4a5f808648f..0b9689453ee8 100644 >> --- a/drivers/gpu/drm/tidss/tidss_dispc.c >> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c >> @@ -1326,6 +1326,16 @@ int dispc_vp_set_clk_rate(struct dispc_device >> *dispc, u32 hw_videoport, >> int r; >> unsigned long new_rate; >> + /* >> + * For AM625 OLDI video ports, the requested pixel clock needs to >> take into account the >> + * serial clock required for the serialization of DPI signals >> into LVDS signals. The >> + * incoming pixel clock on the OLDI video port gets divided by 7 >> whenever OLDI enable bit >> + * gets set. >> + */ >> + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI && >> + dispc->feat->subrev == DISPC_AM625) >> + rate *= 7; >> + >> r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); >> if (r) { >> dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", > > The AM625 TRM seems to be missing the "DSS integration" section, even if > it's referred to in three places in the TRM. Supposedly that has details > about the clocking. > > Shouldn't the source clock be 3.5x when dual-link mode is used? There should not be. Whenever OLDI is enabled, the clock generated from the PLL is 7 times the required pixel clock. For the OLDI TXes, the clock passes through a /2 divider. This divider only gets activated when the dual mode has been enabled in the OLDI configuration. Thus the OLDI TXes get 3.5x the pixel clock in dual mode. When the OLDI has been configured for a single mode, the PLL clock passes through the /2 divider without any change. > > While I don't know the details, this doesn't feel correct. We're > supposed to be setting the VP pixel clock here, and the serial clock > would be derived from that as it's done on AM65x. Is the DT clock tree > wrong for AM625? Ideally, yes, its the pixel frequency that we are supposed to set here. The same PLL clock (7 times the pixel frequency) passes through a /7 clock divider. This clock divider only gets active when OLDI is enabled. Thus, the DSS VP clock input, only gets the actual pixel frequency that it needs. Since, the /7 divider is controlled by a signal from the DSS, the driver needs to request 7 times more the pixel clock to accommodate for the divider. In AM65X, the system FW is able to model the 7 times requirement because the divider is not controlled by the DSS signal. DSS signal controls a multiplexer which receives both PLL Clock and PLL / 7 clock. Regards Aradhya
next prev parent reply other threads:[~2022-07-29 3:57 UTC|newest] Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-19 8:08 sFrom b69208b75f7ae8e223c81783afb04fecd2f5faf8 Mon Sep 17 00:00:00 2001 Aradhya Bhatia 2022-07-19 8:08 ` Aradhya Bhatia 2022-07-19 8:08 ` [PATCH 1/8] dt-bindings: display: ti,am65x-dss: Add port properties for DSS Aradhya Bhatia 2022-07-19 8:08 ` [PATCH 1/8] dt-bindings: display: ti, am65x-dss: " Aradhya Bhatia 2022-07-20 23:28 ` [PATCH 1/8] dt-bindings: display: ti,am65x-dss: " Rob Herring 2022-07-20 23:28 ` Rob Herring 2022-07-22 16:16 ` Nishanth Menon 2022-07-22 16:16 ` Nishanth Menon 2022-07-28 6:28 ` Tomi Valkeinen 2022-07-28 6:28 ` Tomi Valkeinen 2022-07-25 11:26 ` Aradhya Bhatia 2022-07-25 11:26 ` Aradhya Bhatia 2022-07-25 22:14 ` Francesco Dolcini 2022-07-25 22:14 ` Francesco Dolcini 2022-08-10 17:48 ` Rob Herring 2022-08-10 17:48 ` Rob Herring 2022-07-28 11:16 ` Tomi Valkeinen 2022-07-28 11:16 ` Tomi Valkeinen 2022-07-19 8:08 ` [PATCH 2/8] dt-bindings: display: ti,am65x-dss: Add IO CTRL property for AM625 OLDI Aradhya Bhatia 2022-07-19 8:08 ` [PATCH 2/8] dt-bindings: display: ti, am65x-dss: " Aradhya Bhatia 2022-07-20 23:32 ` [PATCH 2/8] dt-bindings: display: ti,am65x-dss: " Rob Herring 2022-07-20 23:32 ` Rob Herring 2022-07-25 11:34 ` Aradhya Bhatia 2022-07-25 11:34 ` Aradhya Bhatia 2022-07-19 8:08 ` [PATCH 3/8] drm/tidss: Add support for DSS port properties Aradhya Bhatia 2022-07-19 8:08 ` Aradhya Bhatia 2022-07-28 12:07 ` Tomi Valkeinen 2022-07-28 12:07 ` Tomi Valkeinen 2022-07-19 8:08 ` [PATCH 4/8] drm/tidss: Add support for Dual Link LVDS Bus Format Aradhya Bhatia 2022-07-19 8:08 ` Aradhya Bhatia 2022-07-28 11:03 ` Tomi Valkeinen 2022-07-28 11:03 ` Tomi Valkeinen 2022-07-28 11:45 ` Tomi Valkeinen 2022-07-28 11:45 ` Tomi Valkeinen 2022-08-09 5:58 ` Aradhya Bhatia 2022-08-09 5:58 ` Aradhya Bhatia 2022-08-09 6:28 ` Tomi Valkeinen 2022-08-09 6:28 ` Tomi Valkeinen 2022-08-09 9:06 ` Aradhya Bhatia 2022-08-09 9:06 ` Aradhya Bhatia 2022-08-09 9:51 ` Tomi Valkeinen 2022-08-09 9:51 ` Tomi Valkeinen 2022-08-09 13:34 ` Aradhya Bhatia 2022-08-09 13:34 ` Aradhya Bhatia 2022-08-01 3:32 ` Aradhya Bhatia 2022-07-19 8:08 ` [PATCH 5/8] drm/tidss: dt property to force 16bit VP output to a 24bit bridge Aradhya Bhatia 2022-07-19 8:08 ` Aradhya Bhatia 2022-07-19 8:08 ` [PATCH 6/8] drm/tidss: Add IO CTRL and Power support for OLDI TX in AM625 Aradhya Bhatia 2022-07-19 8:08 ` Aradhya Bhatia 2022-07-19 8:08 ` [PATCH 7/8] drm/tidss: Fix clock request value for OLDI videoports Aradhya Bhatia 2022-07-19 8:08 ` Aradhya Bhatia 2022-07-28 10:05 ` Tomi Valkeinen 2022-07-28 10:05 ` Tomi Valkeinen 2022-07-29 3:56 ` Aradhya Bhatia [this message] 2022-07-29 3:56 ` Aradhya Bhatia 2022-07-29 8:13 ` Tomi Valkeinen 2022-07-29 8:13 ` Tomi Valkeinen 2022-07-19 8:08 ` [PATCH 8/8] drm/tidss: Enable Dual and Duplicate Modes for OLDI Aradhya Bhatia 2022-07-19 8:08 ` Aradhya Bhatia 2022-07-27 13:22 ` Tomi Valkeinen 2022-07-27 13:22 ` Tomi Valkeinen 2022-07-28 6:46 ` Tomi Valkeinen 2022-07-28 6:46 ` Tomi Valkeinen 2022-07-28 8:49 ` Aradhya Bhatia 2022-07-28 8:49 ` Aradhya Bhatia 2022-07-28 11:29 ` Tomi Valkeinen 2022-07-28 11:29 ` Tomi Valkeinen
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