* [PATCH v1 0/3] hw/intc: A few fixes for the Ibex PLIC
@ 2020-07-25 5:34 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-07-25 5:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
Recently some SiFive PLIC fixes have been merged into QEMU, this applies
those fixes to the Ibex PLIC as well as an update on how claiming
interrupts works.
Alistair Francis (3):
hw/intc: ibex_plic: Update the pending irqs
hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
hw/intc: ibex_plic: Honour source priorities
include/hw/intc/ibex_plic.h | 1 +
hw/intc/ibex_plic.c | 36 +++++++++++++++++++++++++++++++-----
2 files changed, 32 insertions(+), 5 deletions(-)
--
2.27.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 1/3] hw/intc: ibex_plic: Update the pending irqs
2020-07-25 5:34 ` Alistair Francis
@ 2020-07-25 5:34 ` Alistair Francis
-1 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-07-25 5:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
After a claim or a priority change we need to update the pending
interrupts. This is based on the same patch for the SiFive PLIC:
55765822804f5a58594e "riscv: plic: Add a couple of mising
sifive_plic_update calls"
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
---
hw/intc/ibex_plic.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 41079518c6..578edd2ce0 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
s->pending[pending_num] &= ~(1 << (s->claim % 32));
ret = s->claim;
+
+ /* Update the interrupt status after the claim */
+ ibex_plic_update(s);
}
return ret;
@@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
} else if (addr_between(addr, s->priority_base, s->priority_num)) {
uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
s->priority[irq] = value & 7;
+ ibex_plic_update(s);
} else if (addr_between(addr, s->enable_base, s->enable_num)) {
uint32_t enable_reg = (addr - s->enable_base) / 4;
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v1 1/3] hw/intc: ibex_plic: Update the pending irqs
@ 2020-07-25 5:34 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-07-25 5:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
After a claim or a priority change we need to update the pending
interrupts. This is based on the same patch for the SiFive PLIC:
55765822804f5a58594e "riscv: plic: Add a couple of mising
sifive_plic_update calls"
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
---
hw/intc/ibex_plic.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 41079518c6..578edd2ce0 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
s->pending[pending_num] &= ~(1 << (s->claim % 32));
ret = s->claim;
+
+ /* Update the interrupt status after the claim */
+ ibex_plic_update(s);
}
return ret;
@@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
} else if (addr_between(addr, s->priority_base, s->priority_num)) {
uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
s->priority[irq] = value & 7;
+ ibex_plic_update(s);
} else if (addr_between(addr, s->enable_base, s->enable_num)) {
uint32_t enable_reg = (addr - s->enable_base) / 4;
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 1/3] hw/intc: ibex_plic: Update the pending irqs
2020-07-25 5:34 ` Alistair Francis
@ 2020-08-12 18:54 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-08-12 18:54 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, palmer
On 7/25/20 7:34 AM, Alistair Francis wrote:
> After a claim or a priority change we need to update the pending
> interrupts. This is based on the same patch for the SiFive PLIC:
> 55765822804f5a58594e "riscv: plic: Add a couple of mising
> sifive_plic_update calls"
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/intc/ibex_plic.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index 41079518c6..578edd2ce0 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
> s->pending[pending_num] &= ~(1 << (s->claim % 32));
>
> ret = s->claim;
> +
> + /* Update the interrupt status after the claim */
> + ibex_plic_update(s);
> }
>
> return ret;
> @@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
> } else if (addr_between(addr, s->priority_base, s->priority_num)) {
> uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
> s->priority[irq] = value & 7;
> + ibex_plic_update(s);
> } else if (addr_between(addr, s->enable_base, s->enable_num)) {
> uint32_t enable_reg = (addr - s->enable_base) / 4;
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 1/3] hw/intc: ibex_plic: Update the pending irqs
@ 2020-08-12 18:54 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-08-12 18:54 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: palmer, alistair23
On 7/25/20 7:34 AM, Alistair Francis wrote:
> After a claim or a priority change we need to update the pending
> interrupts. This is based on the same patch for the SiFive PLIC:
> 55765822804f5a58594e "riscv: plic: Add a couple of mising
> sifive_plic_update calls"
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/intc/ibex_plic.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index 41079518c6..578edd2ce0 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
> s->pending[pending_num] &= ~(1 << (s->claim % 32));
>
> ret = s->claim;
> +
> + /* Update the interrupt status after the claim */
> + ibex_plic_update(s);
> }
>
> return ret;
> @@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
> } else if (addr_between(addr, s->priority_base, s->priority_num)) {
> uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
> s->priority[irq] = value & 7;
> + ibex_plic_update(s);
> } else if (addr_between(addr, s->enable_base, s->enable_num)) {
> uint32_t enable_reg = (addr - s->enable_base) / 4;
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 2/3] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
2020-07-25 5:34 ` Alistair Francis
@ 2020-07-25 5:34 ` Alistair Francis
-1 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-07-25 5:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
Once an interrupt has been claimed, but before it has been compelted we
shouldn't receive any more pending interrupts. This patche keeps track
of this to ensure that we don't see any more interrupts until it is
completed.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/intc/ibex_plic.h | 1 +
hw/intc/ibex_plic.c | 17 +++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
index ddc7909903..d8eb09b258 100644
--- a/include/hw/intc/ibex_plic.h
+++ b/include/hw/intc/ibex_plic.h
@@ -33,6 +33,7 @@ typedef struct IbexPlicState {
MemoryRegion mmio;
uint32_t *pending;
+ uint32_t *claimed;
uint32_t *source;
uint32_t *priority;
uint32_t *enable;
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 578edd2ce0..669247ef08 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -43,6 +43,14 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
{
int pending_num = irq / 32;
+ if (s->claimed[pending_num] & 1 << (irq % 32)) {
+ /*
+ * The interrupt has been claimed, but not compelted.
+ * The pending bit can't be set.
+ */
+ return;
+ }
+
s->pending[pending_num] |= level << (irq % 32);
}
@@ -120,6 +128,10 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
int pending_num = s->claim / 32;
s->pending[pending_num] &= ~(1 << (s->claim % 32));
+ /* Set the interrupt as claimed, but not compelted */
+ s->claimed[pending_num] |= 1 << (s->claim % 32);
+
+ /* Return the current claimed interrupt */
ret = s->claim;
/* Update the interrupt status after the claim */
@@ -155,6 +167,10 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
/* Interrupt was completed */
s->claim = 0;
}
+ if (s->claimed[value / 32] & 1 << (value % 32)) {
+ /* This value was already claimed, clear it. */
+ s->claimed[value / 32] &= ~(1 << (value % 32));
+ }
}
ibex_plic_update(s);
@@ -215,6 +231,7 @@ static void ibex_plic_realize(DeviceState *dev, Error **errp)
int i;
s->pending = g_new0(uint32_t, s->pending_num);
+ s->claimed = g_new0(uint32_t, s->pending_num);
s->source = g_new0(uint32_t, s->source_num);
s->priority = g_new0(uint32_t, s->priority_num);
s->enable = g_new0(uint32_t, s->enable_num);
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v1 2/3] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
@ 2020-07-25 5:34 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-07-25 5:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
Once an interrupt has been claimed, but before it has been compelted we
shouldn't receive any more pending interrupts. This patche keeps track
of this to ensure that we don't see any more interrupts until it is
completed.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/intc/ibex_plic.h | 1 +
hw/intc/ibex_plic.c | 17 +++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
index ddc7909903..d8eb09b258 100644
--- a/include/hw/intc/ibex_plic.h
+++ b/include/hw/intc/ibex_plic.h
@@ -33,6 +33,7 @@ typedef struct IbexPlicState {
MemoryRegion mmio;
uint32_t *pending;
+ uint32_t *claimed;
uint32_t *source;
uint32_t *priority;
uint32_t *enable;
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 578edd2ce0..669247ef08 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -43,6 +43,14 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
{
int pending_num = irq / 32;
+ if (s->claimed[pending_num] & 1 << (irq % 32)) {
+ /*
+ * The interrupt has been claimed, but not compelted.
+ * The pending bit can't be set.
+ */
+ return;
+ }
+
s->pending[pending_num] |= level << (irq % 32);
}
@@ -120,6 +128,10 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
int pending_num = s->claim / 32;
s->pending[pending_num] &= ~(1 << (s->claim % 32));
+ /* Set the interrupt as claimed, but not compelted */
+ s->claimed[pending_num] |= 1 << (s->claim % 32);
+
+ /* Return the current claimed interrupt */
ret = s->claim;
/* Update the interrupt status after the claim */
@@ -155,6 +167,10 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
/* Interrupt was completed */
s->claim = 0;
}
+ if (s->claimed[value / 32] & 1 << (value % 32)) {
+ /* This value was already claimed, clear it. */
+ s->claimed[value / 32] &= ~(1 << (value % 32));
+ }
}
ibex_plic_update(s);
@@ -215,6 +231,7 @@ static void ibex_plic_realize(DeviceState *dev, Error **errp)
int i;
s->pending = g_new0(uint32_t, s->pending_num);
+ s->claimed = g_new0(uint32_t, s->pending_num);
s->source = g_new0(uint32_t, s->source_num);
s->priority = g_new0(uint32_t, s->priority_num);
s->enable = g_new0(uint32_t, s->enable_num);
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 3/3] hw/intc: ibex_plic: Honour source priorities
2020-07-25 5:34 ` Alistair Francis
@ 2020-07-25 5:34 ` Alistair Francis
-1 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-07-25 5:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
priorities" does and ensures that the highest priority interrupt will be
serviced first.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
---
hw/intc/ibex_plic.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 669247ef08..f49fa67c91 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -57,6 +57,8 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
{
int i;
+ uint32_t max_irq = 0;
+ uint32_t max_prio = s->threshold;
for (i = 0; i < s->pending_num; i++) {
uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
@@ -66,14 +68,17 @@ static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
continue;
}
- if (s->priority[irq_num] > s->threshold) {
- if (!s->claim) {
- s->claim = irq_num;
- }
- return true;
+ if (s->priority[irq_num] > max_prio) {
+ max_irq = irq_num;
+ max_prio = s->priority[irq_num];
}
}
+ if (max_irq) {
+ s->claim = max_irq;
+ return true;
+ }
+
return false;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v1 3/3] hw/intc: ibex_plic: Honour source priorities
@ 2020-07-25 5:34 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-07-25 5:34 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
priorities" does and ensures that the highest priority interrupt will be
serviced first.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
---
hw/intc/ibex_plic.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 669247ef08..f49fa67c91 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -57,6 +57,8 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
{
int i;
+ uint32_t max_irq = 0;
+ uint32_t max_prio = s->threshold;
for (i = 0; i < s->pending_num; i++) {
uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
@@ -66,14 +68,17 @@ static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
continue;
}
- if (s->priority[irq_num] > s->threshold) {
- if (!s->claim) {
- s->claim = irq_num;
- }
- return true;
+ if (s->priority[irq_num] > max_prio) {
+ max_irq = irq_num;
+ max_prio = s->priority[irq_num];
}
}
+ if (max_irq) {
+ s->claim = max_irq;
+ return true;
+ }
+
return false;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 3/3] hw/intc: ibex_plic: Honour source priorities
2020-07-25 5:34 ` Alistair Francis
@ 2020-08-12 18:56 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-08-12 18:56 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, palmer
On 7/25/20 7:34 AM, Alistair Francis wrote:
> This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
> priorities" does and ensures that the highest priority interrupt will be
> serviced first.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/intc/ibex_plic.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index 669247ef08..f49fa67c91 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -57,6 +57,8 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
> static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
> {
> int i;
> + uint32_t max_irq = 0;
> + uint32_t max_prio = s->threshold;
>
> for (i = 0; i < s->pending_num; i++) {
> uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
> @@ -66,14 +68,17 @@ static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
> continue;
> }
>
> - if (s->priority[irq_num] > s->threshold) {
> - if (!s->claim) {
> - s->claim = irq_num;
> - }
> - return true;
> + if (s->priority[irq_num] > max_prio) {
> + max_irq = irq_num;
> + max_prio = s->priority[irq_num];
> }
> }
>
> + if (max_irq) {
> + s->claim = max_irq;
> + return true;
> + }
> +
> return false;
> }
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 3/3] hw/intc: ibex_plic: Honour source priorities
@ 2020-08-12 18:56 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-08-12 18:56 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: palmer, alistair23
On 7/25/20 7:34 AM, Alistair Francis wrote:
> This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
> priorities" does and ensures that the highest priority interrupt will be
> serviced first.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/intc/ibex_plic.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index 669247ef08..f49fa67c91 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -57,6 +57,8 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
> static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
> {
> int i;
> + uint32_t max_irq = 0;
> + uint32_t max_prio = s->threshold;
>
> for (i = 0; i < s->pending_num; i++) {
> uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
> @@ -66,14 +68,17 @@ static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
> continue;
> }
>
> - if (s->priority[irq_num] > s->threshold) {
> - if (!s->claim) {
> - s->claim = irq_num;
> - }
> - return true;
> + if (s->priority[irq_num] > max_prio) {
> + max_irq = irq_num;
> + max_prio = s->priority[irq_num];
> }
> }
>
> + if (max_irq) {
> + s->claim = max_irq;
> + return true;
> + }
> +
> return false;
> }
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 0/3] hw/intc: A few fixes for the Ibex PLIC
2020-07-25 5:34 ` Alistair Francis
@ 2020-08-12 16:28 ` Alistair Francis
-1 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-08-12 16:28 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, open list:RISC-V, qemu-devel@nongnu.org Developers
On Fri, Jul 24, 2020 at 10:44 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Recently some SiFive PLIC fixes have been merged into QEMU, this applies
> those fixes to the Ibex PLIC as well as an update on how claiming
> interrupts works.
>
> Alistair Francis (3):
> hw/intc: ibex_plic: Update the pending irqs
> hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
> hw/intc: ibex_plic: Honour source priorities
Applied to riscv-to-apply.next
Alistair
>
> include/hw/intc/ibex_plic.h | 1 +
> hw/intc/ibex_plic.c | 36 +++++++++++++++++++++++++++++++-----
> 2 files changed, 32 insertions(+), 5 deletions(-)
>
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 0/3] hw/intc: A few fixes for the Ibex PLIC
@ 2020-08-12 16:28 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-08-12 16:28 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Palmer Dabbelt
On Fri, Jul 24, 2020 at 10:44 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Recently some SiFive PLIC fixes have been merged into QEMU, this applies
> those fixes to the Ibex PLIC as well as an update on how claiming
> interrupts works.
>
> Alistair Francis (3):
> hw/intc: ibex_plic: Update the pending irqs
> hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
> hw/intc: ibex_plic: Honour source priorities
Applied to riscv-to-apply.next
Alistair
>
> include/hw/intc/ibex_plic.h | 1 +
> hw/intc/ibex_plic.c | 36 +++++++++++++++++++++++++++++++-----
> 2 files changed, 32 insertions(+), 5 deletions(-)
>
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread