[MODERATED] Re: [patch V8 09/15] SSB 9

[Tim Chen <tim.c.chen@linux.intel.com>]

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On 04/30/2018 08:04 AM, speck for Thomas Gleixner wrote:

> 
> void x86_set_spec_ctrl(u64 val)
> {
>-	if (val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_RDS))
>+	if (val & x86_spec_ctrl_mask)
> 		WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
> 	else
> 		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
>@@ -459,6 +465,7 @@ static enum ssb_mitigation_cmd __init __
> 		switch (boot_cpu_data.x86_vendor) {
> 		case X86_VENDOR_INTEL:
> 			x86_spec_ctrl_base |= SPEC_CTRL_RDS;
>+			x86_spec_ctrl_mask &= ~(SPEC_CTRL_RDS);
> 			x86_set_spec_ctrl(SPEC_CTRL_RDS);

We only have cpu 0's RDS set when we ask for SSB to be turned off for whole system
in current v8 patchset.

I noticed that the x86_set_spec_ctrl call in
init_intel got dropped in current patchset.  It was in Konrad's original patchset.

Now only cpu 0 got RDS set in the code above and not the other CPUs when we are
asking for RDS to be turned on for whole system.

root@otc-cfl-s-02:~# cat /sys/devices/system/cpu/vulnerabilities/spec_store_bypass 
Mitigation: Speculative Store Bypass disabled

root@otc-cfl-s-02:~/md_test# ./md_dump
msr 0x48 cpu 0  val: 4
msr 0x48 cpu 1  val: 0
msr 0x48 cpu 2  val: 0
msr 0x48 cpu 3  val: 0
msr 0x48 cpu 4  val: 0
msr 0x48 cpu 5  val: 0
msr 0x48 cpu 6  val: 0
msr 0x48 cpu 7  val: 0
msr 0x48 cpu 8  val: 0
msr 0x48 cpu 9  val: 0
msr 0x48 cpu 10  val: 0
msr 0x48 cpu 11  val: 0

We should get val: 4 for all CPUs.

With the proposed fix below, I get the expected value of 4 for all CPU.

Tim

---

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ef3f9c0..c799e48 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -770,6 +770,9 @@ static void init_intel(struct cpuinfo_x86 *c)
 	init_intel_energy_perf(c);
 
 	init_intel_misc_features(c);
+
+	if (cpu_has(c, X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
+		x86_set_spec_ctrl(SPEC_CTRL_RDS);
 }
 
 #ifdef CONFIG_X86_32