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From: Thomas Gleixner <tglx@linutronix.de>
To: speck@linutronix.de
Subject: Re: [patch V8 09/15] SSB 9
Date: Tue, 1 May 2018 12:11:42 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.21.1805011207200.1596@nanos.tec.linutronix.de> (raw)
In-Reply-To: <alpine.DEB.2.21.1805011147380.1596@nanos.tec.linutronix.de>

On Tue, 1 May 2018, speck for Thomas Gleixner wrote:
> On Tue, 1 May 2018, speck for Thomas Gleixner wrote:
> > >  
> > >  	init_intel_misc_features(c);
> > > +
> > > +	if (cpu_has(c, X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
> > > +		x86_set_spec_ctrl(SPEC_CTRL_RDS);
> > 
> > Groan no. x86_setup_ap_spec_ctrl() needs to be investigated not random crap
> > added to some random place again.
> > 
> > x86_setup_ap_spec_ctrl()
> > {
> >        if (boot_cpu_has(X86_FEATURE_IBRS))
> >                 x86_set_spec_ctrl(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
> > 
> > So that's the issue.
> 
> And if that does not work on your machine then
> 
>        if (boot_cpu_has(X86_FEATURE_IBRS))
>                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
> 
> in check_bugs() does not work either. So how is your crappy hack solving
> anything?

And if your machine has the SPEC CTL MSR then it should have set
FEATURE_IBRS as well because:

       if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
	        set_cpu_cap(c, X86_FEATURE_IBRS);
                set_cpu_cap(c, X86_FEATURE_IBPB);
        }

And if FEATURE_RDS is set and FEATURE_SPEC_CTRL is not then something is
even more wrong.

Papering over symptoms without trying to understand the root cause is the
worst engineering approach.

Thanks,

	tglx

  reply	other threads:[~2018-05-01 10:11 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-30 15:04 [patch V8 00/15] SSB 0 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 01/15] SSB 1 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 02/15] SSB 2 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 03/15] SSB 3 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 04/15] SSB 4 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 05/15] SSB 5 Thomas Gleixner
2018-04-30 18:53   ` [MODERATED] " Andi Kleen
2018-04-30 20:57   ` Tim Chen
2018-04-30 23:12     ` Tim Chen
2018-04-30 15:04 ` [patch V8 06/15] SSB 6 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 07/15] SSB 7 Thomas Gleixner
2018-04-30 18:59   ` [MODERATED] " Andi Kleen
2018-04-30 15:04 ` [patch V8 08/15] SSB 8 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 09/15] SSB 9 Thomas Gleixner
2018-05-01  1:25   ` [MODERATED] " Tim Chen
2018-05-01  2:15     ` Konrad Rzeszutek Wilk
2018-05-01  2:26       ` Tim Chen
2018-05-01 13:11       ` Thomas Gleixner
2018-05-01  7:58     ` Thomas Gleixner
2018-05-01  9:49       ` Thomas Gleixner
2018-05-01 10:11         ` Thomas Gleixner [this message]
2018-04-30 15:04 ` [patch V8 10/15] SSB 10 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 11/15] SSB 11 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 12/15] SSB 12 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 13/15] SSB 13 Thomas Gleixner
2018-04-30 20:12   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30 20:26     ` Thomas Gleixner
2018-04-30 21:03       ` [MODERATED] " Kees Cook
2018-04-30 21:05         ` Linus Torvalds
2018-04-30 21:25           ` Thomas Gleixner
2018-04-30 21:51   ` [MODERATED] " Kees Cook
2018-05-01  8:06     ` Thomas Gleixner
2018-05-01 13:29       ` Thomas Gleixner
2018-04-30 15:04 ` [patch V8 14/15] SSB 14 Thomas Gleixner
2018-04-30 15:04 ` [patch V8 15/15] SSB 15 Thomas Gleixner
2018-04-30 22:15   ` [MODERATED] " Kees Cook
2018-05-01  0:34     ` Andi Kleen
2018-05-01 13:15       ` Thomas Gleixner
2018-05-01 17:45         ` [MODERATED] " Jon Masters
2018-05-01 21:45     ` Thomas Gleixner
2018-05-01  2:32   ` [MODERATED] " Tim Chen
2018-05-01  8:02     ` Thomas Gleixner

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