* [PATCH 00/13] MT8183 IOMMU SUPPORT
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
This patchset mainly adds support for mt8183 IOMMU and SMI.
mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
----------
| |
gals0-rx gals1-rx
| |
| |
gals0-tx gals1-tx
| |
------------
SMI Common
------------
|
+-----+-----+--------+-----+-----+-------+-------+
| | | | | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | | | | | | |
| | | | | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | | | | | | |
larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
disp vdec IPU0 IPU1 venc IPU1 cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional between larb2/3/5/6 and
SMI-common. GALS can help synchronize for the modules in different
clock frequence, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it don't have the
register, thus it has the special "smi" clock and it don't have the
"apb" clock. From the diagram above, we add "gals0" and "gals1"
clockes for smi-common and add a "gals" clock for smi-larb.
>From the diagram above, CCU(Camera Control Unit) is connected with
smi-common directly, we can look it as "larb7" but its register space
is different with the normal larb.
This patchset is based on v4.19-rc1.
the patch 1/2/3/4/5 add the iommu/smi support for mt8183;
the patch 6/7/8/9 add mmu1 support;
the last patches contain some minor changes:
-patch 10 fix a issue.
-patch 11 improve the code flow(add shutdown).
-patch 12 cleanup some smi codes(delete need_larbid).
-patch 13 switch to SPDX license.
this patchset don't contain the dtsi part since it need depend on the
ccf and power-domain nodes which has not been accepted.
Yong Wu (13):
dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
iommu/mediatek: Use a struct as the platform data
memory: mtk-smi: Use a general config_port interface
iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
iommu/mediatek: Add mt8183 IOMMU support
iommu/mediatek: Add mmu1 support
memory: mtk-smi: Invoke pm runtime_callback to enable clocks
memory: mtk-smi: Use a struct for the platform data for smi-common
memory: mtk-smi: Add bus_sel for mt8183
iommu/mediatek: Add VLD_PA_RANGE register backup when suspend
iommu/mediatek: Add shutdown callback
memory: mtk-smi: Get rid of need_larbid
iommu/mediatek: Switch to SPDX license identifier
.../devicetree/bindings/iommu/mediatek,iommu.txt | 15 +-
.../memory-controllers/mediatek,smi-common.txt | 11 +-
.../memory-controllers/mediatek,smi-larb.txt | 3 +
drivers/iommu/io-pgtable-arm-v7s.c | 38 ++-
drivers/iommu/io-pgtable.h | 8 +-
drivers/iommu/mtk_iommu.c | 145 +++++++----
drivers/iommu/mtk_iommu.h | 23 +-
drivers/iommu/mtk_iommu_v1.c | 10 +-
drivers/memory/mtk-smi.c | 267 ++++++++++++++-------
include/dt-bindings/memory/mt2701-larb-port.h | 10 +-
include/dt-bindings/memory/mt8173-larb-port.h | 10 +-
include/dt-bindings/memory/mt8183-larb-port.h | 130 ++++++++++
include/soc/mediatek/smi.h | 10 +-
13 files changed, 476 insertions(+), 204 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
--
1.9.1
^ permalink raw reply [flat|nested] 61+ messages in thread* [PATCH 00/13] MT8183 IOMMU SUPPORT
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
This patchset mainly adds support for mt8183 IOMMU and SMI.
mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
----------
| |
gals0-rx gals1-rx
| |
| |
gals0-tx gals1-tx
| |
------------
SMI Common
------------
|
+-----+-----+--------+-----+-----+-------+-------+
| | | | | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | | | | | | |
| | | | | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | | | | | | |
larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
disp vdec IPU0 IPU1 venc IPU1 cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional between larb2/3/5/6 and
SMI-common. GALS can help synchronize for the modules in different
clock frequence, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it don't have the
register, thus it has the special "smi" clock and it don't have the
"apb" clock. From the diagram above, we add "gals0" and "gals1"
clockes for smi-common and add a "gals" clock for smi-larb.
>From the diagram above, CCU(Camera Control Unit) is connected with
smi-common directly, we can look it as "larb7" but its register space
is different with the normal larb.
This patchset is based on v4.19-rc1.
the patch 1/2/3/4/5 add the iommu/smi support for mt8183;
the patch 6/7/8/9 add mmu1 support;
the last patches contain some minor changes:
-patch 10 fix a issue.
-patch 11 improve the code flow(add shutdown).
-patch 12 cleanup some smi codes(delete need_larbid).
-patch 13 switch to SPDX license.
this patchset don't contain the dtsi part since it need depend on the
ccf and power-domain nodes which has not been accepted.
Yong Wu (13):
dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
iommu/mediatek: Use a struct as the platform data
memory: mtk-smi: Use a general config_port interface
iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
iommu/mediatek: Add mt8183 IOMMU support
iommu/mediatek: Add mmu1 support
memory: mtk-smi: Invoke pm runtime_callback to enable clocks
memory: mtk-smi: Use a struct for the platform data for smi-common
memory: mtk-smi: Add bus_sel for mt8183
iommu/mediatek: Add VLD_PA_RANGE register backup when suspend
iommu/mediatek: Add shutdown callback
memory: mtk-smi: Get rid of need_larbid
iommu/mediatek: Switch to SPDX license identifier
.../devicetree/bindings/iommu/mediatek,iommu.txt | 15 +-
.../memory-controllers/mediatek,smi-common.txt | 11 +-
.../memory-controllers/mediatek,smi-larb.txt | 3 +
drivers/iommu/io-pgtable-arm-v7s.c | 38 ++-
drivers/iommu/io-pgtable.h | 8 +-
drivers/iommu/mtk_iommu.c | 145 +++++++----
drivers/iommu/mtk_iommu.h | 23 +-
drivers/iommu/mtk_iommu_v1.c | 10 +-
drivers/memory/mtk-smi.c | 267 ++++++++++++++-------
include/dt-bindings/memory/mt2701-larb-port.h | 10 +-
include/dt-bindings/memory/mt8173-larb-port.h | 10 +-
include/dt-bindings/memory/mt8183-larb-port.h | 130 ++++++++++
include/soc/mediatek/smi.h | 10 +-
13 files changed, 476 insertions(+), 204 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
--
1.9.1
^ permalink raw reply [flat|nested] 61+ messages in thread* [PATCH 01/13] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
This patch adds decriptions for mt8183 IOMMU and SMI.
mt8183 has one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
----------
| |
gals0-rx gals1-rx
| |
| |
gals0-tx gals1-tx
| |
------------
SMI Common
------------
|
+-----+-----+--------+-----+-----+-------+-------+
| | | | | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | | | | | | |
| | | | | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | | | | | | |
larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
disp vdec IPU0 IPU1 venc IPU1 cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional between larb2/3/5/6 and
SMI-common. GALS can help synchronize for the modules in different
clock frequence, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it don't have the
register, thus it has the special "smi" clock and it don't have the
"apb" clock. From the diagram above, we add "gals0" and "gals1"
clockes for smi-common and add a "gals" clock for smi-larb.
From the diagram above, CCU(Camera Control Unit) is connected with
smi-common directly, we can look it as "larb7" but its register space
is different with the normal larb.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
.../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
.../memory-controllers/mediatek,smi-common.txt | 11 +-
.../memory-controllers/mediatek,smi-larb.txt | 3 +
include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
4 files changed, 153 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index df5db73..03bb0e0 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -36,24 +36,33 @@ each local arbiter.
like display, video decode, and camera. And there are different ports
in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
+ In some Socs, there may be a GALS(Global Async Local Sync) module between
+smi-common and m4u, and additional GALS module between smi-larb and
+smi-common. GALS can been seen as a "asynchronous fifo" which could help
+synchronize for the modules in different clock frequence.
Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
+ "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
- clocks : must contain one entry for each clock-names.
-- clock-names : must be "bclk", It is the block clock of m4u.
+- clock-names : Only 1 optional clock:
+ - "bclk": the block clock of m4u.
+ Note that m4u use the EMI clock which always has been enabled before kernel
+ if there is no this "bclk".
- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701,
- dt-binding/memory/mt2712-larb-port.h for mt2712, and
- dt-binding/memory/mt8173-larb-port.h for mt8173.
+ dt-binding/memory/mt2712-larb-port.h for mt2712,
+ dt-binding/memory/mt8173-larb-port.h for mt8173, and
+ dt-binding/memory/mt8183-larb-port.h for mt8183.
Example:
iommu: iommu@10205000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index 615abdd..abab51b 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -2,9 +2,10 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
-the second generation of SMI HW while mt2701 uses the first generation HW of
-SMI.
+Mediatek SMI have two generations of HW architecture, here is the list
+which generation the Socs use:
+generation 1: mt2701.
+generation 2: mt2712, mt8173 and mt8183.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
@@ -18,6 +19,7 @@ Required properties:
"mediatek,mt2701-smi-common"
"mediatek,mt2712-smi-common"
"mediatek,mt8173-smi-common"
+ "mediatek,mt8183-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
@@ -29,6 +31,9 @@ Required properties:
They may be the same if both source clocks are the same.
- "async" : asynchronous clock, it help transform the smi clock into the emi
clock domain, this clock is only needed by generation 1 smi HW.
+ and these 2 option clocks for generation 2 smi HW:
+ - "gals0": the path0 clock of GALS(Global Async Local Sync).
+ - "gals1": the path1 clock of GALS(Global Async Local Sync).
Example:
smi_common: smi@14022000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
index 083155c..e46bf5e 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -7,6 +7,7 @@ Required properties:
"mediatek,mt2701-smi-larb"
"mediatek,mt2712-smi-larb"
"mediatek,mt8173-smi-larb"
+ "mediatek,mt8183-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
@@ -15,6 +16,8 @@ Required properties:
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
the register.
- "smi" : It's the clock for transfer data and command.
+ and this optional clock name:
+ - "gals": the clock for gals(Global Async Local Sync).
Required property for mt2701 and mt2712:
- mediatek,larb-id :the hardware id of this larb.
diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h
new file mode 100644
index 0000000..2c579f3
--- /dev/null
+++ b/include/dt-bindings/memory/mt8183-larb-port.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_IOMMU_PORT_MT8183_H
+#define __DTS_IOMMU_PORT_MT8183_H
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+#define M4U_LARB4_ID 4
+#define M4U_LARB5_ID 5
+#define M4U_LARB6_ID 6
+#define M4U_LARB7_ID 7
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8)
+#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
+
+/* larb2 VPU0 */
+#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2)
+
+/* larb3 VPU1 */
+#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4)
+
+/* larb4 */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5)
+#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10)
+
+/* larb5 */
+#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8)
+#define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9)
+#define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10)
+#define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11)
+#define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12)
+#define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13)
+#define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14)
+#define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15)
+#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16)
+#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17)
+#define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18)
+#define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19)
+#define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20)
+#define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21)
+#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22)
+#define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23)
+#define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24)
+
+/* larb6 */
+#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2)
+#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3)
+#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4)
+#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5)
+#define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6)
+#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7)
+#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8)
+#define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9)
+#define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10)
+#define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11)
+#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12)
+#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13)
+#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14)
+#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15)
+#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16)
+#define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17)
+#define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18)
+#define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19)
+#define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20)
+#define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21)
+#define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22)
+#define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23)
+#define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24)
+#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25)
+#define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26)
+#define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27)
+#define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28)
+#define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29)
+#define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30)
+
+/* CCU */
+#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1)
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 01/13] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds decriptions for mt8183 IOMMU and SMI.
mt8183 has one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
----------
| |
gals0-rx gals1-rx
| |
| |
gals0-tx gals1-tx
| |
------------
SMI Common
------------
|
+-----+-----+--------+-----+-----+-------+-------+
| | | | | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | | | | | | |
| | | | | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | | | | | | |
larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
disp vdec IPU0 IPU1 venc IPU1 cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional between larb2/3/5/6 and
SMI-common. GALS can help synchronize for the modules in different
clock frequence, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it don't have the
register, thus it has the special "smi" clock and it don't have the
"apb" clock. From the diagram above, we add "gals0" and "gals1"
clockes for smi-common and add a "gals" clock for smi-larb.
>From the diagram above, CCU(Camera Control Unit) is connected with
smi-common directly, we can look it as "larb7" but its register space
is different with the normal larb.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
.../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
.../memory-controllers/mediatek,smi-common.txt | 11 +-
.../memory-controllers/mediatek,smi-larb.txt | 3 +
include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
4 files changed, 153 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index df5db73..03bb0e0 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -36,24 +36,33 @@ each local arbiter.
like display, video decode, and camera. And there are different ports
in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
+ In some Socs, there may be a GALS(Global Async Local Sync) module between
+smi-common and m4u, and additional GALS module between smi-larb and
+smi-common. GALS can been seen as a "asynchronous fifo" which could help
+synchronize for the modules in different clock frequence.
Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
+ "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
- clocks : must contain one entry for each clock-names.
-- clock-names : must be "bclk", It is the block clock of m4u.
+- clock-names : Only 1 optional clock:
+ - "bclk": the block clock of m4u.
+ Note that m4u use the EMI clock which always has been enabled before kernel
+ if there is no this "bclk".
- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701,
- dt-binding/memory/mt2712-larb-port.h for mt2712, and
- dt-binding/memory/mt8173-larb-port.h for mt8173.
+ dt-binding/memory/mt2712-larb-port.h for mt2712,
+ dt-binding/memory/mt8173-larb-port.h for mt8173, and
+ dt-binding/memory/mt8183-larb-port.h for mt8183.
Example:
iommu: iommu at 10205000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index 615abdd..abab51b 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -2,9 +2,10 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
-the second generation of SMI HW while mt2701 uses the first generation HW of
-SMI.
+Mediatek SMI have two generations of HW architecture, here is the list
+which generation the Socs use:
+generation 1: mt2701.
+generation 2: mt2712, mt8173 and mt8183.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
@@ -18,6 +19,7 @@ Required properties:
"mediatek,mt2701-smi-common"
"mediatek,mt2712-smi-common"
"mediatek,mt8173-smi-common"
+ "mediatek,mt8183-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
@@ -29,6 +31,9 @@ Required properties:
They may be the same if both source clocks are the same.
- "async" : asynchronous clock, it help transform the smi clock into the emi
clock domain, this clock is only needed by generation 1 smi HW.
+ and these 2 option clocks for generation 2 smi HW:
+ - "gals0": the path0 clock of GALS(Global Async Local Sync).
+ - "gals1": the path1 clock of GALS(Global Async Local Sync).
Example:
smi_common: smi at 14022000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
index 083155c..e46bf5e 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -7,6 +7,7 @@ Required properties:
"mediatek,mt2701-smi-larb"
"mediatek,mt2712-smi-larb"
"mediatek,mt8173-smi-larb"
+ "mediatek,mt8183-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
@@ -15,6 +16,8 @@ Required properties:
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
the register.
- "smi" : It's the clock for transfer data and command.
+ and this optional clock name:
+ - "gals": the clock for gals(Global Async Local Sync).
Required property for mt2701 and mt2712:
- mediatek,larb-id :the hardware id of this larb.
diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h
new file mode 100644
index 0000000..2c579f3
--- /dev/null
+++ b/include/dt-bindings/memory/mt8183-larb-port.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_IOMMU_PORT_MT8183_H
+#define __DTS_IOMMU_PORT_MT8183_H
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+#define M4U_LARB4_ID 4
+#define M4U_LARB5_ID 5
+#define M4U_LARB6_ID 6
+#define M4U_LARB7_ID 7
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8)
+#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
+
+/* larb2 VPU0 */
+#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2)
+
+/* larb3 VPU1 */
+#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4)
+
+/* larb4 */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5)
+#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10)
+
+/* larb5 */
+#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8)
+#define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9)
+#define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10)
+#define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11)
+#define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12)
+#define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13)
+#define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14)
+#define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15)
+#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16)
+#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17)
+#define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18)
+#define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19)
+#define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20)
+#define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21)
+#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22)
+#define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23)
+#define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24)
+
+/* larb6 */
+#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2)
+#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3)
+#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4)
+#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5)
+#define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6)
+#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7)
+#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8)
+#define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9)
+#define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10)
+#define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11)
+#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12)
+#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13)
+#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14)
+#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15)
+#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16)
+#define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17)
+#define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18)
+#define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19)
+#define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20)
+#define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21)
+#define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22)
+#define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23)
+#define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24)
+#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25)
+#define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26)
+#define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27)
+#define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28)
+#define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29)
+#define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30)
+
+/* CCU */
+#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1)
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 01/13] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This patch adds decriptions for mt8183 IOMMU and SMI.
mt8183 has one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
----------
| |
gals0-rx gals1-rx
| |
| |
gals0-tx gals1-tx
| |
------------
SMI Common
------------
|
+-----+-----+--------+-----+-----+-------+-------+
| | | | | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | | | | | | |
| | | | | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | | | | | | |
larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
disp vdec IPU0 IPU1 venc IPU1 cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional between larb2/3/5/6 and
SMI-common. GALS can help synchronize for the modules in different
clock frequence, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it don't have the
register, thus it has the special "smi" clock and it don't have the
"apb" clock. From the diagram above, we add "gals0" and "gals1"
clockes for smi-common and add a "gals" clock for smi-larb.
>From the diagram above, CCU(Camera Control Unit) is connected with
smi-common directly, we can look it as "larb7" but its register space
is different with the normal larb.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
.../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
.../memory-controllers/mediatek,smi-common.txt | 11 +-
.../memory-controllers/mediatek,smi-larb.txt | 3 +
include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
4 files changed, 153 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index df5db73..03bb0e0 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -36,24 +36,33 @@ each local arbiter.
like display, video decode, and camera. And there are different ports
in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
+ In some Socs, there may be a GALS(Global Async Local Sync) module between
+smi-common and m4u, and additional GALS module between smi-larb and
+smi-common. GALS can been seen as a "asynchronous fifo" which could help
+synchronize for the modules in different clock frequence.
Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
+ "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
- clocks : must contain one entry for each clock-names.
-- clock-names : must be "bclk", It is the block clock of m4u.
+- clock-names : Only 1 optional clock:
+ - "bclk": the block clock of m4u.
+ Note that m4u use the EMI clock which always has been enabled before kernel
+ if there is no this "bclk".
- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701,
- dt-binding/memory/mt2712-larb-port.h for mt2712, and
- dt-binding/memory/mt8173-larb-port.h for mt8173.
+ dt-binding/memory/mt2712-larb-port.h for mt2712,
+ dt-binding/memory/mt8173-larb-port.h for mt8173, and
+ dt-binding/memory/mt8183-larb-port.h for mt8183.
Example:
iommu: iommu@10205000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index 615abdd..abab51b 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -2,9 +2,10 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
-the second generation of SMI HW while mt2701 uses the first generation HW of
-SMI.
+Mediatek SMI have two generations of HW architecture, here is the list
+which generation the Socs use:
+generation 1: mt2701.
+generation 2: mt2712, mt8173 and mt8183.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
@@ -18,6 +19,7 @@ Required properties:
"mediatek,mt2701-smi-common"
"mediatek,mt2712-smi-common"
"mediatek,mt8173-smi-common"
+ "mediatek,mt8183-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
@@ -29,6 +31,9 @@ Required properties:
They may be the same if both source clocks are the same.
- "async" : asynchronous clock, it help transform the smi clock into the emi
clock domain, this clock is only needed by generation 1 smi HW.
+ and these 2 option clocks for generation 2 smi HW:
+ - "gals0": the path0 clock of GALS(Global Async Local Sync).
+ - "gals1": the path1 clock of GALS(Global Async Local Sync).
Example:
smi_common: smi@14022000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
index 083155c..e46bf5e 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -7,6 +7,7 @@ Required properties:
"mediatek,mt2701-smi-larb"
"mediatek,mt2712-smi-larb"
"mediatek,mt8173-smi-larb"
+ "mediatek,mt8183-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
@@ -15,6 +16,8 @@ Required properties:
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
the register.
- "smi" : It's the clock for transfer data and command.
+ and this optional clock name:
+ - "gals": the clock for gals(Global Async Local Sync).
Required property for mt2701 and mt2712:
- mediatek,larb-id :the hardware id of this larb.
diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h
new file mode 100644
index 0000000..2c579f3
--- /dev/null
+++ b/include/dt-bindings/memory/mt8183-larb-port.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
+ */
+#ifndef __DTS_IOMMU_PORT_MT8183_H
+#define __DTS_IOMMU_PORT_MT8183_H
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+#define M4U_LARB4_ID 4
+#define M4U_LARB5_ID 5
+#define M4U_LARB6_ID 6
+#define M4U_LARB7_ID 7
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8)
+#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
+
+/* larb2 VPU0 */
+#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2)
+
+/* larb3 VPU1 */
+#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4)
+
+/* larb4 */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5)
+#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10)
+
+/* larb5 */
+#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8)
+#define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9)
+#define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10)
+#define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11)
+#define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12)
+#define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13)
+#define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14)
+#define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15)
+#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16)
+#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17)
+#define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18)
+#define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19)
+#define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20)
+#define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21)
+#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22)
+#define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23)
+#define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24)
+
+/* larb6 */
+#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2)
+#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3)
+#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4)
+#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5)
+#define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6)
+#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7)
+#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8)
+#define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9)
+#define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10)
+#define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11)
+#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12)
+#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13)
+#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14)
+#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15)
+#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16)
+#define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17)
+#define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18)
+#define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19)
+#define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20)
+#define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21)
+#define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22)
+#define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23)
+#define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24)
+#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25)
+#define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26)
+#define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27)
+#define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28)
+#define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29)
+#define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30)
+
+/* CCU */
+#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1)
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread[parent not found: <1535954502-30646-2-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH 01/13] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
2018-09-03 6:01 ` Yong Wu
@ 2018-09-16 22:26 ` Rob Herring
-1 siblings, 0 replies; 61+ messages in thread
From: Rob Herring @ 2018-09-16 22:26 UTC (permalink / raw)
To: Yong Wu
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Daniel Kurtz,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Matthias Brugger,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Robin Murphy,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, Sep 03, 2018 at 02:01:30PM +0800, Yong Wu wrote:
> This patch adds decriptions for mt8183 IOMMU and SMI.
>
> mt8183 has one M4U like mt8173 and is also MTK IOMMU gen2 which
> uses ARM Short-Descriptor translation table format.
>
> The mt8183 M4U-SMI HW diagram is as below:
>
> EMI
> |
> M4U
> |
> ----------
> | |
> gals0-rx gals1-rx
> | |
> | |
> gals0-tx gals1-tx
> | |
> ------------
> SMI Common
> ------------
> |
> +-----+-----+--------+-----+-----+-------+-------+
> | | | | | | | |
> | | gals-rx gals-rx | gals-rx gals-rx gals-rx
> | | | | | | | |
> | | | | | | | |
> | | gals-tx gals-tx | gals-tx gals-tx gals-tx
> | | | | | | | |
> larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
> disp vdec IPU0 IPU1 venc IPU1 cam
>
> All the connections are HW fixed, SW can NOT adjust it.
>
> Compared with mt8173, we add a GALS(Global Async Local Sync) module
> between SMI-common and M4U, and additional between larb2/3/5/6 and
> SMI-common. GALS can help synchronize for the modules in different
> clock frequence, it can be seen as a "asynchronous fifo".
s/frequence/frequency/
> GALS can only help transfer the command/data while it don't have the
> register, thus it has the special "smi" clock and it don't have the
> "apb" clock. From the diagram above, we add "gals0" and "gals1"
> clockes for smi-common and add a "gals" clock for smi-larb.
s/clockes/clocks/
s/don't/doesn't/
> From the diagram above, CCU(Camera Control Unit) is connected with
> smi-common directly, we can look it as "larb7" but its register space
> is different with the normal larb.
>
> Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> .../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
> .../memory-controllers/mediatek,smi-common.txt | 11 +-
> .../memory-controllers/mediatek,smi-larb.txt | 3 +
> include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
> 4 files changed, 153 insertions(+), 6 deletions(-)
> create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
With those fixed,
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 01/13] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
@ 2018-09-16 22:26 ` Rob Herring
0 siblings, 0 replies; 61+ messages in thread
From: Rob Herring @ 2018-09-16 22:26 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Sep 03, 2018 at 02:01:30PM +0800, Yong Wu wrote:
> This patch adds decriptions for mt8183 IOMMU and SMI.
>
> mt8183 has one M4U like mt8173 and is also MTK IOMMU gen2 which
> uses ARM Short-Descriptor translation table format.
>
> The mt8183 M4U-SMI HW diagram is as below:
>
> EMI
> |
> M4U
> |
> ----------
> | |
> gals0-rx gals1-rx
> | |
> | |
> gals0-tx gals1-tx
> | |
> ------------
> SMI Common
> ------------
> |
> +-----+-----+--------+-----+-----+-------+-------+
> | | | | | | | |
> | | gals-rx gals-rx | gals-rx gals-rx gals-rx
> | | | | | | | |
> | | | | | | | |
> | | gals-tx gals-tx | gals-tx gals-tx gals-tx
> | | | | | | | |
> larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
> disp vdec IPU0 IPU1 venc IPU1 cam
>
> All the connections are HW fixed, SW can NOT adjust it.
>
> Compared with mt8173, we add a GALS(Global Async Local Sync) module
> between SMI-common and M4U, and additional between larb2/3/5/6 and
> SMI-common. GALS can help synchronize for the modules in different
> clock frequence, it can be seen as a "asynchronous fifo".
s/frequence/frequency/
> GALS can only help transfer the command/data while it don't have the
> register, thus it has the special "smi" clock and it don't have the
> "apb" clock. From the diagram above, we add "gals0" and "gals1"
> clockes for smi-common and add a "gals" clock for smi-larb.
s/clockes/clocks/
s/don't/doesn't/
> From the diagram above, CCU(Camera Control Unit) is connected with
> smi-common directly, we can look it as "larb7" but its register space
> is different with the normal larb.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> .../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
> .../memory-controllers/mediatek,smi-common.txt | 11 +-
> .../memory-controllers/mediatek,smi-larb.txt | 3 +
> include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
> 4 files changed, 153 insertions(+), 6 deletions(-)
> create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
With those fixed,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH 01/13] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
@ 2018-09-17 6:15 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-17 6:15 UTC (permalink / raw)
To: Rob Herring
Cc: Joerg Roedel, Matthias Brugger, Robin Murphy, Tomasz Figa,
Will Deacon, Daniel Kurtz, linux-mediatek, srv_heupstream,
devicetree, linux-kernel, linux-arm-kernel, iommu, arnd,
yingjoe.chen
On Sun, 2018-09-16 at 17:26 -0500, Rob Herring wrote:
> On Mon, Sep 03, 2018 at 02:01:30PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8183 IOMMU and SMI.
> >
> > mt8183 has one M4U like mt8173 and is also MTK IOMMU gen2 which
> > uses ARM Short-Descriptor translation table format.
> >
> > The mt8183 M4U-SMI HW diagram is as below:
> >
> > EMI
> > |
> > M4U
> > |
> > ----------
> > | |
> > gals0-rx gals1-rx
> > | |
> > | |
> > gals0-tx gals1-tx
> > | |
> > ------------
> > SMI Common
> > ------------
> > |
> > +-----+-----+--------+-----+-----+-------+-------+
> > | | | | | | | |
> > | | gals-rx gals-rx | gals-rx gals-rx gals-rx
> > | | | | | | | |
> > | | | | | | | |
> > | | gals-tx gals-tx | gals-tx gals-tx gals-tx
> > | | | | | | | |
> > larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
> > disp vdec IPU0 IPU1 venc IPU1 cam
> >
> > All the connections are HW fixed, SW can NOT adjust it.
> >
> > Compared with mt8173, we add a GALS(Global Async Local Sync) module
> > between SMI-common and M4U, and additional between larb2/3/5/6 and
> > SMI-common. GALS can help synchronize for the modules in different
> > clock frequence, it can be seen as a "asynchronous fifo".
>
> s/frequence/frequency/
>
>
> > GALS can only help transfer the command/data while it don't have the
> > register, thus it has the special "smi" clock and it don't have the
> > "apb" clock. From the diagram above, we add "gals0" and "gals1"
> > clockes for smi-common and add a "gals" clock for smi-larb.
>
> s/clockes/clocks/
> s/don't/doesn't/
>
> > From the diagram above, CCU(Camera Control Unit) is connected with
> > smi-common directly, we can look it as "larb7" but its register space
> > is different with the normal larb.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > .../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
> > .../memory-controllers/mediatek,smi-common.txt | 11 +-
> > .../memory-controllers/mediatek,smi-larb.txt | 3 +
> > include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
> > 4 files changed, 153 insertions(+), 6 deletions(-)
> > create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
>
> With those fixed,
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Thanks Rob. I will fix them in next version.
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 01/13] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
@ 2018-09-17 6:15 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-17 6:15 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, 2018-09-16 at 17:26 -0500, Rob Herring wrote:
> On Mon, Sep 03, 2018 at 02:01:30PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8183 IOMMU and SMI.
> >
> > mt8183 has one M4U like mt8173 and is also MTK IOMMU gen2 which
> > uses ARM Short-Descriptor translation table format.
> >
> > The mt8183 M4U-SMI HW diagram is as below:
> >
> > EMI
> > |
> > M4U
> > |
> > ----------
> > | |
> > gals0-rx gals1-rx
> > | |
> > | |
> > gals0-tx gals1-tx
> > | |
> > ------------
> > SMI Common
> > ------------
> > |
> > +-----+-----+--------+-----+-----+-------+-------+
> > | | | | | | | |
> > | | gals-rx gals-rx | gals-rx gals-rx gals-rx
> > | | | | | | | |
> > | | | | | | | |
> > | | gals-tx gals-tx | gals-tx gals-tx gals-tx
> > | | | | | | | |
> > larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
> > disp vdec IPU0 IPU1 venc IPU1 cam
> >
> > All the connections are HW fixed, SW can NOT adjust it.
> >
> > Compared with mt8173, we add a GALS(Global Async Local Sync) module
> > between SMI-common and M4U, and additional between larb2/3/5/6 and
> > SMI-common. GALS can help synchronize for the modules in different
> > clock frequence, it can be seen as a "asynchronous fifo".
>
> s/frequence/frequency/
>
>
> > GALS can only help transfer the command/data while it don't have the
> > register, thus it has the special "smi" clock and it don't have the
> > "apb" clock. From the diagram above, we add "gals0" and "gals1"
> > clockes for smi-common and add a "gals" clock for smi-larb.
>
> s/clockes/clocks/
> s/don't/doesn't/
>
> > From the diagram above, CCU(Camera Control Unit) is connected with
> > smi-common directly, we can look it as "larb7" but its register space
> > is different with the normal larb.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > .../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
> > .../memory-controllers/mediatek,smi-common.txt | 11 +-
> > .../memory-controllers/mediatek,smi-larb.txt | 3 +
> > include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
> > 4 files changed, 153 insertions(+), 6 deletions(-)
> > create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
>
> With those fixed,
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Thanks Rob. I will fix them in next version.
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH 01/13] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
@ 2018-09-17 6:15 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-17 6:15 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Daniel Kurtz,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Matthias Brugger,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Robin Murphy,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Sun, 2018-09-16 at 17:26 -0500, Rob Herring wrote:
> On Mon, Sep 03, 2018 at 02:01:30PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8183 IOMMU and SMI.
> >
> > mt8183 has one M4U like mt8173 and is also MTK IOMMU gen2 which
> > uses ARM Short-Descriptor translation table format.
> >
> > The mt8183 M4U-SMI HW diagram is as below:
> >
> > EMI
> > |
> > M4U
> > |
> > ----------
> > | |
> > gals0-rx gals1-rx
> > | |
> > | |
> > gals0-tx gals1-tx
> > | |
> > ------------
> > SMI Common
> > ------------
> > |
> > +-----+-----+--------+-----+-----+-------+-------+
> > | | | | | | | |
> > | | gals-rx gals-rx | gals-rx gals-rx gals-rx
> > | | | | | | | |
> > | | | | | | | |
> > | | gals-tx gals-tx | gals-tx gals-tx gals-tx
> > | | | | | | | |
> > larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
> > disp vdec IPU0 IPU1 venc IPU1 cam
> >
> > All the connections are HW fixed, SW can NOT adjust it.
> >
> > Compared with mt8173, we add a GALS(Global Async Local Sync) module
> > between SMI-common and M4U, and additional between larb2/3/5/6 and
> > SMI-common. GALS can help synchronize for the modules in different
> > clock frequence, it can be seen as a "asynchronous fifo".
>
> s/frequence/frequency/
>
>
> > GALS can only help transfer the command/data while it don't have the
> > register, thus it has the special "smi" clock and it don't have the
> > "apb" clock. From the diagram above, we add "gals0" and "gals1"
> > clockes for smi-common and add a "gals" clock for smi-larb.
>
> s/clockes/clocks/
> s/don't/doesn't/
>
> > From the diagram above, CCU(Camera Control Unit) is connected with
> > smi-common directly, we can look it as "larb7" but its register space
> > is different with the normal larb.
> >
> > Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > .../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
> > .../memory-controllers/mediatek,smi-common.txt | 11 +-
> > .../memory-controllers/mediatek,smi-larb.txt | 3 +
> > include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
> > 4 files changed, 153 insertions(+), 6 deletions(-)
> > create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
>
> With those fixed,
>
> Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Thanks Rob. I will fix them in next version.
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 02/13] iommu/mediatek: Use a struct as the platform data
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
Use a struct as the platform special data instead of the enumeration.
This is a prepare patch for adding mt8183 iommu support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 24 ++++++++++++++++--------
drivers/iommu/mtk_iommu.h | 6 +++++-
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index f9f69f7..c0e2da5 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -54,7 +54,7 @@
#define REG_MMU_CTRL_REG 0x110
#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
- ((data)->m4u_plat == M4U_MT2712 ? 4 : 5)
+ ((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)
/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
#define F_MMU_TF_PROTECT_SEL(prot, data) \
(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
@@ -517,7 +517,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
regval = F_MMU_TF_PROTECT_SEL(2, data);
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
@@ -538,14 +538,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
upper_32_bits(data->protect_base);
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
- if (data->enable_4GB && data->m4u_plat != M4U_MT8173) {
+ if (data->enable_4GB && data->plat_data->m4u_plat != M4U_MT8173) {
/*
* If 4GB mode is enabled, the validate PA range is from
* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
@@ -556,7 +556,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
/* It's MISC control register whose default value is ok except mt8173.*/
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -589,7 +589,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
data->dev = dev;
- data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev);
+ data->plat_data = of_device_get_match_data(dev);
/* Protect memory. HW will access here while translation fault.*/
protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
@@ -733,9 +733,17 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
};
+static const struct mtk_iommu_plat_data mt2712_data = {
+ .m4u_plat = M4U_MT2712,
+};
+
+static const struct mtk_iommu_plat_data mt8173_data = {
+ .m4u_plat = M4U_MT8173,
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
- { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712},
- { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173},
+ { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
+ { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 778498b..333a0ef 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -41,6 +41,10 @@ enum mtk_iommu_plat {
M4U_MT8173,
};
+struct mtk_iommu_plat_data {
+ enum mtk_iommu_plat m4u_plat;
+};
+
struct mtk_iommu_domain;
struct mtk_iommu_data {
@@ -57,7 +61,7 @@ struct mtk_iommu_data {
bool tlb_flush_active;
struct iommu_device iommu;
- enum mtk_iommu_plat m4u_plat;
+ const struct mtk_iommu_plat_data *plat_data;
struct list_head list;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 02/13] iommu/mediatek: Use a struct as the platform data
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Use a struct as the platform special data instead of the enumeration.
This is a prepare patch for adding mt8183 iommu support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 24 ++++++++++++++++--------
drivers/iommu/mtk_iommu.h | 6 +++++-
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index f9f69f7..c0e2da5 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -54,7 +54,7 @@
#define REG_MMU_CTRL_REG 0x110
#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
- ((data)->m4u_plat == M4U_MT2712 ? 4 : 5)
+ ((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)
/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
#define F_MMU_TF_PROTECT_SEL(prot, data) \
(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
@@ -517,7 +517,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
regval = F_MMU_TF_PROTECT_SEL(2, data);
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
@@ -538,14 +538,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
upper_32_bits(data->protect_base);
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
- if (data->enable_4GB && data->m4u_plat != M4U_MT8173) {
+ if (data->enable_4GB && data->plat_data->m4u_plat != M4U_MT8173) {
/*
* If 4GB mode is enabled, the validate PA range is from
* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
@@ -556,7 +556,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
/* It's MISC control register whose default value is ok except mt8173.*/
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -589,7 +589,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
data->dev = dev;
- data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev);
+ data->plat_data = of_device_get_match_data(dev);
/* Protect memory. HW will access here while translation fault.*/
protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
@@ -733,9 +733,17 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
};
+static const struct mtk_iommu_plat_data mt2712_data = {
+ .m4u_plat = M4U_MT2712,
+};
+
+static const struct mtk_iommu_plat_data mt8173_data = {
+ .m4u_plat = M4U_MT8173,
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
- { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712},
- { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173},
+ { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
+ { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 778498b..333a0ef 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -41,6 +41,10 @@ enum mtk_iommu_plat {
M4U_MT8173,
};
+struct mtk_iommu_plat_data {
+ enum mtk_iommu_plat m4u_plat;
+};
+
struct mtk_iommu_domain;
struct mtk_iommu_data {
@@ -57,7 +61,7 @@ struct mtk_iommu_data {
bool tlb_flush_active;
struct iommu_device iommu;
- enum mtk_iommu_plat m4u_plat;
+ const struct mtk_iommu_plat_data *plat_data;
struct list_head list;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 02/13] iommu/mediatek: Use a struct as the platform data
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Use a struct as the platform special data instead of the enumeration.
This is a prepare patch for adding mt8183 iommu support.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 24 ++++++++++++++++--------
drivers/iommu/mtk_iommu.h | 6 +++++-
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index f9f69f7..c0e2da5 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -54,7 +54,7 @@
#define REG_MMU_CTRL_REG 0x110
#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
- ((data)->m4u_plat == M4U_MT2712 ? 4 : 5)
+ ((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)
/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
#define F_MMU_TF_PROTECT_SEL(prot, data) \
(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
@@ -517,7 +517,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
regval = F_MMU_TF_PROTECT_SEL(2, data);
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
@@ -538,14 +538,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
upper_32_bits(data->protect_base);
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
- if (data->enable_4GB && data->m4u_plat != M4U_MT8173) {
+ if (data->enable_4GB && data->plat_data->m4u_plat != M4U_MT8173) {
/*
* If 4GB mode is enabled, the validate PA range is from
* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
@@ -556,7 +556,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
/* It's MISC control register whose default value is ok except mt8173.*/
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -589,7 +589,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
data->dev = dev;
- data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev);
+ data->plat_data = of_device_get_match_data(dev);
/* Protect memory. HW will access here while translation fault.*/
protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
@@ -733,9 +733,17 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
};
+static const struct mtk_iommu_plat_data mt2712_data = {
+ .m4u_plat = M4U_MT2712,
+};
+
+static const struct mtk_iommu_plat_data mt8173_data = {
+ .m4u_plat = M4U_MT8173,
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
- { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712},
- { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173},
+ { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
+ { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 778498b..333a0ef 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -41,6 +41,10 @@ enum mtk_iommu_plat {
M4U_MT8173,
};
+struct mtk_iommu_plat_data {
+ enum mtk_iommu_plat m4u_plat;
+};
+
struct mtk_iommu_domain;
struct mtk_iommu_data {
@@ -57,7 +61,7 @@ struct mtk_iommu_data {
bool tlb_flush_active;
struct iommu_device iommu;
- enum mtk_iommu_plat m4u_plat;
+ const struct mtk_iommu_plat_data *plat_data;
struct list_head list;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 03/13] memory: mtk-smi: Use a general config_port interface
2018-09-03 6:01 ` Yong Wu
(?)
@ 2018-09-03 6:01 ` Yong Wu
-1 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
The config_port of mt2712 and mt8183 are the same. Use a general
config_port interface instead.
In addition, in mt2712, larb8 and larb9 are the bdpsys larbs which
are not the normal larb, their register space are different from the
normal one. thus, we can not call the general config_port. In mt8183,
CCU connects with smi-common directly, it's also not a normal larb.
Hence, we add a "larb_special_mask" for these special larbs.
This is also a prepare patch for adding mt8183 SMI support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 8f2d152..e37e54b 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -53,6 +53,7 @@ struct mtk_smi_larb_gen {
bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
void (*config_port)(struct device *);
+ unsigned int larb_special_mask; /* The special larbs mask. */
};
struct mtk_smi {
@@ -176,17 +177,13 @@ void mtk_smi_larb_put(struct device *larbdev)
return -ENODEV;
}
-static void mtk_smi_larb_config_port_mt2712(struct device *dev)
+static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
u32 reg;
int i;
- /*
- * larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly.
- * Don't need to set it again.
- */
- if (larb->larbid == 8 || larb->larbid == 9)
+ if (BIT(larb->larbid) & larb->larb_gen->larb_special_mask)
return;
for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
@@ -261,7 +258,8 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
.need_larbid = true,
- .config_port = mtk_smi_larb_config_port_mt2712,
+ .config_port = mtk_smi_larb_config_port_gen2_general,
+ .larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
static const struct of_device_id mtk_smi_larb_of_ids[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 03/13] memory: mtk-smi: Use a general config_port interface
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
The config_port of mt2712 and mt8183 are the same. Use a general
config_port interface instead.
In addition, in mt2712, larb8 and larb9 are the bdpsys larbs which
are not the normal larb, their register space are different from the
normal one. thus, we can not call the general config_port. In mt8183,
CCU connects with smi-common directly, it's also not a normal larb.
Hence, we add a "larb_special_mask" for these special larbs.
This is also a prepare patch for adding mt8183 SMI support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 8f2d152..e37e54b 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -53,6 +53,7 @@ struct mtk_smi_larb_gen {
bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
void (*config_port)(struct device *);
+ unsigned int larb_special_mask; /* The special larbs mask. */
};
struct mtk_smi {
@@ -176,17 +177,13 @@ void mtk_smi_larb_put(struct device *larbdev)
return -ENODEV;
}
-static void mtk_smi_larb_config_port_mt2712(struct device *dev)
+static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
u32 reg;
int i;
- /*
- * larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly.
- * Don't need to set it again.
- */
- if (larb->larbid == 8 || larb->larbid == 9)
+ if (BIT(larb->larbid) & larb->larb_gen->larb_special_mask)
return;
for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
@@ -261,7 +258,8 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
.need_larbid = true,
- .config_port = mtk_smi_larb_config_port_mt2712,
+ .config_port = mtk_smi_larb_config_port_gen2_general,
+ .larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
static const struct of_device_id mtk_smi_larb_of_ids[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 03/13] memory: mtk-smi: Use a general config_port interface
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
The config_port of mt2712 and mt8183 are the same. Use a general
config_port interface instead.
In addition, in mt2712, larb8 and larb9 are the bdpsys larbs which
are not the normal larb, their register space are different from the
normal one. thus, we can not call the general config_port. In mt8183,
CCU connects with smi-common directly, it's also not a normal larb.
Hence, we add a "larb_special_mask" for these special larbs.
This is also a prepare patch for adding mt8183 SMI support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 8f2d152..e37e54b 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -53,6 +53,7 @@ struct mtk_smi_larb_gen {
bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
void (*config_port)(struct device *);
+ unsigned int larb_special_mask; /* The special larbs mask. */
};
struct mtk_smi {
@@ -176,17 +177,13 @@ void mtk_smi_larb_put(struct device *larbdev)
return -ENODEV;
}
-static void mtk_smi_larb_config_port_mt2712(struct device *dev)
+static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
u32 reg;
int i;
- /*
- * larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly.
- * Don't need to set it again.
- */
- if (larb->larbid == 8 || larb->larbid == 9)
+ if (BIT(larb->larbid) & larb->larb_gen->larb_special_mask)
return;
for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
@@ -261,7 +258,8 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
.need_larbid = true,
- .config_port = mtk_smi_larb_config_port_mt2712,
+ .config_port = mtk_smi_larb_config_port_gen2_general,
+ .larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
static const struct of_device_id mtk_smi_larb_of_ids[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
2018-09-03 6:01 ` Yong Wu
(?)
@ 2018-09-03 6:01 ` Yong Wu
-1 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
MediaTek extend the arm v7s descriptor to support the dram over 4GB.
In the mt2712 and mt8173, it's called "4GB mode", the physical address
is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
bit32 is always enabled. thus, in the M4U, we always enable the bit9
for all PTEs which means to enable bit32 of physical address.
but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
32bits.
In order to unify code, in the "4GB mode", we add the bit32 for the
physical address manually in our driver.
Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
has to been moved into v7s.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
still is 32bits. Acturally, our HW extend the v7s pgtable. currently
the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
for us currently, thus we don't change it.
---
drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
drivers/iommu/io-pgtable.h | 8 ++++----
drivers/iommu/mtk_iommu.c | 15 +++++++++------
drivers/iommu/mtk_iommu.h | 1 +
4 files changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index b5948ba..47538dd 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -124,7 +124,9 @@
#define ARM_V7S_TEX_MASK 0x7
#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
-#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
+/* MTK extend the two bits below for over 4GB mode */
+#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
+#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
/* *well, except for TEX on level 2 large pages, of course :( */
#define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
@@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
}
static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
- struct io_pgtable_cfg *cfg)
+ struct io_pgtable_cfg *cfg,
+ phys_addr_t paddr) /* Only for MTK */
{
bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
@@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
pte |= ARM_V7S_ATTR_NS_SECTION;
- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
- pte |= ARM_V7S_ATTR_MTK_4GB;
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
+ if (paddr & BIT_ULL(32))
+ pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
+ if (paddr & BIT_ULL(33))
+ pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
+ }
return pte;
}
@@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
return -EEXIST;
}
- pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
+ pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
if (num_entries > 1)
pte = arm_v7s_pte_to_cont(pte, lvl);
@@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
return 0;
- if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
+ if (WARN_ON(upper_32_bits(iova)))
+ return -ERANGE;
+
+ if (WARN_ON(upper_32_bits(paddr) &&
+ !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
return -ERANGE;
ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
@@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
num_entries = size >> ARM_V7S_LVL_SHIFT(2);
unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
- pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
+ pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
if (num_entries > 1)
pte = arm_v7s_pte_to_cont(pte, 2);
@@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
unsigned long iova)
{
struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ struct io_pgtable_cfg *cfg = &data->iop.cfg;
arm_v7s_iopte *ptep = data->pgd, pte;
+ phys_addr_t paddr;
int lvl = 0;
u32 mask;
@@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
mask = ARM_V7S_LVL_MASK(lvl);
if (arm_v7s_pte_is_cont(pte, lvl))
mask *= ARM_V7S_CONT_PAGES;
- return (pte & mask) | (iova & ~mask);
+ paddr = (pte & mask) | (iova & ~mask);
+
+ if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
+ cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
+ if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
+ paddr |= BIT_ULL(32);
+ if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
+ paddr |= BIT_ULL(33);
+ }
+ return paddr;
}
static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
index 2df7909..0eeed94 100644
--- a/drivers/iommu/io-pgtable.h
+++ b/drivers/iommu/io-pgtable.h
@@ -62,10 +62,10 @@ struct io_pgtable_cfg {
* (unmapped) entries but the hardware might do so anyway, perform
* TLB maintenance when mapping as well as when unmapping.
*
- * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
- * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
- * when the SoC is in "4GB mode" and they can only access the high
- * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
+ * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
+ * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
+ * address bit when the SoC dram is over 4GB and they can access
+ * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
*
* IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
* be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index c0e2da5..86bf647 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
unsigned long flags;
int ret;
+ if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
+ data->plat_data->has_4gb_mode &&
+ data->enable_4GB)
+ paddr |= BIT_ULL(32);
+
spin_lock_irqsave(&dom->pgtlock, flags);
- ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
- size, prot);
+ ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
spin_unlock_irqrestore(&dom->pgtlock, flags);
return ret;
@@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
unsigned long flags;
phys_addr_t pa;
@@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
pa = dom->iop->iova_to_phys(dom->iop, iova);
spin_unlock_irqrestore(&dom->pgtlock, flags);
- if (data->enable_4GB)
- pa |= BIT_ULL(32);
-
return pa;
}
@@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
+ .has_4gb_mode = true,
};
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
+ .has_4gb_mode = true,
};
static const struct of_device_id mtk_iommu_of_ids[] = {
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 333a0ef..a243047 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -43,6 +43,7 @@ enum mtk_iommu_plat {
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
+ bool has_4gb_mode;
};
struct mtk_iommu_domain;
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
MediaTek extend the arm v7s descriptor to support the dram over 4GB.
In the mt2712 and mt8173, it's called "4GB mode", the physical address
is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
bit32 is always enabled. thus, in the M4U, we always enable the bit9
for all PTEs which means to enable bit32 of physical address.
but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
32bits.
In order to unify code, in the "4GB mode", we add the bit32 for the
physical address manually in our driver.
Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
has to been moved into v7s.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
still is 32bits. Acturally, our HW extend the v7s pgtable. currently
the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
for us currently, thus we don't change it.
---
drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
drivers/iommu/io-pgtable.h | 8 ++++----
drivers/iommu/mtk_iommu.c | 15 +++++++++------
drivers/iommu/mtk_iommu.h | 1 +
4 files changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index b5948ba..47538dd 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -124,7 +124,9 @@
#define ARM_V7S_TEX_MASK 0x7
#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
-#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
+/* MTK extend the two bits below for over 4GB mode */
+#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
+#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
/* *well, except for TEX on level 2 large pages, of course :( */
#define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
@@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
}
static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
- struct io_pgtable_cfg *cfg)
+ struct io_pgtable_cfg *cfg,
+ phys_addr_t paddr) /* Only for MTK */
{
bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
@@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
pte |= ARM_V7S_ATTR_NS_SECTION;
- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
- pte |= ARM_V7S_ATTR_MTK_4GB;
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
+ if (paddr & BIT_ULL(32))
+ pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
+ if (paddr & BIT_ULL(33))
+ pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
+ }
return pte;
}
@@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
return -EEXIST;
}
- pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
+ pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
if (num_entries > 1)
pte = arm_v7s_pte_to_cont(pte, lvl);
@@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
return 0;
- if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
+ if (WARN_ON(upper_32_bits(iova)))
+ return -ERANGE;
+
+ if (WARN_ON(upper_32_bits(paddr) &&
+ !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
return -ERANGE;
ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
@@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
num_entries = size >> ARM_V7S_LVL_SHIFT(2);
unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
- pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
+ pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
if (num_entries > 1)
pte = arm_v7s_pte_to_cont(pte, 2);
@@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
unsigned long iova)
{
struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ struct io_pgtable_cfg *cfg = &data->iop.cfg;
arm_v7s_iopte *ptep = data->pgd, pte;
+ phys_addr_t paddr;
int lvl = 0;
u32 mask;
@@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
mask = ARM_V7S_LVL_MASK(lvl);
if (arm_v7s_pte_is_cont(pte, lvl))
mask *= ARM_V7S_CONT_PAGES;
- return (pte & mask) | (iova & ~mask);
+ paddr = (pte & mask) | (iova & ~mask);
+
+ if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
+ cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
+ if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
+ paddr |= BIT_ULL(32);
+ if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
+ paddr |= BIT_ULL(33);
+ }
+ return paddr;
}
static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
index 2df7909..0eeed94 100644
--- a/drivers/iommu/io-pgtable.h
+++ b/drivers/iommu/io-pgtable.h
@@ -62,10 +62,10 @@ struct io_pgtable_cfg {
* (unmapped) entries but the hardware might do so anyway, perform
* TLB maintenance when mapping as well as when unmapping.
*
- * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
- * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
- * when the SoC is in "4GB mode" and they can only access the high
- * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
+ * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
+ * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
+ * address bit when the SoC dram is over 4GB and they can access
+ * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
*
* IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
* be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index c0e2da5..86bf647 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
unsigned long flags;
int ret;
+ if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
+ data->plat_data->has_4gb_mode &&
+ data->enable_4GB)
+ paddr |= BIT_ULL(32);
+
spin_lock_irqsave(&dom->pgtlock, flags);
- ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
- size, prot);
+ ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
spin_unlock_irqrestore(&dom->pgtlock, flags);
return ret;
@@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
unsigned long flags;
phys_addr_t pa;
@@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
pa = dom->iop->iova_to_phys(dom->iop, iova);
spin_unlock_irqrestore(&dom->pgtlock, flags);
- if (data->enable_4GB)
- pa |= BIT_ULL(32);
-
return pa;
}
@@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
+ .has_4gb_mode = true,
};
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
+ .has_4gb_mode = true,
};
static const struct of_device_id mtk_iommu_of_ids[] = {
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 333a0ef..a243047 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -43,6 +43,7 @@ enum mtk_iommu_plat {
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
+ bool has_4gb_mode;
};
struct mtk_iommu_domain;
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
MediaTek extend the arm v7s descriptor to support the dram over 4GB.
In the mt2712 and mt8173, it's called "4GB mode", the physical address
is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
bit32 is always enabled. thus, in the M4U, we always enable the bit9
for all PTEs which means to enable bit32 of physical address.
but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
32bits.
In order to unify code, in the "4GB mode", we add the bit32 for the
physical address manually in our driver.
Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
has to been moved into v7s.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
still is 32bits. Acturally, our HW extend the v7s pgtable. currently
the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
for us currently, thus we don't change it.
---
drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
drivers/iommu/io-pgtable.h | 8 ++++----
drivers/iommu/mtk_iommu.c | 15 +++++++++------
drivers/iommu/mtk_iommu.h | 1 +
4 files changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index b5948ba..47538dd 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -124,7 +124,9 @@
#define ARM_V7S_TEX_MASK 0x7
#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
-#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
+/* MTK extend the two bits below for over 4GB mode */
+#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
+#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
/* *well, except for TEX on level 2 large pages, of course :( */
#define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
@@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
}
static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
- struct io_pgtable_cfg *cfg)
+ struct io_pgtable_cfg *cfg,
+ phys_addr_t paddr) /* Only for MTK */
{
bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
@@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
pte |= ARM_V7S_ATTR_NS_SECTION;
- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
- pte |= ARM_V7S_ATTR_MTK_4GB;
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
+ if (paddr & BIT_ULL(32))
+ pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
+ if (paddr & BIT_ULL(33))
+ pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
+ }
return pte;
}
@@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
return -EEXIST;
}
- pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
+ pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
if (num_entries > 1)
pte = arm_v7s_pte_to_cont(pte, lvl);
@@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
return 0;
- if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
+ if (WARN_ON(upper_32_bits(iova)))
+ return -ERANGE;
+
+ if (WARN_ON(upper_32_bits(paddr) &&
+ !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
return -ERANGE;
ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
@@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
num_entries = size >> ARM_V7S_LVL_SHIFT(2);
unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
- pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
+ pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
if (num_entries > 1)
pte = arm_v7s_pte_to_cont(pte, 2);
@@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
unsigned long iova)
{
struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ struct io_pgtable_cfg *cfg = &data->iop.cfg;
arm_v7s_iopte *ptep = data->pgd, pte;
+ phys_addr_t paddr;
int lvl = 0;
u32 mask;
@@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
mask = ARM_V7S_LVL_MASK(lvl);
if (arm_v7s_pte_is_cont(pte, lvl))
mask *= ARM_V7S_CONT_PAGES;
- return (pte & mask) | (iova & ~mask);
+ paddr = (pte & mask) | (iova & ~mask);
+
+ if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
+ cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
+ if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
+ paddr |= BIT_ULL(32);
+ if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
+ paddr |= BIT_ULL(33);
+ }
+ return paddr;
}
static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
index 2df7909..0eeed94 100644
--- a/drivers/iommu/io-pgtable.h
+++ b/drivers/iommu/io-pgtable.h
@@ -62,10 +62,10 @@ struct io_pgtable_cfg {
* (unmapped) entries but the hardware might do so anyway, perform
* TLB maintenance when mapping as well as when unmapping.
*
- * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
- * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
- * when the SoC is in "4GB mode" and they can only access the high
- * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
+ * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
+ * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
+ * address bit when the SoC dram is over 4GB and they can access
+ * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
*
* IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
* be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index c0e2da5..86bf647 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
unsigned long flags;
int ret;
+ if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
+ data->plat_data->has_4gb_mode &&
+ data->enable_4GB)
+ paddr |= BIT_ULL(32);
+
spin_lock_irqsave(&dom->pgtlock, flags);
- ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
- size, prot);
+ ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
spin_unlock_irqrestore(&dom->pgtlock, flags);
return ret;
@@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
unsigned long flags;
phys_addr_t pa;
@@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
pa = dom->iop->iova_to_phys(dom->iop, iova);
spin_unlock_irqrestore(&dom->pgtlock, flags);
- if (data->enable_4GB)
- pa |= BIT_ULL(32);
-
return pa;
}
@@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
+ .has_4gb_mode = true,
};
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
+ .has_4gb_mode = true,
};
static const struct of_device_id mtk_iommu_of_ids[] = {
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 333a0ef..a243047 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -43,6 +43,7 @@ enum mtk_iommu_plat {
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
+ bool has_4gb_mode;
};
struct mtk_iommu_domain;
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-20 5:54 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-20 5:54 UTC (permalink / raw)
To: Robin Murphy
Cc: Joerg Roedel, Rob Herring, Matthias Brugger, Tomasz Figa,
Will Deacon, Daniel Kurtz, linux-mediatek, srv_heupstream,
devicetree, linux-kernel, linux-arm-kernel, iommu, arnd,
yingjoe.chen
Hi Robin,
Could you help take a look at this patch since I changed the v7s
here?
Thanks.
On Mon, 2018-09-03 at 14:01 +0800, Yong Wu wrote:
> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>
> In the mt2712 and mt8173, it's called "4GB mode", the physical address
> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> bit32 is always enabled. thus, in the M4U, we always enable the bit9
> for all PTEs which means to enable bit32 of physical address.
>
> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> 32bits.
>
> In order to unify code, in the "4GB mode", we add the bit32 for the
> physical address manually in our driver.
>
> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> has to been moved into v7s.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> for us currently, thus we don't change it.
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> drivers/iommu/io-pgtable.h | 8 ++++----
> drivers/iommu/mtk_iommu.c | 15 +++++++++------
> drivers/iommu/mtk_iommu.h | 1 +
> 4 files changed, 44 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index b5948ba..47538dd 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -124,7 +124,9 @@
> #define ARM_V7S_TEX_MASK 0x7
> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>
> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> +/* MTK extend the two bits below for over 4GB mode */
> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>
> /* *well, except for TEX on level 2 large pages, of course :( */
> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> }
>
> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> - struct io_pgtable_cfg *cfg)
> + struct io_pgtable_cfg *cfg,
> + phys_addr_t paddr) /* Only for MTK */
> {
> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> pte |= ARM_V7S_ATTR_NS_SECTION;
>
> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> - pte |= ARM_V7S_ATTR_MTK_4GB;
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (paddr & BIT_ULL(32))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> + if (paddr & BIT_ULL(33))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> + }
>
> return pte;
> }
> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> return -EEXIST;
> }
>
> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, lvl);
>
> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> return 0;
>
> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> + if (WARN_ON(upper_32_bits(iova)))
> + return -ERANGE;
> +
> + if (WARN_ON(upper_32_bits(paddr) &&
> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
> return -ERANGE;
>
> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>
> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, 2);
>
> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> unsigned long iova)
> {
> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> arm_v7s_iopte *ptep = data->pgd, pte;
> + phys_addr_t paddr;
> int lvl = 0;
> u32 mask;
>
> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> mask = ARM_V7S_LVL_MASK(lvl);
> if (arm_v7s_pte_is_cont(pte, lvl))
> mask *= ARM_V7S_CONT_PAGES;
> - return (pte & mask) | (iova & ~mask);
> + paddr = (pte & mask) | (iova & ~mask);
> +
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> + paddr |= BIT_ULL(32);
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> + paddr |= BIT_ULL(33);
> + }
> + return paddr;
> }
>
> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> index 2df7909..0eeed94 100644
> --- a/drivers/iommu/io-pgtable.h
> +++ b/drivers/iommu/io-pgtable.h
> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> * (unmapped) entries but the hardware might do so anyway, perform
> * TLB maintenance when mapping as well as when unmapping.
> *
> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> - * when the SoC is in "4GB mode" and they can only access the high
> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
> + * address bit when the SoC dram is over 4GB and they can access
> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> *
> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index c0e2da5..86bf647 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> phys_addr_t paddr, size_t size, int prot)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> int ret;
>
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + data->plat_data->has_4gb_mode &&
> + data->enable_4GB)
> + paddr |= BIT_ULL(32);
> +
> spin_lock_irqsave(&dom->pgtlock, flags);
> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> - size, prot);
> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> return ret;
> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> dma_addr_t iova)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> phys_addr_t pa;
>
> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> pa = dom->iop->iova_to_phys(dom->iop, iova);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> - if (data->enable_4GB)
> - pa |= BIT_ULL(32);
> -
> return pa;
> }
>
> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>
> static const struct mtk_iommu_plat_data mt2712_data = {
> .m4u_plat = M4U_MT2712,
> + .has_4gb_mode = true,
> };
>
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> + .has_4gb_mode = true,
> };
>
> static const struct of_device_id mtk_iommu_of_ids[] = {
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 333a0ef..a243047 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>
> struct mtk_iommu_plat_data {
> enum mtk_iommu_plat m4u_plat;
> + bool has_4gb_mode;
> };
>
> struct mtk_iommu_domain;
^ permalink raw reply [flat|nested] 61+ messages in thread* [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-20 5:54 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-20 5:54 UTC (permalink / raw)
To: linux-arm-kernel
Hi Robin,
Could you help take a look at this patch since I changed the v7s
here?
Thanks.
On Mon, 2018-09-03 at 14:01 +0800, Yong Wu wrote:
> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>
> In the mt2712 and mt8173, it's called "4GB mode", the physical address
> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> bit32 is always enabled. thus, in the M4U, we always enable the bit9
> for all PTEs which means to enable bit32 of physical address.
>
> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> 32bits.
>
> In order to unify code, in the "4GB mode", we add the bit32 for the
> physical address manually in our driver.
>
> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> has to been moved into v7s.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> for us currently, thus we don't change it.
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> drivers/iommu/io-pgtable.h | 8 ++++----
> drivers/iommu/mtk_iommu.c | 15 +++++++++------
> drivers/iommu/mtk_iommu.h | 1 +
> 4 files changed, 44 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index b5948ba..47538dd 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -124,7 +124,9 @@
> #define ARM_V7S_TEX_MASK 0x7
> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>
> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> +/* MTK extend the two bits below for over 4GB mode */
> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>
> /* *well, except for TEX on level 2 large pages, of course :( */
> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> }
>
> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> - struct io_pgtable_cfg *cfg)
> + struct io_pgtable_cfg *cfg,
> + phys_addr_t paddr) /* Only for MTK */
> {
> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> pte |= ARM_V7S_ATTR_NS_SECTION;
>
> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> - pte |= ARM_V7S_ATTR_MTK_4GB;
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (paddr & BIT_ULL(32))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> + if (paddr & BIT_ULL(33))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> + }
>
> return pte;
> }
> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> return -EEXIST;
> }
>
> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, lvl);
>
> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> return 0;
>
> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> + if (WARN_ON(upper_32_bits(iova)))
> + return -ERANGE;
> +
> + if (WARN_ON(upper_32_bits(paddr) &&
> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
> return -ERANGE;
>
> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>
> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, 2);
>
> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> unsigned long iova)
> {
> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> arm_v7s_iopte *ptep = data->pgd, pte;
> + phys_addr_t paddr;
> int lvl = 0;
> u32 mask;
>
> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> mask = ARM_V7S_LVL_MASK(lvl);
> if (arm_v7s_pte_is_cont(pte, lvl))
> mask *= ARM_V7S_CONT_PAGES;
> - return (pte & mask) | (iova & ~mask);
> + paddr = (pte & mask) | (iova & ~mask);
> +
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> + paddr |= BIT_ULL(32);
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> + paddr |= BIT_ULL(33);
> + }
> + return paddr;
> }
>
> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> index 2df7909..0eeed94 100644
> --- a/drivers/iommu/io-pgtable.h
> +++ b/drivers/iommu/io-pgtable.h
> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> * (unmapped) entries but the hardware might do so anyway, perform
> * TLB maintenance when mapping as well as when unmapping.
> *
> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> - * when the SoC is in "4GB mode" and they can only access the high
> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
> + * address bit when the SoC dram is over 4GB and they can access
> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> *
> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index c0e2da5..86bf647 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> phys_addr_t paddr, size_t size, int prot)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> int ret;
>
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + data->plat_data->has_4gb_mode &&
> + data->enable_4GB)
> + paddr |= BIT_ULL(32);
> +
> spin_lock_irqsave(&dom->pgtlock, flags);
> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> - size, prot);
> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> return ret;
> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> dma_addr_t iova)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> phys_addr_t pa;
>
> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> pa = dom->iop->iova_to_phys(dom->iop, iova);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> - if (data->enable_4GB)
> - pa |= BIT_ULL(32);
> -
> return pa;
> }
>
> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>
> static const struct mtk_iommu_plat_data mt2712_data = {
> .m4u_plat = M4U_MT2712,
> + .has_4gb_mode = true,
> };
>
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> + .has_4gb_mode = true,
> };
>
> static const struct of_device_id mtk_iommu_of_ids[] = {
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 333a0ef..a243047 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>
> struct mtk_iommu_plat_data {
> enum mtk_iommu_plat m4u_plat;
> + bool has_4gb_mode;
> };
>
> struct mtk_iommu_domain;
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-20 5:54 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-20 5:54 UTC (permalink / raw)
To: Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Rob Herring,
Daniel Kurtz, yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w,
Matthias Brugger,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi Robin,
Could you help take a look at this patch since I changed the v7s
here?
Thanks.
On Mon, 2018-09-03 at 14:01 +0800, Yong Wu wrote:
> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>
> In the mt2712 and mt8173, it's called "4GB mode", the physical address
> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> bit32 is always enabled. thus, in the M4U, we always enable the bit9
> for all PTEs which means to enable bit32 of physical address.
>
> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> 32bits.
>
> In order to unify code, in the "4GB mode", we add the bit32 for the
> physical address manually in our driver.
>
> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> has to been moved into v7s.
>
> Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> for us currently, thus we don't change it.
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> drivers/iommu/io-pgtable.h | 8 ++++----
> drivers/iommu/mtk_iommu.c | 15 +++++++++------
> drivers/iommu/mtk_iommu.h | 1 +
> 4 files changed, 44 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index b5948ba..47538dd 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -124,7 +124,9 @@
> #define ARM_V7S_TEX_MASK 0x7
> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>
> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> +/* MTK extend the two bits below for over 4GB mode */
> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>
> /* *well, except for TEX on level 2 large pages, of course :( */
> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> }
>
> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> - struct io_pgtable_cfg *cfg)
> + struct io_pgtable_cfg *cfg,
> + phys_addr_t paddr) /* Only for MTK */
> {
> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> pte |= ARM_V7S_ATTR_NS_SECTION;
>
> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> - pte |= ARM_V7S_ATTR_MTK_4GB;
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (paddr & BIT_ULL(32))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> + if (paddr & BIT_ULL(33))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> + }
>
> return pte;
> }
> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> return -EEXIST;
> }
>
> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, lvl);
>
> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> return 0;
>
> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> + if (WARN_ON(upper_32_bits(iova)))
> + return -ERANGE;
> +
> + if (WARN_ON(upper_32_bits(paddr) &&
> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
> return -ERANGE;
>
> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>
> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, 2);
>
> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> unsigned long iova)
> {
> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> arm_v7s_iopte *ptep = data->pgd, pte;
> + phys_addr_t paddr;
> int lvl = 0;
> u32 mask;
>
> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> mask = ARM_V7S_LVL_MASK(lvl);
> if (arm_v7s_pte_is_cont(pte, lvl))
> mask *= ARM_V7S_CONT_PAGES;
> - return (pte & mask) | (iova & ~mask);
> + paddr = (pte & mask) | (iova & ~mask);
> +
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> + paddr |= BIT_ULL(32);
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> + paddr |= BIT_ULL(33);
> + }
> + return paddr;
> }
>
> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> index 2df7909..0eeed94 100644
> --- a/drivers/iommu/io-pgtable.h
> +++ b/drivers/iommu/io-pgtable.h
> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> * (unmapped) entries but the hardware might do so anyway, perform
> * TLB maintenance when mapping as well as when unmapping.
> *
> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> - * when the SoC is in "4GB mode" and they can only access the high
> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
> + * address bit when the SoC dram is over 4GB and they can access
> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> *
> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index c0e2da5..86bf647 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> phys_addr_t paddr, size_t size, int prot)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> int ret;
>
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + data->plat_data->has_4gb_mode &&
> + data->enable_4GB)
> + paddr |= BIT_ULL(32);
> +
> spin_lock_irqsave(&dom->pgtlock, flags);
> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> - size, prot);
> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> return ret;
> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> dma_addr_t iova)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> phys_addr_t pa;
>
> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> pa = dom->iop->iova_to_phys(dom->iop, iova);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> - if (data->enable_4GB)
> - pa |= BIT_ULL(32);
> -
> return pa;
> }
>
> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>
> static const struct mtk_iommu_plat_data mt2712_data = {
> .m4u_plat = M4U_MT2712,
> + .has_4gb_mode = true,
> };
>
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> + .has_4gb_mode = true,
> };
>
> static const struct of_device_id mtk_iommu_of_ids[] = {
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 333a0ef..a243047 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>
> struct mtk_iommu_plat_data {
> enum mtk_iommu_plat m4u_plat;
> + bool has_4gb_mode;
> };
>
> struct mtk_iommu_domain;
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
2018-09-20 5:54 ` Yong Wu
(?)
@ 2018-09-20 11:54 ` Robin Murphy
-1 siblings, 0 replies; 61+ messages in thread
From: Robin Murphy @ 2018-09-20 11:54 UTC (permalink / raw)
To: Yong Wu
Cc: Joerg Roedel, Rob Herring, Matthias Brugger, Tomasz Figa,
Will Deacon, Daniel Kurtz, linux-mediatek, srv_heupstream,
devicetree, linux-kernel, linux-arm-kernel, iommu, arnd,
yingjoe.chen
On 20/09/18 06:54, Yong Wu wrote:
> Hi Robin,
>
> Could you help take a look at this patch since I changed the v7s
> here?
> Thanks.
Sorry, I did have a very quick skim through this series when it landed
in my inbox but I've not yet found the chance to go through it properly.
Since I am actually back doing io-pgtable stuff right now, I'll take a
look shortly.
Thanks,
Robin.
> On Mon, 2018-09-03 at 14:01 +0800, Yong Wu wrote:
>> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>>
>> In the mt2712 and mt8173, it's called "4GB mode", the physical address
>> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
>> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
>> bit32 is always enabled. thus, in the M4U, we always enable the bit9
>> for all PTEs which means to enable bit32 of physical address.
>>
>> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
>> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
>> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
>> 32bits.
>>
>> In order to unify code, in the "4GB mode", we add the bit32 for the
>> physical address manually in our driver.
>>
>> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
>> has to been moved into v7s.
>>
>> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
>> ---
>> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
>> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
>> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
>> for us currently, thus we don't change it.
>> ---
>> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
>> drivers/iommu/io-pgtable.h | 8 ++++----
>> drivers/iommu/mtk_iommu.c | 15 +++++++++------
>> drivers/iommu/mtk_iommu.h | 1 +
>> 4 files changed, 44 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
>> index b5948ba..47538dd 100644
>> --- a/drivers/iommu/io-pgtable-arm-v7s.c
>> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
>> @@ -124,7 +124,9 @@
>> #define ARM_V7S_TEX_MASK 0x7
>> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>>
>> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
>> +/* MTK extend the two bits below for over 4GB mode */
>> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
>> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>>
>> /* *well, except for TEX on level 2 large pages, of course :( */
>> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
>> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
>> }
>>
>> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
>> - struct io_pgtable_cfg *cfg)
>> + struct io_pgtable_cfg *cfg,
>> + phys_addr_t paddr) /* Only for MTK */
>> {
>> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
>> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
>> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
>> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
>> pte |= ARM_V7S_ATTR_NS_SECTION;
>>
>> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
>> - pte |= ARM_V7S_ATTR_MTK_4GB;
>> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
>> + if (paddr & BIT_ULL(32))
>> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
>> + if (paddr & BIT_ULL(33))
>> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
>> + }
>>
>> return pte;
>> }
>> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
>> return -EEXIST;
>> }
>>
>> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
>> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
>> if (num_entries > 1)
>> pte = arm_v7s_pte_to_cont(pte, lvl);
>>
>> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
>> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
>> return 0;
>>
>> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
>> + if (WARN_ON(upper_32_bits(iova)))
>> + return -ERANGE;
>> +
>> + if (WARN_ON(upper_32_bits(paddr) &&
>> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
>> return -ERANGE;
>>
>> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
>> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
>> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
>> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>>
>> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
>> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
>> if (num_entries > 1)
>> pte = arm_v7s_pte_to_cont(pte, 2);
>>
>> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
>> unsigned long iova)
>> {
>> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
>> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
>> arm_v7s_iopte *ptep = data->pgd, pte;
>> + phys_addr_t paddr;
>> int lvl = 0;
>> u32 mask;
>>
>> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
>> mask = ARM_V7S_LVL_MASK(lvl);
>> if (arm_v7s_pte_is_cont(pte, lvl))
>> mask *= ARM_V7S_CONT_PAGES;
>> - return (pte & mask) | (iova & ~mask);
>> + paddr = (pte & mask) | (iova & ~mask);
>> +
>> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
>> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
>> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
>> + paddr |= BIT_ULL(32);
>> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
>> + paddr |= BIT_ULL(33);
>> + }
>> + return paddr;
>> }
>>
>> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
>> index 2df7909..0eeed94 100644
>> --- a/drivers/iommu/io-pgtable.h
>> +++ b/drivers/iommu/io-pgtable.h
>> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
>> * (unmapped) entries but the hardware might do so anyway, perform
>> * TLB maintenance when mapping as well as when unmapping.
>> *
>> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
>> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
>> - * when the SoC is in "4GB mode" and they can only access the high
>> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
>> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
>> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
>> + * address bit when the SoC dram is over 4GB and they can access
>> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
>> *
>> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
>> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
>> index c0e2da5..86bf647 100644
>> --- a/drivers/iommu/mtk_iommu.c
>> +++ b/drivers/iommu/mtk_iommu.c
>> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
>> phys_addr_t paddr, size_t size, int prot)
>> {
>> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
>> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
>> unsigned long flags;
>> int ret;
>>
>> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
>> + data->plat_data->has_4gb_mode &&
>> + data->enable_4GB)
>> + paddr |= BIT_ULL(32);
>> +
>> spin_lock_irqsave(&dom->pgtlock, flags);
>> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
>> - size, prot);
>> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
>> spin_unlock_irqrestore(&dom->pgtlock, flags);
>>
>> return ret;
>> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
>> dma_addr_t iova)
>> {
>> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
>> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
>> unsigned long flags;
>> phys_addr_t pa;
>>
>> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
>> pa = dom->iop->iova_to_phys(dom->iop, iova);
>> spin_unlock_irqrestore(&dom->pgtlock, flags);
>>
>> - if (data->enable_4GB)
>> - pa |= BIT_ULL(32);
>> -
>> return pa;
>> }
>>
>> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>>
>> static const struct mtk_iommu_plat_data mt2712_data = {
>> .m4u_plat = M4U_MT2712,
>> + .has_4gb_mode = true,
>> };
>>
>> static const struct mtk_iommu_plat_data mt8173_data = {
>> .m4u_plat = M4U_MT8173,
>> + .has_4gb_mode = true,
>> };
>>
>> static const struct of_device_id mtk_iommu_of_ids[] = {
>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
>> index 333a0ef..a243047 100644
>> --- a/drivers/iommu/mtk_iommu.h
>> +++ b/drivers/iommu/mtk_iommu.h
>> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>>
>> struct mtk_iommu_plat_data {
>> enum mtk_iommu_plat m4u_plat;
>> + bool has_4gb_mode;
>> };
>>
>> struct mtk_iommu_domain;
>
>
^ permalink raw reply [flat|nested] 61+ messages in thread* [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-20 11:54 ` Robin Murphy
0 siblings, 0 replies; 61+ messages in thread
From: Robin Murphy @ 2018-09-20 11:54 UTC (permalink / raw)
To: linux-arm-kernel
On 20/09/18 06:54, Yong Wu wrote:
> Hi Robin,
>
> Could you help take a look at this patch since I changed the v7s
> here?
> Thanks.
Sorry, I did have a very quick skim through this series when it landed
in my inbox but I've not yet found the chance to go through it properly.
Since I am actually back doing io-pgtable stuff right now, I'll take a
look shortly.
Thanks,
Robin.
> On Mon, 2018-09-03 at 14:01 +0800, Yong Wu wrote:
>> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>>
>> In the mt2712 and mt8173, it's called "4GB mode", the physical address
>> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
>> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
>> bit32 is always enabled. thus, in the M4U, we always enable the bit9
>> for all PTEs which means to enable bit32 of physical address.
>>
>> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
>> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
>> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
>> 32bits.
>>
>> In order to unify code, in the "4GB mode", we add the bit32 for the
>> physical address manually in our driver.
>>
>> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
>> has to been moved into v7s.
>>
>> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
>> ---
>> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
>> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
>> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
>> for us currently, thus we don't change it.
>> ---
>> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
>> drivers/iommu/io-pgtable.h | 8 ++++----
>> drivers/iommu/mtk_iommu.c | 15 +++++++++------
>> drivers/iommu/mtk_iommu.h | 1 +
>> 4 files changed, 44 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
>> index b5948ba..47538dd 100644
>> --- a/drivers/iommu/io-pgtable-arm-v7s.c
>> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
>> @@ -124,7 +124,9 @@
>> #define ARM_V7S_TEX_MASK 0x7
>> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>>
>> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
>> +/* MTK extend the two bits below for over 4GB mode */
>> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
>> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>>
>> /* *well, except for TEX on level 2 large pages, of course :( */
>> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
>> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
>> }
>>
>> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
>> - struct io_pgtable_cfg *cfg)
>> + struct io_pgtable_cfg *cfg,
>> + phys_addr_t paddr) /* Only for MTK */
>> {
>> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
>> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
>> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
>> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
>> pte |= ARM_V7S_ATTR_NS_SECTION;
>>
>> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
>> - pte |= ARM_V7S_ATTR_MTK_4GB;
>> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
>> + if (paddr & BIT_ULL(32))
>> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
>> + if (paddr & BIT_ULL(33))
>> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
>> + }
>>
>> return pte;
>> }
>> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
>> return -EEXIST;
>> }
>>
>> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
>> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
>> if (num_entries > 1)
>> pte = arm_v7s_pte_to_cont(pte, lvl);
>>
>> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
>> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
>> return 0;
>>
>> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
>> + if (WARN_ON(upper_32_bits(iova)))
>> + return -ERANGE;
>> +
>> + if (WARN_ON(upper_32_bits(paddr) &&
>> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
>> return -ERANGE;
>>
>> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
>> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
>> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
>> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>>
>> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
>> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
>> if (num_entries > 1)
>> pte = arm_v7s_pte_to_cont(pte, 2);
>>
>> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
>> unsigned long iova)
>> {
>> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
>> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
>> arm_v7s_iopte *ptep = data->pgd, pte;
>> + phys_addr_t paddr;
>> int lvl = 0;
>> u32 mask;
>>
>> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
>> mask = ARM_V7S_LVL_MASK(lvl);
>> if (arm_v7s_pte_is_cont(pte, lvl))
>> mask *= ARM_V7S_CONT_PAGES;
>> - return (pte & mask) | (iova & ~mask);
>> + paddr = (pte & mask) | (iova & ~mask);
>> +
>> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
>> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
>> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
>> + paddr |= BIT_ULL(32);
>> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
>> + paddr |= BIT_ULL(33);
>> + }
>> + return paddr;
>> }
>>
>> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
>> index 2df7909..0eeed94 100644
>> --- a/drivers/iommu/io-pgtable.h
>> +++ b/drivers/iommu/io-pgtable.h
>> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
>> * (unmapped) entries but the hardware might do so anyway, perform
>> * TLB maintenance when mapping as well as when unmapping.
>> *
>> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
>> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
>> - * when the SoC is in "4GB mode" and they can only access the high
>> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
>> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
>> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
>> + * address bit when the SoC dram is over 4GB and they can access
>> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
>> *
>> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
>> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
>> index c0e2da5..86bf647 100644
>> --- a/drivers/iommu/mtk_iommu.c
>> +++ b/drivers/iommu/mtk_iommu.c
>> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
>> phys_addr_t paddr, size_t size, int prot)
>> {
>> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
>> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
>> unsigned long flags;
>> int ret;
>>
>> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
>> + data->plat_data->has_4gb_mode &&
>> + data->enable_4GB)
>> + paddr |= BIT_ULL(32);
>> +
>> spin_lock_irqsave(&dom->pgtlock, flags);
>> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
>> - size, prot);
>> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
>> spin_unlock_irqrestore(&dom->pgtlock, flags);
>>
>> return ret;
>> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
>> dma_addr_t iova)
>> {
>> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
>> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
>> unsigned long flags;
>> phys_addr_t pa;
>>
>> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
>> pa = dom->iop->iova_to_phys(dom->iop, iova);
>> spin_unlock_irqrestore(&dom->pgtlock, flags);
>>
>> - if (data->enable_4GB)
>> - pa |= BIT_ULL(32);
>> -
>> return pa;
>> }
>>
>> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>>
>> static const struct mtk_iommu_plat_data mt2712_data = {
>> .m4u_plat = M4U_MT2712,
>> + .has_4gb_mode = true,
>> };
>>
>> static const struct mtk_iommu_plat_data mt8173_data = {
>> .m4u_plat = M4U_MT8173,
>> + .has_4gb_mode = true,
>> };
>>
>> static const struct of_device_id mtk_iommu_of_ids[] = {
>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
>> index 333a0ef..a243047 100644
>> --- a/drivers/iommu/mtk_iommu.h
>> +++ b/drivers/iommu/mtk_iommu.h
>> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>>
>> struct mtk_iommu_plat_data {
>> enum mtk_iommu_plat m4u_plat;
>> + bool has_4gb_mode;
>> };
>>
>> struct mtk_iommu_domain;
>
>
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-20 11:54 ` Robin Murphy
0 siblings, 0 replies; 61+ messages in thread
From: Robin Murphy @ 2018-09-20 11:54 UTC (permalink / raw)
To: Yong Wu
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Rob Herring,
Daniel Kurtz, yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w,
Matthias Brugger,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 20/09/18 06:54, Yong Wu wrote:
> Hi Robin,
>
> Could you help take a look at this patch since I changed the v7s
> here?
> Thanks.
Sorry, I did have a very quick skim through this series when it landed
in my inbox but I've not yet found the chance to go through it properly.
Since I am actually back doing io-pgtable stuff right now, I'll take a
look shortly.
Thanks,
Robin.
> On Mon, 2018-09-03 at 14:01 +0800, Yong Wu wrote:
>> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>>
>> In the mt2712 and mt8173, it's called "4GB mode", the physical address
>> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
>> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
>> bit32 is always enabled. thus, in the M4U, we always enable the bit9
>> for all PTEs which means to enable bit32 of physical address.
>>
>> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
>> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
>> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
>> 32bits.
>>
>> In order to unify code, in the "4GB mode", we add the bit32 for the
>> physical address manually in our driver.
>>
>> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
>> has to been moved into v7s.
>>
>> Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>> ---
>> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
>> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
>> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
>> for us currently, thus we don't change it.
>> ---
>> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
>> drivers/iommu/io-pgtable.h | 8 ++++----
>> drivers/iommu/mtk_iommu.c | 15 +++++++++------
>> drivers/iommu/mtk_iommu.h | 1 +
>> 4 files changed, 44 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
>> index b5948ba..47538dd 100644
>> --- a/drivers/iommu/io-pgtable-arm-v7s.c
>> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
>> @@ -124,7 +124,9 @@
>> #define ARM_V7S_TEX_MASK 0x7
>> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>>
>> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
>> +/* MTK extend the two bits below for over 4GB mode */
>> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
>> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>>
>> /* *well, except for TEX on level 2 large pages, of course :( */
>> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
>> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
>> }
>>
>> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
>> - struct io_pgtable_cfg *cfg)
>> + struct io_pgtable_cfg *cfg,
>> + phys_addr_t paddr) /* Only for MTK */
>> {
>> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
>> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
>> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
>> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
>> pte |= ARM_V7S_ATTR_NS_SECTION;
>>
>> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
>> - pte |= ARM_V7S_ATTR_MTK_4GB;
>> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
>> + if (paddr & BIT_ULL(32))
>> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
>> + if (paddr & BIT_ULL(33))
>> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
>> + }
>>
>> return pte;
>> }
>> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
>> return -EEXIST;
>> }
>>
>> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
>> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
>> if (num_entries > 1)
>> pte = arm_v7s_pte_to_cont(pte, lvl);
>>
>> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
>> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
>> return 0;
>>
>> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
>> + if (WARN_ON(upper_32_bits(iova)))
>> + return -ERANGE;
>> +
>> + if (WARN_ON(upper_32_bits(paddr) &&
>> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
>> return -ERANGE;
>>
>> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
>> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
>> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
>> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>>
>> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
>> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
>> if (num_entries > 1)
>> pte = arm_v7s_pte_to_cont(pte, 2);
>>
>> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
>> unsigned long iova)
>> {
>> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
>> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
>> arm_v7s_iopte *ptep = data->pgd, pte;
>> + phys_addr_t paddr;
>> int lvl = 0;
>> u32 mask;
>>
>> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
>> mask = ARM_V7S_LVL_MASK(lvl);
>> if (arm_v7s_pte_is_cont(pte, lvl))
>> mask *= ARM_V7S_CONT_PAGES;
>> - return (pte & mask) | (iova & ~mask);
>> + paddr = (pte & mask) | (iova & ~mask);
>> +
>> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
>> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
>> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
>> + paddr |= BIT_ULL(32);
>> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
>> + paddr |= BIT_ULL(33);
>> + }
>> + return paddr;
>> }
>>
>> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
>> index 2df7909..0eeed94 100644
>> --- a/drivers/iommu/io-pgtable.h
>> +++ b/drivers/iommu/io-pgtable.h
>> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
>> * (unmapped) entries but the hardware might do so anyway, perform
>> * TLB maintenance when mapping as well as when unmapping.
>> *
>> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
>> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
>> - * when the SoC is in "4GB mode" and they can only access the high
>> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
>> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
>> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
>> + * address bit when the SoC dram is over 4GB and they can access
>> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
>> *
>> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
>> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
>> index c0e2da5..86bf647 100644
>> --- a/drivers/iommu/mtk_iommu.c
>> +++ b/drivers/iommu/mtk_iommu.c
>> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
>> phys_addr_t paddr, size_t size, int prot)
>> {
>> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
>> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
>> unsigned long flags;
>> int ret;
>>
>> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
>> + data->plat_data->has_4gb_mode &&
>> + data->enable_4GB)
>> + paddr |= BIT_ULL(32);
>> +
>> spin_lock_irqsave(&dom->pgtlock, flags);
>> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
>> - size, prot);
>> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
>> spin_unlock_irqrestore(&dom->pgtlock, flags);
>>
>> return ret;
>> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
>> dma_addr_t iova)
>> {
>> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
>> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
>> unsigned long flags;
>> phys_addr_t pa;
>>
>> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
>> pa = dom->iop->iova_to_phys(dom->iop, iova);
>> spin_unlock_irqrestore(&dom->pgtlock, flags);
>>
>> - if (data->enable_4GB)
>> - pa |= BIT_ULL(32);
>> -
>> return pa;
>> }
>>
>> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>>
>> static const struct mtk_iommu_plat_data mt2712_data = {
>> .m4u_plat = M4U_MT2712,
>> + .has_4gb_mode = true,
>> };
>>
>> static const struct mtk_iommu_plat_data mt8173_data = {
>> .m4u_plat = M4U_MT8173,
>> + .has_4gb_mode = true,
>> };
>>
>> static const struct of_device_id mtk_iommu_of_ids[] = {
>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
>> index 333a0ef..a243047 100644
>> --- a/drivers/iommu/mtk_iommu.h
>> +++ b/drivers/iommu/mtk_iommu.h
>> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>>
>> struct mtk_iommu_plat_data {
>> enum mtk_iommu_plat m4u_plat;
>> + bool has_4gb_mode;
>> };
>>
>> struct mtk_iommu_domain;
>
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-20 17:31 ` Robin Murphy
0 siblings, 0 replies; 61+ messages in thread
From: Robin Murphy @ 2018-09-20 17:31 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen
On 03/09/18 07:01, Yong Wu wrote:
> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>
> In the mt2712 and mt8173, it's called "4GB mode", the physical address
> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> bit32 is always enabled. thus, in the M4U, we always enable the bit9
> for all PTEs which means to enable bit32 of physical address.
>
> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> 32bits.
>
> In order to unify code, in the "4GB mode", we add the bit32 for the
> physical address manually in our driver.
>
> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> has to been moved into v7s.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> for us currently, thus we don't change it.
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> drivers/iommu/io-pgtable.h | 8 ++++----
> drivers/iommu/mtk_iommu.c | 15 +++++++++------
> drivers/iommu/mtk_iommu.h | 1 +
> 4 files changed, 44 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index b5948ba..47538dd 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -124,7 +124,9 @@
> #define ARM_V7S_TEX_MASK 0x7
> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>
> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> +/* MTK extend the two bits below for over 4GB mode */
> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>
> /* *well, except for TEX on level 2 large pages, of course :( */
> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> }
>
> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> - struct io_pgtable_cfg *cfg)
> + struct io_pgtable_cfg *cfg,
> + phys_addr_t paddr) /* Only for MTK */
I'd rather keep this function dedicated to just generating the
permissions and attributes. If necessary I'm quite happy to add
additional helpers for getting/setting the address, much like LPAE now
has for handling 52-bit IOVAs.
> {
> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> pte |= ARM_V7S_ATTR_NS_SECTION;
>
> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> - pte |= ARM_V7S_ATTR_MTK_4GB;
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (paddr & BIT_ULL(32))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> + if (paddr & BIT_ULL(33))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> + }
>
> return pte;
> }
> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> return -EEXIST;
> }
>
> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, lvl);
>
> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> return 0;
>
> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> + if (WARN_ON(upper_32_bits(iova)))
> + return -ERANGE;
> +
> + if (WARN_ON(upper_32_bits(paddr) &&
> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
TBH I'd just cram the quirk check into the right-hand-side of the ||
rather than introduce a separate if() - there's already too many
parentheses to read the whole thing easily ;)
> return -ERANGE;
>
> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>
> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, 2);
>
> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> unsigned long iova)
> {
> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> arm_v7s_iopte *ptep = data->pgd, pte;
> + phys_addr_t paddr;
> int lvl = 0;
> u32 mask;
>
> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> mask = ARM_V7S_LVL_MASK(lvl);
> if (arm_v7s_pte_is_cont(pte, lvl))
> mask *= ARM_V7S_CONT_PAGES;
> - return (pte & mask) | (iova & ~mask);
> + paddr = (pte & mask) | (iova & ~mask);
> +
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> + paddr |= BIT_ULL(32);
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> + paddr |= BIT_ULL(33);
> + }
> + return paddr;
> }
>
> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> index 2df7909..0eeed94 100644
> --- a/drivers/iommu/io-pgtable.h
> +++ b/drivers/iommu/io-pgtable.h
> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> * (unmapped) entries but the hardware might do so anyway, perform
> * TLB maintenance when mapping as well as when unmapping.
> *
> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> - * when the SoC is in "4GB mode" and they can only access the high
> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
The "all PTEs" part referred to the fact that io-pgtable was forcing bit
9 on unconditionally. Since that logic is now moving into the MTK driver
itself, all the quirk means now from io-pgtable's point of view is that
PAs may be up to 34 bits where bits 32 and 33 of the address are encoded
in bits 9 and 4 of the PTE respectively...
> + * address bit when the SoC dram is over 4GB and they can access
> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> *
> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index c0e2da5..86bf647 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> phys_addr_t paddr, size_t size, int prot)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> int ret;
>
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + data->plat_data->has_4gb_mode &&
> + data->enable_4GB)
> + paddr |= BIT_ULL(32);
...so it might be worth moving the rationale part of the current quirk
comment (i.e. that the "4GB mode" IOMMUs physically cannot use the lower
remap of RAM) to here where it now applies.
Robin.
> +
> spin_lock_irqsave(&dom->pgtlock, flags);
> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> - size, prot);
> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> return ret;
> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> dma_addr_t iova)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> phys_addr_t pa;
>
> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> pa = dom->iop->iova_to_phys(dom->iop, iova);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> - if (data->enable_4GB)
> - pa |= BIT_ULL(32);
> -
> return pa;
> }
>
> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>
> static const struct mtk_iommu_plat_data mt2712_data = {
> .m4u_plat = M4U_MT2712,
> + .has_4gb_mode = true,
> };
>
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> + .has_4gb_mode = true,
> };
>
> static const struct of_device_id mtk_iommu_of_ids[] = {
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 333a0ef..a243047 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>
> struct mtk_iommu_plat_data {
> enum mtk_iommu_plat m4u_plat;
> + bool has_4gb_mode;
> };
>
> struct mtk_iommu_domain;
>
^ permalink raw reply [flat|nested] 61+ messages in thread* [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-20 17:31 ` Robin Murphy
0 siblings, 0 replies; 61+ messages in thread
From: Robin Murphy @ 2018-09-20 17:31 UTC (permalink / raw)
To: linux-arm-kernel
On 03/09/18 07:01, Yong Wu wrote:
> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>
> In the mt2712 and mt8173, it's called "4GB mode", the physical address
> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> bit32 is always enabled. thus, in the M4U, we always enable the bit9
> for all PTEs which means to enable bit32 of physical address.
>
> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> 32bits.
>
> In order to unify code, in the "4GB mode", we add the bit32 for the
> physical address manually in our driver.
>
> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> has to been moved into v7s.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> for us currently, thus we don't change it.
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> drivers/iommu/io-pgtable.h | 8 ++++----
> drivers/iommu/mtk_iommu.c | 15 +++++++++------
> drivers/iommu/mtk_iommu.h | 1 +
> 4 files changed, 44 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index b5948ba..47538dd 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -124,7 +124,9 @@
> #define ARM_V7S_TEX_MASK 0x7
> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>
> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> +/* MTK extend the two bits below for over 4GB mode */
> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>
> /* *well, except for TEX on level 2 large pages, of course :( */
> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> }
>
> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> - struct io_pgtable_cfg *cfg)
> + struct io_pgtable_cfg *cfg,
> + phys_addr_t paddr) /* Only for MTK */
I'd rather keep this function dedicated to just generating the
permissions and attributes. If necessary I'm quite happy to add
additional helpers for getting/setting the address, much like LPAE now
has for handling 52-bit IOVAs.
> {
> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> pte |= ARM_V7S_ATTR_NS_SECTION;
>
> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> - pte |= ARM_V7S_ATTR_MTK_4GB;
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (paddr & BIT_ULL(32))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> + if (paddr & BIT_ULL(33))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> + }
>
> return pte;
> }
> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> return -EEXIST;
> }
>
> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, lvl);
>
> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> return 0;
>
> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> + if (WARN_ON(upper_32_bits(iova)))
> + return -ERANGE;
> +
> + if (WARN_ON(upper_32_bits(paddr) &&
> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
TBH I'd just cram the quirk check into the right-hand-side of the ||
rather than introduce a separate if() - there's already too many
parentheses to read the whole thing easily ;)
> return -ERANGE;
>
> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>
> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, 2);
>
> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> unsigned long iova)
> {
> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> arm_v7s_iopte *ptep = data->pgd, pte;
> + phys_addr_t paddr;
> int lvl = 0;
> u32 mask;
>
> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> mask = ARM_V7S_LVL_MASK(lvl);
> if (arm_v7s_pte_is_cont(pte, lvl))
> mask *= ARM_V7S_CONT_PAGES;
> - return (pte & mask) | (iova & ~mask);
> + paddr = (pte & mask) | (iova & ~mask);
> +
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> + paddr |= BIT_ULL(32);
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> + paddr |= BIT_ULL(33);
> + }
> + return paddr;
> }
>
> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> index 2df7909..0eeed94 100644
> --- a/drivers/iommu/io-pgtable.h
> +++ b/drivers/iommu/io-pgtable.h
> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> * (unmapped) entries but the hardware might do so anyway, perform
> * TLB maintenance when mapping as well as when unmapping.
> *
> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> - * when the SoC is in "4GB mode" and they can only access the high
> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
The "all PTEs" part referred to the fact that io-pgtable was forcing bit
9 on unconditionally. Since that logic is now moving into the MTK driver
itself, all the quirk means now from io-pgtable's point of view is that
PAs may be up to 34 bits where bits 32 and 33 of the address are encoded
in bits 9 and 4 of the PTE respectively...
> + * address bit when the SoC dram is over 4GB and they can access
> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> *
> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index c0e2da5..86bf647 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> phys_addr_t paddr, size_t size, int prot)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> int ret;
>
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + data->plat_data->has_4gb_mode &&
> + data->enable_4GB)
> + paddr |= BIT_ULL(32);
...so it might be worth moving the rationale part of the current quirk
comment (i.e. that the "4GB mode" IOMMUs physically cannot use the lower
remap of RAM) to here where it now applies.
Robin.
> +
> spin_lock_irqsave(&dom->pgtlock, flags);
> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> - size, prot);
> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> return ret;
> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> dma_addr_t iova)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> phys_addr_t pa;
>
> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> pa = dom->iop->iova_to_phys(dom->iop, iova);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> - if (data->enable_4GB)
> - pa |= BIT_ULL(32);
> -
> return pa;
> }
>
> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>
> static const struct mtk_iommu_plat_data mt2712_data = {
> .m4u_plat = M4U_MT2712,
> + .has_4gb_mode = true,
> };
>
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> + .has_4gb_mode = true,
> };
>
> static const struct of_device_id mtk_iommu_of_ids[] = {
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 333a0ef..a243047 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>
> struct mtk_iommu_plat_data {
> enum mtk_iommu_plat m4u_plat;
> + bool has_4gb_mode;
> };
>
> struct mtk_iommu_domain;
>
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-20 17:31 ` Robin Murphy
0 siblings, 0 replies; 61+ messages in thread
From: Robin Murphy @ 2018-09-20 17:31 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Rob Herring, Matthias Brugger
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 03/09/18 07:01, Yong Wu wrote:
> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>
> In the mt2712 and mt8173, it's called "4GB mode", the physical address
> is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> bit32 is always enabled. thus, in the M4U, we always enable the bit9
> for all PTEs which means to enable bit32 of physical address.
>
> but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> 32bits.
>
> In order to unify code, in the "4GB mode", we add the bit32 for the
> physical address manually in our driver.
>
> Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> has to been moved into v7s.
>
> Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> for us currently, thus we don't change it.
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> drivers/iommu/io-pgtable.h | 8 ++++----
> drivers/iommu/mtk_iommu.c | 15 +++++++++------
> drivers/iommu/mtk_iommu.h | 1 +
> 4 files changed, 44 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index b5948ba..47538dd 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -124,7 +124,9 @@
> #define ARM_V7S_TEX_MASK 0x7
> #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
>
> -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> +/* MTK extend the two bits below for over 4GB mode */
> +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
>
> /* *well, except for TEX on level 2 large pages, of course :( */
> #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> }
>
> static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> - struct io_pgtable_cfg *cfg)
> + struct io_pgtable_cfg *cfg,
> + phys_addr_t paddr) /* Only for MTK */
I'd rather keep this function dedicated to just generating the
permissions and attributes. If necessary I'm quite happy to add
additional helpers for getting/setting the address, much like LPAE now
has for handling 52-bit IOVAs.
> {
> bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> pte |= ARM_V7S_ATTR_NS_SECTION;
>
> - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> - pte |= ARM_V7S_ATTR_MTK_4GB;
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (paddr & BIT_ULL(32))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> + if (paddr & BIT_ULL(33))
> + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> + }
>
> return pte;
> }
> @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> return -EEXIST;
> }
>
> - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, lvl);
>
> @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> return 0;
>
> - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> + if (WARN_ON(upper_32_bits(iova)))
> + return -ERANGE;
> +
> + if (WARN_ON(upper_32_bits(paddr) &&
> + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
TBH I'd just cram the quirk check into the right-hand-side of the ||
rather than introduce a separate if() - there's already too many
parentheses to read the whole thing easily ;)
> return -ERANGE;
>
> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
>
> - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> if (num_entries > 1)
> pte = arm_v7s_pte_to_cont(pte, 2);
>
> @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> unsigned long iova)
> {
> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> arm_v7s_iopte *ptep = data->pgd, pte;
> + phys_addr_t paddr;
> int lvl = 0;
> u32 mask;
>
> @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> mask = ARM_V7S_LVL_MASK(lvl);
> if (arm_v7s_pte_is_cont(pte, lvl))
> mask *= ARM_V7S_CONT_PAGES;
> - return (pte & mask) | (iova & ~mask);
> + paddr = (pte & mask) | (iova & ~mask);
> +
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> + paddr |= BIT_ULL(32);
> + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> + paddr |= BIT_ULL(33);
> + }
> + return paddr;
> }
>
> static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> index 2df7909..0eeed94 100644
> --- a/drivers/iommu/io-pgtable.h
> +++ b/drivers/iommu/io-pgtable.h
> @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> * (unmapped) entries but the hardware might do so anyway, perform
> * TLB maintenance when mapping as well as when unmapping.
> *
> - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> - * when the SoC is in "4GB mode" and they can only access the high
> - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
The "all PTEs" part referred to the fact that io-pgtable was forcing bit
9 on unconditionally. Since that logic is now moving into the MTK driver
itself, all the quirk means now from io-pgtable's point of view is that
PAs may be up to 34 bits where bits 32 and 33 of the address are encoded
in bits 9 and 4 of the PTE respectively...
> + * address bit when the SoC dram is over 4GB and they can access
> + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> *
> * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index c0e2da5..86bf647 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> phys_addr_t paddr, size_t size, int prot)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> int ret;
>
> + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> + data->plat_data->has_4gb_mode &&
> + data->enable_4GB)
> + paddr |= BIT_ULL(32);
...so it might be worth moving the rationale part of the current quirk
comment (i.e. that the "4GB mode" IOMMUs physically cannot use the lower
remap of RAM) to here where it now applies.
Robin.
> +
> spin_lock_irqsave(&dom->pgtlock, flags);
> - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> - size, prot);
> + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> return ret;
> @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> dma_addr_t iova)
> {
> struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> unsigned long flags;
> phys_addr_t pa;
>
> @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> pa = dom->iop->iova_to_phys(dom->iop, iova);
> spin_unlock_irqrestore(&dom->pgtlock, flags);
>
> - if (data->enable_4GB)
> - pa |= BIT_ULL(32);
> -
> return pa;
> }
>
> @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>
> static const struct mtk_iommu_plat_data mt2712_data = {
> .m4u_plat = M4U_MT2712,
> + .has_4gb_mode = true,
> };
>
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> + .has_4gb_mode = true,
> };
>
> static const struct of_device_id mtk_iommu_of_ids[] = {
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 333a0ef..a243047 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
>
> struct mtk_iommu_plat_data {
> enum mtk_iommu_plat m4u_plat;
> + bool has_4gb_mode;
> };
>
> struct mtk_iommu_domain;
>
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
2018-09-20 17:31 ` Robin Murphy
(?)
@ 2018-09-24 9:26 ` Yong Wu
-1 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-24 9:26 UTC (permalink / raw)
To: Robin Murphy
Cc: Joerg Roedel, Rob Herring, Matthias Brugger, Tomasz Figa,
Will Deacon, Daniel Kurtz, linux-mediatek, srv_heupstream,
devicetree, linux-kernel, linux-arm-kernel, iommu, arnd,
yingjoe.chen
On Thu, 2018-09-20 at 18:31 +0100, Robin Murphy wrote:
> On 03/09/18 07:01, Yong Wu wrote:
> > MediaTek extend the arm v7s descriptor to support the dram over 4GB.
> >
> > In the mt2712 and mt8173, it's called "4GB mode", the physical address
> > is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> > is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> > bit32 is always enabled. thus, in the M4U, we always enable the bit9
> > for all PTEs which means to enable bit32 of physical address.
> >
> > but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> > which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> > PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> > 32bits.
> >
> > In order to unify code, in the "4GB mode", we add the bit32 for the
> > physical address manually in our driver.
> >
> > Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> > has to been moved into v7s.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> > still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> > the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> > for us currently, thus we don't change it.
> > ---
> > drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> > drivers/iommu/io-pgtable.h | 8 ++++----
> > drivers/iommu/mtk_iommu.c | 15 +++++++++------
> > drivers/iommu/mtk_iommu.h | 1 +
> > 4 files changed, 44 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index b5948ba..47538dd 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -124,7 +124,9 @@
> > #define ARM_V7S_TEX_MASK 0x7
> > #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
> >
> > -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> > +/* MTK extend the two bits below for over 4GB mode */
> > +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> > +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
> >
> > /* *well, except for TEX on level 2 large pages, of course :( */
> > #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> > @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> > }
> >
> > static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> > - struct io_pgtable_cfg *cfg)
> > + struct io_pgtable_cfg *cfg,
> > + phys_addr_t paddr) /* Only for MTK */
>
> I'd rather keep this function dedicated to just generating the
> permissions and attributes. If necessary I'm quite happy to add
> additional helpers for getting/setting the address, much like LPAE now
> has for handling 52-bit IOVAs.
Adding the two additional helpers looks need touch many lines. thus, I
use a new patch for it.
Thanks very much for your review.
>
> > {
> > bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> > arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> > @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> > if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> > pte |= ARM_V7S_ATTR_NS_SECTION;
> >
> > - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> > - pte |= ARM_V7S_ATTR_MTK_4GB;
> > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> > + if (paddr & BIT_ULL(32))
> > + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> > + if (paddr & BIT_ULL(33))
> > + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> > + }
> >
> > return pte;
> > }
> > @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> > return -EEXIST;
> > }
> >
> > - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> > + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> > if (num_entries > 1)
> > pte = arm_v7s_pte_to_cont(pte, lvl);
> >
> > @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> > if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> > return 0;
> >
> > - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> > + if (WARN_ON(upper_32_bits(iova)))
> > + return -ERANGE;
> > +
> > + if (WARN_ON(upper_32_bits(paddr) &&
> > + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
>
> TBH I'd just cram the quirk check into the right-hand-side of the ||
> rather than introduce a separate if() - there's already too many
> parentheses to read the whole thing easily ;)
Fix it in v2.
Also, the comments below are fixed.
Thanks.
>
> > return -ERANGE;
> >
> > ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> > @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> > num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> > unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
> >
> > - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> > + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> > if (num_entries > 1)
> > pte = arm_v7s_pte_to_cont(pte, 2);
> >
> > @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> > unsigned long iova)
> > {
> > struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> > + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> > arm_v7s_iopte *ptep = data->pgd, pte;
> > + phys_addr_t paddr;
> > int lvl = 0;
> > u32 mask;
> >
> > @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> > mask = ARM_V7S_LVL_MASK(lvl);
> > if (arm_v7s_pte_is_cont(pte, lvl))
> > mask *= ARM_V7S_CONT_PAGES;
> > - return (pte & mask) | (iova & ~mask);
> > + paddr = (pte & mask) | (iova & ~mask);
> > +
> > + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> > + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> > + paddr |= BIT_ULL(32);
> > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> > + paddr |= BIT_ULL(33);
> > + }
> > + return paddr;
> > }
> >
> > static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> > diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> > index 2df7909..0eeed94 100644
> > --- a/drivers/iommu/io-pgtable.h
> > +++ b/drivers/iommu/io-pgtable.h
> > @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> > * (unmapped) entries but the hardware might do so anyway, perform
> > * TLB maintenance when mapping as well as when unmapping.
> > *
> > - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> > - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> > - * when the SoC is in "4GB mode" and they can only access the high
> > - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> > + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> > + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
>
> The "all PTEs" part referred to the fact that io-pgtable was forcing bit
> 9 on unconditionally. Since that logic is now moving into the MTK driver
> itself, all the quirk means now from io-pgtable's point of view is that
> PAs may be up to 34 bits where bits 32 and 33 of the address are encoded
> in bits 9 and 4 of the PTE respectively...
>
> > + * address bit when the SoC dram is over 4GB and they can access
> > + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> > *
> > * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> > * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index c0e2da5..86bf647 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> > phys_addr_t paddr, size_t size, int prot)
> > {
> > struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> > + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> > unsigned long flags;
> > int ret;
> >
> > + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> > + data->plat_data->has_4gb_mode &&
> > + data->enable_4GB)
> > + paddr |= BIT_ULL(32);
>
> ...so it might be worth moving the rationale part of the current quirk
> comment (i.e. that the "4GB mode" IOMMUs physically cannot use the lower
> remap of RAM) to here where it now applies.
>
> Robin.
>
> > +
> > spin_lock_irqsave(&dom->pgtlock, flags);
> > - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> > - size, prot);
> > + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> > spin_unlock_irqrestore(&dom->pgtlock, flags);
> >
> > return ret;
> > @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> > dma_addr_t iova)
> > {
> > struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> > - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> > unsigned long flags;
> > phys_addr_t pa;
> >
> > @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> > pa = dom->iop->iova_to_phys(dom->iop, iova);
> > spin_unlock_irqrestore(&dom->pgtlock, flags);
> >
> > - if (data->enable_4GB)
> > - pa |= BIT_ULL(32);
> > -
> > return pa;
> > }
> >
> > @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
> >
> > static const struct mtk_iommu_plat_data mt2712_data = {
> > .m4u_plat = M4U_MT2712,
> > + .has_4gb_mode = true,
> > };
> >
> > static const struct mtk_iommu_plat_data mt8173_data = {
> > .m4u_plat = M4U_MT8173,
> > + .has_4gb_mode = true,
> > };
> >
> > static const struct of_device_id mtk_iommu_of_ids[] = {
> > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> > index 333a0ef..a243047 100644
> > --- a/drivers/iommu/mtk_iommu.h
> > +++ b/drivers/iommu/mtk_iommu.h
> > @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
> >
> > struct mtk_iommu_plat_data {
> > enum mtk_iommu_plat m4u_plat;
> > + bool has_4gb_mode;
> > };
> >
> > struct mtk_iommu_domain;
> >
^ permalink raw reply [flat|nested] 61+ messages in thread* [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-24 9:26 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-24 9:26 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2018-09-20 at 18:31 +0100, Robin Murphy wrote:
> On 03/09/18 07:01, Yong Wu wrote:
> > MediaTek extend the arm v7s descriptor to support the dram over 4GB.
> >
> > In the mt2712 and mt8173, it's called "4GB mode", the physical address
> > is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> > is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> > bit32 is always enabled. thus, in the M4U, we always enable the bit9
> > for all PTEs which means to enable bit32 of physical address.
> >
> > but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> > which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> > PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> > 32bits.
> >
> > In order to unify code, in the "4GB mode", we add the bit32 for the
> > physical address manually in our driver.
> >
> > Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> > has to been moved into v7s.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> > still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> > the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> > for us currently, thus we don't change it.
> > ---
> > drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> > drivers/iommu/io-pgtable.h | 8 ++++----
> > drivers/iommu/mtk_iommu.c | 15 +++++++++------
> > drivers/iommu/mtk_iommu.h | 1 +
> > 4 files changed, 44 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index b5948ba..47538dd 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -124,7 +124,9 @@
> > #define ARM_V7S_TEX_MASK 0x7
> > #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
> >
> > -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> > +/* MTK extend the two bits below for over 4GB mode */
> > +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> > +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
> >
> > /* *well, except for TEX on level 2 large pages, of course :( */
> > #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> > @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> > }
> >
> > static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> > - struct io_pgtable_cfg *cfg)
> > + struct io_pgtable_cfg *cfg,
> > + phys_addr_t paddr) /* Only for MTK */
>
> I'd rather keep this function dedicated to just generating the
> permissions and attributes. If necessary I'm quite happy to add
> additional helpers for getting/setting the address, much like LPAE now
> has for handling 52-bit IOVAs.
Adding the two additional helpers looks need touch many lines. thus, I
use a new patch for it.
Thanks very much for your review.
>
> > {
> > bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> > arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> > @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> > if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> > pte |= ARM_V7S_ATTR_NS_SECTION;
> >
> > - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> > - pte |= ARM_V7S_ATTR_MTK_4GB;
> > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> > + if (paddr & BIT_ULL(32))
> > + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> > + if (paddr & BIT_ULL(33))
> > + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> > + }
> >
> > return pte;
> > }
> > @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> > return -EEXIST;
> > }
> >
> > - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> > + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> > if (num_entries > 1)
> > pte = arm_v7s_pte_to_cont(pte, lvl);
> >
> > @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> > if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> > return 0;
> >
> > - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> > + if (WARN_ON(upper_32_bits(iova)))
> > + return -ERANGE;
> > +
> > + if (WARN_ON(upper_32_bits(paddr) &&
> > + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
>
> TBH I'd just cram the quirk check into the right-hand-side of the ||
> rather than introduce a separate if() - there's already too many
> parentheses to read the whole thing easily ;)
Fix it in v2.
Also, the comments below are fixed.
Thanks.
>
> > return -ERANGE;
> >
> > ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> > @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> > num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> > unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
> >
> > - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> > + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> > if (num_entries > 1)
> > pte = arm_v7s_pte_to_cont(pte, 2);
> >
> > @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> > unsigned long iova)
> > {
> > struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> > + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> > arm_v7s_iopte *ptep = data->pgd, pte;
> > + phys_addr_t paddr;
> > int lvl = 0;
> > u32 mask;
> >
> > @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> > mask = ARM_V7S_LVL_MASK(lvl);
> > if (arm_v7s_pte_is_cont(pte, lvl))
> > mask *= ARM_V7S_CONT_PAGES;
> > - return (pte & mask) | (iova & ~mask);
> > + paddr = (pte & mask) | (iova & ~mask);
> > +
> > + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> > + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> > + paddr |= BIT_ULL(32);
> > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> > + paddr |= BIT_ULL(33);
> > + }
> > + return paddr;
> > }
> >
> > static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> > diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> > index 2df7909..0eeed94 100644
> > --- a/drivers/iommu/io-pgtable.h
> > +++ b/drivers/iommu/io-pgtable.h
> > @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> > * (unmapped) entries but the hardware might do so anyway, perform
> > * TLB maintenance when mapping as well as when unmapping.
> > *
> > - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> > - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> > - * when the SoC is in "4GB mode" and they can only access the high
> > - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> > + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> > + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
>
> The "all PTEs" part referred to the fact that io-pgtable was forcing bit
> 9 on unconditionally. Since that logic is now moving into the MTK driver
> itself, all the quirk means now from io-pgtable's point of view is that
> PAs may be up to 34 bits where bits 32 and 33 of the address are encoded
> in bits 9 and 4 of the PTE respectively...
>
> > + * address bit when the SoC dram is over 4GB and they can access
> > + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> > *
> > * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> > * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index c0e2da5..86bf647 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> > phys_addr_t paddr, size_t size, int prot)
> > {
> > struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> > + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> > unsigned long flags;
> > int ret;
> >
> > + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> > + data->plat_data->has_4gb_mode &&
> > + data->enable_4GB)
> > + paddr |= BIT_ULL(32);
>
> ...so it might be worth moving the rationale part of the current quirk
> comment (i.e. that the "4GB mode" IOMMUs physically cannot use the lower
> remap of RAM) to here where it now applies.
>
> Robin.
>
> > +
> > spin_lock_irqsave(&dom->pgtlock, flags);
> > - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> > - size, prot);
> > + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> > spin_unlock_irqrestore(&dom->pgtlock, flags);
> >
> > return ret;
> > @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> > dma_addr_t iova)
> > {
> > struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> > - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> > unsigned long flags;
> > phys_addr_t pa;
> >
> > @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> > pa = dom->iop->iova_to_phys(dom->iop, iova);
> > spin_unlock_irqrestore(&dom->pgtlock, flags);
> >
> > - if (data->enable_4GB)
> > - pa |= BIT_ULL(32);
> > -
> > return pa;
> > }
> >
> > @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
> >
> > static const struct mtk_iommu_plat_data mt2712_data = {
> > .m4u_plat = M4U_MT2712,
> > + .has_4gb_mode = true,
> > };
> >
> > static const struct mtk_iommu_plat_data mt8173_data = {
> > .m4u_plat = M4U_MT8173,
> > + .has_4gb_mode = true,
> > };
> >
> > static const struct of_device_id mtk_iommu_of_ids[] = {
> > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> > index 333a0ef..a243047 100644
> > --- a/drivers/iommu/mtk_iommu.h
> > +++ b/drivers/iommu/mtk_iommu.h
> > @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
> >
> > struct mtk_iommu_plat_data {
> > enum mtk_iommu_plat m4u_plat;
> > + bool has_4gb_mode;
> > };
> >
> > struct mtk_iommu_domain;
> >
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH 04/13] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB mode
@ 2018-09-24 9:26 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-24 9:26 UTC (permalink / raw)
To: Robin Murphy
Cc: Joerg Roedel, Rob Herring, Matthias Brugger, Tomasz Figa,
Will Deacon, Daniel Kurtz, linux-mediatek, srv_heupstream,
devicetree, linux-kernel, linux-arm-kernel, iommu, arnd,
yingjoe.chen
On Thu, 2018-09-20 at 18:31 +0100, Robin Murphy wrote:
> On 03/09/18 07:01, Yong Wu wrote:
> > MediaTek extend the arm v7s descriptor to support the dram over 4GB.
> >
> > In the mt2712 and mt8173, it's called "4GB mode", the physical address
> > is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> > is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> > bit32 is always enabled. thus, in the M4U, we always enable the bit9
> > for all PTEs which means to enable bit32 of physical address.
> >
> > but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff
> > which isn't remaped. We extend the PTEs: the bit9 represent bit32 of
> > PA and the bit4 represent bit33 of PA. Meanwhile the iova still is
> > 32bits.
> >
> > In order to unify code, in the "4GB mode", we add the bit32 for the
> > physical address manually in our driver.
> >
> > Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys
> > has to been moved into v7s.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > In mt8183, the PA is from 0x4000_0000 to 0x3_ffff_ffff while the iova
> > still is 32bits. Acturally, our HW extend the v7s pgtable. currently
> > the lvl1 pgtable is 16KB, our HW double it. but 32bit iova is enough
> > for us currently, thus we don't change it.
> > ---
> > drivers/iommu/io-pgtable-arm-v7s.c | 38 ++++++++++++++++++++++++++++++--------
> > drivers/iommu/io-pgtable.h | 8 ++++----
> > drivers/iommu/mtk_iommu.c | 15 +++++++++------
> > drivers/iommu/mtk_iommu.h | 1 +
> > 4 files changed, 44 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index b5948ba..47538dd 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -124,7 +124,9 @@
> > #define ARM_V7S_TEX_MASK 0x7
> > #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
> >
> > -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
> > +/* MTK extend the two bits below for over 4GB mode */
> > +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
> > +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
> >
> > /* *well, except for TEX on level 2 large pages, of course :( */
> > #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
> > @@ -268,7 +270,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
> > }
> >
> > static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> > - struct io_pgtable_cfg *cfg)
> > + struct io_pgtable_cfg *cfg,
> > + phys_addr_t paddr) /* Only for MTK */
>
> I'd rather keep this function dedicated to just generating the
> permissions and attributes. If necessary I'm quite happy to add
> additional helpers for getting/setting the address, much like LPAE now
> has for handling 52-bit IOVAs.
Adding the two additional helpers looks need touch many lines. thus, I
use a new patch for it.
Thanks very much for your review.
>
> > {
> > bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
> > arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
> > @@ -295,8 +298,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
> > if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
> > pte |= ARM_V7S_ATTR_NS_SECTION;
> >
> > - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
> > - pte |= ARM_V7S_ATTR_MTK_4GB;
> > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> > + if (paddr & BIT_ULL(32))
> > + pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> > + if (paddr & BIT_ULL(33))
> > + pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
> > + }
> >
> > return pte;
> > }
> > @@ -392,7 +399,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
> > return -EEXIST;
> > }
> >
> > - pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
> > + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr);
> > if (num_entries > 1)
> > pte = arm_v7s_pte_to_cont(pte, lvl);
> >
> > @@ -484,7 +491,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> > if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> > return 0;
> >
> > - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
> > + if (WARN_ON(upper_32_bits(iova)))
> > + return -ERANGE;
> > +
> > + if (WARN_ON(upper_32_bits(paddr) &&
> > + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)))
>
> TBH I'd just cram the quirk check into the right-hand-side of the ||
> rather than introduce a separate if() - there's already too many
> parentheses to read the whole thing easily ;)
Fix it in v2.
Also, the comments below are fixed.
Thanks.
>
> > return -ERANGE;
> >
> > ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
> > @@ -563,7 +574,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
> > num_entries = size >> ARM_V7S_LVL_SHIFT(2);
> > unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
> >
> > - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
> > + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0);
> > if (num_entries > 1)
> > pte = arm_v7s_pte_to_cont(pte, 2);
> >
> > @@ -677,7 +688,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> > unsigned long iova)
> > {
> > struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> > + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> > arm_v7s_iopte *ptep = data->pgd, pte;
> > + phys_addr_t paddr;
> > int lvl = 0;
> > u32 mask;
> >
> > @@ -693,7 +706,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
> > mask = ARM_V7S_LVL_MASK(lvl);
> > if (arm_v7s_pte_is_cont(pte, lvl))
> > mask *= ARM_V7S_CONT_PAGES;
> > - return (pte & mask) | (iova & ~mask);
> > + paddr = (pte & mask) | (iova & ~mask);
> > +
> > + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> > + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) {
> > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
> > + paddr |= BIT_ULL(32);
> > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
> > + paddr |= BIT_ULL(33);
> > + }
> > + return paddr;
> > }
> >
> > static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> > diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
> > index 2df7909..0eeed94 100644
> > --- a/drivers/iommu/io-pgtable.h
> > +++ b/drivers/iommu/io-pgtable.h
> > @@ -62,10 +62,10 @@ struct io_pgtable_cfg {
> > * (unmapped) entries but the hardware might do so anyway, perform
> > * TLB maintenance when mapping as well as when unmapping.
> > *
> > - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
> > - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
> > - * when the SoC is in "4GB mode" and they can only access the high
> > - * remap of DRAM (0x1_00000000 to 0x1_ffffffff).
> > + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all
> > + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd
>
> The "all PTEs" part referred to the fact that io-pgtable was forcing bit
> 9 on unconditionally. Since that logic is now moving into the MTK driver
> itself, all the quirk means now from io-pgtable's point of view is that
> PAs may be up to 34 bits where bits 32 and 33 of the address are encoded
> in bits 9 and 4 of the PTE respectively...
>
> > + * address bit when the SoC dram is over 4GB and they can access
> > + * the physical address from 0x4000_0000 to 0x3_ffff_ffff.
> > *
> > * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
> > * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index c0e2da5..86bf647 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -367,12 +367,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
> > phys_addr_t paddr, size_t size, int prot)
> > {
> > struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> > + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> > unsigned long flags;
> > int ret;
> >
> > + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
> > + data->plat_data->has_4gb_mode &&
> > + data->enable_4GB)
> > + paddr |= BIT_ULL(32);
>
> ...so it might be worth moving the rationale part of the current quirk
> comment (i.e. that the "4GB mode" IOMMUs physically cannot use the lower
> remap of RAM) to here where it now applies.
>
> Robin.
>
> > +
> > spin_lock_irqsave(&dom->pgtlock, flags);
> > - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
> > - size, prot);
> > + ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
> > spin_unlock_irqrestore(&dom->pgtlock, flags);
> >
> > return ret;
> > @@ -401,7 +406,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> > dma_addr_t iova)
> > {
> > struct mtk_iommu_domain *dom = to_mtk_domain(domain);
> > - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
> > unsigned long flags;
> > phys_addr_t pa;
> >
> > @@ -409,9 +413,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
> > pa = dom->iop->iova_to_phys(dom->iop, iova);
> > spin_unlock_irqrestore(&dom->pgtlock, flags);
> >
> > - if (data->enable_4GB)
> > - pa |= BIT_ULL(32);
> > -
> > return pa;
> > }
> >
> > @@ -735,10 +736,12 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
> >
> > static const struct mtk_iommu_plat_data mt2712_data = {
> > .m4u_plat = M4U_MT2712,
> > + .has_4gb_mode = true,
> > };
> >
> > static const struct mtk_iommu_plat_data mt8173_data = {
> > .m4u_plat = M4U_MT8173,
> > + .has_4gb_mode = true,
> > };
> >
> > static const struct of_device_id mtk_iommu_of_ids[] = {
> > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> > index 333a0ef..a243047 100644
> > --- a/drivers/iommu/mtk_iommu.h
> > +++ b/drivers/iommu/mtk_iommu.h
> > @@ -43,6 +43,7 @@ enum mtk_iommu_plat {
> >
> > struct mtk_iommu_plat_data {
> > enum mtk_iommu_plat m4u_plat;
> > + bool has_4gb_mode;
> > };
> >
> > struct mtk_iommu_domain;
> >
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 05/13] iommu/mediatek: Add mt8183 IOMMU support
2018-09-03 6:01 ` Yong Wu
(?)
@ 2018-09-03 6:01 ` Yong Wu
-1 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use
the ARM Short-descriptor like mt8173, and most of the HW registers
are the same.
Here list main changes in mt8183:
1) mt8183 has only one M4U HW like mt8173.
2) mt8183 don't have its "bclk" clock, the M4U use the EMI clock
which has already been enabled before kernel.
3) mt8183 can support the dram over 4GB, but it don't call this "4GB
mode".
4) mt8183 pgtable base register(0x0) extend bit[1:0] which represent
the bit[33:32] in the physical address of the pgtable base, But the
standard ttbr0[1] that means the S bit is enabled defaultly, Hence,
we add a mask.
5) mt8183 HW has a GALS modules, the SMI should add "gals" clock
support.
6) the larb-id in smi-common has been remapped. This means the
larb-id reported in the mtk_iommu_isr is not the real larb-id, here
is the remapping relationship of mt8183:
M4U
|
--------------------------------------------------
| SMI common |
-0-----7-----5------6-----1-----2-------3-------4- <- Id remapped
| | | | | | | |
larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
disp vdec IPU0 IPU1 venc IPU1 cam
As above, larb0 connects with the id 0 in smi-common.
larb1 connects with the id 7 in smi-common.
...
Take a example, if the larb-id reported in the mtk_iommu_isr is 7,
actually it is larb1(vdec).
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 51 +++++++++++++++++++++++++++++++++++++----------
drivers/iommu/mtk_iommu.h | 5 +++++
drivers/memory/mtk-smi.c | 47 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 92 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 86bf647..5e3e50f 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -36,6 +36,7 @@
#include "mtk_iommu.h"
#define REG_MMU_PT_BASE_ADDR 0x000
+#define MMU_PT_ADDR_MASK GENMASK(31, 7)
#define REG_MMU_INVALIDATE 0x020
#define F_ALL_INVLD 0x2
@@ -54,7 +55,7 @@
#define REG_MMU_CTRL_REG 0x110
#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
- ((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)
+ ((data)->plat_data->m4u_plat == M4U_MT8173 ? 5 : 4)
/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
#define F_MMU_TF_PROTECT_SEL(prot, data) \
(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
@@ -202,12 +203,23 @@ static void mtk_iommu_tlb_sync(void *cookie)
.tlb_sync = mtk_iommu_tlb_sync,
};
+static int mtk_iommu_get_larbid(const struct mtk_iommu_data *data,
+ const unsigned int fault_larb)
+{
+ int i;
+
+ for (i = 0; i < MTK_LARB_NR_MAX; i++)
+ if (data->plat_data->inputid_in_common[i] == fault_larb)
+ return i;
+ return -ERANGE;
+}
+
static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
u32 int_state, regval, fault_iova, fault_pa;
- unsigned int fault_larb, fault_port;
+ int fault_larb, fault_port;
bool layer, write;
/* Read error info from registers */
@@ -220,6 +232,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
fault_port = F_MMU0_INT_ID_PORT_ID(regval);
+ if (data->plat_data->larbid_remap_enable)
+ fault_larb = mtk_iommu_get_larbid(data, fault_larb);
+
if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
@@ -344,7 +359,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
/* Update the pgtable base address register of the M4U HW */
if (!data->m4u_dom) {
data->m4u_dom = dom;
- writel(dom->cfg.arm_v7s_cfg.ttbr[0],
+ writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
data->base + REG_MMU_PT_BASE_ADDR);
}
@@ -508,6 +523,7 @@ static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
{
+ enum mtk_iommu_plat m4u_plat = data->plat_data->m4u_plat;
u32 regval;
int ret;
@@ -518,7 +534,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
regval = F_MMU_TF_PROTECT_SEL(2, data);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (m4u_plat == M4U_MT8173)
regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
@@ -539,14 +555,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (m4u_plat == M4U_MT8173)
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
upper_32_bits(data->protect_base);
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
- if (data->enable_4GB && data->plat_data->m4u_plat != M4U_MT8173) {
+ if (data->enable_4GB && m4u_plat == M4U_MT2712) {
/*
* If 4GB mode is enabled, the validate PA range is from
* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
@@ -556,8 +572,11 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
- /* It's MISC control register whose default value is ok except mt8173.*/
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ /*
+ * It's MISC control register whose default value is ok
+ * except mt8173 and mt8183.
+ */
+ if (m4u_plat == M4U_MT8173 || m4u_plat == M4U_MT8183)
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -612,7 +631,9 @@ static int mtk_iommu_probe(struct platform_device *pdev)
return data->irq;
data->bclk = devm_clk_get(dev, "bclk");
- if (IS_ERR(data->bclk))
+ if (PTR_ERR(data->bclk) == -ENOENT)
+ data->bclk = NULL;
+ else if (IS_ERR(data->bclk))
return PTR_ERR(data->bclk);
larb_nr = of_count_phandle_with_args(dev->of_node,
@@ -709,6 +730,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
+ struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
void __iomem *base = data->base;
int ret;
@@ -724,8 +746,8 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
- if (data->m4u_dom)
- writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
+ if (m4u_dom)
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
base + REG_MMU_PT_BASE_ADDR);
return 0;
}
@@ -744,9 +766,16 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
.has_4gb_mode = true,
};
+static const struct mtk_iommu_plat_data mt8183_data = {
+ .m4u_plat = M4U_MT8183,
+ .larbid_remap_enable = true,
+ .inputid_in_common = {0, 7, 5, 6, 1, 2, 3, 4},
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
+ { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index a243047..8bf76be 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -39,11 +39,16 @@ enum mtk_iommu_plat {
M4U_MT2701,
M4U_MT2712,
M4U_MT8173,
+ M4U_MT8183,
};
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
bool has_4gb_mode;
+
+ /* The larb-id may be remapped in the smi-common. */
+ bool larbid_remap_enable;
+ unsigned int inputid_in_common[MTK_LARB_NR_MAX];
};
struct mtk_iommu_domain;
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e37e54b..697795a 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -59,6 +59,7 @@ struct mtk_smi_larb_gen {
struct mtk_smi {
struct device *dev;
struct clk *clk_apb, *clk_smi;
+ struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
void __iomem *smi_ao_base;
};
@@ -93,8 +94,20 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
if (ret)
goto err_disable_apb;
+ ret = clk_prepare_enable(smi->clk_gals0);
+ if (ret)
+ goto err_disable_smi;
+
+ ret = clk_prepare_enable(smi->clk_gals1);
+ if (ret)
+ goto err_disable_gals0;
+
return 0;
+err_disable_gals0:
+ clk_disable_unprepare(smi->clk_gals0);
+err_disable_smi:
+ clk_disable_unprepare(smi->clk_smi);
err_disable_apb:
clk_disable_unprepare(smi->clk_apb);
err_put_pm:
@@ -104,6 +117,8 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
static void mtk_smi_disable(const struct mtk_smi *smi)
{
+ clk_disable_unprepare(smi->clk_gals1);
+ clk_disable_unprepare(smi->clk_gals0);
clk_disable_unprepare(smi->clk_smi);
clk_disable_unprepare(smi->clk_apb);
pm_runtime_put_sync(smi->dev);
@@ -262,6 +277,12 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
.larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
+ .need_larbid = true,
+ .config_port = mtk_smi_larb_config_port_gen2_general,
+ .larb_special_mask = BIT(7), /* CCU */
+};
+
static const struct of_device_id mtk_smi_larb_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-larb",
@@ -275,6 +296,10 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
.compatible = "mediatek,mt2712-smi-larb",
.data = &mtk_smi_larb_mt2712
},
+ {
+ .compatible = "mediatek,mt8183-smi-larb",
+ .data = &mtk_smi_larb_mt8183
+ },
{}
};
@@ -304,6 +329,12 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
larb->smi.clk_smi = devm_clk_get(dev, "smi");
if (IS_ERR(larb->smi.clk_smi))
return PTR_ERR(larb->smi.clk_smi);
+
+ larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
+ if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
+ larb->smi.clk_gals0 = NULL;
+ else if (IS_ERR(larb->smi.clk_gals0))
+ return PTR_ERR(larb->smi.clk_gals0);
larb->smi.dev = dev;
if (larb->larb_gen->need_larbid) {
@@ -364,6 +395,10 @@ static int mtk_smi_larb_remove(struct platform_device *pdev)
.compatible = "mediatek,mt2712-smi-common",
.data = (void *)MTK_SMI_GEN2
},
+ {
+ .compatible = "mediatek,mt8183-smi-common",
+ .data = (void *)MTK_SMI_GEN2
+ },
{}
};
@@ -388,6 +423,18 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
if (IS_ERR(common->clk_smi))
return PTR_ERR(common->clk_smi);
+ common->clk_gals0 = devm_clk_get(dev, "gals0");
+ if (PTR_ERR(common->clk_gals0) == -ENOENT)
+ common->clk_gals0 = NULL;
+ else if (IS_ERR(common->clk_gals0))
+ return PTR_ERR(common->clk_gals0);
+
+ common->clk_gals1 = devm_clk_get(dev, "gals1");
+ if (PTR_ERR(common->clk_gals1) == -ENOENT)
+ common->clk_gals1 = NULL;
+ else if (IS_ERR(common->clk_gals1))
+ return PTR_ERR(common->clk_gals1);
+
/*
* for mtk smi gen 1, we need to get the ao(always on) base to config
* m4u port, and we need to enable the aync clock for transform the smi
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 05/13] iommu/mediatek: Add mt8183 IOMMU support
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use
the ARM Short-descriptor like mt8173, and most of the HW registers
are the same.
Here list main changes in mt8183:
1) mt8183 has only one M4U HW like mt8173.
2) mt8183 don't have its "bclk" clock, the M4U use the EMI clock
which has already been enabled before kernel.
3) mt8183 can support the dram over 4GB, but it don't call this "4GB
mode".
4) mt8183 pgtable base register(0x0) extend bit[1:0] which represent
the bit[33:32] in the physical address of the pgtable base, But the
standard ttbr0[1] that means the S bit is enabled defaultly, Hence,
we add a mask.
5) mt8183 HW has a GALS modules, the SMI should add "gals" clock
support.
6) the larb-id in smi-common has been remapped. This means the
larb-id reported in the mtk_iommu_isr is not the real larb-id, here
is the remapping relationship of mt8183:
M4U
|
--------------------------------------------------
| SMI common |
-0-----7-----5------6-----1-----2-------3-------4- <- Id remapped
| | | | | | | |
larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
disp vdec IPU0 IPU1 venc IPU1 cam
As above, larb0 connects with the id 0 in smi-common.
larb1 connects with the id 7 in smi-common.
...
Take a example, if the larb-id reported in the mtk_iommu_isr is 7,
actually it is larb1(vdec).
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 51 +++++++++++++++++++++++++++++++++++++----------
drivers/iommu/mtk_iommu.h | 5 +++++
drivers/memory/mtk-smi.c | 47 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 92 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 86bf647..5e3e50f 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -36,6 +36,7 @@
#include "mtk_iommu.h"
#define REG_MMU_PT_BASE_ADDR 0x000
+#define MMU_PT_ADDR_MASK GENMASK(31, 7)
#define REG_MMU_INVALIDATE 0x020
#define F_ALL_INVLD 0x2
@@ -54,7 +55,7 @@
#define REG_MMU_CTRL_REG 0x110
#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
- ((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)
+ ((data)->plat_data->m4u_plat == M4U_MT8173 ? 5 : 4)
/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
#define F_MMU_TF_PROTECT_SEL(prot, data) \
(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
@@ -202,12 +203,23 @@ static void mtk_iommu_tlb_sync(void *cookie)
.tlb_sync = mtk_iommu_tlb_sync,
};
+static int mtk_iommu_get_larbid(const struct mtk_iommu_data *data,
+ const unsigned int fault_larb)
+{
+ int i;
+
+ for (i = 0; i < MTK_LARB_NR_MAX; i++)
+ if (data->plat_data->inputid_in_common[i] == fault_larb)
+ return i;
+ return -ERANGE;
+}
+
static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
u32 int_state, regval, fault_iova, fault_pa;
- unsigned int fault_larb, fault_port;
+ int fault_larb, fault_port;
bool layer, write;
/* Read error info from registers */
@@ -220,6 +232,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
fault_port = F_MMU0_INT_ID_PORT_ID(regval);
+ if (data->plat_data->larbid_remap_enable)
+ fault_larb = mtk_iommu_get_larbid(data, fault_larb);
+
if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
@@ -344,7 +359,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
/* Update the pgtable base address register of the M4U HW */
if (!data->m4u_dom) {
data->m4u_dom = dom;
- writel(dom->cfg.arm_v7s_cfg.ttbr[0],
+ writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
data->base + REG_MMU_PT_BASE_ADDR);
}
@@ -508,6 +523,7 @@ static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
{
+ enum mtk_iommu_plat m4u_plat = data->plat_data->m4u_plat;
u32 regval;
int ret;
@@ -518,7 +534,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
regval = F_MMU_TF_PROTECT_SEL(2, data);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (m4u_plat == M4U_MT8173)
regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
@@ -539,14 +555,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (m4u_plat == M4U_MT8173)
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
upper_32_bits(data->protect_base);
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
- if (data->enable_4GB && data->plat_data->m4u_plat != M4U_MT8173) {
+ if (data->enable_4GB && m4u_plat == M4U_MT2712) {
/*
* If 4GB mode is enabled, the validate PA range is from
* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
@@ -556,8 +572,11 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
- /* It's MISC control register whose default value is ok except mt8173.*/
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ /*
+ * It's MISC control register whose default value is ok
+ * except mt8173 and mt8183.
+ */
+ if (m4u_plat == M4U_MT8173 || m4u_plat == M4U_MT8183)
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -612,7 +631,9 @@ static int mtk_iommu_probe(struct platform_device *pdev)
return data->irq;
data->bclk = devm_clk_get(dev, "bclk");
- if (IS_ERR(data->bclk))
+ if (PTR_ERR(data->bclk) == -ENOENT)
+ data->bclk = NULL;
+ else if (IS_ERR(data->bclk))
return PTR_ERR(data->bclk);
larb_nr = of_count_phandle_with_args(dev->of_node,
@@ -709,6 +730,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
+ struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
void __iomem *base = data->base;
int ret;
@@ -724,8 +746,8 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
- if (data->m4u_dom)
- writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
+ if (m4u_dom)
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
base + REG_MMU_PT_BASE_ADDR);
return 0;
}
@@ -744,9 +766,16 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
.has_4gb_mode = true,
};
+static const struct mtk_iommu_plat_data mt8183_data = {
+ .m4u_plat = M4U_MT8183,
+ .larbid_remap_enable = true,
+ .inputid_in_common = {0, 7, 5, 6, 1, 2, 3, 4},
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
+ { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index a243047..8bf76be 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -39,11 +39,16 @@ enum mtk_iommu_plat {
M4U_MT2701,
M4U_MT2712,
M4U_MT8173,
+ M4U_MT8183,
};
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
bool has_4gb_mode;
+
+ /* The larb-id may be remapped in the smi-common. */
+ bool larbid_remap_enable;
+ unsigned int inputid_in_common[MTK_LARB_NR_MAX];
};
struct mtk_iommu_domain;
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e37e54b..697795a 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -59,6 +59,7 @@ struct mtk_smi_larb_gen {
struct mtk_smi {
struct device *dev;
struct clk *clk_apb, *clk_smi;
+ struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
void __iomem *smi_ao_base;
};
@@ -93,8 +94,20 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
if (ret)
goto err_disable_apb;
+ ret = clk_prepare_enable(smi->clk_gals0);
+ if (ret)
+ goto err_disable_smi;
+
+ ret = clk_prepare_enable(smi->clk_gals1);
+ if (ret)
+ goto err_disable_gals0;
+
return 0;
+err_disable_gals0:
+ clk_disable_unprepare(smi->clk_gals0);
+err_disable_smi:
+ clk_disable_unprepare(smi->clk_smi);
err_disable_apb:
clk_disable_unprepare(smi->clk_apb);
err_put_pm:
@@ -104,6 +117,8 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
static void mtk_smi_disable(const struct mtk_smi *smi)
{
+ clk_disable_unprepare(smi->clk_gals1);
+ clk_disable_unprepare(smi->clk_gals0);
clk_disable_unprepare(smi->clk_smi);
clk_disable_unprepare(smi->clk_apb);
pm_runtime_put_sync(smi->dev);
@@ -262,6 +277,12 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
.larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
+ .need_larbid = true,
+ .config_port = mtk_smi_larb_config_port_gen2_general,
+ .larb_special_mask = BIT(7), /* CCU */
+};
+
static const struct of_device_id mtk_smi_larb_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-larb",
@@ -275,6 +296,10 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
.compatible = "mediatek,mt2712-smi-larb",
.data = &mtk_smi_larb_mt2712
},
+ {
+ .compatible = "mediatek,mt8183-smi-larb",
+ .data = &mtk_smi_larb_mt8183
+ },
{}
};
@@ -304,6 +329,12 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
larb->smi.clk_smi = devm_clk_get(dev, "smi");
if (IS_ERR(larb->smi.clk_smi))
return PTR_ERR(larb->smi.clk_smi);
+
+ larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
+ if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
+ larb->smi.clk_gals0 = NULL;
+ else if (IS_ERR(larb->smi.clk_gals0))
+ return PTR_ERR(larb->smi.clk_gals0);
larb->smi.dev = dev;
if (larb->larb_gen->need_larbid) {
@@ -364,6 +395,10 @@ static int mtk_smi_larb_remove(struct platform_device *pdev)
.compatible = "mediatek,mt2712-smi-common",
.data = (void *)MTK_SMI_GEN2
},
+ {
+ .compatible = "mediatek,mt8183-smi-common",
+ .data = (void *)MTK_SMI_GEN2
+ },
{}
};
@@ -388,6 +423,18 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
if (IS_ERR(common->clk_smi))
return PTR_ERR(common->clk_smi);
+ common->clk_gals0 = devm_clk_get(dev, "gals0");
+ if (PTR_ERR(common->clk_gals0) == -ENOENT)
+ common->clk_gals0 = NULL;
+ else if (IS_ERR(common->clk_gals0))
+ return PTR_ERR(common->clk_gals0);
+
+ common->clk_gals1 = devm_clk_get(dev, "gals1");
+ if (PTR_ERR(common->clk_gals1) == -ENOENT)
+ common->clk_gals1 = NULL;
+ else if (IS_ERR(common->clk_gals1))
+ return PTR_ERR(common->clk_gals1);
+
/*
* for mtk smi gen 1, we need to get the ao(always on) base to config
* m4u port, and we need to enable the aync clock for transform the smi
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 05/13] iommu/mediatek: Add mt8183 IOMMU support
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use
the ARM Short-descriptor like mt8173, and most of the HW registers
are the same.
Here list main changes in mt8183:
1) mt8183 has only one M4U HW like mt8173.
2) mt8183 don't have its "bclk" clock, the M4U use the EMI clock
which has already been enabled before kernel.
3) mt8183 can support the dram over 4GB, but it don't call this "4GB
mode".
4) mt8183 pgtable base register(0x0) extend bit[1:0] which represent
the bit[33:32] in the physical address of the pgtable base, But the
standard ttbr0[1] that means the S bit is enabled defaultly, Hence,
we add a mask.
5) mt8183 HW has a GALS modules, the SMI should add "gals" clock
support.
6) the larb-id in smi-common has been remapped. This means the
larb-id reported in the mtk_iommu_isr is not the real larb-id, here
is the remapping relationship of mt8183:
M4U
|
--------------------------------------------------
| SMI common |
-0-----7-----5------6-----1-----2-------3-------4- <- Id remapped
| | | | | | | |
larb0 larb1 larb2 larb3 larb4 larb5 larb6 CCU
disp vdec IPU0 IPU1 venc IPU1 cam
As above, larb0 connects with the id 0 in smi-common.
larb1 connects with the id 7 in smi-common.
...
Take a example, if the larb-id reported in the mtk_iommu_isr is 7,
actually it is larb1(vdec).
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 51 +++++++++++++++++++++++++++++++++++++----------
drivers/iommu/mtk_iommu.h | 5 +++++
drivers/memory/mtk-smi.c | 47 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 92 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 86bf647..5e3e50f 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -36,6 +36,7 @@
#include "mtk_iommu.h"
#define REG_MMU_PT_BASE_ADDR 0x000
+#define MMU_PT_ADDR_MASK GENMASK(31, 7)
#define REG_MMU_INVALIDATE 0x020
#define F_ALL_INVLD 0x2
@@ -54,7 +55,7 @@
#define REG_MMU_CTRL_REG 0x110
#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
- ((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)
+ ((data)->plat_data->m4u_plat == M4U_MT8173 ? 5 : 4)
/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
#define F_MMU_TF_PROTECT_SEL(prot, data) \
(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
@@ -202,12 +203,23 @@ static void mtk_iommu_tlb_sync(void *cookie)
.tlb_sync = mtk_iommu_tlb_sync,
};
+static int mtk_iommu_get_larbid(const struct mtk_iommu_data *data,
+ const unsigned int fault_larb)
+{
+ int i;
+
+ for (i = 0; i < MTK_LARB_NR_MAX; i++)
+ if (data->plat_data->inputid_in_common[i] == fault_larb)
+ return i;
+ return -ERANGE;
+}
+
static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
u32 int_state, regval, fault_iova, fault_pa;
- unsigned int fault_larb, fault_port;
+ int fault_larb, fault_port;
bool layer, write;
/* Read error info from registers */
@@ -220,6 +232,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
fault_port = F_MMU0_INT_ID_PORT_ID(regval);
+ if (data->plat_data->larbid_remap_enable)
+ fault_larb = mtk_iommu_get_larbid(data, fault_larb);
+
if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
@@ -344,7 +359,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
/* Update the pgtable base address register of the M4U HW */
if (!data->m4u_dom) {
data->m4u_dom = dom;
- writel(dom->cfg.arm_v7s_cfg.ttbr[0],
+ writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
data->base + REG_MMU_PT_BASE_ADDR);
}
@@ -508,6 +523,7 @@ static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
{
+ enum mtk_iommu_plat m4u_plat = data->plat_data->m4u_plat;
u32 regval;
int ret;
@@ -518,7 +534,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
regval = F_MMU_TF_PROTECT_SEL(2, data);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (m4u_plat == M4U_MT8173)
regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
@@ -539,14 +555,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (m4u_plat == M4U_MT8173)
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
upper_32_bits(data->protect_base);
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
- if (data->enable_4GB && data->plat_data->m4u_plat != M4U_MT8173) {
+ if (data->enable_4GB && m4u_plat == M4U_MT2712) {
/*
* If 4GB mode is enabled, the validate PA range is from
* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
@@ -556,8 +572,11 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
- /* It's MISC control register whose default value is ok except mt8173.*/
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ /*
+ * It's MISC control register whose default value is ok
+ * except mt8173 and mt8183.
+ */
+ if (m4u_plat == M4U_MT8173 || m4u_plat == M4U_MT8183)
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -612,7 +631,9 @@ static int mtk_iommu_probe(struct platform_device *pdev)
return data->irq;
data->bclk = devm_clk_get(dev, "bclk");
- if (IS_ERR(data->bclk))
+ if (PTR_ERR(data->bclk) == -ENOENT)
+ data->bclk = NULL;
+ else if (IS_ERR(data->bclk))
return PTR_ERR(data->bclk);
larb_nr = of_count_phandle_with_args(dev->of_node,
@@ -709,6 +730,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
+ struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
void __iomem *base = data->base;
int ret;
@@ -724,8 +746,8 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
- if (data->m4u_dom)
- writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
+ if (m4u_dom)
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
base + REG_MMU_PT_BASE_ADDR);
return 0;
}
@@ -744,9 +766,16 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
.has_4gb_mode = true,
};
+static const struct mtk_iommu_plat_data mt8183_data = {
+ .m4u_plat = M4U_MT8183,
+ .larbid_remap_enable = true,
+ .inputid_in_common = {0, 7, 5, 6, 1, 2, 3, 4},
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
+ { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index a243047..8bf76be 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -39,11 +39,16 @@ enum mtk_iommu_plat {
M4U_MT2701,
M4U_MT2712,
M4U_MT8173,
+ M4U_MT8183,
};
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
bool has_4gb_mode;
+
+ /* The larb-id may be remapped in the smi-common. */
+ bool larbid_remap_enable;
+ unsigned int inputid_in_common[MTK_LARB_NR_MAX];
};
struct mtk_iommu_domain;
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e37e54b..697795a 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -59,6 +59,7 @@ struct mtk_smi_larb_gen {
struct mtk_smi {
struct device *dev;
struct clk *clk_apb, *clk_smi;
+ struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
void __iomem *smi_ao_base;
};
@@ -93,8 +94,20 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
if (ret)
goto err_disable_apb;
+ ret = clk_prepare_enable(smi->clk_gals0);
+ if (ret)
+ goto err_disable_smi;
+
+ ret = clk_prepare_enable(smi->clk_gals1);
+ if (ret)
+ goto err_disable_gals0;
+
return 0;
+err_disable_gals0:
+ clk_disable_unprepare(smi->clk_gals0);
+err_disable_smi:
+ clk_disable_unprepare(smi->clk_smi);
err_disable_apb:
clk_disable_unprepare(smi->clk_apb);
err_put_pm:
@@ -104,6 +117,8 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
static void mtk_smi_disable(const struct mtk_smi *smi)
{
+ clk_disable_unprepare(smi->clk_gals1);
+ clk_disable_unprepare(smi->clk_gals0);
clk_disable_unprepare(smi->clk_smi);
clk_disable_unprepare(smi->clk_apb);
pm_runtime_put_sync(smi->dev);
@@ -262,6 +277,12 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
.larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
+ .need_larbid = true,
+ .config_port = mtk_smi_larb_config_port_gen2_general,
+ .larb_special_mask = BIT(7), /* CCU */
+};
+
static const struct of_device_id mtk_smi_larb_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-larb",
@@ -275,6 +296,10 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
.compatible = "mediatek,mt2712-smi-larb",
.data = &mtk_smi_larb_mt2712
},
+ {
+ .compatible = "mediatek,mt8183-smi-larb",
+ .data = &mtk_smi_larb_mt8183
+ },
{}
};
@@ -304,6 +329,12 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
larb->smi.clk_smi = devm_clk_get(dev, "smi");
if (IS_ERR(larb->smi.clk_smi))
return PTR_ERR(larb->smi.clk_smi);
+
+ larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
+ if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
+ larb->smi.clk_gals0 = NULL;
+ else if (IS_ERR(larb->smi.clk_gals0))
+ return PTR_ERR(larb->smi.clk_gals0);
larb->smi.dev = dev;
if (larb->larb_gen->need_larbid) {
@@ -364,6 +395,10 @@ static int mtk_smi_larb_remove(struct platform_device *pdev)
.compatible = "mediatek,mt2712-smi-common",
.data = (void *)MTK_SMI_GEN2
},
+ {
+ .compatible = "mediatek,mt8183-smi-common",
+ .data = (void *)MTK_SMI_GEN2
+ },
{}
};
@@ -388,6 +423,18 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
if (IS_ERR(common->clk_smi))
return PTR_ERR(common->clk_smi);
+ common->clk_gals0 = devm_clk_get(dev, "gals0");
+ if (PTR_ERR(common->clk_gals0) == -ENOENT)
+ common->clk_gals0 = NULL;
+ else if (IS_ERR(common->clk_gals0))
+ return PTR_ERR(common->clk_gals0);
+
+ common->clk_gals1 = devm_clk_get(dev, "gals1");
+ if (PTR_ERR(common->clk_gals1) == -ENOENT)
+ common->clk_gals1 = NULL;
+ else if (IS_ERR(common->clk_gals1))
+ return PTR_ERR(common->clk_gals1);
+
/*
* for mtk smi gen 1, we need to get the ao(always on) base to config
* m4u port, and we need to enable the aync clock for transform the smi
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 06/13] iommu/mediatek: Add mmu1 support
2018-09-03 6:01 ` Yong Wu
(?)
@ 2018-09-03 6:01 ` Yong Wu
-1 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
Normally the M4U HW connect EMI with smi. the diagram is like below:
EMI
|
M4U
|
smi-common
|
-----------------
| | | | ...
larb0 larb1 larb2 larb3
Actually there are 2 mmu cells in the M4U HW, like this diagram:
EMI
---------
| |
mmu0 mmu1 <- M4U
| |
---------
|
smi-common
|
-----------------
| | | | ...
larb0 larb1 larb2 larb3
This patch add support for mmu1. In order to get better performance,
we could adjust some larbs go to mmu1 while the others still go to
mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220).
mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default
value of that register is 0 which means all the larbs go to mmu0
defaultly.
This is a prepare patch for adjust SMI_BUS_SEL for mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++------------------
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5e3e50f..e9665ad 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -74,27 +74,32 @@
#define F_MISS_FIFO_ERR_INT_EN BIT(6)
#define F_INT_CLR_BIT BIT(12)
-#define REG_MMU_INT_MAIN_CONTROL 0x124
-#define F_INT_TRANSLATION_FAULT BIT(0)
-#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
-#define F_INT_INVALID_PA_FAULT BIT(2)
-#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
-#define F_INT_TLB_MISS_FAULT BIT(4)
-#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5)
-#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6)
+#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */
+#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
+#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
+#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
+#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
+#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
+#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
+#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
#define REG_MMU_CPE_DONE 0x12C
#define REG_MMU_FAULT_ST1 0x134
+#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
+#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
-#define REG_MMU_FAULT_VA 0x13c
+#define REG_MMU0_FAULT_VA 0x13c
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
-#define REG_MMU_INVLD_PA 0x140
-#define REG_MMU_INT_ID 0x150
-#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
-#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
+#define REG_MMU0_INVLD_PA 0x140
+#define REG_MMU1_FAULT_VA 0x144
+#define REG_MMU1_INVLD_PA 0x148
+#define REG_MMU0_INT_ID 0x150
+#define REG_MMU1_INT_ID 0x154
+#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
+#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
#define MTK_PROTECT_PA_ALIGN 128
@@ -224,13 +229,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
/* Read error info from registers */
int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
- fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
+ if (int_state & F_REG_MMU0_FAULT_MASK) {
+ regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
+ fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
+ fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
+ } else {
+ regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
+ fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
+ fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
+ }
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
- fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
- regval = readl_relaxed(data->base + REG_MMU_INT_ID);
- fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
- fault_port = F_MMU0_INT_ID_PORT_ID(regval);
+ fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (data->plat_data->larbid_remap_enable)
fault_larb = mtk_iommu_get_larbid(data, fault_larb);
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 06/13] iommu/mediatek: Add mmu1 support
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Normally the M4U HW connect EMI with smi. the diagram is like below:
EMI
|
M4U
|
smi-common
|
-----------------
| | | | ...
larb0 larb1 larb2 larb3
Actually there are 2 mmu cells in the M4U HW, like this diagram:
EMI
---------
| |
mmu0 mmu1 <- M4U
| |
---------
|
smi-common
|
-----------------
| | | | ...
larb0 larb1 larb2 larb3
This patch add support for mmu1. In order to get better performance,
we could adjust some larbs go to mmu1 while the others still go to
mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220).
mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default
value of that register is 0 which means all the larbs go to mmu0
defaultly.
This is a prepare patch for adjust SMI_BUS_SEL for mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++------------------
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5e3e50f..e9665ad 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -74,27 +74,32 @@
#define F_MISS_FIFO_ERR_INT_EN BIT(6)
#define F_INT_CLR_BIT BIT(12)
-#define REG_MMU_INT_MAIN_CONTROL 0x124
-#define F_INT_TRANSLATION_FAULT BIT(0)
-#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
-#define F_INT_INVALID_PA_FAULT BIT(2)
-#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
-#define F_INT_TLB_MISS_FAULT BIT(4)
-#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5)
-#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6)
+#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */
+#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
+#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
+#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
+#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
+#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
+#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
+#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
#define REG_MMU_CPE_DONE 0x12C
#define REG_MMU_FAULT_ST1 0x134
+#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
+#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
-#define REG_MMU_FAULT_VA 0x13c
+#define REG_MMU0_FAULT_VA 0x13c
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
-#define REG_MMU_INVLD_PA 0x140
-#define REG_MMU_INT_ID 0x150
-#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
-#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
+#define REG_MMU0_INVLD_PA 0x140
+#define REG_MMU1_FAULT_VA 0x144
+#define REG_MMU1_INVLD_PA 0x148
+#define REG_MMU0_INT_ID 0x150
+#define REG_MMU1_INT_ID 0x154
+#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
+#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
#define MTK_PROTECT_PA_ALIGN 128
@@ -224,13 +229,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
/* Read error info from registers */
int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
- fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
+ if (int_state & F_REG_MMU0_FAULT_MASK) {
+ regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
+ fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
+ fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
+ } else {
+ regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
+ fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
+ fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
+ }
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
- fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
- regval = readl_relaxed(data->base + REG_MMU_INT_ID);
- fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
- fault_port = F_MMU0_INT_ID_PORT_ID(regval);
+ fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (data->plat_data->larbid_remap_enable)
fault_larb = mtk_iommu_get_larbid(data, fault_larb);
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 06/13] iommu/mediatek: Add mmu1 support
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
Normally the M4U HW connect EMI with smi. the diagram is like below:
EMI
|
M4U
|
smi-common
|
-----------------
| | | | ...
larb0 larb1 larb2 larb3
Actually there are 2 mmu cells in the M4U HW, like this diagram:
EMI
---------
| |
mmu0 mmu1 <- M4U
| |
---------
|
smi-common
|
-----------------
| | | | ...
larb0 larb1 larb2 larb3
This patch add support for mmu1. In order to get better performance,
we could adjust some larbs go to mmu1 while the others still go to
mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220).
mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default
value of that register is 0 which means all the larbs go to mmu0
defaultly.
This is a prepare patch for adjust SMI_BUS_SEL for mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++------------------
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5e3e50f..e9665ad 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -74,27 +74,32 @@
#define F_MISS_FIFO_ERR_INT_EN BIT(6)
#define F_INT_CLR_BIT BIT(12)
-#define REG_MMU_INT_MAIN_CONTROL 0x124
-#define F_INT_TRANSLATION_FAULT BIT(0)
-#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
-#define F_INT_INVALID_PA_FAULT BIT(2)
-#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
-#define F_INT_TLB_MISS_FAULT BIT(4)
-#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5)
-#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6)
+#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */
+#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
+#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
+#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
+#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
+#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
+#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
+#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
#define REG_MMU_CPE_DONE 0x12C
#define REG_MMU_FAULT_ST1 0x134
+#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
+#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
-#define REG_MMU_FAULT_VA 0x13c
+#define REG_MMU0_FAULT_VA 0x13c
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
-#define REG_MMU_INVLD_PA 0x140
-#define REG_MMU_INT_ID 0x150
-#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
-#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
+#define REG_MMU0_INVLD_PA 0x140
+#define REG_MMU1_FAULT_VA 0x144
+#define REG_MMU1_INVLD_PA 0x148
+#define REG_MMU0_INT_ID 0x150
+#define REG_MMU1_INT_ID 0x154
+#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
+#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
#define MTK_PROTECT_PA_ALIGN 128
@@ -224,13 +229,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
/* Read error info from registers */
int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
- fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
+ if (int_state & F_REG_MMU0_FAULT_MASK) {
+ regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
+ fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
+ fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
+ } else {
+ regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
+ fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
+ fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
+ }
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
- fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
- regval = readl_relaxed(data->base + REG_MMU_INT_ID);
- fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
- fault_port = F_MMU0_INT_ID_PORT_ID(regval);
+ fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (data->plat_data->larbid_remap_enable)
fault_larb = mtk_iommu_get_larbid(data, fault_larb);
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 07/13] memory: mtk-smi: Invoke pm runtime_callback to enable clocks
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
This patch only move the clk_prepare_enable and config_port into the
runtime suspend/resume callback. It doesn't change the code content
and sequence.
This is a prepare patch for adjusting SMI_BUS_SEL for mt8183.
(SMI_BUS_SEL need to be restored after smi-common resume every time.)
Also it gives a chance to get rid of mtk_smi_larb_get/put which could
be a next topic.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 113 ++++++++++++++++++++++++++++++-----------------
1 file changed, 72 insertions(+), 41 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 697795a..e6a7382 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -78,17 +78,13 @@ enum mtk_smi_gen {
MTK_SMI_GEN2
};
-static int mtk_smi_enable(const struct mtk_smi *smi)
+static int mtk_smi_clk_enable(const struct mtk_smi *smi)
{
int ret;
- ret = pm_runtime_get_sync(smi->dev);
- if (ret < 0)
- return ret;
-
ret = clk_prepare_enable(smi->clk_apb);
if (ret)
- goto err_put_pm;
+ return ret;
ret = clk_prepare_enable(smi->clk_smi);
if (ret)
@@ -110,59 +106,28 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
clk_disable_unprepare(smi->clk_smi);
err_disable_apb:
clk_disable_unprepare(smi->clk_apb);
-err_put_pm:
- pm_runtime_put_sync(smi->dev);
return ret;
}
-static void mtk_smi_disable(const struct mtk_smi *smi)
+static void mtk_smi_clk_disable(const struct mtk_smi *smi)
{
clk_disable_unprepare(smi->clk_gals1);
clk_disable_unprepare(smi->clk_gals0);
clk_disable_unprepare(smi->clk_smi);
clk_disable_unprepare(smi->clk_apb);
- pm_runtime_put_sync(smi->dev);
}
int mtk_smi_larb_get(struct device *larbdev)
{
- struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
- const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
- struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
- int ret;
+ int ret = pm_runtime_get_sync(larbdev);
- /* Enable the smi-common's power and clocks */
- ret = mtk_smi_enable(common);
- if (ret)
- return ret;
-
- /* Enable the larb's power and clocks */
- ret = mtk_smi_enable(&larb->smi);
- if (ret) {
- mtk_smi_disable(common);
- return ret;
- }
-
- /* Configure the iommu info for this larb */
- larb_gen->config_port(larbdev);
-
- return 0;
+ return (ret < 0) ? ret : 0;
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
void mtk_smi_larb_put(struct device *larbdev)
{
- struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
- struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
-
- /*
- * Don't de-configure the iommu info for this larb since there may be
- * several modules in this larb.
- * The iommu info will be reset after power off.
- */
-
- mtk_smi_disable(&larb->smi);
- mtk_smi_disable(common);
+ pm_runtime_put_sync(larbdev);
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
@@ -373,12 +338,52 @@ static int mtk_smi_larb_remove(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+ const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
+ int ret;
+
+ /* Power on smi-common. */
+ ret = pm_runtime_get_sync(larb->smi_common_dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
+ return ret;
+ }
+
+ ret = mtk_smi_clk_enable(&larb->smi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable clock(%d).\n", ret);
+ pm_runtime_put_sync(larb->smi_common_dev);
+ return ret;
+ }
+
+ /* Configure the basic setting for this larb */
+ larb_gen->config_port(dev);
+
+ return 0;
+}
+
+static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+
+ mtk_smi_clk_disable(&larb->smi);
+ pm_runtime_put_sync(larb->smi_common_dev);
+ return 0;
+}
+
+static const struct dev_pm_ops smi_larb_pm_ops = {
+ SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
+};
+
static struct platform_driver mtk_smi_larb_driver = {
.probe = mtk_smi_larb_probe,
.remove = mtk_smi_larb_remove,
.driver = {
.name = "mtk-smi-larb",
.of_match_table = mtk_smi_larb_of_ids,
+ .pm = &smi_larb_pm_ops,
}
};
@@ -467,12 +472,38 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused mtk_smi_common_resume(struct device *dev)
+{
+ struct mtk_smi *common = dev_get_drvdata(dev);
+ int ret;
+
+ ret = mtk_smi_clk_enable(common);
+ if (ret) {
+ dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
+{
+ struct mtk_smi *common = dev_get_drvdata(dev);
+
+ mtk_smi_clk_disable(common);
+ return 0;
+}
+
+static const struct dev_pm_ops smi_common_pm_ops = {
+ SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
+};
+
static struct platform_driver mtk_smi_common_driver = {
.probe = mtk_smi_common_probe,
.remove = mtk_smi_common_remove,
.driver = {
.name = "mtk-smi-common",
.of_match_table = mtk_smi_common_of_ids,
+ .pm = &smi_common_pm_ops,
}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 07/13] memory: mtk-smi: Invoke pm runtime_callback to enable clocks
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
This patch only move the clk_prepare_enable and config_port into the
runtime suspend/resume callback. It doesn't change the code content
and sequence.
This is a prepare patch for adjusting SMI_BUS_SEL for mt8183.
(SMI_BUS_SEL need to be restored after smi-common resume every time.)
Also it gives a chance to get rid of mtk_smi_larb_get/put which could
be a next topic.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 113 ++++++++++++++++++++++++++++++-----------------
1 file changed, 72 insertions(+), 41 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 697795a..e6a7382 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -78,17 +78,13 @@ enum mtk_smi_gen {
MTK_SMI_GEN2
};
-static int mtk_smi_enable(const struct mtk_smi *smi)
+static int mtk_smi_clk_enable(const struct mtk_smi *smi)
{
int ret;
- ret = pm_runtime_get_sync(smi->dev);
- if (ret < 0)
- return ret;
-
ret = clk_prepare_enable(smi->clk_apb);
if (ret)
- goto err_put_pm;
+ return ret;
ret = clk_prepare_enable(smi->clk_smi);
if (ret)
@@ -110,59 +106,28 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
clk_disable_unprepare(smi->clk_smi);
err_disable_apb:
clk_disable_unprepare(smi->clk_apb);
-err_put_pm:
- pm_runtime_put_sync(smi->dev);
return ret;
}
-static void mtk_smi_disable(const struct mtk_smi *smi)
+static void mtk_smi_clk_disable(const struct mtk_smi *smi)
{
clk_disable_unprepare(smi->clk_gals1);
clk_disable_unprepare(smi->clk_gals0);
clk_disable_unprepare(smi->clk_smi);
clk_disable_unprepare(smi->clk_apb);
- pm_runtime_put_sync(smi->dev);
}
int mtk_smi_larb_get(struct device *larbdev)
{
- struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
- const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
- struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
- int ret;
+ int ret = pm_runtime_get_sync(larbdev);
- /* Enable the smi-common's power and clocks */
- ret = mtk_smi_enable(common);
- if (ret)
- return ret;
-
- /* Enable the larb's power and clocks */
- ret = mtk_smi_enable(&larb->smi);
- if (ret) {
- mtk_smi_disable(common);
- return ret;
- }
-
- /* Configure the iommu info for this larb */
- larb_gen->config_port(larbdev);
-
- return 0;
+ return (ret < 0) ? ret : 0;
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
void mtk_smi_larb_put(struct device *larbdev)
{
- struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
- struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
-
- /*
- * Don't de-configure the iommu info for this larb since there may be
- * several modules in this larb.
- * The iommu info will be reset after power off.
- */
-
- mtk_smi_disable(&larb->smi);
- mtk_smi_disable(common);
+ pm_runtime_put_sync(larbdev);
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
@@ -373,12 +338,52 @@ static int mtk_smi_larb_remove(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+ const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
+ int ret;
+
+ /* Power on smi-common. */
+ ret = pm_runtime_get_sync(larb->smi_common_dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
+ return ret;
+ }
+
+ ret = mtk_smi_clk_enable(&larb->smi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable clock(%d).\n", ret);
+ pm_runtime_put_sync(larb->smi_common_dev);
+ return ret;
+ }
+
+ /* Configure the basic setting for this larb */
+ larb_gen->config_port(dev);
+
+ return 0;
+}
+
+static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+
+ mtk_smi_clk_disable(&larb->smi);
+ pm_runtime_put_sync(larb->smi_common_dev);
+ return 0;
+}
+
+static const struct dev_pm_ops smi_larb_pm_ops = {
+ SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
+};
+
static struct platform_driver mtk_smi_larb_driver = {
.probe = mtk_smi_larb_probe,
.remove = mtk_smi_larb_remove,
.driver = {
.name = "mtk-smi-larb",
.of_match_table = mtk_smi_larb_of_ids,
+ .pm = &smi_larb_pm_ops,
}
};
@@ -467,12 +472,38 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused mtk_smi_common_resume(struct device *dev)
+{
+ struct mtk_smi *common = dev_get_drvdata(dev);
+ int ret;
+
+ ret = mtk_smi_clk_enable(common);
+ if (ret) {
+ dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
+{
+ struct mtk_smi *common = dev_get_drvdata(dev);
+
+ mtk_smi_clk_disable(common);
+ return 0;
+}
+
+static const struct dev_pm_ops smi_common_pm_ops = {
+ SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
+};
+
static struct platform_driver mtk_smi_common_driver = {
.probe = mtk_smi_common_probe,
.remove = mtk_smi_common_remove,
.driver = {
.name = "mtk-smi-common",
.of_match_table = mtk_smi_common_of_ids,
+ .pm = &smi_common_pm_ops,
}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 07/13] memory: mtk-smi: Invoke pm runtime_callback to enable clocks
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This patch only move the clk_prepare_enable and config_port into the
runtime suspend/resume callback. It doesn't change the code content
and sequence.
This is a prepare patch for adjusting SMI_BUS_SEL for mt8183.
(SMI_BUS_SEL need to be restored after smi-common resume every time.)
Also it gives a chance to get rid of mtk_smi_larb_get/put which could
be a next topic.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/memory/mtk-smi.c | 113 ++++++++++++++++++++++++++++++-----------------
1 file changed, 72 insertions(+), 41 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 697795a..e6a7382 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -78,17 +78,13 @@ enum mtk_smi_gen {
MTK_SMI_GEN2
};
-static int mtk_smi_enable(const struct mtk_smi *smi)
+static int mtk_smi_clk_enable(const struct mtk_smi *smi)
{
int ret;
- ret = pm_runtime_get_sync(smi->dev);
- if (ret < 0)
- return ret;
-
ret = clk_prepare_enable(smi->clk_apb);
if (ret)
- goto err_put_pm;
+ return ret;
ret = clk_prepare_enable(smi->clk_smi);
if (ret)
@@ -110,59 +106,28 @@ static int mtk_smi_enable(const struct mtk_smi *smi)
clk_disable_unprepare(smi->clk_smi);
err_disable_apb:
clk_disable_unprepare(smi->clk_apb);
-err_put_pm:
- pm_runtime_put_sync(smi->dev);
return ret;
}
-static void mtk_smi_disable(const struct mtk_smi *smi)
+static void mtk_smi_clk_disable(const struct mtk_smi *smi)
{
clk_disable_unprepare(smi->clk_gals1);
clk_disable_unprepare(smi->clk_gals0);
clk_disable_unprepare(smi->clk_smi);
clk_disable_unprepare(smi->clk_apb);
- pm_runtime_put_sync(smi->dev);
}
int mtk_smi_larb_get(struct device *larbdev)
{
- struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
- const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
- struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
- int ret;
+ int ret = pm_runtime_get_sync(larbdev);
- /* Enable the smi-common's power and clocks */
- ret = mtk_smi_enable(common);
- if (ret)
- return ret;
-
- /* Enable the larb's power and clocks */
- ret = mtk_smi_enable(&larb->smi);
- if (ret) {
- mtk_smi_disable(common);
- return ret;
- }
-
- /* Configure the iommu info for this larb */
- larb_gen->config_port(larbdev);
-
- return 0;
+ return (ret < 0) ? ret : 0;
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
void mtk_smi_larb_put(struct device *larbdev)
{
- struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
- struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
-
- /*
- * Don't de-configure the iommu info for this larb since there may be
- * several modules in this larb.
- * The iommu info will be reset after power off.
- */
-
- mtk_smi_disable(&larb->smi);
- mtk_smi_disable(common);
+ pm_runtime_put_sync(larbdev);
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
@@ -373,12 +338,52 @@ static int mtk_smi_larb_remove(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+ const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
+ int ret;
+
+ /* Power on smi-common. */
+ ret = pm_runtime_get_sync(larb->smi_common_dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
+ return ret;
+ }
+
+ ret = mtk_smi_clk_enable(&larb->smi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable clock(%d).\n", ret);
+ pm_runtime_put_sync(larb->smi_common_dev);
+ return ret;
+ }
+
+ /* Configure the basic setting for this larb */
+ larb_gen->config_port(dev);
+
+ return 0;
+}
+
+static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+
+ mtk_smi_clk_disable(&larb->smi);
+ pm_runtime_put_sync(larb->smi_common_dev);
+ return 0;
+}
+
+static const struct dev_pm_ops smi_larb_pm_ops = {
+ SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
+};
+
static struct platform_driver mtk_smi_larb_driver = {
.probe = mtk_smi_larb_probe,
.remove = mtk_smi_larb_remove,
.driver = {
.name = "mtk-smi-larb",
.of_match_table = mtk_smi_larb_of_ids,
+ .pm = &smi_larb_pm_ops,
}
};
@@ -467,12 +472,38 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
return 0;
}
+static int __maybe_unused mtk_smi_common_resume(struct device *dev)
+{
+ struct mtk_smi *common = dev_get_drvdata(dev);
+ int ret;
+
+ ret = mtk_smi_clk_enable(common);
+ if (ret) {
+ dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
+{
+ struct mtk_smi *common = dev_get_drvdata(dev);
+
+ mtk_smi_clk_disable(common);
+ return 0;
+}
+
+static const struct dev_pm_ops smi_common_pm_ops = {
+ SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
+};
+
static struct platform_driver mtk_smi_common_driver = {
.probe = mtk_smi_common_probe,
.remove = mtk_smi_common_remove,
.driver = {
.name = "mtk-smi-common",
.of_match_table = mtk_smi_common_of_ids,
+ .pm = &smi_common_pm_ops,
}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 08/13] memory: mtk-smi: Use a struct for the platform data for smi-common
2018-09-03 6:01 ` Yong Wu
(?)
@ 2018-09-03 6:01 ` Yong Wu
-1 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
Use a struct as the platform special data instead of the enumeration.
Also there is a minor change that moving the position of
"enum mtk_smi_gen" definition, this is because we expect define
"struct mtk_smi_common_plat" before it is referred.
This is a prepare patch for adding bus_sel for mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 37 +++++++++++++++++++++++++------------
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e6a7382..f306aa8 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -49,6 +49,15 @@
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
+enum mtk_smi_gen {
+ MTK_SMI_GEN1,
+ MTK_SMI_GEN2
+};
+
+struct mtk_smi_common_plat {
+ enum mtk_smi_gen gen;
+};
+
struct mtk_smi_larb_gen {
bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
@@ -62,6 +71,8 @@ struct mtk_smi {
struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
void __iomem *smi_ao_base;
+
+ const struct mtk_smi_common_plat *plat;
};
struct mtk_smi_larb { /* larb: local arbiter */
@@ -73,11 +84,6 @@ struct mtk_smi_larb { /* larb: local arbiter */
u32 *mmu;
};
-enum mtk_smi_gen {
- MTK_SMI_GEN1,
- MTK_SMI_GEN2
-};
-
static int mtk_smi_clk_enable(const struct mtk_smi *smi)
{
int ret;
@@ -387,22 +393,30 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
}
};
+static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
+ .gen = MTK_SMI_GEN1,
+};
+
+static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
+ .gen = MTK_SMI_GEN2,
+};
+
static const struct of_device_id mtk_smi_common_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{
.compatible = "mediatek,mt2701-smi-common",
- .data = (void *)MTK_SMI_GEN1
+ .data = &mtk_smi_common_gen1,
},
{
.compatible = "mediatek,mt2712-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{
.compatible = "mediatek,mt8183-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{}
};
@@ -412,13 +426,13 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct mtk_smi *common;
struct resource *res;
- enum mtk_smi_gen smi_gen;
int ret;
common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
if (!common)
return -ENOMEM;
common->dev = dev;
+ common->plat = of_device_get_match_data(dev);
common->clk_apb = devm_clk_get(dev, "apb");
if (IS_ERR(common->clk_apb))
@@ -446,8 +460,7 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
* clock into emi clock domain, but for mtk smi gen2, there's no smi ao
* base.
*/
- smi_gen = (enum mtk_smi_gen)of_device_get_match_data(dev);
- if (smi_gen == MTK_SMI_GEN1) {
+ if (common->plat->gen == MTK_SMI_GEN1) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
common->smi_ao_base = devm_ioremap_resource(dev, res);
if (IS_ERR(common->smi_ao_base))
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 08/13] memory: mtk-smi: Use a struct for the platform data for smi-common
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Use a struct as the platform special data instead of the enumeration.
Also there is a minor change that moving the position of
"enum mtk_smi_gen" definition, this is because we expect define
"struct mtk_smi_common_plat" before it is referred.
This is a prepare patch for adding bus_sel for mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 37 +++++++++++++++++++++++++------------
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e6a7382..f306aa8 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -49,6 +49,15 @@
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
+enum mtk_smi_gen {
+ MTK_SMI_GEN1,
+ MTK_SMI_GEN2
+};
+
+struct mtk_smi_common_plat {
+ enum mtk_smi_gen gen;
+};
+
struct mtk_smi_larb_gen {
bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
@@ -62,6 +71,8 @@ struct mtk_smi {
struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
void __iomem *smi_ao_base;
+
+ const struct mtk_smi_common_plat *plat;
};
struct mtk_smi_larb { /* larb: local arbiter */
@@ -73,11 +84,6 @@ struct mtk_smi_larb { /* larb: local arbiter */
u32 *mmu;
};
-enum mtk_smi_gen {
- MTK_SMI_GEN1,
- MTK_SMI_GEN2
-};
-
static int mtk_smi_clk_enable(const struct mtk_smi *smi)
{
int ret;
@@ -387,22 +393,30 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
}
};
+static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
+ .gen = MTK_SMI_GEN1,
+};
+
+static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
+ .gen = MTK_SMI_GEN2,
+};
+
static const struct of_device_id mtk_smi_common_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{
.compatible = "mediatek,mt2701-smi-common",
- .data = (void *)MTK_SMI_GEN1
+ .data = &mtk_smi_common_gen1,
},
{
.compatible = "mediatek,mt2712-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{
.compatible = "mediatek,mt8183-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{}
};
@@ -412,13 +426,13 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct mtk_smi *common;
struct resource *res;
- enum mtk_smi_gen smi_gen;
int ret;
common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
if (!common)
return -ENOMEM;
common->dev = dev;
+ common->plat = of_device_get_match_data(dev);
common->clk_apb = devm_clk_get(dev, "apb");
if (IS_ERR(common->clk_apb))
@@ -446,8 +460,7 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
* clock into emi clock domain, but for mtk smi gen2, there's no smi ao
* base.
*/
- smi_gen = (enum mtk_smi_gen)of_device_get_match_data(dev);
- if (smi_gen == MTK_SMI_GEN1) {
+ if (common->plat->gen == MTK_SMI_GEN1) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
common->smi_ao_base = devm_ioremap_resource(dev, res);
if (IS_ERR(common->smi_ao_base))
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 08/13] memory: mtk-smi: Use a struct for the platform data for smi-common
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
Use a struct as the platform special data instead of the enumeration.
Also there is a minor change that moving the position of
"enum mtk_smi_gen" definition, this is because we expect define
"struct mtk_smi_common_plat" before it is referred.
This is a prepare patch for adding bus_sel for mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 37 +++++++++++++++++++++++++------------
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e6a7382..f306aa8 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -49,6 +49,15 @@
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
+enum mtk_smi_gen {
+ MTK_SMI_GEN1,
+ MTK_SMI_GEN2
+};
+
+struct mtk_smi_common_plat {
+ enum mtk_smi_gen gen;
+};
+
struct mtk_smi_larb_gen {
bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
@@ -62,6 +71,8 @@ struct mtk_smi {
struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
void __iomem *smi_ao_base;
+
+ const struct mtk_smi_common_plat *plat;
};
struct mtk_smi_larb { /* larb: local arbiter */
@@ -73,11 +84,6 @@ struct mtk_smi_larb { /* larb: local arbiter */
u32 *mmu;
};
-enum mtk_smi_gen {
- MTK_SMI_GEN1,
- MTK_SMI_GEN2
-};
-
static int mtk_smi_clk_enable(const struct mtk_smi *smi)
{
int ret;
@@ -387,22 +393,30 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
}
};
+static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
+ .gen = MTK_SMI_GEN1,
+};
+
+static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
+ .gen = MTK_SMI_GEN2,
+};
+
static const struct of_device_id mtk_smi_common_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{
.compatible = "mediatek,mt2701-smi-common",
- .data = (void *)MTK_SMI_GEN1
+ .data = &mtk_smi_common_gen1,
},
{
.compatible = "mediatek,mt2712-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{
.compatible = "mediatek,mt8183-smi-common",
- .data = (void *)MTK_SMI_GEN2
+ .data = &mtk_smi_common_gen2,
},
{}
};
@@ -412,13 +426,13 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct mtk_smi *common;
struct resource *res;
- enum mtk_smi_gen smi_gen;
int ret;
common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
if (!common)
return -ENOMEM;
common->dev = dev;
+ common->plat = of_device_get_match_data(dev);
common->clk_apb = devm_clk_get(dev, "apb");
if (IS_ERR(common->clk_apb))
@@ -446,8 +460,7 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
* clock into emi clock domain, but for mtk smi gen2, there's no smi ao
* base.
*/
- smi_gen = (enum mtk_smi_gen)of_device_get_match_data(dev);
- if (smi_gen == MTK_SMI_GEN1) {
+ if (common->plat->gen == MTK_SMI_GEN1) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
common->smi_ao_base = devm_ioremap_resource(dev, res);
if (IS_ERR(common->smi_ao_base))
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 09/13] memory: mtk-smi: Add bus_sel for mt8183
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
mmu0 or mmu1 to balance the bandwidth via the smi-common register
SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).
In mt8183, For better performance, we switch larb1/2/3/7 to enter
mmu1 while the others still keep enter mmu0.
In mt8173 and mt2712, we don't get the performance issue,
Keep its default value(0x0), that means all the larbs enter mmu0.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 29 ++++++++++++++++++++++++++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index f306aa8..31d0431 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -49,6 +49,12 @@
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
+/* SMI COMMON */
+#define SMI_BUS_SEL 0x220
+#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
+/* All are MMU0 defaultly. Only specialize mmu1 here. */
+#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
+
enum mtk_smi_gen {
MTK_SMI_GEN1,
MTK_SMI_GEN2
@@ -56,6 +62,8 @@ enum mtk_smi_gen {
struct mtk_smi_common_plat {
enum mtk_smi_gen gen;
+
+ u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
};
struct mtk_smi_larb_gen {
@@ -70,8 +78,8 @@ struct mtk_smi {
struct clk *clk_apb, *clk_smi;
struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
- void __iomem *smi_ao_base;
-
+ void __iomem *smi_ao_base; /* only for gen1 */
+ void __iomem *base; /* only for gen2 */
const struct mtk_smi_common_plat *plat;
};
@@ -401,6 +409,12 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
.gen = MTK_SMI_GEN2,
};
+static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
+ .gen = MTK_SMI_GEN2,
+ .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(4) |
+ F_MMU1_LARB(7),
+};
+
static const struct of_device_id mtk_smi_common_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-common",
@@ -416,7 +430,7 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
},
{
.compatible = "mediatek,mt8183-smi-common",
- .data = &mtk_smi_common_gen2,
+ .data = &mtk_smi_common_mt8183,
},
{}
};
@@ -473,6 +487,11 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
ret = clk_prepare_enable(common->clk_async);
if (ret)
return ret;
+ } else {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ common->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(common->base))
+ return PTR_ERR(common->base);
}
pm_runtime_enable(dev);
platform_set_drvdata(pdev, common);
@@ -488,6 +507,7 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
static int __maybe_unused mtk_smi_common_resume(struct device *dev)
{
struct mtk_smi *common = dev_get_drvdata(dev);
+ u32 bus_sel = common->plat->bus_sel;
int ret;
ret = mtk_smi_clk_enable(common);
@@ -495,6 +515,9 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev)
dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
return ret;
}
+
+ if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
+ writel(bus_sel, common->base + SMI_BUS_SEL);
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 09/13] memory: mtk-smi: Add bus_sel for mt8183
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
mmu0 or mmu1 to balance the bandwidth via the smi-common register
SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).
In mt8183, For better performance, we switch larb1/2/3/7 to enter
mmu1 while the others still keep enter mmu0.
In mt8173 and mt2712, we don't get the performance issue,
Keep its default value(0x0), that means all the larbs enter mmu0.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 29 ++++++++++++++++++++++++++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index f306aa8..31d0431 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -49,6 +49,12 @@
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
+/* SMI COMMON */
+#define SMI_BUS_SEL 0x220
+#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
+/* All are MMU0 defaultly. Only specialize mmu1 here. */
+#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
+
enum mtk_smi_gen {
MTK_SMI_GEN1,
MTK_SMI_GEN2
@@ -56,6 +62,8 @@ enum mtk_smi_gen {
struct mtk_smi_common_plat {
enum mtk_smi_gen gen;
+
+ u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
};
struct mtk_smi_larb_gen {
@@ -70,8 +78,8 @@ struct mtk_smi {
struct clk *clk_apb, *clk_smi;
struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
- void __iomem *smi_ao_base;
-
+ void __iomem *smi_ao_base; /* only for gen1 */
+ void __iomem *base; /* only for gen2 */
const struct mtk_smi_common_plat *plat;
};
@@ -401,6 +409,12 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
.gen = MTK_SMI_GEN2,
};
+static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
+ .gen = MTK_SMI_GEN2,
+ .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(4) |
+ F_MMU1_LARB(7),
+};
+
static const struct of_device_id mtk_smi_common_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-common",
@@ -416,7 +430,7 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
},
{
.compatible = "mediatek,mt8183-smi-common",
- .data = &mtk_smi_common_gen2,
+ .data = &mtk_smi_common_mt8183,
},
{}
};
@@ -473,6 +487,11 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
ret = clk_prepare_enable(common->clk_async);
if (ret)
return ret;
+ } else {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ common->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(common->base))
+ return PTR_ERR(common->base);
}
pm_runtime_enable(dev);
platform_set_drvdata(pdev, common);
@@ -488,6 +507,7 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
static int __maybe_unused mtk_smi_common_resume(struct device *dev)
{
struct mtk_smi *common = dev_get_drvdata(dev);
+ u32 bus_sel = common->plat->bus_sel;
int ret;
ret = mtk_smi_clk_enable(common);
@@ -495,6 +515,9 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev)
dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
return ret;
}
+
+ if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
+ writel(bus_sel, common->base + SMI_BUS_SEL);
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 09/13] memory: mtk-smi: Add bus_sel for mt8183
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
mmu0 or mmu1 to balance the bandwidth via the smi-common register
SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).
In mt8183, For better performance, we switch larb1/2/3/7 to enter
mmu1 while the others still keep enter mmu0.
In mt8173 and mt2712, we don't get the performance issue,
Keep its default value(0x0), that means all the larbs enter mmu0.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/memory/mtk-smi.c | 29 ++++++++++++++++++++++++++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index f306aa8..31d0431 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -49,6 +49,12 @@
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
+/* SMI COMMON */
+#define SMI_BUS_SEL 0x220
+#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
+/* All are MMU0 defaultly. Only specialize mmu1 here. */
+#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
+
enum mtk_smi_gen {
MTK_SMI_GEN1,
MTK_SMI_GEN2
@@ -56,6 +62,8 @@ enum mtk_smi_gen {
struct mtk_smi_common_plat {
enum mtk_smi_gen gen;
+
+ u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
};
struct mtk_smi_larb_gen {
@@ -70,8 +78,8 @@ struct mtk_smi {
struct clk *clk_apb, *clk_smi;
struct clk *clk_gals0, *clk_gals1;
struct clk *clk_async; /*only needed by mt2701*/
- void __iomem *smi_ao_base;
-
+ void __iomem *smi_ao_base; /* only for gen1 */
+ void __iomem *base; /* only for gen2 */
const struct mtk_smi_common_plat *plat;
};
@@ -401,6 +409,12 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
.gen = MTK_SMI_GEN2,
};
+static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
+ .gen = MTK_SMI_GEN2,
+ .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(4) |
+ F_MMU1_LARB(7),
+};
+
static const struct of_device_id mtk_smi_common_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-common",
@@ -416,7 +430,7 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
},
{
.compatible = "mediatek,mt8183-smi-common",
- .data = &mtk_smi_common_gen2,
+ .data = &mtk_smi_common_mt8183,
},
{}
};
@@ -473,6 +487,11 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
ret = clk_prepare_enable(common->clk_async);
if (ret)
return ret;
+ } else {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ common->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(common->base))
+ return PTR_ERR(common->base);
}
pm_runtime_enable(dev);
platform_set_drvdata(pdev, common);
@@ -488,6 +507,7 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
static int __maybe_unused mtk_smi_common_resume(struct device *dev)
{
struct mtk_smi *common = dev_get_drvdata(dev);
+ u32 bus_sel = common->plat->bus_sel;
int ret;
ret = mtk_smi_clk_enable(common);
@@ -495,6 +515,9 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev)
dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
return ret;
}
+
+ if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
+ writel(bus_sel, common->base + SMI_BUS_SEL);
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 10/13] iommu/mediatek: Add VLD_PA_RANGE register backup when suspend
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
The register VLD_PA_RNG(0x118) was forgot to backup while adding 4GB
mode support for mt2712. this patch add it.
Fixes: 30e2fccf9512 ("iommu/mediatek: Enlarge the validate PA range
for 4GB mode")
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 2 ++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index e9665ad..2f907dd 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -733,6 +733,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
+ reg->vld_pa_range = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
clk_disable_unprepare(data->bclk);
return 0;
}
@@ -757,6 +758,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
+ writel_relaxed(reg->vld_pa_range, base + REG_MMU_VLD_PA_RNG);
if (m4u_dom)
writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
base + REG_MMU_PT_BASE_ADDR);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 8bf76be..1b423fe 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -33,6 +33,7 @@ struct mtk_iommu_suspend_reg {
u32 int_control0;
u32 int_main_control;
u32 ivrp_paddr;
+ u32 vld_pa_range;
};
enum mtk_iommu_plat {
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 10/13] iommu/mediatek: Add VLD_PA_RANGE register backup when suspend
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
The register VLD_PA_RNG(0x118) was forgot to backup while adding 4GB
mode support for mt2712. this patch add it.
Fixes: 30e2fccf9512 ("iommu/mediatek: Enlarge the validate PA range
for 4GB mode")
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 2 ++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index e9665ad..2f907dd 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -733,6 +733,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
+ reg->vld_pa_range = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
clk_disable_unprepare(data->bclk);
return 0;
}
@@ -757,6 +758,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
+ writel_relaxed(reg->vld_pa_range, base + REG_MMU_VLD_PA_RNG);
if (m4u_dom)
writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
base + REG_MMU_PT_BASE_ADDR);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 8bf76be..1b423fe 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -33,6 +33,7 @@ struct mtk_iommu_suspend_reg {
u32 int_control0;
u32 int_main_control;
u32 ivrp_paddr;
+ u32 vld_pa_range;
};
enum mtk_iommu_plat {
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 10/13] iommu/mediatek: Add VLD_PA_RANGE register backup when suspend
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
The register VLD_PA_RNG(0x118) was forgot to backup while adding 4GB
mode support for mt2712. this patch add it.
Fixes: 30e2fccf9512 ("iommu/mediatek: Enlarge the validate PA range
for 4GB mode")
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 2 ++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index e9665ad..2f907dd 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -733,6 +733,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
+ reg->vld_pa_range = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
clk_disable_unprepare(data->bclk);
return 0;
}
@@ -757,6 +758,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
+ writel_relaxed(reg->vld_pa_range, base + REG_MMU_VLD_PA_RNG);
if (m4u_dom)
writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
base + REG_MMU_PT_BASE_ADDR);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 8bf76be..1b423fe 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -33,6 +33,7 @@ struct mtk_iommu_suspend_reg {
u32 int_control0;
u32 int_main_control;
u32 ivrp_paddr;
+ u32 vld_pa_range;
};
enum mtk_iommu_plat {
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 11/13] iommu/mediatek: Add shutdown callback
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
In the reboot burning test, if some Multimedia HW has something wrong,
It may keep send the invalid request to IOMMU. In order to avoid
affect the reboot flow, we add the shutdown callback to disable
M4U HW when shutdown.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 2f907dd..dd7521c 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -720,6 +720,11 @@ static int mtk_iommu_remove(struct platform_device *pdev)
return 0;
}
+static void mtk_iommu_shutdown(struct platform_device *pdev)
+{
+ mtk_iommu_remove(pdev);
+}
+
static int __maybe_unused mtk_iommu_suspend(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
@@ -795,6 +800,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
static struct platform_driver mtk_iommu_driver = {
.probe = mtk_iommu_probe,
.remove = mtk_iommu_remove,
+ .shutdown = mtk_iommu_shutdown,
.driver = {
.name = "mtk-iommu",
.of_match_table = of_match_ptr(mtk_iommu_of_ids),
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 11/13] iommu/mediatek: Add shutdown callback
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
In the reboot burning test, if some Multimedia HW has something wrong,
It may keep send the invalid request to IOMMU. In order to avoid
affect the reboot flow, we add the shutdown callback to disable
M4U HW when shutdown.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 2f907dd..dd7521c 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -720,6 +720,11 @@ static int mtk_iommu_remove(struct platform_device *pdev)
return 0;
}
+static void mtk_iommu_shutdown(struct platform_device *pdev)
+{
+ mtk_iommu_remove(pdev);
+}
+
static int __maybe_unused mtk_iommu_suspend(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
@@ -795,6 +800,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
static struct platform_driver mtk_iommu_driver = {
.probe = mtk_iommu_probe,
.remove = mtk_iommu_remove,
+ .shutdown = mtk_iommu_shutdown,
.driver = {
.name = "mtk-iommu",
.of_match_table = of_match_ptr(mtk_iommu_of_ids),
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 11/13] iommu/mediatek: Add shutdown callback
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In the reboot burning test, if some Multimedia HW has something wrong,
It may keep send the invalid request to IOMMU. In order to avoid
affect the reboot flow, we add the shutdown callback to disable
M4U HW when shutdown.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 2f907dd..dd7521c 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -720,6 +720,11 @@ static int mtk_iommu_remove(struct platform_device *pdev)
return 0;
}
+static void mtk_iommu_shutdown(struct platform_device *pdev)
+{
+ mtk_iommu_remove(pdev);
+}
+
static int __maybe_unused mtk_iommu_suspend(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
@@ -795,6 +800,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
static struct platform_driver mtk_iommu_driver = {
.probe = mtk_iommu_probe,
.remove = mtk_iommu_remove,
+ .shutdown = mtk_iommu_shutdown,
.driver = {
.name = "mtk-iommu",
.of_match_table = of_match_ptr(mtk_iommu_of_ids),
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 12/13] memory: mtk-smi: Get rid of need_larbid
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
It's no need to parse it again in SMI driver. Only clean some codes.
This patch is fit for all the current mt2701, mt2712, mt8173 and
mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 27 ++-------------------------
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 31d0431..1a00f5b 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -67,7 +67,6 @@ struct mtk_smi_common_plat {
};
struct mtk_smi_larb_gen {
- bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
void (*config_port)(struct device *);
unsigned int larb_special_mask; /* The special larbs mask. */
@@ -152,18 +151,9 @@ void mtk_smi_larb_put(struct device *larbdev)
struct mtk_smi_iommu *smi_iommu = data;
unsigned int i;
- if (larb->larb_gen->need_larbid) {
- larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
- return 0;
- }
-
- /*
- * If there is no larbid property, Loop to find the corresponding
- * iommu information.
- */
- for (i = 0; i < smi_iommu->larb_nr; i++) {
+ for (i = 0; i < MTK_LARB_NR_MAX; i++) {
if (dev == smi_iommu->larb_imu[i].dev) {
- /* The 'mmu' may be updated in iommu-attach/detach. */
+ larb->larbid = i;
larb->mmu = &smi_iommu->larb_imu[i].mmu;
return 0;
}
@@ -242,7 +232,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
- .need_larbid = true,
.port_in_larb = {
LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
@@ -251,13 +240,11 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
- .need_larbid = true,
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
- .need_larbid = true,
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_special_mask = BIT(7), /* CCU */
};
@@ -289,7 +276,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *smi_node;
struct platform_device *smi_pdev;
- int err;
larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
if (!larb)
@@ -316,15 +302,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
return PTR_ERR(larb->smi.clk_gals0);
larb->smi.dev = dev;
- if (larb->larb_gen->need_larbid) {
- err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
- &larb->larbid);
- if (err) {
- dev_err(dev, "missing larbid property\n");
- return err;
- }
- }
-
smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
if (!smi_node)
return -EINVAL;
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 12/13] memory: mtk-smi: Get rid of need_larbid
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
It's no need to parse it again in SMI driver. Only clean some codes.
This patch is fit for all the current mt2701, mt2712, mt8173 and
mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 27 ++-------------------------
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 31d0431..1a00f5b 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -67,7 +67,6 @@ struct mtk_smi_common_plat {
};
struct mtk_smi_larb_gen {
- bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
void (*config_port)(struct device *);
unsigned int larb_special_mask; /* The special larbs mask. */
@@ -152,18 +151,9 @@ void mtk_smi_larb_put(struct device *larbdev)
struct mtk_smi_iommu *smi_iommu = data;
unsigned int i;
- if (larb->larb_gen->need_larbid) {
- larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
- return 0;
- }
-
- /*
- * If there is no larbid property, Loop to find the corresponding
- * iommu information.
- */
- for (i = 0; i < smi_iommu->larb_nr; i++) {
+ for (i = 0; i < MTK_LARB_NR_MAX; i++) {
if (dev == smi_iommu->larb_imu[i].dev) {
- /* The 'mmu' may be updated in iommu-attach/detach. */
+ larb->larbid = i;
larb->mmu = &smi_iommu->larb_imu[i].mmu;
return 0;
}
@@ -242,7 +232,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
- .need_larbid = true,
.port_in_larb = {
LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
@@ -251,13 +240,11 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
- .need_larbid = true,
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
- .need_larbid = true,
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_special_mask = BIT(7), /* CCU */
};
@@ -289,7 +276,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *smi_node;
struct platform_device *smi_pdev;
- int err;
larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
if (!larb)
@@ -316,15 +302,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
return PTR_ERR(larb->smi.clk_gals0);
larb->smi.dev = dev;
- if (larb->larb_gen->need_larbid) {
- err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
- &larb->larbid);
- if (err) {
- dev_err(dev, "missing larbid property\n");
- return err;
- }
- }
-
smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
if (!smi_node)
return -EINVAL;
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH 12/13] memory: mtk-smi: Get rid of need_larbid
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
It's no need to parse it again in SMI driver. Only clean some codes.
This patch is fit for all the current mt2701, mt2712, mt8173 and
mt8183.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/memory/mtk-smi.c | 27 ++-------------------------
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 31d0431..1a00f5b 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -67,7 +67,6 @@ struct mtk_smi_common_plat {
};
struct mtk_smi_larb_gen {
- bool need_larbid;
int port_in_larb[MTK_LARB_NR_MAX + 1];
void (*config_port)(struct device *);
unsigned int larb_special_mask; /* The special larbs mask. */
@@ -152,18 +151,9 @@ void mtk_smi_larb_put(struct device *larbdev)
struct mtk_smi_iommu *smi_iommu = data;
unsigned int i;
- if (larb->larb_gen->need_larbid) {
- larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
- return 0;
- }
-
- /*
- * If there is no larbid property, Loop to find the corresponding
- * iommu information.
- */
- for (i = 0; i < smi_iommu->larb_nr; i++) {
+ for (i = 0; i < MTK_LARB_NR_MAX; i++) {
if (dev == smi_iommu->larb_imu[i].dev) {
- /* The 'mmu' may be updated in iommu-attach/detach. */
+ larb->larbid = i;
larb->mmu = &smi_iommu->larb_imu[i].mmu;
return 0;
}
@@ -242,7 +232,6 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
- .need_larbid = true,
.port_in_larb = {
LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
@@ -251,13 +240,11 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
- .need_larbid = true,
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_special_mask = BIT(8) | BIT(9), /* bdpsys */
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
- .need_larbid = true,
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_special_mask = BIT(7), /* CCU */
};
@@ -289,7 +276,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *smi_node;
struct platform_device *smi_pdev;
- int err;
larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
if (!larb)
@@ -316,15 +302,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
return PTR_ERR(larb->smi.clk_gals0);
larb->smi.dev = dev;
- if (larb->larb_gen->need_larbid) {
- err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
- &larb->larbid);
- if (err) {
- dev_err(dev, "missing larbid property\n");
- return err;
- }
- }
-
smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
if (!smi_node)
return -EINVAL;
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 13/13] iommu/mediatek: Switch to SPDX license identifier
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: Tomasz Figa, Will Deacon, Daniel Kurtz, linux-mediatek,
srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
iommu, arnd, yingjoe.chen, yong.wu
Switch to SPDX license identifier for MediaTek iommu/smi and their
header files.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 10 +---------
drivers/iommu/mtk_iommu.h | 10 +---------
drivers/iommu/mtk_iommu_v1.c | 10 +---------
drivers/memory/mtk-smi.c | 10 +---------
include/dt-bindings/memory/mt2701-larb-port.h | 10 +---------
include/dt-bindings/memory/mt8173-larb-port.h | 10 +---------
include/soc/mediatek/smi.h | 10 +---------
7 files changed, 7 insertions(+), 63 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index dd7521c..6e4209e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/bootmem.h>
#include <linux/bug.h>
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 1b423fe..856c10d 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MTK_IOMMU_H_
diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
index 676c029..f477300 100644
--- a/drivers/iommu/mtk_iommu_v1.c
+++ b/drivers/iommu/mtk_iommu_v1.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang@mediatek.com>
*
* Based on driver/iommu/mtk_iommu.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/bootmem.h>
#include <linux/bug.h>
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 1a00f5b..a053295 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/component.h>
diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h
index 6764d74..c511f0f 100644
--- a/include/dt-bindings/memory/mt2701-larb-port.h
+++ b/include/dt-bindings/memory/mt2701-larb-port.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MT2701_LARB_PORT_H_
diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h
index 111b4b0..a62bfeb 100644
--- a/include/dt-bindings/memory/mt8173-larb-port.h
+++ b/include/dt-bindings/memory/mt8173-larb-port.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __DTS_IOMMU_PORT_MT8173_H
#define __DTS_IOMMU_PORT_MT8173_H
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index 5201e90..2b410d2 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef MTK_IOMMU_SMI_H
#define MTK_IOMMU_SMI_H
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 13/13] iommu/mediatek: Switch to SPDX license identifier
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Switch to SPDX license identifier for MediaTek iommu/smi and their
header files.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 10 +---------
drivers/iommu/mtk_iommu.h | 10 +---------
drivers/iommu/mtk_iommu_v1.c | 10 +---------
drivers/memory/mtk-smi.c | 10 +---------
include/dt-bindings/memory/mt2701-larb-port.h | 10 +---------
include/dt-bindings/memory/mt8173-larb-port.h | 10 +---------
include/soc/mediatek/smi.h | 10 +---------
7 files changed, 7 insertions(+), 63 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index dd7521c..6e4209e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/bootmem.h>
#include <linux/bug.h>
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 1b423fe..856c10d 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MTK_IOMMU_H_
diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
index 676c029..f477300 100644
--- a/drivers/iommu/mtk_iommu_v1.c
+++ b/drivers/iommu/mtk_iommu_v1.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang@mediatek.com>
*
* Based on driver/iommu/mtk_iommu.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/bootmem.h>
#include <linux/bug.h>
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 1a00f5b..a053295 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/component.h>
diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h
index 6764d74..c511f0f 100644
--- a/include/dt-bindings/memory/mt2701-larb-port.h
+++ b/include/dt-bindings/memory/mt2701-larb-port.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MT2701_LARB_PORT_H_
diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h
index 111b4b0..a62bfeb 100644
--- a/include/dt-bindings/memory/mt8173-larb-port.h
+++ b/include/dt-bindings/memory/mt8173-larb-port.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __DTS_IOMMU_PORT_MT8173_H
#define __DTS_IOMMU_PORT_MT8173_H
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index 5201e90..2b410d2 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef MTK_IOMMU_SMI_H
#define MTK_IOMMU_SMI_H
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH 13/13] iommu/mediatek: Switch to SPDX license identifier
@ 2018-09-03 6:01 ` Yong Wu
0 siblings, 0 replies; 61+ messages in thread
From: Yong Wu @ 2018-09-03 6:01 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Daniel Kurtz,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Switch to SPDX license identifier for MediaTek iommu/smi and their
header files.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 10 +---------
drivers/iommu/mtk_iommu.h | 10 +---------
drivers/iommu/mtk_iommu_v1.c | 10 +---------
drivers/memory/mtk-smi.c | 10 +---------
include/dt-bindings/memory/mt2701-larb-port.h | 10 +---------
include/dt-bindings/memory/mt8173-larb-port.h | 10 +---------
include/soc/mediatek/smi.h | 10 +---------
7 files changed, 7 insertions(+), 63 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index dd7521c..6e4209e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/bootmem.h>
#include <linux/bug.h>
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 1b423fe..856c10d 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MTK_IOMMU_H_
diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
index 676c029..f477300 100644
--- a/drivers/iommu/mtk_iommu_v1.c
+++ b/drivers/iommu/mtk_iommu_v1.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
*
* Based on driver/iommu/mtk_iommu.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/bootmem.h>
#include <linux/bug.h>
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 1a00f5b..a053295 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/component.h>
diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h
index 6764d74..c511f0f 100644
--- a/include/dt-bindings/memory/mt2701-larb-port.h
+++ b/include/dt-bindings/memory/mt2701-larb-port.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MT2701_LARB_PORT_H_
diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h
index 111b4b0..a62bfeb 100644
--- a/include/dt-bindings/memory/mt8173-larb-port.h
+++ b/include/dt-bindings/memory/mt8173-larb-port.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __DTS_IOMMU_PORT_MT8173_H
#define __DTS_IOMMU_PORT_MT8173_H
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index 5201e90..2b410d2 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef MTK_IOMMU_SMI_H
#define MTK_IOMMU_SMI_H
--
1.9.1
^ permalink raw reply related [flat|nested] 61+ messages in thread
[parent not found: <1535954502-30646-14-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH 13/13] iommu/mediatek: Switch to SPDX license identifier
2018-09-03 6:01 ` Yong Wu
@ 2018-09-17 5:44 ` Rob Herring
-1 siblings, 0 replies; 61+ messages in thread
From: Rob Herring @ 2018-09-17 5:44 UTC (permalink / raw)
To: Yong Wu
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Will Deacon,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomasz Figa,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Daniel Kurtz,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, Matthias Brugger,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Robin Murphy,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, 3 Sep 2018 14:01:42 +0800, Yong Wu wrote:
> Switch to SPDX license identifier for MediaTek iommu/smi and their
> header files.
>
> Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> drivers/iommu/mtk_iommu.c | 10 +---------
> drivers/iommu/mtk_iommu.h | 10 +---------
> drivers/iommu/mtk_iommu_v1.c | 10 +---------
> drivers/memory/mtk-smi.c | 10 +---------
> include/dt-bindings/memory/mt2701-larb-port.h | 10 +---------
> include/dt-bindings/memory/mt8173-larb-port.h | 10 +---------
> include/soc/mediatek/smi.h | 10 +---------
> 7 files changed, 7 insertions(+), 63 deletions(-)
>
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH 13/13] iommu/mediatek: Switch to SPDX license identifier
@ 2018-09-17 5:44 ` Rob Herring
0 siblings, 0 replies; 61+ messages in thread
From: Rob Herring @ 2018-09-17 5:44 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 3 Sep 2018 14:01:42 +0800, Yong Wu wrote:
> Switch to SPDX license identifier for MediaTek iommu/smi and their
> header files.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 10 +---------
> drivers/iommu/mtk_iommu.h | 10 +---------
> drivers/iommu/mtk_iommu_v1.c | 10 +---------
> drivers/memory/mtk-smi.c | 10 +---------
> include/dt-bindings/memory/mt2701-larb-port.h | 10 +---------
> include/dt-bindings/memory/mt8173-larb-port.h | 10 +---------
> include/soc/mediatek/smi.h | 10 +---------
> 7 files changed, 7 insertions(+), 63 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 61+ messages in thread