* [PATCH 0/2] drm/i915: fix edp link training, hopefully @ 2014-04-22 17:17 Jani Nikula 2014-04-22 17:17 ` [PATCH 1/2] drm/i915: clean up VBT eDP link param decoding Jani Nikula 2014-04-22 17:17 ` [PATCH 2/2] drm/i915: use lane count and link rate from VBT as minimums for eDP Jani Nikula 0 siblings, 2 replies; 4+ messages in thread From: Jani Nikula @ 2014-04-22 17:17 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula These are RFC-ish patches to use link params from VBT for eDP, to hopefully fix issues related to preferring fast over wide lane configuration with some eDP panels. Untested, as I don't have hw that actually fails. BR, Jani. Jani Nikula (2): drm/i915: clean up VBT eDP link param decoding drm/i915: use lane count and link rate from VBT as minimums for eDP drivers/gpu/drm/i915/intel_bios.c | 52 ++++++++++++++++++++++++++++----------- drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++------ 2 files changed, 54 insertions(+), 21 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] drm/i915: clean up VBT eDP link param decoding 2014-04-22 17:17 [PATCH 0/2] drm/i915: fix edp link training, hopefully Jani Nikula @ 2014-04-22 17:17 ` Jani Nikula 2014-04-22 17:17 ` [PATCH 2/2] drm/i915: use lane count and link rate from VBT as minimums for eDP Jani Nikula 1 sibling, 0 replies; 4+ messages in thread From: Jani Nikula @ 2014-04-22 17:17 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_bios.c | 52 ++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index fba9efd09e87..87a1fa6485be 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -592,47 +592,71 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) dev_priv->vbt.edp_pps = *edp_pps; - dev_priv->vbt.edp_rate = edp_link_params->rate ? DP_LINK_BW_2_7 : - DP_LINK_BW_1_62; + switch (edp_link_params->rate) { + case EDP_RATE_1_62: + dev_priv->vbt.edp_rate = DP_LINK_BW_1_62; + break; + case EDP_RATE_2_7: + dev_priv->vbt.edp_rate = DP_LINK_BW_2_7; + break; + default: + DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n", + edp_link_params->rate); + break; + } + switch (edp_link_params->lanes) { - case 0: + case EDP_LANE_1: dev_priv->vbt.edp_lanes = 1; break; - case 1: + case EDP_LANE_2: dev_priv->vbt.edp_lanes = 2; break; - case 3: - default: + case EDP_LANE_4: dev_priv->vbt.edp_lanes = 4; break; + default: + DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n", + edp_link_params->lanes); + break; } + switch (edp_link_params->preemphasis) { - case 0: + case EDP_PREEMPHASIS_NONE: dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0; break; - case 1: + case EDP_PREEMPHASIS_3_5dB: dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5; break; - case 2: + case EDP_PREEMPHASIS_6dB: dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6; break; - case 3: + case EDP_PREEMPHASIS_9_5dB: dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5; break; + default: + DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n", + edp_link_params->preemphasis); + break; } + switch (edp_link_params->vswing) { - case 0: + case EDP_VSWING_0_4V: dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400; break; - case 1: + case EDP_VSWING_0_6V: dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600; break; - case 2: + case EDP_VSWING_0_8V: dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800; break; - case 3: + case EDP_VSWING_1_2V: dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200; break; + default: + DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n", + edp_link_params->vswing); + break; } } -- 1.9.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/i915: use lane count and link rate from VBT as minimums for eDP 2014-04-22 17:17 [PATCH 0/2] drm/i915: fix edp link training, hopefully Jani Nikula 2014-04-22 17:17 ` [PATCH 1/2] drm/i915: clean up VBT eDP link param decoding Jani Nikula @ 2014-04-22 17:17 ` Jani Nikula 2014-04-22 21:00 ` Daniel Vetter 1 sibling, 1 reply; 4+ messages in thread From: Jani Nikula @ 2014-04-22 17:17 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Most likely the minimums for both should be enough for enabling the native resolution on the eDP. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73539 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76711 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 80e5598d66ed..c613da9cb1a9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -764,8 +764,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc *intel_crtc = encoder->new_crtc; struct intel_connector *intel_connector = intel_dp->attached_connector; int lane_count, clock; + int min_lane_count = 1; int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); /* Conveniently, the link BW constants become indices with a shift...*/ + int min_clock = 0; int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; int bpp, mode_rate; static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; @@ -798,19 +800,26 @@ intel_dp_compute_config(struct intel_encoder *encoder, /* Walk through all bpp values. Luckily they're all nicely spaced with 2 * bpc in between. */ bpp = pipe_config->pipe_bpp; - if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && - dev_priv->vbt.edp_bpp < bpp) { - DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", - dev_priv->vbt.edp_bpp); - bpp = dev_priv->vbt.edp_bpp; + if (is_edp(intel_dp)) { + if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { + DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", + dev_priv->vbt.edp_bpp); + bpp = dev_priv->vbt.edp_bpp; + } + + if (dev_priv->vbt.edp_lanes) + min_lane_count = min(dev_priv->vbt.edp_lanes, + max_lane_count); + if (dev_priv->vbt.edp_rate) + min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); } for (; bpp >= 6*3; bpp -= 2*3) { mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, bpp); - for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { - for (clock = 0; clock <= max_clock; clock++) { + for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { + for (clock = min_clock; clock <= max_clock; clock++) { link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); link_avail = intel_dp_max_data_rate(link_clock, lane_count); -- 1.9.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/i915: use lane count and link rate from VBT as minimums for eDP 2014-04-22 17:17 ` [PATCH 2/2] drm/i915: use lane count and link rate from VBT as minimums for eDP Jani Nikula @ 2014-04-22 21:00 ` Daniel Vetter 0 siblings, 0 replies; 4+ messages in thread From: Daniel Vetter @ 2014-04-22 21:00 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Tue, Apr 22, 2014 at 08:17:52PM +0300, Jani Nikula wrote: > Most likely the minimums for both should be enough for enabling the > native resolution on the eDP. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73539 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76711 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Markus Blank-Burian <burian@muenster.de> > --- > drivers/gpu/drm/i915/intel_dp.c | 23 ++++++++++++++++------- > 1 file changed, 16 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 80e5598d66ed..c613da9cb1a9 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -764,8 +764,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, > struct intel_crtc *intel_crtc = encoder->new_crtc; > struct intel_connector *intel_connector = intel_dp->attached_connector; > int lane_count, clock; > + int min_lane_count = 1; > int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); > /* Conveniently, the link BW constants become indices with a shift...*/ > + int min_clock = 0; > int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; > int bpp, mode_rate; > static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; > @@ -798,19 +800,26 @@ intel_dp_compute_config(struct intel_encoder *encoder, > /* Walk through all bpp values. Luckily they're all nicely spaced with 2 > * bpc in between. */ > bpp = pipe_config->pipe_bpp; > - if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && > - dev_priv->vbt.edp_bpp < bpp) { > - DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", > - dev_priv->vbt.edp_bpp); > - bpp = dev_priv->vbt.edp_bpp; > + if (is_edp(intel_dp)) { > + if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { > + DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", > + dev_priv->vbt.edp_bpp); > + bpp = dev_priv->vbt.edp_bpp; > + } > + > + if (dev_priv->vbt.edp_lanes) > + min_lane_count = min(dev_priv->vbt.edp_lanes, > + max_lane_count); > + if (dev_priv->vbt.edp_rate) > + min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); > } > > for (; bpp >= 6*3; bpp -= 2*3) { > mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, > bpp); > > - for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { > - for (clock = 0; clock <= max_clock; clock++) { > + for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { > + for (clock = min_clock; clock <= max_clock; clock++) { > link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); > link_avail = intel_dp_max_data_rate(link_clock, > lane_count); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-04-22 21:00 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2014-04-22 17:17 [PATCH 0/2] drm/i915: fix edp link training, hopefully Jani Nikula 2014-04-22 17:17 ` [PATCH 1/2] drm/i915: clean up VBT eDP link param decoding Jani Nikula 2014-04-22 17:17 ` [PATCH 2/2] drm/i915: use lane count and link rate from VBT as minimums for eDP Jani Nikula 2014-04-22 21:00 ` Daniel Vetter
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