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* [PATCH 1/2] ram: k3-ddrss: Fix register name and explain its usage
@ 2022-03-22 12:11 Dominic Rath
  2022-03-22 14:38 ` Dave Gerlach
  2022-04-04 18:51 ` Tom Rini
  0 siblings, 2 replies; 5+ messages in thread
From: Dominic Rath @ 2022-03-22 12:11 UTC (permalink / raw)
  To: u-boot, d-gerlach, trini, christian.gmeiner

The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
default that says 8 GB, which the AM64x DDR controller wouldn't support).

The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG
was that of the next register at offset 0x24.

Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>
---
  drivers/ram/k3-ddrss/k3-ddrss.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c 
b/drivers/ram/k3-ddrss/k3-ddrss.c
index 25e3976e65..261ba64506 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -27,7 +27,7 @@
  #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS	0x80
  #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS	0xc0
  -#define DDRSS_V2A_R1_MAT_REG			0x0020
+#define DDRSS_V2A_CTL_REG			0x0020
  #define DDRSS_ECC_CTRL_REG			0x0120
   #define SINGLE_DDR_SUBSYSTEM	0x1
@@ -529,8 +529,8 @@ static int k3_ddrss_probe(struct udevice *dev)
  		return ret;
   #ifdef CONFIG_K3_AM64_DDRSS
-
-	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
+	/* AM64x supports only up to 2 GB SDRAM */
+	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
  	writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
  #endif
  -- 2.35.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ram: k3-ddrss: Fix register name and explain its usage
  2022-03-22 12:11 [PATCH 1/2] ram: k3-ddrss: Fix register name and explain its usage Dominic Rath
@ 2022-03-22 14:38 ` Dave Gerlach
  2022-04-04 18:51 ` Tom Rini
  1 sibling, 0 replies; 5+ messages in thread
From: Dave Gerlach @ 2022-03-22 14:38 UTC (permalink / raw)
  To: Dominic Rath, u-boot, trini, christian.gmeiner

Hi,

On 3/22/22 07:11, Dominic Rath wrote:
> The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
> the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
> default that says 8 GB, which the AM64x DDR controller wouldn't support).
> 
> The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG
> was that of the next register at offset 0x24.
> 
> Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>

This patch looks good to me.

Acked-by: Dave Gerlach <d-gerlach@ti.com>

> ---
>   drivers/ram/k3-ddrss/k3-ddrss.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c 
> b/drivers/ram/k3-ddrss/k3-ddrss.c
> index 25e3976e65..261ba64506 100644
> --- a/drivers/ram/k3-ddrss/k3-ddrss.c
> +++ b/drivers/ram/k3-ddrss/k3-ddrss.c
> @@ -27,7 +27,7 @@
>   #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS	0x80
>   #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS	0xc0
>   -#define DDRSS_V2A_R1_MAT_REG			0x0020
> +#define DDRSS_V2A_CTL_REG			0x0020
>   #define DDRSS_ECC_CTRL_REG			0x0120
>    #define SINGLE_DDR_SUBSYSTEM	0x1
> @@ -529,8 +529,8 @@ static int k3_ddrss_probe(struct udevice *dev)
>   		return ret;
>    #ifdef CONFIG_K3_AM64_DDRSS
> -
> -	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
> +	/* AM64x supports only up to 2 GB SDRAM */
> +	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
>   	writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
>   #endif
>   -- 2.35.1
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ram: k3-ddrss: Fix register name and explain its usage
  2022-03-22 12:11 [PATCH 1/2] ram: k3-ddrss: Fix register name and explain its usage Dominic Rath
  2022-03-22 14:38 ` Dave Gerlach
@ 2022-04-04 18:51 ` Tom Rini
  2022-04-06  9:56   ` [PATCH v2] " Dominic Rath
  1 sibling, 1 reply; 5+ messages in thread
From: Tom Rini @ 2022-04-04 18:51 UTC (permalink / raw)
  To: Dominic Rath; +Cc: u-boot, d-gerlach, christian.gmeiner

[-- Attachment #1: Type: text/plain, Size: 1631 bytes --]

On Tue, Mar 22, 2022 at 01:11:17PM +0100, Dominic Rath wrote:

> The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
> the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
> default that says 8 GB, which the AM64x DDR controller wouldn't support).
> 
> The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG
> was that of the next register at offset 0x24.
> 
> Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>
> Acked-by: Dave Gerlach <d-gerlach@ti.com>
> ---
>   drivers/ram/k3-ddrss/k3-ddrss.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
>    #ifdef CONFIG_K3_AM64_DDRSS
> -
> -	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
> +	/* AM64x supports only up to 2 GB SDRAM */
> +	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
>   	writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
>   #endif
>   -- 2.35.1
> 
> diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c 
> b/drivers/ram/k3-ddrss/k3-ddrss.c
> index 25e3976e65..261ba64506 100644
> --- a/drivers/ram/k3-ddrss/k3-ddrss.c
> +++ b/drivers/ram/k3-ddrss/k3-ddrss.c
> @@ -27,7 +27,7 @@
>   #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS	0x80
>   #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS	0xc0
>   -#define DDRSS_V2A_R1_MAT_REG			0x0020
> +#define DDRSS_V2A_CTL_REG			0x0020
>   #define DDRSS_ECC_CTRL_REG			0x0120
>    #define SINGLE_DDR_SUBSYSTEM	0x1
> @@ -529,8 +529,8 @@ static int k3_ddrss_probe(struct udevice *dev)
>   		return ret;

Please re-format and resubmit the patch, the spacing has gone very
wrong, thanks

-- 
Tom

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^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2] ram: k3-ddrss: Fix register name and explain its usage
  2022-04-04 18:51 ` Tom Rini
@ 2022-04-06  9:56   ` Dominic Rath
  2022-04-20 19:23     ` Tom Rini
  0 siblings, 1 reply; 5+ messages in thread
From: Dominic Rath @ 2022-04-06  9:56 UTC (permalink / raw)
  To: u-boot; +Cc: trini, christian.gmeiner, d-gerlach, dominic.rath, Dominic Rath

From: Dominic Rath <rath@ibv-augsburg.net>

The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
default that says 8 GB, which the AM64x DDR controller wouldn't support).

The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG
was that of the next register at offset 0x24.

Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>
---
Changes for v2:
- re-formatted patch

 drivers/ram/k3-ddrss/k3-ddrss.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 2467f122a8..6217f98b33 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -30,7 +30,7 @@
 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS	0x80
 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS	0xc0
 
-#define DDRSS_V2A_R1_MAT_REG			0x0020
+#define DDRSS_V2A_CTL_REG			0x0020
 #define DDRSS_ECC_CTRL_REG			0x0120
 
 #define DDRSS_ECC_CTRL_REG_ECC_EN		BIT(0)
@@ -620,8 +620,8 @@ static int k3_ddrss_probe(struct udevice *dev)
 		return ret;
 
 #ifdef CONFIG_K3_AM64_DDRSS
-
-	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
+	/* AM64x supports only up to 2 GB SDRAM */
+	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
 	writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
 #endif
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] ram: k3-ddrss: Fix register name and explain its usage
  2022-04-06  9:56   ` [PATCH v2] " Dominic Rath
@ 2022-04-20 19:23     ` Tom Rini
  0 siblings, 0 replies; 5+ messages in thread
From: Tom Rini @ 2022-04-20 19:23 UTC (permalink / raw)
  To: Dominic Rath; +Cc: u-boot, christian.gmeiner, d-gerlach, Dominic Rath

[-- Attachment #1: Type: text/plain, Size: 578 bytes --]

On Wed, Apr 06, 2022 at 11:56:47AM +0200, Dominic Rath wrote:

> From: Dominic Rath <rath@ibv-augsburg.net>
> 
> The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
> the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
> default that says 8 GB, which the AM64x DDR controller wouldn't support).
> 
> The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG
> was that of the next register at offset 0x24.
> 
> Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>

Applied to u-boot/master, thanks!

-- 
Tom

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^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-04-20 19:23 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-22 12:11 [PATCH 1/2] ram: k3-ddrss: Fix register name and explain its usage Dominic Rath
2022-03-22 14:38 ` Dave Gerlach
2022-04-04 18:51 ` Tom Rini
2022-04-06  9:56   ` [PATCH v2] " Dominic Rath
2022-04-20 19:23     ` Tom Rini

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