From: Paolo Bonzini <pbonzini@redhat.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Gavin Shan <gshan@redhat.com>,
kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org,
shan.gavin@gmail.com, catalin.marinas@arm.com, will@kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFCv2 9/9] arm64: Support async page fault
Date: Mon, 1 Jun 2020 11:21:41 +0200 [thread overview]
Message-ID: <5c72c597-732e-7dbf-d056-665674ec1792@redhat.com> (raw)
In-Reply-To: <4337cca152df47c93d96e092189a0e36@kernel.org>
On 31/05/20 14:44, Marc Zyngier wrote:
>>
>> Is there an ARM-approved way to reuse the S2 fault syndromes to detect
>> async page faults?
>
> It would mean being able to set an ESR_EL2 register value into ESR_EL1,
> and there is nothing in the architecture that would allow that,
I understand that this is not what you want to do and I'm not proposing
it, but I want to understand this better: _in practice_ do CPUs check
closely what is written in ESR_EL1?
In any case, the only way to implement this, it seems to me, would be a
completely paravirtualized exception vector that doesn't use ESR at all.
On the other hand, for the page ready (interrupt) side assigning a PPI
seems complicated but doable.
Paolo
> with
> the exception of nested virt: a VHE guest hypervisor running at EL1
> must be able to observe S2 faults for its own S2, as synthesized by
> the host hypervisor.
> The trouble is that:
> - there is so far no commercially available CPU supporting NV
> - even if you could get hold of such a machine, there is no
> guarantee that such "EL2 syndrome at EL1" is valid outside of
> the nested context
> - this doesn't solve the issue for non-NV CPUs anyway
WARNING: multiple messages have this Message-ID (diff)
From: Paolo Bonzini <pbonzini@redhat.com>
To: Marc Zyngier <maz@kernel.org>
Cc: catalin.marinas@arm.com, linux-kernel@vger.kernel.org,
shan.gavin@gmail.com, will@kernel.org,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFCv2 9/9] arm64: Support async page fault
Date: Mon, 1 Jun 2020 11:21:41 +0200 [thread overview]
Message-ID: <5c72c597-732e-7dbf-d056-665674ec1792@redhat.com> (raw)
In-Reply-To: <4337cca152df47c93d96e092189a0e36@kernel.org>
On 31/05/20 14:44, Marc Zyngier wrote:
>>
>> Is there an ARM-approved way to reuse the S2 fault syndromes to detect
>> async page faults?
>
> It would mean being able to set an ESR_EL2 register value into ESR_EL1,
> and there is nothing in the architecture that would allow that,
I understand that this is not what you want to do and I'm not proposing
it, but I want to understand this better: _in practice_ do CPUs check
closely what is written in ESR_EL1?
In any case, the only way to implement this, it seems to me, would be a
completely paravirtualized exception vector that doesn't use ESR at all.
On the other hand, for the page ready (interrupt) side assigning a PPI
seems complicated but doable.
Paolo
> with
> the exception of nested virt: a VHE guest hypervisor running at EL1
> must be able to observe S2 faults for its own S2, as synthesized by
> the host hypervisor.
> The trouble is that:
> - there is so far no commercially available CPU supporting NV
> - even if you could get hold of such a machine, there is no
> guarantee that such "EL2 syndrome at EL1" is valid outside of
> the nested context
> - this doesn't solve the issue for non-NV CPUs anyway
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Paolo Bonzini <pbonzini@redhat.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Gavin Shan <gshan@redhat.com>,
catalin.marinas@arm.com, linux-kernel@vger.kernel.org,
shan.gavin@gmail.com, will@kernel.org,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFCv2 9/9] arm64: Support async page fault
Date: Mon, 1 Jun 2020 11:21:41 +0200 [thread overview]
Message-ID: <5c72c597-732e-7dbf-d056-665674ec1792@redhat.com> (raw)
In-Reply-To: <4337cca152df47c93d96e092189a0e36@kernel.org>
On 31/05/20 14:44, Marc Zyngier wrote:
>>
>> Is there an ARM-approved way to reuse the S2 fault syndromes to detect
>> async page faults?
>
> It would mean being able to set an ESR_EL2 register value into ESR_EL1,
> and there is nothing in the architecture that would allow that,
I understand that this is not what you want to do and I'm not proposing
it, but I want to understand this better: _in practice_ do CPUs check
closely what is written in ESR_EL1?
In any case, the only way to implement this, it seems to me, would be a
completely paravirtualized exception vector that doesn't use ESR at all.
On the other hand, for the page ready (interrupt) side assigning a PPI
seems complicated but doable.
Paolo
> with
> the exception of nested virt: a VHE guest hypervisor running at EL1
> must be able to observe S2 faults for its own S2, as synthesized by
> the host hypervisor.
> The trouble is that:
> - there is so far no commercially available CPU supporting NV
> - even if you could get hold of such a machine, there is no
> guarantee that such "EL2 syndrome at EL1" is valid outside of
> the nested context
> - this doesn't solve the issue for non-NV CPUs anyway
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-01 9:21 UTC|newest]
Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 3:29 [PATCH RFCv2 0/9] kvm/arm64: Support Async Page Fault Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 1/9] arm64: Probe for the presence of KVM hypervisor services during boot Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 2/9] arm/arm64: KVM: Advertise KVM UID to guests via SMCCC Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 3/9] kvm/arm64: Rename kvm_vcpu_get_hsr() to kvm_vcpu_get_esr() Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-26 10:42 ` Mark Rutland
2020-05-26 10:42 ` Mark Rutland
2020-05-26 10:42 ` Mark Rutland
2020-05-27 2:43 ` Gavin Shan
2020-05-27 2:43 ` Gavin Shan
2020-05-27 2:43 ` Gavin Shan
2020-05-27 7:20 ` Marc Zyngier
2020-05-27 7:20 ` Marc Zyngier
2020-05-27 7:20 ` Marc Zyngier
2020-05-28 6:34 ` Gavin Shan
2020-05-28 6:34 ` Gavin Shan
2020-05-28 6:34 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 4/9] kvm/arm64: Detach ESR operator from vCPU struct Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-26 10:51 ` Mark Rutland
2020-05-26 10:51 ` Mark Rutland
2020-05-26 10:51 ` Mark Rutland
2020-05-27 2:55 ` Gavin Shan
2020-05-27 2:55 ` Gavin Shan
2020-05-27 2:55 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 5/9] kvm/arm64: Replace hsr with esr Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-26 10:45 ` Mark Rutland
2020-05-26 10:45 ` Mark Rutland
2020-05-26 10:45 ` Mark Rutland
2020-05-27 2:56 ` Gavin Shan
2020-05-27 2:56 ` Gavin Shan
2020-05-27 2:56 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 6/9] kvm/arm64: Export kvm_handle_user_mem_abort() with prefault mode Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-26 10:58 ` Mark Rutland
2020-05-26 10:58 ` Mark Rutland
2020-05-26 10:58 ` Mark Rutland
2020-05-27 3:01 ` Gavin Shan
2020-05-27 3:01 ` Gavin Shan
2020-05-27 3:01 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 7/9] kvm/arm64: Support async page fault Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-26 12:34 ` Mark Rutland
2020-05-26 12:34 ` Mark Rutland
2020-05-26 12:34 ` Mark Rutland
2020-05-27 4:05 ` Gavin Shan
2020-05-27 4:05 ` Gavin Shan
2020-05-27 4:05 ` Gavin Shan
2020-05-27 7:37 ` Marc Zyngier
2020-05-27 7:37 ` Marc Zyngier
2020-05-27 7:37 ` Marc Zyngier
2020-05-28 6:32 ` Gavin Shan
2020-05-28 6:32 ` Gavin Shan
2020-05-28 6:32 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 8/9] kernel/sched: Add cpu_rq_is_locked() Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` [PATCH RFCv2 9/9] arm64: Support async page fault Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-08 3:29 ` Gavin Shan
2020-05-26 12:56 ` Mark Rutland
2020-05-26 12:56 ` Mark Rutland
2020-05-26 12:56 ` Mark Rutland
2020-05-27 6:48 ` Paolo Bonzini
2020-05-27 6:48 ` Paolo Bonzini
2020-05-27 6:48 ` Paolo Bonzini
2020-05-28 6:14 ` Gavin Shan
2020-05-28 6:14 ` Gavin Shan
2020-05-28 6:14 ` Gavin Shan
2020-05-28 7:03 ` Marc Zyngier
2020-05-28 7:03 ` Marc Zyngier
2020-05-28 7:03 ` Marc Zyngier
2020-05-28 10:53 ` Paolo Bonzini
2020-05-28 10:53 ` Paolo Bonzini
2020-05-28 10:53 ` Paolo Bonzini
2020-05-28 10:48 ` Paolo Bonzini
2020-05-28 10:48 ` Paolo Bonzini
2020-05-28 10:48 ` Paolo Bonzini
2020-05-28 23:02 ` Gavin Shan
2020-05-28 23:02 ` Gavin Shan
2020-05-28 23:02 ` Gavin Shan
2020-05-29 9:41 ` Marc Zyngier
2020-05-29 9:41 ` Marc Zyngier
2020-05-29 9:41 ` Marc Zyngier
2020-05-29 11:11 ` Paolo Bonzini
2020-05-29 11:11 ` Paolo Bonzini
2020-05-29 11:11 ` Paolo Bonzini
2020-05-31 12:44 ` Marc Zyngier
2020-05-31 12:44 ` Marc Zyngier
2020-05-31 12:44 ` Marc Zyngier
2020-06-01 9:21 ` Paolo Bonzini [this message]
2020-06-01 9:21 ` Paolo Bonzini
2020-06-01 9:21 ` Paolo Bonzini
2020-06-02 5:44 ` Gavin Shan
2020-06-02 5:44 ` Gavin Shan
2020-06-02 5:44 ` Gavin Shan
2020-05-25 23:39 ` [PATCH RFCv2 0/9] kvm/arm64: Support Async Page Fault Gavin Shan
2020-05-25 23:39 ` Gavin Shan
2020-05-25 23:39 ` Gavin Shan
2020-05-26 13:09 ` Mark Rutland
2020-05-26 13:09 ` Mark Rutland
2020-05-26 13:09 ` Mark Rutland
2020-05-27 2:39 ` Gavin Shan
2020-05-27 2:39 ` Gavin Shan
2020-05-27 2:39 ` Gavin Shan
2020-05-27 7:48 ` Marc Zyngier
2020-05-27 7:48 ` Marc Zyngier
2020-05-27 7:48 ` Marc Zyngier
2020-05-27 16:10 ` Paolo Bonzini
2020-05-27 16:10 ` Paolo Bonzini
2020-05-27 16:10 ` Paolo Bonzini
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