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From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, paul.walmsley@sifive.com,
	aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v3 4/9] riscv: move exception table immediately after RO_DATA
Date: Tue, 10 Mar 2020 00:55:39 +0800	[thread overview]
Message-ID: <5c80357b06faf1caed8fbab2d4dc57a2cbeb8b94.1583772574.git.zong.li@sifive.com> (raw)
In-Reply-To: <cover.1583772574.git.zong.li@sifive.com>

Move EXCEPTION_TABLE immediately after RO_DATA. Make it easy to set the
attribution of the sections which should be read-only at a time.
Add _data to specify the start of data section with write permission.
This patch is prepared for STRICT_KERNEL_RWX support.

Signed-off-by: Zong Li <zong.li@sifive.com>
---
 arch/riscv/kernel/vmlinux.lds.S | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S
index 1e0193ded420..02e948b620af 100644
--- a/arch/riscv/kernel/vmlinux.lds.S
+++ b/arch/riscv/kernel/vmlinux.lds.S
@@ -58,6 +58,10 @@ SECTIONS
 		*(.srodata*)
 	}
 
+	EXCEPTION_TABLE(0x10)
+
+	_data = .;
+
 	RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
 	.sdata : {
 		__global_pointer$ = . + 0x800;
@@ -69,8 +73,6 @@ SECTIONS
 
 	BSS_SECTION(PAGE_SIZE, PAGE_SIZE, 0)
 
-	EXCEPTION_TABLE(0x10)
-
 	.rel.dyn : {
 		*(.rel.dyn*)
 	}
-- 
2.25.1


  parent reply	other threads:[~2020-03-09 16:56 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-09 16:55 [PATCH v3 0/9] Support strict kernel memory permissions for security Zong Li
2020-03-09 16:55 ` [PATCH v3 1/9] riscv: add ARCH_HAS_SET_MEMORY support Zong Li
2020-03-09 16:55 ` [PATCH v3 2/9] riscv: add ARCH_HAS_SET_DIRECT_MAP support Zong Li
2020-03-09 16:55 ` [PATCH v3 3/9] riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support Zong Li
2020-03-09 16:55 ` Zong Li [this message]
2020-03-09 16:55 ` [PATCH v3 5/9] riscv: add alignment for text, rodata and data sections Zong Li
2020-03-09 16:55 ` [PATCH v3 6/9] riscv: add STRICT_KERNEL_RWX support Zong Li
2020-03-09 16:55 ` [PATCH v3 7/9] riscv: add macro to get instruction length Zong Li
2020-03-09 16:55 ` [PATCH v3 8/9] riscv: introduce interfaces to patch kernel code Zong Li
2020-03-31 15:32   ` Masami Hiramatsu
2020-03-31 15:32     ` Masami Hiramatsu
2020-04-01  7:42     ` Zong Li
2020-04-01  7:42       ` Zong Li
2020-04-02  1:17       ` Masami Hiramatsu
2020-04-02  1:17         ` Masami Hiramatsu
2020-04-03  9:04         ` Zong Li
2020-04-03  9:04           ` Zong Li
2020-04-04  3:14           ` Masami Hiramatsu
2020-04-04  3:14             ` Masami Hiramatsu
2020-04-04 12:12             ` Zong Li
2020-04-04 12:12               ` Zong Li
2020-04-06 10:36               ` Zong Li
2020-04-06 10:36                 ` Zong Li
2020-04-07 12:29                 ` Masami Hiramatsu
2020-04-07 12:29                   ` Masami Hiramatsu
2020-04-07 13:06                   ` Zong Li
2020-04-07 13:06                     ` Zong Li
2020-03-09 16:55 ` [PATCH v3 9/9] riscv: patch code by fixmap mapping Zong Li
2020-03-31 13:32 ` [PATCH v3 0/9] Support strict kernel memory permissions for security Masami Hiramatsu
2020-03-31 13:32   ` Masami Hiramatsu
2020-04-01  7:18   ` Zong Li
2020-04-01  7:18     ` Zong Li

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