[PATCH v2 0/3] MIPS system emulation miscellaneous fixes

[PATCH v2 0/3] MIPS system emulation miscellaneous fixes

[Jiaxun Yang]

Hi all,

I was trying to build a MIPS VirtIO board[1] for QEMU that is able
to work with all processors we support.

When I was bring up varoius CPUs on that board I noticed some issues
with the system emulation code that I'm fixing in this series.

Thanks.

- Jiaxun
[1]: https://gitlab.com/FlyGoat/qemu/-/tree/mips-virt

v2: Address review comments

Jiaxun Yang (3):
  target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
  target/mips: Cast offset field of Octeon BBIT to int16_t
  target/mips: Disable DSP ASE for Octeon68XX

 target/mips/cpu-defs.c.inc    | 4 ++--
 target/mips/cpu.c             | 6 ++++++
 target/mips/tcg/octeon.decode | 2 +-
 3 files changed, 9 insertions(+), 3 deletions(-)

-- 
2.34.1

[PATCH v2 1/3] target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F

[Jiaxun Yang]

As per an unpublished document, in later reversion of chips
CP0St_{KX, SX, UX} is not writeable and hardcoded to 1.

Without those bits set, kernel is unable to access XKPHYS address
segmant. So just set them up on CPU reset.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
---
v2:
Rewording to point out the document is unpublished
---
 target/mips/cpu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d0a76b95f7..a870901bfa 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -304,6 +304,12 @@ static void mips_cpu_reset(DeviceState *dev)
     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
+    if (env->insn_flags & INSN_LOONGSON2F) {
+        /* Loongson-2F has those bits hardcoded to 1 */
+        env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) |
+                            (1 << CP0St_UX);
+    }
+
     /*
      * Vectored interrupts not implemented, timer on int 7,
      * no performance counters.
-- 
2.34.1

[PATCH v2 2/3] target/mips: Cast offset field of Octeon BBIT to int16_t

[Jiaxun Yang]

As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2:
Do casting in decodetree. (philmd)
---
 target/mips/tcg/octeon.decode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index 8929ad088e..0c787cb498 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -12,7 +12,7 @@
 # BBIT132    111110 ..... ..... ................
 
 %bbit_p      28:1 16:5
-BBIT         11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
+BBIT         11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p
 
 # Arithmetic
 # BADDU rd, rs, rt
-- 
2.34.1

[PATCH v2 3/3] target/mips: Disable DSP ASE for Octeon68XX

[Jiaxun Yang]

I don't have access to Octeon68XX hardware but accroading to
my investigation Octeon never had DSP ASE support.

As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor
and I can confirm CP0C3_DSPP is read as 0 on that processor.

Further more, in linux kernel:
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
cpu_has_dsp is overridden as 0.

So I believe we shouldn't emulate DSP in QEMU as well.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/cpu-defs.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 7f53c94ec8..480e60aeec 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -934,7 +934,7 @@ const mips_def_t mips_defs[] =
                        (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
-        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
                        (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
                        (3U << CP0C4_MMUSizeExt),
@@ -946,7 +946,7 @@ const mips_def_t mips_defs[] =
         .CP0_Status_rw_bitmask = 0x12F8FFFF,
         .SEGBITS = 42,
         .PABITS = 49,
-        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
+        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
         .mmu_type = MMU_TYPE_R4000,
     },
 
-- 
2.34.1

Re: [PATCH v2 2/3] target/mips: Cast offset field of Octeon BBIT to int16_t

[Pavel Dovgalyuk]

Acked-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>

On 31.10.2022 16:25, Jiaxun Yang wrote:
> As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
> Manual" offset field is signed 16 bit value. However arg_BBIT.offset
> is unsigned. We need to cast it as signed to do address calculation.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> v2:
> Do casting in decodetree. (philmd)
> ---
>   target/mips/tcg/octeon.decode | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
> index 8929ad088e..0c787cb498 100644
> --- a/target/mips/tcg/octeon.decode
> +++ b/target/mips/tcg/octeon.decode
> @@ -12,7 +12,7 @@
>   # BBIT132    111110 ..... ..... ................
>   
>   %bbit_p      28:1 16:5
> -BBIT         11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
> +BBIT         11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p
>   
>   # Arithmetic
>   # BADDU rd, rs, rt

Re: [PATCH v2 3/3] target/mips: Disable DSP ASE for Octeon68XX

[Pavel Dovgalyuk]

On 31.10.2022 16:25, Jiaxun Yang wrote:
> I don't have access to Octeon68XX hardware but accroading to
> my investigation Octeon never had DSP ASE support.
> 
> As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
> Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
> access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor
> and I can confirm CP0C3_DSPP is read as 0 on that processor.
> 
> Further more, in linux kernel:
> arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
> cpu_has_dsp is overridden as 0.
> 
> So I believe we shouldn't emulate DSP in QEMU as well.

That's true. But there is one exception: LBX/LWX/LDX instruction.
These are grouped into DSP extension in QEMU, but Octeon supports them.
I've sent a patch for enabling these instructions.

Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>

> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Acked-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/mips/cpu-defs.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index 7f53c94ec8..480e60aeec 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -934,7 +934,7 @@ const mips_def_t mips_defs[] =
>                          (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
>                          (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>           .CP0_Config2 = MIPS_CONFIG2,
> -        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
>           .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
>                          (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
>                          (3U << CP0C4_MMUSizeExt),
> @@ -946,7 +946,7 @@ const mips_def_t mips_defs[] =
>           .CP0_Status_rw_bitmask = 0x12F8FFFF,
>           .SEGBITS = 42,
>           .PABITS = 49,
> -        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
> +        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
>           .mmu_type = MMU_TYPE_R4000,
>       },
>   

Re: [PATCH v2 2/3] target/mips: Cast offset field of Octeon BBIT to int16_t

[Philippe Mathieu-Daudé]

On 31/10/22 14:25, Jiaxun Yang wrote:
> As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
> Manual" offset field is signed 16 bit value. However arg_BBIT.offset
> is unsigned. We need to cast it as signed to do address calculation.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> v2:
> Do casting in decodetree. (philmd)
> ---
>   target/mips/tcg/octeon.decode | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
> index 8929ad088e..0c787cb498 100644
> --- a/target/mips/tcg/octeon.decode
> +++ b/target/mips/tcg/octeon.decode
> @@ -12,7 +12,7 @@
>   # BBIT132    111110 ..... ..... ................
>   
>   %bbit_p      28:1 16:5
> -BBIT         11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
> +BBIT         11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p
>   
>   # Arithmetic
>   # BADDU rd, rs, rt

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH v2 0/3] MIPS system emulation miscellaneous fixes

[Philippe Mathieu-Daudé]

On 31/10/22 14:25, Jiaxun Yang wrote:
> Hi all,
> 
> I was trying to build a MIPS VirtIO board[1] for QEMU that is able
> to work with all processors we support.
> 
> When I was bring up varoius CPUs on that board I noticed some issues
> with the system emulation code that I'm fixing in this series.
> 
> Thanks.
> 
> - Jiaxun
> [1]: https://gitlab.com/FlyGoat/qemu/-/tree/mips-virt
> 
> v2: Address review comments
> 
> Jiaxun Yang (3):
>    target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
>    target/mips: Cast offset field of Octeon BBIT to int16_t
>    target/mips: Disable DSP ASE for Octeon68XX

Queued to mips-fixes, thanks.