* [Intel-gfx] DG1 VRAM question
@ 2020-06-26 4:37 Dave Airlie
2020-06-26 7:14 ` Lucas De Marchi
0 siblings, 1 reply; 6+ messages in thread
From: Dave Airlie @ 2020-06-26 4:37 UTC (permalink / raw)
To: Intel Graphics Development
I can't figure this out easily so I'd thought I'd just ask, but does
DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of
mappable VRAM vs non-mappable in patches, is it planned to just thrash
the aperture if userspace ever ties to map too much of it.
Are pagetables stored in the visible RAM space?
Dave.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] DG1 VRAM question
2020-06-26 4:37 [Intel-gfx] DG1 VRAM question Dave Airlie
@ 2020-06-26 7:14 ` Lucas De Marchi
2020-06-26 17:17 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 6+ messages in thread
From: Lucas De Marchi @ 2020-06-26 7:14 UTC (permalink / raw)
To: Dave Airlie; +Cc: Intel Graphics Development, Matthew Auld
Cc Matt and Daniele
On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied@gmail.com> wrote:
>
> I can't figure this out easily so I'd thought I'd just ask, but does
> DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of
We'd need to go via lmem since there's no mappable aperture. There are
a few patches in tree for that
(see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not
available.")) but more missing.
Lucas De Marchi
> mappable VRAM vs non-mappable in patches, is it planned to just thrash
> the aperture if userspace ever ties to map too much of it.
>
> Are pagetables stored in the visible RAM space?
>
> Dave.
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] DG1 VRAM question
2020-06-26 7:14 ` Lucas De Marchi
@ 2020-06-26 17:17 ` Daniele Ceraolo Spurio
2020-06-30 23:27 ` Dave Airlie
0 siblings, 1 reply; 6+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-06-26 17:17 UTC (permalink / raw)
To: Lucas De Marchi, Dave Airlie; +Cc: Intel Graphics Development, Matthew Auld
On 6/26/20 12:14 AM, Lucas De Marchi wrote:
> Cc Matt and Daniele
>
> On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied@gmail.com> wrote:
>>
>> I can't figure this out easily so I'd thought I'd just ask, but does
>> DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of
>
> We'd need to go via lmem since there's no mappable aperture. There are
> a few patches in tree for that
> (see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not
> available.")) but more missing.
>
To clarify, although the legacy aperture mapping that allowed the CPU to
access memory via the GGTT for swizzling is gone, VRAM/LMEM is still
cpu-mappable via pci bar.
Will leave the questions about possible trashing to Matt as he's more
familiar than me with how this works.
Daniele
> Lucas De Marchi
>
>> mappable VRAM vs non-mappable in patches, is it planned to just thrash
>> the aperture if userspace ever ties to map too much of it.
>>
>> Are pagetables stored in the visible RAM space?
>>
>> Dave.
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] DG1 VRAM question
2020-06-26 17:17 ` Daniele Ceraolo Spurio
@ 2020-06-30 23:27 ` Dave Airlie
2020-07-07 8:36 ` Matthew Auld
0 siblings, 1 reply; 6+ messages in thread
From: Dave Airlie @ 2020-06-30 23:27 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Intel Graphics Development, Matthew Auld
On Sat, 27 Jun 2020 at 03:17, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
>
>
> On 6/26/20 12:14 AM, Lucas De Marchi wrote:
> > Cc Matt and Daniele
> >
> > On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied@gmail.com> wrote:
> >>
> >> I can't figure this out easily so I'd thought I'd just ask, but does
> >> DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of
> >
> > We'd need to go via lmem since there's no mappable aperture. There are
> > a few patches in tree for that
> > (see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not
> > available.")) but more missing.
> >
>
> To clarify, although the legacy aperture mapping that allowed the CPU to
> access memory via the GGTT for swizzling is gone, VRAM/LMEM is still
> cpu-mappable via pci bar.
> Will leave the questions about possible trashing to Matt as he's more
> familiar than me with how this works.
Matt?
Is DG1 assuming we can get 64-bit BARs always and the CPU will have
access to the complete VRAM? or is there any ideas about what happens
in those situations where 64-bit BARs aren't available and there is
memory pressure on the PCI BAR space.
With other discrete GPUs we've got lots of things like visible VRAM
limitations, writing page tables with GPU hw instead of from the CPU,
having mapping bring things into the visible area, so you can stream
something into VRAM, but then it'll migrated to non-visible area if
it's unmapped and there is memory pressure.
Dave.
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] DG1 VRAM question
2020-06-30 23:27 ` Dave Airlie
@ 2020-07-07 8:36 ` Matthew Auld
2020-07-13 4:45 ` Dave Airlie
0 siblings, 1 reply; 6+ messages in thread
From: Matthew Auld @ 2020-07-07 8:36 UTC (permalink / raw)
To: Dave Airlie, Daniele Ceraolo Spurio; +Cc: Intel Graphics Development
On 01/07/2020 00:27, Dave Airlie wrote:
> On Sat, 27 Jun 2020 at 03:17, Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>>
>>
>>
>> On 6/26/20 12:14 AM, Lucas De Marchi wrote:
>>> Cc Matt and Daniele
>>>
>>> On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied@gmail.com> wrote:
>>>>
>>>> I can't figure this out easily so I'd thought I'd just ask, but does
>>>> DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of
>>>
>>> We'd need to go via lmem since there's no mappable aperture. There are
>>> a few patches in tree for that
>>> (see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not
>>> available.")) but more missing.
>>>
>>
>> To clarify, although the legacy aperture mapping that allowed the CPU to
>> access memory via the GGTT for swizzling is gone, VRAM/LMEM is still
>> cpu-mappable via pci bar.
>> Will leave the questions about possible trashing to Matt as he's more
>> familiar than me with how this works.
>
> Matt?
>
> Is DG1 assuming we can get 64-bit BARs always and the CPU will have
> access to the complete VRAM? or is there any ideas about what happens
> in those situations where 64-bit BARs aren't available and there is
> memory pressure on the PCI BAR space.
>
> With other discrete GPUs we've got lots of things like visible VRAM
> limitations, writing page tables with GPU hw instead of from the CPU,
> having mapping bring things into the visible area, so you can stream
> something into VRAM, but then it'll migrated to non-visible area if
> it's unmapped and there is memory pressure.
Yes, we just assume that LMEM size == LMEMBAR size, where the whole
thing is 1:1 mapped and CPU visible. We don't currently have the concept
of CPU visible/non-visible LMEM.
>
> Dave.
>
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] DG1 VRAM question
2020-07-07 8:36 ` Matthew Auld
@ 2020-07-13 4:45 ` Dave Airlie
0 siblings, 0 replies; 6+ messages in thread
From: Dave Airlie @ 2020-07-13 4:45 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development
On Tue, 7 Jul 2020 at 18:36, Matthew Auld <matthew.auld@intel.com> wrote:
>
> On 01/07/2020 00:27, Dave Airlie wrote:
> > On Sat, 27 Jun 2020 at 03:17, Daniele Ceraolo Spurio
> > <daniele.ceraolospurio@intel.com> wrote:
> >>
> >>
> >>
> >> On 6/26/20 12:14 AM, Lucas De Marchi wrote:
> >>> Cc Matt and Daniele
> >>>
> >>> On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied@gmail.com> wrote:
> >>>>
> >>>> I can't figure this out easily so I'd thought I'd just ask, but does
> >>>> DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of
> >>>
> >>> We'd need to go via lmem since there's no mappable aperture. There are
> >>> a few patches in tree for that
> >>> (see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not
> >>> available.")) but more missing.
> >>>
> >>
> >> To clarify, although the legacy aperture mapping that allowed the CPU to
> >> access memory via the GGTT for swizzling is gone, VRAM/LMEM is still
> >> cpu-mappable via pci bar.
> >> Will leave the questions about possible trashing to Matt as he's more
> >> familiar than me with how this works.
> >
> > Matt?
> >
> > Is DG1 assuming we can get 64-bit BARs always and the CPU will have
> > access to the complete VRAM? or is there any ideas about what happens
> > in those situations where 64-bit BARs aren't available and there is
> > memory pressure on the PCI BAR space.
> >
> > With other discrete GPUs we've got lots of things like visible VRAM
> > limitations, writing page tables with GPU hw instead of from the CPU,
> > having mapping bring things into the visible area, so you can stream
> > something into VRAM, but then it'll migrated to non-visible area if
> > it's unmapped and there is memory pressure.
>
> Yes, we just assume that LMEM size == LMEMBAR size, where the whole
> thing is 1:1 mapped and CPU visible. We don't currently have the concept
> of CPU visible/non-visible LMEM.
Okay, so this GPU is happy never being supported when connected to
anything where the firmware doesn't enable 64-bit BARs?
I'd love to say 64-bit BARs were everywhere, I suppose in some worlds
BIOSes and OS might even work flawlessly with them enabled. Considered
plugging one of these in over thunderbolt? (maybe TB always gets a
64-bit BAR).
Dave.
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-07-13 4:46 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-26 4:37 [Intel-gfx] DG1 VRAM question Dave Airlie
2020-06-26 7:14 ` Lucas De Marchi
2020-06-26 17:17 ` Daniele Ceraolo Spurio
2020-06-30 23:27 ` Dave Airlie
2020-07-07 8:36 ` Matthew Auld
2020-07-13 4:45 ` Dave Airlie
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