* [Intel-gfx] [PATCH] drm/i915: Reserving some Multi-thread forcewake bits.
@ 2022-04-13 21:39 Rodrigo Vivi
2022-04-14 3:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2022-04-14 21:14 ` [Intel-gfx] [PATCH] " Matt Roper
0 siblings, 2 replies; 4+ messages in thread
From: Rodrigo Vivi @ 2022-04-13 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Bit 0: Currently bit used by i915. Ideally only i915 touches it
in a Linux stack.
Bits 1 and 2: A while ago we were using Bit 1 for i915 and bit 2
for the user space, until commit 7130630323c5 ("drm/i915:
Use fallback forcewake if primary ack missing") changed it
to bit 1.
Now we have a situation where PCODE is also using this bit-1
in one case, while it should actually be using the Bit-3.
So, let's redirect users back to bit-2 and mark this 1 as
reserved.
Bit 3: Let's reserve for PCODE.
Bit 4: Let's reserve for PSMI.
Cc: Tilak Tangudu <tilak.tangudu@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 0a5c2648aaf0..15ceaaace4d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1399,8 +1399,11 @@
#define FORCEWAKE_MT_ACK _MMIO(0x130040)
#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
-#define FORCEWAKE_KERNEL BIT(0)
-#define FORCEWAKE_USER BIT(1)
+#define FORCEWAKE_KERNEL BIT(0) /* For i915 use only */
+#define FORCEWAKE_RSVD BIT(1)
+#define FORCEWAKE_USER BIT(2)
+#define FORCEWAKE_PCODE BIT(3)
+#define FORCEWAKE_PSMI BIT(4)
#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
#define FORCEWAKE_ACK _MMIO(0x130090)
#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Reserving some Multi-thread forcewake bits. 2022-04-13 21:39 [Intel-gfx] [PATCH] drm/i915: Reserving some Multi-thread forcewake bits Rodrigo Vivi @ 2022-04-14 3:36 ` Patchwork 2022-04-14 21:14 ` [Intel-gfx] [PATCH] " Matt Roper 1 sibling, 0 replies; 4+ messages in thread From: Patchwork @ 2022-04-14 3:36 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 15006 bytes --] == Series Details == Series: drm/i915: Reserving some Multi-thread forcewake bits. URL : https://patchwork.freedesktop.org/series/102673/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11497 -> Patchwork_102673v1 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_102673v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_102673v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/index.html Participating hosts (39 -> 40) ------------------------------ Additional (5): bat-dg1-6 bat-dg1-5 fi-icl-u2 bat-adlp-6 bat-rpls-2 Missing (4): fi-bsw-cyan bat-jsl-2 fi-bdw-samus fi-tgl-u2 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_102673v1: ### IGT changes ### #### Possible regressions #### * igt@gem_lmem_swapping@parallel-random-engines: - bat-dg1-5: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@gem_lmem_swapping@parallel-random-engines.html - bat-dg1-6: NOTRUN -> [FAIL][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@gem_lmem_swapping@parallel-random-engines.html Known issues ------------ Here are the changes found in Patchwork_102673v1 that come from known issues: ### CI changes ### #### Possible fixes #### * boot: - fi-ilk-650: [FAIL][3] -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-ilk-650/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-ilk-650/boot.html ### IGT changes ### #### Issues hit #### * igt@fbdev@write: - bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#2582]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@fbdev@write.html * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][6] -> [INCOMPLETE][7] ([i915#146]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html * igt@gem_huc_copy@huc-copy: - fi-ilk-650: NOTRUN -> [SKIP][8] ([fdo#109271]) +21 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-ilk-650/igt@gem_huc_copy@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][9] ([i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-icl-u2/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@gem_mmap@basic.html - bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4083]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@gem_mmap@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4077]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@gem_tiled_blits@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4077]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4079]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@gem_tiled_pread_basic.html - bat-dg1-6: NOTRUN -> [SKIP][16] ([i915#4079]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#1155]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@i915_pm_backlight@basic-brightness.html - bat-dg1-6: NOTRUN -> [SKIP][18] ([i915#1155]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#4212]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][20] ([i915#4215]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html - bat-dg1-6: NOTRUN -> [SKIP][21] ([i915#4215]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-5: NOTRUN -> [SKIP][22] ([i915#4212]) +7 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_addfb_basic@tile-pitch-mismatch.html * igt@kms_busy@basic: - bat-dg1-5: NOTRUN -> [SKIP][23] ([i915#4303]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_busy@basic.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +8 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-ilk-650/igt@kms_chamelium@dp-hpd-fast.html * igt@kms_chamelium@hdmi-edid-read: - bat-dg1-6: NOTRUN -> [SKIP][25] ([fdo#111827]) +8 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][26] ([fdo#111827]) +8 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html - bat-dg1-5: NOTRUN -> [SKIP][27] ([fdo#111827]) +8 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg1-6: NOTRUN -> [SKIP][28] ([i915#4103] / [i915#4213]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][29] ([fdo#109278]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html - bat-dg1-5: NOTRUN -> [SKIP][30] ([i915#4103] / [i915#4213]) +1 similar issue [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-dg1-5: NOTRUN -> [SKIP][31] ([i915#4078]) +23 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_flip@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-6: NOTRUN -> [SKIP][32] ([fdo#109285]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html - bat-dg1-5: NOTRUN -> [SKIP][33] ([fdo#109285]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html - fi-icl-u2: NOTRUN -> [SKIP][34] ([fdo#109285]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - bat-dg1-5: NOTRUN -> [SKIP][35] ([i915#4078] / [i915#5341]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html - fi-ilk-650: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#5341]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-ilk-650/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html * igt@kms_psr@primary_page_flip: - bat-dg1-5: NOTRUN -> [SKIP][37] ([i915#1072] / [i915#4078]) +3 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_psr@primary_page_flip.html * igt@kms_psr@sprite_plane_onoff: - bat-dg1-6: NOTRUN -> [SKIP][38] ([i915#1072] / [i915#4078]) +3 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - fi-icl-u2: NOTRUN -> [SKIP][39] ([i915#3555]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html - bat-dg1-6: NOTRUN -> [SKIP][40] ([i915#3555]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html - bat-dg1-5: NOTRUN -> [SKIP][41] ([i915#3555]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-mmap: - bat-dg1-5: NOTRUN -> [SKIP][42] ([i915#3708] / [i915#4077]) +1 similar issue [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@prime_vgem@basic-fence-mmap.html * igt@prime_vgem@basic-gtt: - bat-dg1-6: NOTRUN -> [SKIP][43] ([i915#3708] / [i915#4077]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@prime_vgem@basic-gtt.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][44] ([i915#3301]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-icl-u2/igt@prime_vgem@basic-userptr.html - bat-dg1-6: NOTRUN -> [SKIP][45] ([i915#3708] / [i915#4873]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@prime_vgem@basic-userptr.html - bat-dg1-5: NOTRUN -> [SKIP][46] ([i915#3708] / [i915#4873]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@prime_vgem@basic-userptr.html * igt@prime_vgem@basic-write: - bat-dg1-5: NOTRUN -> [SKIP][47] ([i915#3708]) +3 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@prime_vgem@basic-write.html - bat-dg1-6: NOTRUN -> [SKIP][48] ([i915#3708]) +3 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@prime_vgem@basic-write.html * igt@runner@aborted: - bat-dg1-5: NOTRUN -> [FAIL][49] ([i915#4312]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-5/igt@runner@aborted.html - bat-dg1-6: NOTRUN -> [FAIL][50] ([i915#4312]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/bat-dg1-6/igt@runner@aborted.html #### Possible fixes #### * igt@i915_selftest@live@gt_heartbeat: - fi-skl-guc: [DMESG-FAIL][51] -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#5329]: https://gitlab.freedesktop.org/drm/intel/issues/5329 [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341 [i915#5634]: https://gitlab.freedesktop.org/drm/intel/issues/5634 Build changes ------------- * Linux: CI_DRM_11497 -> Patchwork_102673v1 CI-20190529: 20190529 CI_DRM_11497: d883cffbf2383a96420fd6dc099056295de24a12 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6420: a3885810ccc0ce9e6552a20c910a0a322eca466c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_102673v1: d883cffbf2383a96420fd6dc099056295de24a12 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 711c70c99afb drm/i915: Reserving some Multi-thread forcewake bits. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102673v1/index.html [-- Attachment #2: Type: text/html, Size: 18575 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Reserving some Multi-thread forcewake bits. 2022-04-13 21:39 [Intel-gfx] [PATCH] drm/i915: Reserving some Multi-thread forcewake bits Rodrigo Vivi 2022-04-14 3:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork @ 2022-04-14 21:14 ` Matt Roper 2022-04-14 21:30 ` Vivi, Rodrigo 1 sibling, 1 reply; 4+ messages in thread From: Matt Roper @ 2022-04-14 21:14 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx On Wed, Apr 13, 2022 at 05:39:27PM -0400, Rodrigo Vivi wrote: > Bit 0: Currently bit used by i915. Ideally only i915 touches it > in a Linux stack. > > Bits 1 and 2: A while ago we were using Bit 1 for i915 and bit 2 > for the user space, until commit 7130630323c5 ("drm/i915: > Use fallback forcewake if primary ack missing") changed it > to bit 1. That commit didn't change the bits, just the notation used to describe them. 0x1 == BIT(0) and 0x2 == BIT(1) so no functional change. In general userspace shouldn't ever be using forcewake and the very few exceptions to that rule aren't using the definitions in our kernel register header anyway so I don't see much value in trying to reserve bits in our kernel header. I believe the only userspace users of forcewake are/were: * The old Intel-specific DDX driver (which has now been replaced by the vendor-agnostic xf86-video-modesetting) used to grab forcewake via the command streamer while waiting for scanline on hsw-gen9 b[3] = MI_LOAD_REGISTER_IMM | 1; b[4] = 0xa188; /* FORCEWAKE_MT */ b[5] = 2 << 16 | 2; So the usage of bit 1 (i.e., 0x2) is hardcoded into the DDX; you'd need to update the DDX itself if you're worried about clashes with pcode on those old platforms. Honestly I don't know if the above register update even lands...at least for modern platforms bspec page 45546 doesn't list 0xa188 as a register that userspace has permission to update via the command streamer (it would probably be a security concern if it was!), so this old DDX strategy of using an LRI instruction to update the register shouldn't be something we even need to consider going forward. * debug tools like intel_reg that run as root can manipulate registers directly, including the forcewake register. But the bits that get used are up to whoever is running the tool; the definitions in i915 code don't matter. * There's an "i915_forcewake_user" debugfs entry that holds forcewake while userspace holds an open file descriptor on it. But usage of that debugfs still utilizes the FORCEWAKE_KERNEL bit rather than the "userspace" bit. Since FORCEWAKE_USER is completely unused by i915, I'd suggest just dropping the definition so that people don't even get the bad idea that manipulating forcewake from userspace is okay. Just leave FORCEWAKE_KERNEL and FORCEWAKE_KERNEL_FALLBACK as the only ones defined since from our point of view those are the only ones that matter. Matt > Now we have a situation where PCODE is also using this bit-1 > in one case, while it should actually be using the Bit-3. > So, let's redirect users back to bit-2 and mark this 1 as > reserved. > > Bit 3: Let's reserve for PCODE. > > Bit 4: Let's reserve for PSMI. > > Cc: Tilak Tangudu <tilak.tangudu@intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 0a5c2648aaf0..15ceaaace4d9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1399,8 +1399,11 @@ > #define FORCEWAKE_MT_ACK _MMIO(0x130040) > #define FORCEWAKE_ACK_HSW _MMIO(0x130044) > #define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044) > -#define FORCEWAKE_KERNEL BIT(0) > -#define FORCEWAKE_USER BIT(1) > +#define FORCEWAKE_KERNEL BIT(0) /* For i915 use only */ > +#define FORCEWAKE_RSVD BIT(1) > +#define FORCEWAKE_USER BIT(2) > +#define FORCEWAKE_PCODE BIT(3) > +#define FORCEWAKE_PSMI BIT(4) > #define FORCEWAKE_KERNEL_FALLBACK BIT(15) > #define FORCEWAKE_ACK _MMIO(0x130090) > #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Reserving some Multi-thread forcewake bits. 2022-04-14 21:14 ` [Intel-gfx] [PATCH] " Matt Roper @ 2022-04-14 21:30 ` Vivi, Rodrigo 0 siblings, 0 replies; 4+ messages in thread From: Vivi, Rodrigo @ 2022-04-14 21:30 UTC (permalink / raw) To: Roper, Matthew D; +Cc: intel-gfx On Thu, 2022-04-14 at 14:14 -0700, Matt Roper wrote: > On Wed, Apr 13, 2022 at 05:39:27PM -0400, Rodrigo Vivi wrote: > > Bit 0: Currently bit used by i915. Ideally only i915 touches it > > in a Linux stack. > > > > Bits 1 and 2: A while ago we were using Bit 1 for i915 and bit 2 > > for the user space, until commit 7130630323c5 > > ("drm/i915: > > Use fallback forcewake if primary ack missing") > > changed it > > to bit 1. > > That commit didn't change the bits, just the notation used to > describe > them. 0x1 == BIT(0) and 0x2 == BIT(1) so no functional change. I could swear I had seen (1 << 1) and (1 << 2)... defining the value instead of the bit on this file confused me... Glad that that patch actually fixed this. > > In general userspace shouldn't ever be using forcewake and the very > few > exceptions to that rule aren't using the definitions in our kernel > register header anyway so I don't see much value in trying to reserve > bits in our kernel header. I believe the only userspace users of > forcewake are/were: > > * The old Intel-specific DDX driver (which has now been replaced by > the > vendor-agnostic xf86-video-modesetting) used to grab forcewake via > the command streamer while waiting for scanline on hsw-gen9 > > b[3] = MI_LOAD_REGISTER_IMM | 1; > b[4] = 0xa188; /* FORCEWAKE_MT */ > b[5] = 2 << 16 | 2; > > So the usage of bit 1 (i.e., 0x2) is hardcoded into the DDX; you'd > need to update the DDX itself if you're worried about clashes with > pcode on those old platforms. I don't believe that's the case... so we should be good. > > Honestly I don't know if the above register update even lands...at > least for modern platforms bspec page 45546 doesn't list 0xa188 as > a > register that userspace has permission to update via the command > streamer (it would probably be a security concern if it was!), so > this old DDX strategy of using an LRI instruction to update the > register shouldn't be something we even need to consider going > forward. > > * debug tools like intel_reg that run as root can manipulate > registers > directly, including the forcewake register. But the bits that get > used are up to whoever is running the tool; the definitions in > i915 > code don't matter. > > * There's an "i915_forcewake_user" debugfs entry that holds > forcewake > while userspace holds an open file descriptor on it. But usage of > that debugfs still utilizes the FORCEWAKE_KERNEL bit rather than > the > "userspace" bit. > > Since FORCEWAKE_USER is completely unused by i915, I'd suggest just > dropping the definition so that people don't even get the bad idea > that > manipulating forcewake from userspace is okay. Just leave > FORCEWAKE_KERNEL and FORCEWAKE_KERNEL_FALLBACK as the only ones > defined > since from our point of view those are the only ones that matter. I'd like to use this place to keep documented what bits we are reserving for what cases. So in the future when PCODE or yet another comment comes and ask who is using what we show this list and they know what to use or not. For instance PSMI in older platforms were using bit 12, not it changed to bit 0... But I also found out if they change back to bit 12 we might conflict with a PCODE w/a.... It's unfortunate that this wasn't documented in BSpec and windows driver and linux are already totally different in the bits usages, but we need to at least answer what bits in a linux stack we know to be used by what... Even if we need to add DG2_FORCEWAKE_PCODE BIT(12) PVC_FORCEWAKE_PCODE BIT(1) etc... > > > Matt > > > Now we have a situation where PCODE is also using > > this bit-1 > > in one case, while it should actually be using the > > Bit-3. > > So, let's redirect users back to bit-2 and mark this > > 1 as > > reserved. > > > > Bit 3: Let's reserve for PCODE. > > > > Bit 4: Let's reserve for PSMI. > > > > Cc: Tilak Tangudu <tilak.tangudu@intel.com> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 +++++-- > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 0a5c2648aaf0..15ceaaace4d9 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -1399,8 +1399,11 @@ > > #define FORCEWAKE_MT_ACK _MMIO(0x130040) > > #define FORCEWAKE_ACK_HSW _MMIO(0x130044) > > #define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044) > > -#define FORCEWAKE_KERNEL BIT(0) > > -#define FORCEWAKE_USER BIT(1) > > +#define FORCEWAKE_KERNEL BIT(0) /* For i915 > > use only */ > > +#define FORCEWAKE_RSVD BIT(1) > > +#define FORCEWAKE_USER BIT(2) > > +#define FORCEWAKE_PCODE BIT(3) > > +#define FORCEWAKE_PSMI BIT(4) > > #define FORCEWAKE_KERNEL_FALLBACK BIT(15) > > #define FORCEWAKE_ACK _MMIO(0x130090) > > #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) > > -- > > 2.34.1 > > > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-04-14 21:30 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-13 21:39 [Intel-gfx] [PATCH] drm/i915: Reserving some Multi-thread forcewake bits Rodrigo Vivi 2022-04-14 3:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork 2022-04-14 21:14 ` [Intel-gfx] [PATCH] " Matt Roper 2022-04-14 21:30 ` Vivi, Rodrigo
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