[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Kever Yang]

The rk3288 spl size is very close to 32KB while the rk3288 bootrom
has the limitation of maximum size of SPL is 32KB. After apply this
patch, the SPL size will exceed 32KB if we do not enable macro
CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.

I think this patch is usful and should be go upstream other than the
size issue.

This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.



Kever Yang (2):
  rk3288: sdram: auto-detect the capacity
  dts: rk3288: remove node in dmc which not need anymore

 arch/arm/dts/rk3288-evb.dts                  |   3 -
 arch/arm/dts/rk3288-fennec.dts               |   3 -
 arch/arm/dts/rk3288-firefly.dts              |   2 -
 arch/arm/dts/rk3288-miniarm.dts              |   3 -
 arch/arm/dts/rk3288-popmetal.dts             |   3 -
 arch/arm/dts/rk3288-rock2-square.dts         |   2 -
 arch/arm/dts/rk3288-veyron.dtsi              |   2 -
 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 237 ++++++++++++++++++++++-----
 8 files changed, 198 insertions(+), 57 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH 1/2] rk3288: sdram: auto-detect the capacity

[Kever Yang]

Add support for rk3288 dram capacity auto detect, support DDR3 and
LPDDR3, DDR2 is not supported.
The program will automatically detect:
- channel number
- rank number
- column address number
- row address number

The dts file do not need to describe those info after apply this patch.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 237 ++++++++++++++++++++++-----
 1 file changed, 198 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index cf9ef2e..faabbd4 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -57,6 +57,10 @@ struct rk3288_sdram_params {
 	struct regmap *map;
 };
 
+#define TEST_PATTEN	0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0	(1 << 4)
+#define DQS_GATE_TRAINING_ERROR_RANK1	(2 << 4)
+
 #ifdef CONFIG_SPL_BUILD
 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
 {
@@ -214,7 +218,7 @@ static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel,
 }
 
 static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
-		     const struct rk3288_sdram_params *sdram_params,
+		     struct rk3288_sdram_params *sdram_params,
 		     struct rk3288_grf *grf)
 {
 	unsigned int burstlen;
@@ -264,7 +268,7 @@ static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
 }
 
 static void phy_cfg(const struct chan_info *chan, u32 channel,
-		    const struct rk3288_sdram_params *sdram_params)
+		    struct rk3288_sdram_params *sdram_params)
 {
 	struct rk3288_ddr_publ *publ = chan->publ;
 	struct rk3288_msch *msch = chan->msch;
@@ -446,7 +450,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
 }
 
 static int data_training(const struct chan_info *chan, u32 channel,
-			 const struct rk3288_sdram_params *sdram_params)
+			 struct rk3288_sdram_params *sdram_params)
 {
 	unsigned int j;
 	int ret = 0;
@@ -549,7 +553,7 @@ static void move_to_access_state(const struct chan_info *chan)
 }
 
 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
-			 const struct rk3288_sdram_params *sdram_params)
+			 struct rk3288_sdram_params *sdram_params)
 {
 	struct rk3288_ddr_publ *publ = chan->publ;
 
@@ -563,7 +567,7 @@ static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
 }
 
 static void dram_all_config(const struct dram_info *dram,
-			    const struct rk3288_sdram_params *sdram_params)
+			    struct rk3288_sdram_params *sdram_params)
 {
 	unsigned int chan;
 	u32 sys_reg = 0;
@@ -589,9 +593,173 @@ static void dram_all_config(const struct dram_info *dram,
 	writel(sys_reg, &dram->pmu->sys_reg[2]);
 	rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
 }
+const int ddrconf_table[] = {
+	/* col	    row */
+	0,
+	((1 << 4) | 1),
+	((2 << 4) | 1),
+	((3 << 4) | 1),
+	((4 << 4) | 1),
+	((1 << 4) | 2),
+	((2 << 4) | 2),
+	((3 << 4) | 2),
+	((1 << 4) | 0),
+	((2 << 4) | 0),
+	((3 << 4) | 0),
+	0,
+	0,
+	0,
+	0,
+	((4 << 4) | 2),
+};
+
+static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
+		struct rk3288_sdram_params *sdram_params)
+{
+	int reg;
+	int need_trainig = 0;
+	const struct chan_info *chan = &dram->chan[channel];
+	struct rk3288_ddr_publ *publ = chan->publ;
+
+	if (-1 == data_training(chan, channel, sdram_params)) {
+		reg = readl(&publ->datx8[0].dxgsr[0]);
+		/* Check the result for rank 0 */
+		if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
+			debug("data training fail!\n");
+				return -EIO;
+		} else if ((channel == 1) &&
+			   (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
+			sdram_params->num_channels = 1;
+		}
+
+		/* Check the result for rank 1 */
+		if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
+			sdram_params->ch[channel].rank = 1;
+			clrsetbits_le32(&publ->pgcr, 0xF << 18,
+					sdram_params->ch[channel].rank << 18);
+			need_trainig = 1;
+		}
+		reg = readl(&publ->datx8[2].dxgsr[0]);
+		if (reg & (1 << 4)) {
+			sdram_params->ch[channel].bw = 1;
+			set_bandwidth_ratio(chan, channel,
+					    sdram_params->ch[channel].bw,
+					    dram->grf);
+			need_trainig = 1;
+		}
+	}
+	/* Assume the Die bit width are the same with the chip bit width*/
+	sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
+
+	if (need_trainig &&
+	    (-1 == data_training(chan, channel, sdram_params))) {
+		if (sdram_params->base.dramtype == LPDDR3) {
+			ddr_phy_ctl_reset(dram->cru, channel, 1);
+			udelay(10);
+			ddr_phy_ctl_reset(dram->cru, channel, 0);
+			udelay(10);
+		}
+		debug("2nd data training failed!");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void sdram_col_row_detect(struct dram_info *dram, int channel,
+		struct rk3288_sdram_params *sdram_params)
+{
+	int row, col;
+	unsigned int addr;
+	const struct chan_info *chan = &dram->chan[channel];
+	struct rk3288_ddr_pctl *pctl = chan->pctl;
+	struct rk3288_ddr_publ *publ = chan->publ;
+	/* Detect col */
+	for (col = 11; col >= 9; col--) {
+		writel(0, CONFIG_SYS_SDRAM_BASE);
+		addr = CONFIG_SYS_SDRAM_BASE +
+			(1 << (col + sdram_params->ch[channel].bw - 1));
+		writel(TEST_PATTEN, addr);
+		if ((readl(addr) == TEST_PATTEN) &&
+		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+			break;
+	}
+	if (col == 8)
+		debug("Col detect error\n");
+	else
+		sdram_params->ch[channel].col = col;
+
+	move_to_config_state(publ, pctl);
+	writel(4, &chan->msch->ddrconf);
+	move_to_access_state(chan);
+	/* Detect row*/
+	for (row = 16; row >= 12; row--) {
+		writel(0, CONFIG_SYS_SDRAM_BASE);
+		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(TEST_PATTEN, addr);
+		if ((readl(addr) == TEST_PATTEN) &&
+		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+			break;
+	}
+	if (row == 11)
+		debug("Row detect error\n");
+	else
+		sdram_params->ch[channel].cs0_row = row;
+	sdram_params->ch[channel].cs1_row = row;
+	sdram_params->ch[channel].row_3_4 = 0;
+	debug("chn %d col %d, row %d\n", channel, col, row);
+}
+
+static void sdram_get_niu_config(struct rk3288_sdram_params *sdram_params)
+{
+	int i, tmp, size;
+
+	tmp = sdram_params->ch[0].col - 9;
+	tmp -= sdram_params->ch[0].bw >> 1;
+	tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4);
+	size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
+	for (i = 0; i < size; i++)
+		if (tmp == ddrconf_table[i])
+			break;
+	if (i >= size)
+		debug("niu config not found\n");
+	else
+		sdram_params->base.ddrconfig = i;
+}
+
+static void sdram_get_stride(struct rk3288_sdram_params *sdram_params)
+{
+	int stride = -1;
+	long cap = sdram_params->num_channels * (1u <<
+			(sdram_params->ch[0].cs0_row +
+			 sdram_params->ch[0].col +
+			 (sdram_params->ch[0].rank - 1) +
+			 sdram_params->ch[0].bw +
+			 3 - 20));
+
+	switch (cap) {
+	case 512:
+		stride = 0;
+		break;
+	case 1024:
+		stride = 5;
+		break;
+	case 2048:
+		stride = 9;
+		break;
+	case 4096:
+		stride = 0xd;
+		break;
+	default:
+		stride = -1;
+		debug("could not find correct stride, cap error!\n");
+		break;
+	}
+	sdram_params->base.stride = stride;
+}
 
 static int sdram_init(struct dram_info *dram,
-		      const struct rk3288_sdram_params *sdram_params)
+		      struct rk3288_sdram_params *sdram_params)
 {
 	int channel;
 	int zqcr;
@@ -619,12 +787,13 @@ static int sdram_init(struct dram_info *dram,
 		struct rk3288_ddr_pctl *pctl = chan->pctl;
 		struct rk3288_ddr_publ *publ = chan->publ;
 
+		if (channel)
+			rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17);
+		else
+			rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a);
 		phy_pctrl_reset(dram->cru, publ, channel);
 		phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
 
-		if (channel >= sdram_params->num_channels)
-			continue;
-
 		dfi_cfg(pctl, sdram_params->base.dramtype);
 
 		pctl_cfg(channel, pctl, sdram_params, dram->grf);
@@ -658,16 +827,20 @@ static int sdram_init(struct dram_info *dram,
 			udelay(1);
 		}
 
+		/* Using 32bit bus width for detect */
+		sdram_params->ch[channel].bw = 2;
 		set_bandwidth_ratio(chan, channel,
 				    sdram_params->ch[channel].bw, dram->grf);
 		/*
-		 * set cs
+		 * set cs, using n=3 for detect
 		 * CS0, n=1
 		 * CS1, n=2
 		 * CS0 & CS1, n = 3
 		 */
+		sdram_params->ch[channel].rank = 2,
 		clrsetbits_le32(&publ->pgcr, 0xF << 18,
 				(sdram_params->ch[channel].rank | 1) << 18);
+
 		/* DS=40ohm,ODT=155ohm */
 		zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
 			2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
@@ -693,16 +866,8 @@ static int sdram_init(struct dram_info *dram,
 			}
 		}
 
-		if (-1 == data_training(chan, channel, sdram_params)) {
-			if (sdram_params->base.dramtype == LPDDR3) {
-				ddr_phy_ctl_reset(dram->cru, channel, 1);
-				udelay(10);
-				ddr_phy_ctl_reset(dram->cru, channel, 0);
-				udelay(10);
-			}
-			debug("failed!");
-			return -EIO;
-		}
+		/* Detect the rank and bit-width with data-training */
+		sdram_rank_bw_detect(dram, channel, sdram_params);
 
 		if (sdram_params->base.dramtype == LPDDR3) {
 			u32 i;
@@ -710,8 +875,18 @@ static int sdram_init(struct dram_info *dram,
 			for (i = 0; i < 17; i++)
 				send_command_op(pctl, 1, MRR_CMD, i, 0);
 		}
+		writel(15, &chan->msch->ddrconf);
 		move_to_access_state(chan);
+		/* DDR3 and LPDDR3 are always 8 bank, no need detect */
+		sdram_params->ch[channel].bk = 3;
+		/* Detect Col and Row number*/
+		sdram_col_row_detect(dram, channel, sdram_params);
 	}
+	/* Find NIU DDR configuration */
+	sdram_get_niu_config(sdram_params);
+	/* Find stride setting */
+	sdram_get_stride(sdram_params);
+
 	dram_all_config(dram, sdram_params);
 	debug("%s done\n", __func__);
 
@@ -743,7 +918,6 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
 			SYS_REG_BW_MASK));
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
-
 		chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
 
 		if (rank > 1)
@@ -814,21 +988,10 @@ static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
 	struct rk3288_sdram_params *params = dev_get_platdata(dev);
 	const void *blob = gd->fdt_blob;
 	int node = dev->of_offset;
-	int i, ret;
+	int ret;
 
-	params->num_channels = fdtdec_get_int(blob, node,
-					      "rockchip,num-channels", 1);
-	for (i = 0; i < params->num_channels; i++) {
-		ret = fdtdec_get_byte_array(blob, node,
-					    "rockchip,sdram-channel",
-					    (u8 *)&params->ch[i],
-					    sizeof(params->ch[i]));
-		if (ret) {
-			debug("%s: Cannot read rockchip,sdram-channel\n",
-			      __func__);
-			return -EINVAL;
-		}
-	}
+	/* Controller support dual-channel, set default channel num to 2 */
+	params->num_channels = 2;
 	ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
 				   (u32 *)&params->pctl_timing,
 				   sizeof(params->pctl_timing) / sizeof(u32));
@@ -871,10 +1034,6 @@ static int conv_of_platdata(struct udevice *dev)
 	struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
 	int i, ret;
 
-	for (i = 0; i < 2; i++) {
-		memcpy(&plat->ch[i], of_plat->rockchip_sdram_channel,
-		       sizeof(plat->ch[i]));
-	}
 	memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
 	       sizeof(plat->pctl_timing));
 	memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
-- 
1.9.1

[U-Boot] [PATCH 2/2] dts: rk3288: remove node in dmc which not need anymore

[Kever Yang]

Since we implement the dram capacity auto detect, we don't
need to set the channel number and sdram-channel in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/dts/rk3288-evb.dts          | 3 ---
 arch/arm/dts/rk3288-fennec.dts       | 3 ---
 arch/arm/dts/rk3288-firefly.dts      | 2 --
 arch/arm/dts/rk3288-miniarm.dts      | 3 ---
 arch/arm/dts/rk3288-popmetal.dts     | 3 ---
 arch/arm/dts/rk3288-rock2-square.dts | 2 --
 arch/arm/dts/rk3288-veyron.dtsi      | 2 --
 7 files changed, 18 deletions(-)

diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts
index 3e1ee58..3f03e13 100644
--- a/arch/arm/dts/rk3288-evb.dts
+++ b/arch/arm/dts/rk3288-evb.dts
@@ -17,7 +17,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
 		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
 		0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
@@ -25,8 +24,6 @@
 		0x8 0x1f4>;
 	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
 		0x0 0xc3 0x6 0x2>;
-	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>;
 	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
 };
 
diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts
index 36e9f3d..66ddf8d 100644
--- a/arch/arm/dts/rk3288-fennec.dts
+++ b/arch/arm/dts/rk3288-fennec.dts
@@ -17,7 +17,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
 		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
 		0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
@@ -25,8 +24,6 @@
 		0x8 0x1f4>;
 	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
 		0x0 0xc3 0x6 0x2>;
-	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>;
 	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
 };
 
diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
index 3176d50..97568a3 100644
--- a/arch/arm/dts/rk3288-firefly.dts
+++ b/arch/arm/dts/rk3288-firefly.dts
@@ -22,7 +22,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -31,7 +30,6 @@
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
 	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 
diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts
index c741082..9083028 100644
--- a/arch/arm/dts/rk3288-miniarm.dts
+++ b/arch/arm/dts/rk3288-miniarm.dts
@@ -17,7 +17,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -25,8 +24,6 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 
diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts
index 3f61a61..284d5ed 100644
--- a/arch/arm/dts/rk3288-popmetal.dts
+++ b/arch/arm/dts/rk3288-popmetal.dts
@@ -17,7 +17,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -25,8 +24,6 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 
diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
index 2c30355..11c580a 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -184,7 +184,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -192,7 +191,6 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index d9d5187..2ffe39c 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -245,7 +245,6 @@
 		533000 1150000
 		666000 1200000
 	>;
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -253,7 +252,6 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 
-- 
1.9.1

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Vagrant Cascadian]

On 2016-09-08, Kever Yang wrote:
> The rk3288 spl size is very close to 32KB while the rk3288 bootrom
> has the limitation of maximum size of SPL is 32KB. After apply this
> patch, the SPL size will exceed 32KB if we do not enable macro
> CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.
>
> I think this patch is usful and should be go upstream other than the
> size issue.
>
> This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.

Thanks for the patch!

Unfortunately, fails to build the firefly-rk3288 target, using
arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1 20160705, applied to
u-boot master 01c5075506afcb7a74e0db8600af8979f45881b5:

  CC      spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function
  'conv_of_platdata':
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1042:30: error: 'struct
  dtd_rockchip_rk3288_dmc' has no member named 'rockchip_num_channels';
  did you mean 'rockchip_noc'?
  plat->num_channels = of_plat->rockchip_num_channels;
                              ^~
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1035:6: warning: unused
  variable 'i' [-Wunused-variable]
  int i, ret;
      ^
scripts/Makefile.build:280: recipe for target
  'spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o' failed
make[3]: *** [spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o] Error 1
scripts/Makefile.build:425: recipe for target
  'spl/arch/arm/mach-rockchip/rk3288' failed
make[2]: *** [spl/arch/arm/mach-rockchip/rk3288] Error 2
scripts/Makefile.spl:292: recipe for target 'spl/arch/arm/mach-rockchip'
  failed
make[1]: *** [spl/arch/arm/mach-rockchip] Error 2
Makefile:1334: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2


live well,
  vagrant
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[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Ziyuan Xu]

hi Vagrant,


On 2016?09?09? 03:28, Vagrant Cascadian wrote:
> On 2016-09-08, Kever Yang wrote:
>> The rk3288 spl size is very close to 32KB while the rk3288 bootrom
>> has the limitation of maximum size of SPL is 32KB. After apply this
>> patch, the SPL size will exceed 32KB if we do not enable macro
>> CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.
>>
>> I think this patch is usful and should be go upstream other than the
>> size issue.
>>
>> This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.
> Thanks for the patch!
>
> Unfortunately, fails to build the firefly-rk3288 target, using
> arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1 20160705, applied to
> u-boot master 01c5075506afcb7a74e0db8600af8979f45881b5:
>
>    CC      spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o
> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function
>    'conv_of_platdata':
> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1042:30: error: 'struct
>    dtd_rockchip_rk3288_dmc' has no member named 'rockchip_num_channels';
>    did you mean 'rockchip_noc'?
>    plat->num_channels = of_plat->rockchip_num_channels;

-       plat->num_channels = of_plat->rockchip_num_channels;
+       plat->num_channels = 2;

firefly-rk3288 deploy CONFIG_OF_PLATDATA,  driver read platform data 
from include/generated/dt-structs.h which is generated according to dts 
file.
Please try above change.

@Kever,

Please fix below.

arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function 
?conv_of_platdata?:
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1035:6: warning: unused 
variable ?i? [-Wunused-variable]


>                                ^~
> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1035:6: warning: unused
>    variable 'i' [-Wunused-variable]
>    int i, ret;
>        ^
> scripts/Makefile.build:280: recipe for target
>    'spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o' failed
> make[3]: *** [spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o] Error 1
> scripts/Makefile.build:425: recipe for target
>    'spl/arch/arm/mach-rockchip/rk3288' failed
> make[2]: *** [spl/arch/arm/mach-rockchip/rk3288] Error 2
> scripts/Makefile.spl:292: recipe for target 'spl/arch/arm/mach-rockchip'
>    failed
> make[1]: *** [spl/arch/arm/mach-rockchip] Error 2
> Makefile:1334: recipe for target 'spl/u-boot-spl' failed
> make: *** [spl/u-boot-spl] Error 2
>
>
> live well,
>    vagrant

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Vagrant Cascadian]

On 2016-09-10, Ziyuan Xu wrote:
> On 2016?09?09? 03:28, Vagrant Cascadian wrote:
>> On 2016-09-08, Kever Yang wrote:
>>> The rk3288 spl size is very close to 32KB while the rk3288 bootrom
>>> has the limitation of maximum size of SPL is 32KB. After apply this
>>> patch, the SPL size will exceed 32KB if we do not enable macro
>>> CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.

With CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y, it fails to boot with no output
on the console.


>>> This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.
>> Thanks for the patch!
>>
>> Unfortunately, fails to build the firefly-rk3288 target, using
>> arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1 20160705, applied to
>> u-boot master 01c5075506afcb7a74e0db8600af8979f45881b5:
>>
>>    CC      spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o
>> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function
>>    'conv_of_platdata':
>> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1042:30: error: 'struct
>>    dtd_rockchip_rk3288_dmc' has no member named 'rockchip_num_channels';
>>    did you mean 'rockchip_noc'?
>>    plat->num_channels = of_plat->rockchip_num_channels;
>
> -       plat->num_channels = of_plat->rockchip_num_channels;
> +       plat->num_channels = 2;
>
> firefly-rk3288 deploy CONFIG_OF_PLATDATA,  driver read platform data
> from include/generated/dt-structs.h which is generated according to dts
> file.
> Please try above change.

With this change, it builds, but it hangs at boot:

  U-Boot SPL 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28)
  Trying to boot from MMC1


  U-Boot 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28 +0000)

  Model: Firefly-RK3288
  DRAM:

This is on a firefly with 2GB of ram. I also have one with 4GB of ram,
hence my interest in this patch series!


live well,
  vagrant
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[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Ziyuan Xu]

hi Vagrant,


On 2016?09?11? 03:01, Vagrant Cascadian wrote:
> On 2016-09-10, Ziyuan Xu wrote:
>> On 2016?09?09? 03:28, Vagrant Cascadian wrote:
>>> On 2016-09-08, Kever Yang wrote:
>>>> The rk3288 spl size is very close to 32KB while the rk3288 bootrom
>>>> has the limitation of maximum size of SPL is 32KB. After apply this
>>>> patch, the SPL size will exceed 32KB if we do not enable macro
>>>> CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.
> With CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y, it fails to boot with no output
> on the console.
>
>
>>>> This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.
>>> Thanks for the patch!
>>>
>>> Unfortunately, fails to build the firefly-rk3288 target, using
>>> arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1 20160705, applied to
>>> u-boot master 01c5075506afcb7a74e0db8600af8979f45881b5:
>>>
>>>     CC      spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o
>>> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function
>>>     'conv_of_platdata':
>>> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1042:30: error: 'struct
>>>     dtd_rockchip_rk3288_dmc' has no member named 'rockchip_num_channels';
>>>     did you mean 'rockchip_noc'?
>>>     plat->num_channels = of_plat->rockchip_num_channels;
>> -       plat->num_channels = of_plat->rockchip_num_channels;
>> +       plat->num_channels = 2;
>>
>> firefly-rk3288 deploy CONFIG_OF_PLATDATA,  driver read platform data
>> from include/generated/dt-structs.h which is generated according to dts
>> file.
>> Please try above change.
> With this change, it builds, but it hangs at boot:
>
>    U-Boot SPL 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28)
>    Trying to boot from MMC1
>
>
>    U-Boot 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28 +0000)
>
>    Model: Firefly-RK3288
>    DRAM:

Could you help to add DEBUG macro in common.h like:
#indef CONFIG_SPL_BUILD
#define DEBUG
#endif

So that we can figure out where it is.

>
> This is on a firefly with 2GB of ram. I also have one with 4GB of ram,
> hence my interest in this patch series!
>
>
> live well,
>    vagrant

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Sandy Patterson]

Hi Kever,

With regards to the SPL size issue, I believe that the
CONFIG_ROCKCHIP_SPL_BACK_TO_BROM option should work with
all of the rk3288 boards. So if your patch causes unbootable SPL's because
they're too big, then you should probably enable the BROM macro (and
disable OF_PLATDATA).

Firefly uses a different method to shrink the SPL which causes a bunch of
changes
throughout the codebase. This patch would need to be applied to the
OF_PLATDATA
sections for firefly to work.

Vagrant,

An alternative for you might be to disable OF_PLATDATA for firefly and
enable BACK_TO_BROM.
You may not be getting any output because you didn't modify your burning
process.
See the README.rockchip section on CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
for details, but you have to dd your images slightly differently with this
macro enabled.

Also, you might get more info from Ziyuan's DEBUG advice.

Sandy Patterson


On Sun, Sep 11, 2016 at 10:01 PM, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:

> hi Vagrant,
>
>
>
> On 2016?09?11? 03:01, Vagrant Cascadian wrote:
>
>> On 2016-09-10, Ziyuan Xu wrote:
>>
>>> On 2016?09?09? 03:28, Vagrant Cascadian wrote:
>>>
>>>> On 2016-09-08, Kever Yang wrote:
>>>>
>>>>> The rk3288 spl size is very close to 32KB while the rk3288 bootrom
>>>>> has the limitation of maximum size of SPL is 32KB. After apply this
>>>>> patch, the SPL size will exceed 32KB if we do not enable macro
>>>>> CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.
>>>>>
>>>> With CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y, it fails to boot with no
>> output
>> on the console.
>>
>>
>> This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.
>>>>>
>>>> Thanks for the patch!
>>>>
>>>> Unfortunately, fails to build the firefly-rk3288 target, using
>>>> arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1 20160705, applied to
>>>> u-boot master 01c5075506afcb7a74e0db8600af8979f45881b5:
>>>>
>>>>     CC      spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o
>>>> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function
>>>>     'conv_of_platdata':
>>>> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1042:30: error: 'struct
>>>>     dtd_rockchip_rk3288_dmc' has no member named
>>>> 'rockchip_num_channels';
>>>>     did you mean 'rockchip_noc'?
>>>>     plat->num_channels = of_plat->rockchip_num_channels;
>>>>
>>> -       plat->num_channels = of_plat->rockchip_num_channels;
>>> +       plat->num_channels = 2;
>>>
>>> firefly-rk3288 deploy CONFIG_OF_PLATDATA,  driver read platform data
>>> from include/generated/dt-structs.h which is generated according to dts
>>> file.
>>> Please try above change.
>>>
>> With this change, it builds, but it hangs at boot:
>>
>>    U-Boot SPL 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28)
>>    Trying to boot from MMC1
>>
>>
>>    U-Boot 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28 +0000)
>>
>>    Model: Firefly-RK3288
>>    DRAM:
>>
>
> Could you help to add DEBUG macro in common.h like:
> #indef CONFIG_SPL_BUILD
> #define DEBUG
> #endif
>
> So that we can figure out where it is.
>
>
>
>> This is on a firefly with 2GB of ram. I also have one with 4GB of ram,
>> hence my interest in this patch series!
>>
>>
>> live well,
>>    vagrant
>>
>
>
>

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Kever Yang]

Hi Sandy Patterson,

On 09/15/2016 08:00 PM, Sandy Patterson wrote:
> Hi Kever,
>
> With regards to the SPL size issue, I believe that the
> CONFIG_ROCKCHIP_SPL_BACK_TO_BROM option should work with
> all of the rk3288 boards. So if your patch causes unbootable SPL's because
> they're too big, then you should probably enable the BROM macro (and 
> disable OF_PLATDATA).
>
> Firefly uses a different method to shrink the SPL which causes a bunch 
> of changes
> throughout the codebase. This patch would need to be applied to the 
> OF_PLATDATA
> sections for firefly to work.

Thanks for your comment, I will update a V2 patch after I make sure it 
works with other board,
but I don't have a firefly on my hand currently.

I think you mean my patch need to work with:
- BROM enabled and OF_PLATDATA disabled
- BROM disabled and OF_PLATDATA enabled
right?

>
> Vagrant,
>
> An alternative for you might be to disable OF_PLATDATA for firefly and 
> enable BACK_TO_BROM.
> You may not be getting any output because you didn't modify your 
> burning process.
> See the README.rockchip section on CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
> for details, but you have to dd your images slightly differently with 
> this macro enabled.
>
> Also, you might get more info from Ziyuan's DEBUG advice.

Hi Vagrant,

     Once you see the SPL output message, that means the DRAM init is 
OK, to double check if the DRAM
init correct, you can add log for return value of sdram_size_mb() after 
apply my patch.

Thanks,
- Kever
>
> Sandy Patterson
>
>
> On Sun, Sep 11, 2016 at 10:01 PM, Ziyuan Xu <xzy.xu@rock-chips.com 
> <mailto:xzy.xu@rock-chips.com>> wrote:
>
>     hi Vagrant,
>
>
>
>     On 2016?09?11? 03:01, Vagrant Cascadian wrote:
>
>         On 2016-09-10, Ziyuan Xu wrote:
>
>             On 2016?09?09? 03:28, Vagrant Cascadian wrote:
>
>                 On 2016-09-08, Kever Yang wrote:
>
>                     The rk3288 spl size is very close to 32KB while
>                     the rk3288 bootrom
>                     has the limitation of maximum size of SPL is 32KB.
>                     After apply this
>                     patch, the SPL size will exceed 32KB if we do not
>                     enable macro
>                     CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.
>
>         With CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y, it fails to boot with
>         no output
>         on the console.
>
>
>                     This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.
>
>                 Thanks for the patch!
>
>                 Unfortunately, fails to build the firefly-rk3288
>                 target, using
>                 arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1
>                 20160705, applied to
>                 u-boot master 01c5075506afcb7a74e0db8600af8979f45881b5:
>
>                     CC     
>                 spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o
>                 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function
>                     'conv_of_platdata':
>                 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1042:30:
>                 error: 'struct
>                     dtd_rockchip_rk3288_dmc' has no member named
>                 'rockchip_num_channels';
>                     did you mean 'rockchip_noc'?
>                     plat->num_channels = of_plat->rockchip_num_channels;
>
>             -       plat->num_channels = of_plat->rockchip_num_channels;
>             +       plat->num_channels = 2;
>
>             firefly-rk3288 deploy CONFIG_OF_PLATDATA,  driver read
>             platform data
>             from include/generated/dt-structs.h which is generated
>             according to dts
>             file.
>             Please try above change.
>
>         With this change, it builds, but it hangs at boot:
>
>            U-Boot SPL 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 -
>         18:51:28)
>            Trying to boot from MMC1
>
>
>            U-Boot 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 -
>         18:51:28 +0000)
>
>            Model: Firefly-RK3288
>            DRAM:
>
>
>     Could you help to add DEBUG macro in common.h like:
>     #indef CONFIG_SPL_BUILD
>     #define DEBUG
>     #endif
>
>     So that we can figure out where it is.
>
>
>
>         This is on a firefly with 2GB of ram. I also have one with 4GB
>         of ram,
>         hence my interest in this patch series!
>
>
>         live well,
>            vagrant
>
>
>
>

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Vagrant Cascadian]

On 2016-09-15, Sandy Patterson wrote:
> An alternative for you might be to disable OF_PLATDATA for firefly and
> enable BACK_TO_BROM.

I wasn't able to successfully build with OF_PLATDATA disabled; sounds
like there are more patches needed for firefly for that to work.


> You may not be getting any output because you didn't modify your burning
> process.
> See the README.rockchip section on CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
> for details, but you have to dd your images slightly differently with this
> macro enabled.

Thanks! Unfortunately, even after using the burning process for
CONFIG_ROCKCHIP_SPL_BACK_TO_BROM described in README.rockchip.

The patches (on top of what was submitted in this series) I've applied
to v2016.09 are:

Index: u-boot/include/common.h
===================================================================
--- u-boot.orig/include/common.h
+++ u-boot/include/common.h
@@ -95,6 +95,10 @@ typedef volatile unsigned char	vu_char;
 #define CONFIG_SYS_SUPPORT_64BIT_DATA
 #endif
 
+#ifndef CONFIG_SPL_BUILD
+#define DEBUG
+#endif
+
 #ifdef DEBUG
 #define _DEBUG	1
 #else

Index: u-boot/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
===================================================================
--- u-boot.orig/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ u-boot/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -1039,7 +1039,7 @@ static int conv_of_platdata(struct udevi
 	memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
 	       sizeof(plat->phy_timing));
 	memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
-	plat->num_channels = of_plat->rockchip_num_channels;
+	plat->num_channels = 2;
 	ret = regmap_init_mem_platdata(dev, of_plat->reg,
 				       ARRAY_SIZE(of_plat->reg) / 2,
 				       &plat->map);

Index: u-boot/configs/firefly-rk3288_defconfig
===================================================================
--- u-boot.orig/configs/firefly-rk3288_defconfig
+++ u-boot/configs/firefly-rk3288_defconfig
@@ -70,3 +70,4 @@ CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
 # CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y


I think I'll wait for an updated series to do more tests, so I'm not
testing patches on patches on patches. Also reduces the liklihood of me
misinterpreting what people are suggesting to try.


live well,
  vagrant
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[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Sandy Patterson]

Hi Kever and Vagrant,

I tested this patch on my rock2 board against 2016.09. (I didn't have my
board with me over the weekend)

1) It seems the BACK_TO_BROM feature is broken. It doesn't boot using the
2016.09. I'm afraid I don't have the time to track it down.
2) It seems the SPL is still small enough to test this feature. (vagrant
you can forget about the back to brom feature unless you need more SPL
space).

3) I get the same behavior as Vagrant on the rock2 board. I'm including
DEBUG output in case that helps Kever. I tried to trace it, but it seems a
larger undertaking than I can manage right now. (vagrant, you can add DEBUG
#define's into the file include/configs/firefly-rk3288.h to get the output
below.. my guess is it's similar.)

This trace is almost exactly the same between enabling the SDRAM detection
and not. I marked the point where it halts. The fdt is a slightly different
size, but that is expected.

Sandy


initcall: 0010af55
U-Boot code: 00100000 -> 0014F8C0  BSS: -> 0018D1B8
initcall: 0010add1
initcall: 0010b359
Model: Radxa Rock 2 Square
initcall: 0010af95
DRAM:  initcall: 00100d19
malloc_simple: size=3c, ptr=7d8, limit=2000: fe79c
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1
   - not found
fdtdec_get_int_array: interrupts
get_prop_check_min_len: interrupts
malloc_simple: size=4, ptr=7dc, limit=2000: fe7d8
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 1
   - -1 -1
   - -1 0
   - found
uclass_find_device_by_seq: 0 1
   - -1 1
   - found
uclass_find_device_by_seq: 0 2
   - -1 1
   - -1 -1
   - -1 0
   - -1 -1
   - not found
fdtdec_get_int_array: interrupts
get_prop_check_min_len: interrupts
malloc_simple: size=14, ptr=7f0, limit=2000: fe7dc
malloc_simple: size=4, ptr=7f4, limit=2000: fe7f0
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 1
   - -1 -1
   - -1 0
   - found
uclass_find_device_by_seq: 0 1
   - -1 1
   - found
uclass_find_device_by_seq: 0 2
   - -1 1
   - -1 -1
   - -1 0
   - -1 2
   - found
uclass_find_device_by_seq: 0 3
   - -1 1
   - -1 -1
   - -1 0
   - -1 2
   - not found
fdtdec_get_int_array: interrupts
get_prop_check_min_len: interrupts
malloc_simple: size=14, ptr=808, limit=2000: fe7f4
malloc_simple: size=c, ptr=814, limit=2000: fe808
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1
   - not found
fdtdec_get_int_array: interrupts
get_prop_check_min_len: interrupts
OF: ** translation for device clock-controller at ff760000 **
OF: bus is default (na=1, ns=1) on
OF: translating address: 000076ff
OF: reached root node
clk_request(dev=000fe474, clk=000fe7bc)
SDRAM base=0, size=80000000
initcall: 0010b129
Monitor len: 0008D1B8
Ram size: 80000000
Ram top: 80000000
initcall: 0010adf1
initcall: 0010af0d
TLB table from 7fff0000 to 7fff4000
initcall: 0010af75
video_reserve: Reserving 4f0000 bytes at 7fb00000 for video device
'vop at ff940000'
Video frame buffers from 7fb00000 to 7fff0000
initcall: 0010ae05
initcall: 0010aecd
Reserving 564k for U-Boot at: 7fa72000
initcall: 0010aea5
Reserving 32776k for malloc() at: 7da70000
initcall: 0010b059
Reserving 80 Bytes for Board Info at: 7da6ffb0
initcall: 0010ae09
initcall: 0010ae7d
Reserving 200 Bytes for Global Data at: 7da6fee8
initcall: 0010ae2d
Reserving 38464 Bytes for FDT at: 7da668a8
initcall: 0010ae11
initcall: 0010b18d
initcall: 0010b113
initcall: 0010b099

RAM Configuration:
====== SDRAM DETECTION FEATURE HALTS HERE ========
Bank #0: 0 2 GiB

DRAM:  2 GiB
initcall: 0010ae19
New Stack Pointer is: 7da66880
initcall: 0010b02d
initcall: 0010afd5
Relocation Offset is: 7f972000
Relocating to 7fa72000, new gd at 7da6fee8, sp at 7da66880
initcall: 7fa7d1cd
initcall: 7fa7d1d1
initcall: 0010b32d (relocated to 7fa7d32d)
dram_bank_mmu_setup: bank: 0
initcall: 0010b305 (relocated to 7fa7d305)
efi_runtime_relocate: Relocating to offset=7fa72000

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Kever Yang]

Hi Sandy,

On 09/19/2016 09:33 PM, Sandy Patterson wrote:
> Hi Kever and Vagrant,
>
> I tested this patch on my rock2 board against 2016.09. (I didn't have 
> my board with me over the weekend)

Thanks for your test and for your log, my source code do have one bug 
and I have fix and upload the V2 patch set.

>
> 1) It seems the BACK_TO_BROM feature is broken. It doesn't boot using 
> the 2016.09. I'm afraid I don't have the time to track it down.
It works fine on my evb, do you flash the image correctly? it's 
different with the way you don't use BACK_TO_BROM.

Regards,
- Kever
> 2) It seems the SPL is still small enough to test this feature. 
> (vagrant you can forget about the back to brom feature unless you need 
> more SPL space).
>
> 3) I get the same behavior as Vagrant on the rock2 board. I'm 
> including DEBUG output in case that helps Kever. I tried to trace it, 
> but it seems a larger undertaking than I can manage right now. 
> (vagrant, you can add DEBUG #define's into the 
> file include/configs/firefly-rk3288.h to get the output below.. my 
> guess is it's similar.)
>
> This trace is almost exactly the same between enabling the SDRAM 
> detection and not. I marked the point where it halts. The fdt is a 
> slightly different size, but that is expected.
>
> Sandy
>
>
> initcall: 0010af55
> U-Boot code: 00100000 -> 0014F8C0  BSS: -> 0018D1B8
> initcall: 0010add1
> initcall: 0010b359
> Model: Radxa Rock 2 Square
> initcall: 0010af95
> DRAM:  initcall: 00100d19
> malloc_simple: size=3c, ptr=7d8, limit=2000: fe79c
> uclass_find_device_by_seq: 0 -1
> uclass_find_device_by_seq: 0 0
>    - -1 -1
>    - not found
> fdtdec_get_int_array: interrupts
> get_prop_check_min_len: interrupts
> malloc_simple: size=4, ptr=7dc, limit=2000: fe7d8
> uclass_find_device_by_seq: 0 -1
> uclass_find_device_by_seq: 0 0
>    - -1 1
>    - -1 -1
>    - -1 0
>    - found
> uclass_find_device_by_seq: 0 1
>    - -1 1
>    - found
> uclass_find_device_by_seq: 0 2
>    - -1 1
>    - -1 -1
>    - -1 0
>    - -1 -1
>    - not found
> fdtdec_get_int_array: interrupts
> get_prop_check_min_len: interrupts
> malloc_simple: size=14, ptr=7f0, limit=2000: fe7dc
> malloc_simple: size=4, ptr=7f4, limit=2000: fe7f0
> uclass_find_device_by_seq: 0 -1
> uclass_find_device_by_seq: 0 0
>    - -1 1
>    - -1 -1
>    - -1 0
>    - found
> uclass_find_device_by_seq: 0 1
>    - -1 1
>    - found
> uclass_find_device_by_seq: 0 2
>    - -1 1
>    - -1 -1
>    - -1 0
>    - -1 2
>    - found
> uclass_find_device_by_seq: 0 3
>    - -1 1
>    - -1 -1
>    - -1 0
>    - -1 2
>    - not found
> fdtdec_get_int_array: interrupts
> get_prop_check_min_len: interrupts
> malloc_simple: size=14, ptr=808, limit=2000: fe7f4
> malloc_simple: size=c, ptr=814, limit=2000: fe808
> uclass_find_device_by_seq: 0 -1
> uclass_find_device_by_seq: 0 0
>    - -1 -1
>    - not found
> fdtdec_get_int_array: interrupts
> get_prop_check_min_len: interrupts
> OF: ** translation for device clock-controller at ff760000 **
> OF: bus is default (na=1, ns=1) on
> OF: translating address: 000076ff
> OF: reached root node
> clk_request(dev=000fe474, clk=000fe7bc)
> SDRAM base=0, size=80000000
> initcall: 0010b129
> Monitor len: 0008D1B8
> Ram size: 80000000
> Ram top: 80000000
> initcall: 0010adf1
> initcall: 0010af0d
> TLB table from 7fff0000 to 7fff4000
> initcall: 0010af75
> video_reserve: Reserving 4f0000 bytes at 7fb00000 for video device 
> 'vop at ff940000'
> Video frame buffers from 7fb00000 to 7fff0000
> initcall: 0010ae05
> initcall: 0010aecd
> Reserving 564k for U-Boot at: 7fa72000
> initcall: 0010aea5
> Reserving 32776k for malloc() at: 7da70000
> initcall: 0010b059
> Reserving 80 Bytes for Board Info at: 7da6ffb0
> initcall: 0010ae09
> initcall: 0010ae7d
> Reserving 200 Bytes for Global Data at: 7da6fee8
> initcall: 0010ae2d
> Reserving 38464 Bytes for FDT at: 7da668a8
> initcall: 0010ae11
> initcall: 0010b18d
> initcall: 0010b113
> initcall: 0010b099
>
> RAM Configuration:
> ====== SDRAM DETECTION FEATURE HALTS HERE ========
> Bank #0: 0 2 GiB
>
> DRAM:  2 GiB
> initcall: 0010ae19
> New Stack Pointer is: 7da66880
> initcall: 0010b02d
> initcall: 0010afd5
> Relocation Offset is: 7f972000
> Relocating to 7fa72000, new gd at 7da6fee8, sp at 7da66880
> initcall: 7fa7d1cd
> initcall: 7fa7d1d1
> initcall: 0010b32d (relocated to 7fa7d32d)
> dram_bank_mmu_setup: bank: 0
> initcall: 0010b305 (relocated to 7fa7d305)
> efi_runtime_relocate: Relocating to offset=7fa72000
>

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Sandy Patterson]

>
> 1) It seems the BACK_TO_BROM feature is broken. It doesn't boot using the
>> 2016.09. I'm afraid I don't have the time to track it down.
>>
> It works fine on my evb, do you flash the image correctly? it's different
> with the way you don't use BACK_TO_BROM.
>

Well, I tested again on the latest master branch and its working now. I
probably had something screwed up. I did notice that the BACK_TO_BROM was
moved to Kconfig.