* [PATCH V4 00/62] Updating SPEAr Support
@ 2011-01-18 7:11 Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 01/62] spear/vmalloc.h: Appending UL to VMALLOC_END Viresh Kumar
` (61 more replies)
0 siblings, 62 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Following set of patches:
- updates SPEAr3xx, 6xx support
- Adds support for SPEAr13xx
- Removes Multiple defconfigs per machine family
Changes since V3:
- SPEAr13xx: gic init, smp and hotplug code updated w.r.t. latest linus/master
- Appending UL to VMALLOC_END Macros
- readl & writle _relaxed used instread _raw in uncompress.h
- infinite loop removed from arch_reset() in
mach-spear13xx/include/mach/system.h
- patch: ST-SPEAr13xx-Modified-static-mappings is broken into two patches.
Now, static mapping for SPEAr1310 RAS will be present only on 1310 machine.
- Updated commit message of: SPEAr Power Management: Added the support for
Standby mode
- Default ssp freq changed to 25MHz.
- patch: ST-SPEAr-13xx-Adding-support-for-SPEAr1310 is splitted into two
patches. Separate patch for 320 CAN is added.
- Wrapper routine spi_init() in spear*evb.c files is removed.
- routine i2c_register_board_devices() is renamed to
i2c_register_default_devices() in arch/arm/plat-spear/i2c_eval_board.c file
- Following patches are removed from this patchset, they will be added
separately:
ST-SPEAr-FSMC-Flexible-Static-Memory-Controller-NOR-.patch
- Following patches are already present in linus-next or already Acked, so they
are also removed from this patchset:
Newly-erased-page-read-workaround.patch
Changes since V2:
- Following patches are removed from this patchset, as they are still under
review:
ST SPEAr: PCIE gadget suppport
ST SPEAr13xx: Adding machine support for pci gadget
ST SPEAr: Add smi driver for serial NOR flash
ST SPEAr: Adding support for serial nor flash in all spear platforms
- Following patches are already present in linus-next, so they are also removed
from this patchset:
mtd/fsmc.h: including linux/io.h for definition of readl
Keyboard: Adding support for spear-keyboard
USB host: Adding USB ehci & ohci support for spear platform
- spear-keyboard machine support is updated according to updations in driver
(driver is already in linus-next)
- rtc driver is updated and ioctl routine is removed.
Changes since V1:
- sev definitions moved to system.h and removed from spear and omap archs
- bug fix added in system controller file sp810.h
- Review Comments incorporated
- Driver and machine support are divided into separate patches
- Nand Driver is removed from patch list as it is already floated by Linus
Walleij.
- Few later patches of SPEAr13xx Patches are merged with initial patches of
SPEAr13xx
- Smaller Defconfigs are used instead of large.
- Clock renaming & minor corrections are moved to clock specific patches from
peripheral machine support patches.
- Removed Commented code related to SPI
- [PATCH] Incrementing the ecc_pos array to contain 128 char - is removed from
list
- Board specific code is moved to *evb.c files from machine files for EMI NOR
- replaced readl with __raw_readl in uncompress.h in plat-spear/include/plat/
Rebased over linus: v2.6.37
e6f597a1425b5af64917be3448b29e2d5a585ac8
Bhupesh Sharma (1):
ST SPEAr 13xx : Adding support for SPEAr1310
Deepak Sikri (5):
ST SPEAr: Adding machine support for USB host
SPEAr Clock Framework: Adding support for PLL frequency change
SPEAr Power Management: Added the support for Standby mode.
SPEAr CPU freq: Adding support for CPU Freq framework
ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms
Pratyush Anand (1):
ST SPEAr: Added PCIE host controller base driver support.
Rajeev Kumar (4):
rtc: Adding support for spear rtc
ST SPEAr: Adding machine support for rtc-spear
ST SPEAr: adding support for synopsis i2c designware
ST SPEAr: Adding machine support for keyboard
Ryan Mallon (5):
SPEAr3xx: Make local structures static
SPEAR3xx: Rename register/irq defines to remove naming conflicts
SPEAr3xx: Rework pmx_dev code to remove conflicts
SPEAr3xx: Rework KConfig to allow all boards to be compiled in
SPEAr3xx: Replace defconfigs with single unified defconfig
Shiraz Hashim (13):
sp810 Fix: Switch to slow mode before sysctl_soft_reset
ST SPEAr: Formalized timer support
ST SPEAr13XX: Adding machine specific header files
ST SPEAr13XX: Adding machine specific src files
ST SPEAr: Adding support for SPEAr13xx SoC in spear generic plat/
ST SPEAr13XX: Added compilation support in arch/arm/
ST SPEAr13xx: Adding default config file
ST SPEAr: Adding Debugfs support on clock framework
ST SPEAr: Replacing SIZE macro's with actual required size
SPEAr: defines base addresses as ulong.
ST SPEAr13xx: add L2 cache support
ST SPEAr13xx: Modified static mappings
ST SPEAr: Adding information in Documentation/ and MAINTAINERS
Vipin Kumar (5):
ST SPEAr: Adding machine support for nand
ST SPEAr : EMI (Extrenal Memory Interface) controller driver
SPEAr : Pad multiplexing handling modified
SPEAr13xx : Fixed part devices in SPEAr13xx addded to the generic
implementation
SPEAr : Updating pad multiplexing support
Vipul-kumar Samar (1):
ST SPEAr: Adding support for CLCD on SPEAr3xx/6xx
Viresh Kumar (27):
spear/vmalloc.h: Appending UL to VMALLOC_END
ST SPEAr: Padmux code Updated
ST SPEAr: Making clock functions more generic
ST SPEAr: Updating Clock Support
ST SPEAr: Correcting SOC Config base address for spear320
ST SPEAr: Adding PLGPIO driver for spear platform
ST SPEAr: Added ARM PL061 GPIO Support on SPEAr13xx and modified
resource size
ST SPEAr: Adding support for ST's PWM IP
ST SPEAr: Adding Watchdog support
ST SPEAr: Adding support for SSP PL022
ST SPEAr: Adding support for SDHCI (SDIO)
ST SPEAr: Changing resource size of amba devices to SZ_4K
ST SPEAr: Adding miscellaneous devices
SPEAr320: Adding support for CAN
ST SPEAr: Adding support for DDR in clock framework
ST SPEAr: replace readl, writel with readl_relaxed, writel_relaxed in
uncompress.h
SPEAr1310: Adding Static Mapping for RAS Area
SPEAr: Adding and Updating Clock definitions
ST SPEAr3xx: Passing pmx devices address from machine *.c files
ST SPEAr Clock Framework: Updating for single image solution
ST SPEAr: Appending spear3** with global structures
ST SPEAr3xx: Updating plgpio and emi source to make it compliant with
single image strategy
SPEAr6xx: Rework Kconfig for single image solution
ST SPEAR6xx: renaming spear600_defconfig as spear6xx_defconfig
ST SPEAr13xx: Pass default padmux settings as parameter to
spear13**_init routine
ST SPEAr: Adding devices & clocks
ST SPEAr: Updating defconfigs
Documentation/arm/SPEAr/overview.txt | 34 +-
MAINTAINERS | 6 +
arch/arm/Kconfig | 6 +-
arch/arm/Makefile | 2 +
arch/arm/configs/spear13xx_defconfig | 127 ++
arch/arm/configs/spear300_defconfig | 51 -
arch/arm/configs/spear310_defconfig | 52 -
arch/arm/configs/spear320_defconfig | 52 -
arch/arm/configs/spear3xx_defconfig | 119 ++
arch/arm/configs/spear600_defconfig | 49 -
arch/arm/configs/spear6xx_defconfig | 109 ++
arch/arm/include/asm/hardware/sp810.h | 3 +
arch/arm/mach-spear13xx/Kconfig | 32 +
arch/arm/mach-spear13xx/Makefile | 23 +
arch/arm/mach-spear13xx/Makefile.boot | 3 +
arch/arm/mach-spear13xx/clock.c | 1204 ++++++++++++++++++++
arch/arm/mach-spear13xx/headsmp.S | 96 ++
arch/arm/mach-spear13xx/hotplug.c | 121 ++
arch/arm/mach-spear13xx/include/mach/clkdev.h | 19 +
arch/arm/mach-spear13xx/include/mach/debug-macro.S | 14 +
arch/arm/mach-spear13xx/include/mach/entry-macro.S | 22 +
arch/arm/mach-spear13xx/include/mach/generic.h | 275 +++++
arch/arm/mach-spear13xx/include/mach/gpio.h | 37 +
arch/arm/mach-spear13xx/include/mach/hardware.h | 37 +
arch/arm/mach-spear13xx/include/mach/io.h | 19 +
arch/arm/mach-spear13xx/include/mach/irqs.h | 153 +++
arch/arm/mach-spear13xx/include/mach/memory.h | 19 +
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 386 +++++++
arch/arm/mach-spear13xx/include/mach/pcie.h | 170 +++
arch/arm/mach-spear13xx/include/mach/smp.h | 25 +
arch/arm/mach-spear13xx/include/mach/spear.h | 95 ++
arch/arm/mach-spear13xx/include/mach/spear1300.h | 21 +
arch/arm/mach-spear13xx/include/mach/spear1310.h | 64 +
arch/arm/mach-spear13xx/include/mach/suspend.h | 47 +
arch/arm/mach-spear13xx/include/mach/system.h | 35 +
arch/arm/mach-spear13xx/include/mach/timex.h | 19 +
arch/arm/mach-spear13xx/include/mach/uncompress.h | 19 +
arch/arm/mach-spear13xx/include/mach/vmalloc.h | 18 +
arch/arm/mach-spear13xx/localtimer.c | 25 +
arch/arm/mach-spear13xx/pcie.c | 861 ++++++++++++++
arch/arm/mach-spear13xx/platsmp.c | 165 +++
arch/arm/mach-spear13xx/pm.c | 107 ++
arch/arm/mach-spear13xx/sleep.S | 435 +++++++
arch/arm/mach-spear13xx/spear1300.c | 38 +
arch/arm/mach-spear13xx/spear1300_evb.c | 146 +++
arch/arm/mach-spear13xx/spear1310.c | 516 +++++++++
arch/arm/mach-spear13xx/spear1310_evb.c | 166 +++
arch/arm/mach-spear13xx/spear13xx.c | 1057 +++++++++++++++++
arch/arm/mach-spear3xx/Kconfig | 30 +-
arch/arm/mach-spear3xx/Kconfig300 | 17 -
arch/arm/mach-spear3xx/Kconfig310 | 17 -
arch/arm/mach-spear3xx/Kconfig320 | 17 -
arch/arm/mach-spear3xx/Makefile | 4 +
arch/arm/mach-spear3xx/clock.c | 576 ++++++++--
arch/arm/mach-spear3xx/emi.c | 117 ++
arch/arm/mach-spear3xx/include/mach/emi.h | 65 ++
arch/arm/mach-spear3xx/include/mach/generic.h | 280 +++--
arch/arm/mach-spear3xx/include/mach/gpio.h | 143 +++
arch/arm/mach-spear3xx/include/mach/irqs.h | 206 ++--
arch/arm/mach-spear3xx/include/mach/misc_regs.h | 12 +-
arch/arm/mach-spear3xx/include/mach/spear.h | 134 +--
arch/arm/mach-spear3xx/include/mach/spear300.h | 86 +-
arch/arm/mach-spear3xx/include/mach/spear310.h | 85 +-
arch/arm/mach-spear3xx/include/mach/spear320.h | 121 +--
arch/arm/mach-spear3xx/include/mach/suspend.h | 44 +
arch/arm/mach-spear3xx/spear300.c | 640 ++++++++---
arch/arm/mach-spear3xx/spear300_evb.c | 109 ++-
arch/arm/mach-spear3xx/spear310.c | 423 ++++++--
arch/arm/mach-spear3xx/spear310_evb.c | 135 ++-
arch/arm/mach-spear3xx/spear320.c | 844 +++++++++++----
arch/arm/mach-spear3xx/spear320_evb.c | 120 ++-
arch/arm/mach-spear3xx/spear3xx.c | 741 ++++++++++---
arch/arm/mach-spear6xx/Kconfig | 15 +-
arch/arm/mach-spear6xx/Kconfig600 | 17 -
arch/arm/mach-spear6xx/clock.c | 438 ++++++--
arch/arm/mach-spear6xx/include/mach/generic.h | 19 +-
arch/arm/mach-spear6xx/include/mach/gpio.h | 27 +
arch/arm/mach-spear6xx/include/mach/misc_regs.h | 12 +-
arch/arm/mach-spear6xx/include/mach/spear.h | 174 +---
arch/arm/mach-spear6xx/include/mach/suspend.h | 44 +
arch/arm/mach-spear6xx/spear600_evb.c | 35 +-
arch/arm/mach-spear6xx/spear6xx.c | 344 ++++++-
arch/arm/mm/Kconfig | 2 +-
arch/arm/plat-spear/Kconfig | 17 +
arch/arm/plat-spear/Makefile | 21 +-
arch/arm/plat-spear/clcd.c | 114 ++
arch/arm/plat-spear/clock.c | 905 +++++++++++++---
arch/arm/plat-spear/cpufreq.c | 159 +++
arch/arm/plat-spear/i2c_eval_board.c | 29 +
arch/arm/plat-spear/include/plat/clock.h | 187 +++-
arch/arm/plat-spear/include/plat/fsmc.h | 36 +
arch/arm/plat-spear/include/plat/gpio.h | 35 +
arch/arm/plat-spear/include/plat/padmux.h | 34 +-
arch/arm/plat-spear/include/plat/spi.h | 74 ++
arch/arm/plat-spear/include/plat/uncompress.h | 4 +-
arch/arm/plat-spear/include/plat/vmalloc.h | 2 +-
arch/arm/plat-spear/padmux.c | 54 +-
arch/arm/plat-spear/plgpio.c | 474 ++++++++
arch/arm/plat-spear/pll_clk.S | 187 +++
arch/arm/plat-spear/pm.c | 104 ++
arch/arm/plat-spear/pwm.c | 484 ++++++++
arch/arm/plat-spear/sleep.S | 288 +++++
arch/arm/plat-spear/time.c | 21 +-
drivers/rtc/Kconfig | 8 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-spear.c | 534 +++++++++
drivers/video/Kconfig | 14 +-
107 files changed, 14992 insertions(+), 1986 deletions(-)
create mode 100644 arch/arm/configs/spear13xx_defconfig
delete mode 100644 arch/arm/configs/spear300_defconfig
delete mode 100644 arch/arm/configs/spear310_defconfig
delete mode 100644 arch/arm/configs/spear320_defconfig
create mode 100644 arch/arm/configs/spear3xx_defconfig
delete mode 100644 arch/arm/configs/spear600_defconfig
create mode 100644 arch/arm/configs/spear6xx_defconfig
create mode 100644 arch/arm/mach-spear13xx/Kconfig
create mode 100644 arch/arm/mach-spear13xx/Makefile
create mode 100644 arch/arm/mach-spear13xx/Makefile.boot
create mode 100644 arch/arm/mach-spear13xx/clock.c
create mode 100644 arch/arm/mach-spear13xx/headsmp.S
create mode 100644 arch/arm/mach-spear13xx/hotplug.c
create mode 100644 arch/arm/mach-spear13xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/io.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/memory.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/pcie.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/smp.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1300.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1310.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/suspend.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-spear13xx/localtimer.c
create mode 100644 arch/arm/mach-spear13xx/pcie.c
create mode 100644 arch/arm/mach-spear13xx/platsmp.c
create mode 100644 arch/arm/mach-spear13xx/pm.c
create mode 100644 arch/arm/mach-spear13xx/sleep.S
create mode 100644 arch/arm/mach-spear13xx/spear1300.c
create mode 100644 arch/arm/mach-spear13xx/spear1300_evb.c
create mode 100644 arch/arm/mach-spear13xx/spear1310.c
create mode 100644 arch/arm/mach-spear13xx/spear1310_evb.c
create mode 100644 arch/arm/mach-spear13xx/spear13xx.c
delete mode 100644 arch/arm/mach-spear3xx/Kconfig300
delete mode 100644 arch/arm/mach-spear3xx/Kconfig310
delete mode 100644 arch/arm/mach-spear3xx/Kconfig320
create mode 100644 arch/arm/mach-spear3xx/emi.c
create mode 100644 arch/arm/mach-spear3xx/include/mach/emi.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/suspend.h
delete mode 100644 arch/arm/mach-spear6xx/Kconfig600
create mode 100644 arch/arm/mach-spear6xx/include/mach/suspend.h
create mode 100644 arch/arm/plat-spear/clcd.c
create mode 100644 arch/arm/plat-spear/cpufreq.c
create mode 100644 arch/arm/plat-spear/i2c_eval_board.c
create mode 100644 arch/arm/plat-spear/include/plat/fsmc.h
create mode 100644 arch/arm/plat-spear/include/plat/spi.h
create mode 100644 arch/arm/plat-spear/plgpio.c
create mode 100644 arch/arm/plat-spear/pll_clk.S
create mode 100644 arch/arm/plat-spear/pm.c
create mode 100644 arch/arm/plat-spear/pwm.c
create mode 100644 arch/arm/plat-spear/sleep.S
create mode 100644 drivers/rtc/rtc-spear.c
--
1.7.2.2
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 01/62] spear/vmalloc.h: Appending UL to VMALLOC_END
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 02/62] sp810 Fix: Switch to slow mode before sysctl_soft_reset Viresh Kumar
` (60 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch fixes following warning:
mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but
argument 12 has type 'unsigned int'
by appending UL to VMALLOC_END's Number.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/plat-spear/include/plat/vmalloc.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
index 09e9372..8c8b24d 100644
--- a/arch/arm/plat-spear/include/plat/vmalloc.h
+++ b/arch/arm/plat-spear/include/plat/vmalloc.h
@@ -14,6 +14,6 @@
#ifndef __PLAT_VMALLOC_H
#define __PLAT_VMALLOC_H
-#define VMALLOC_END 0xF0000000
+#define VMALLOC_END 0xF0000000UL
#endif /* __PLAT_VMALLOC_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 02/62] sp810 Fix: Switch to slow mode before sysctl_soft_reset
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 01/62] spear/vmalloc.h: Appending UL to VMALLOC_END Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 03/62] ST SPEAr: Padmux code Updated Viresh Kumar
` (59 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Before resetting system from system controller, switching to slow
mode is required.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/include/asm/hardware/sp810.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
index a101f10..6e3bafd 100644
--- a/arch/arm/include/asm/hardware/sp810.h
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -52,6 +52,9 @@
static inline void sysctl_soft_reset(void __iomem *base)
{
+ /* switch to slow mode */
+ writel(0x2, base + SCCTRL);
+
/* writing any value to SCSYSSTAT reg will reset system */
writel(0, base + SCSYSSTAT);
}
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 03/62] ST SPEAr: Padmux code Updated
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 01/62] spear/vmalloc.h: Appending UL to VMALLOC_END Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 02/62] sp810 Fix: Switch to slow mode before sysctl_soft_reset Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 04/62] ST SPEAr: Making clock functions more generic Viresh Kumar
` (58 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
- compiling padmux only for spear3xx
- padmux initialization code rearranged in evaluation board and machine files.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 7 -------
arch/arm/mach-spear3xx/spear300.c | 14 ++++++++++----
arch/arm/mach-spear3xx/spear300_evb.c | 9 ++++-----
arch/arm/mach-spear3xx/spear310.c | 11 ++++++-----
arch/arm/mach-spear3xx/spear310_evb.c | 9 ++++-----
arch/arm/mach-spear3xx/spear320.c | 11 ++++++-----
arch/arm/mach-spear3xx/spear320_evb.c | 9 ++++-----
arch/arm/mach-spear3xx/spear3xx.c | 21 ---------------------
arch/arm/plat-spear/Makefile | 4 ++--
9 files changed, 36 insertions(+), 59 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index af7e02c..c16d2f8 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -40,7 +40,6 @@ void __init clk_init(void);
void __init spear3xx_map_io(void);
void __init spear3xx_init_irq(void);
void __init spear3xx_init(void);
-void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size);
/* pad mux declarations */
#define PMX_FIRDA_MASK (1 << 14)
@@ -133,8 +132,6 @@ extern struct pmx_dev pmx_telecom_sdio_4bit;
extern struct pmx_dev pmx_telecom_sdio_8bit;
extern struct pmx_dev pmx_gpio1;
-void spear300_pmx_init(void);
-
/* Add spear300 machine function declarations here */
void __init spear300_init(void);
@@ -154,8 +151,6 @@ extern struct pmx_dev pmx_fsmc;
extern struct pmx_dev pmx_rs485_0_1;
extern struct pmx_dev pmx_tdm0;
-void spear310_pmx_init(void);
-
/* Add spear310 machine function declarations here */
void __init spear310_init(void);
@@ -195,8 +190,6 @@ extern struct pmx_dev pmx_smii0;
extern struct pmx_dev pmx_smii1;
extern struct pmx_dev pmx_i2c1;
-void spear320_pmx_init(void);
-
/* Add spear320 machine function declarations here */
void __init spear320_init(void);
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 5aa2d54..7e01677 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -459,10 +459,16 @@ void __init spear300_init(void)
if (ret)
printk(KERN_ERR "Error registering Shared IRQ\n");
}
-}
-void spear300_pmx_init(void)
-{
- spear_pmx_init(&pmx_driver, SPEAR300_SOC_CONFIG_BASE,
+ /* pmx initialization */
+ pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE,
SPEAR300_SOC_CONFIG_SIZE);
+ if (pmx_driver.base) {
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ printk(KERN_ERR "padmux: registeration failed. err no"
+ ": %d\n", ret);
+ /* Free Mapping, device selection already done */
+ iounmap(pmx_driver.base);
+ }
}
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index bb21db1..2c90663 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -51,14 +51,13 @@ static void __init spear300_evb_init(void)
{
unsigned int i;
- /* call spear300 machine init function */
- spear300_init();
-
- /* padmux initialization */
+ /* padmux initialization, must be done before spear300_init */
pmx_driver.mode = &photo_frame_mode;
pmx_driver.devs = pmx_devs;
pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
- spear300_pmx_init();
+
+ /* call spear300 machine init function */
+ spear300_init();
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 53b41b5..f38eb21 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -293,10 +293,11 @@ void __init spear310_init(void)
if (ret)
printk(KERN_ERR "Error registering Shared IRQ 4\n");
}
-}
-void spear310_pmx_init(void)
-{
- spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE,
- SPEAR310_SOC_CONFIG_SIZE);
+ /* pmx initialization */
+ pmx_driver.base = base;
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
+ ret);
}
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 7facf66..4e55e55 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -58,14 +58,13 @@ static void __init spear310_evb_init(void)
{
unsigned int i;
- /* call spear310 machine init function */
- spear310_init();
-
- /* padmux initialization */
+ /* padmux initialization, must be done before spear310_init */
pmx_driver.mode = NULL;
pmx_driver.devs = pmx_devs;
pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
- spear310_pmx_init();
+
+ /* call spear310 machine init function */
+ spear310_init();
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 88b4652..456bb33 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -540,10 +540,11 @@ void __init spear320_init(void)
if (ret)
printk(KERN_ERR "Error registering Shared IRQ 4\n");
}
-}
-void spear320_pmx_init(void)
-{
- spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE,
- SPEAR320_SOC_CONFIG_SIZE);
+ /* pmx initialization */
+ pmx_driver.base = base;
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
+ ret);
}
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 62ac685..7083a06 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -55,14 +55,13 @@ static void __init spear320_evb_init(void)
{
unsigned int i;
- /* call spear320 machine init function */
- spear320_init();
-
- /* padmux initialization */
+ /* padmux initialization, must be done before spear320_init */
pmx_driver.mode = &auto_net_mii_mode;
pmx_driver.devs = pmx_devs;
pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
- spear320_pmx_init();
+
+ /* call spear320 machine init function */
+ spear320_init();
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 52f553c..faf8709 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -525,24 +525,3 @@ struct pmx_dev pmx_plgpio_45_46_49_50 = {
};
#endif
-
-/* spear padmux initialization function */
-void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size)
-{
- int ret = 0;
-
- /* pad mux initialization */
- pmx_driver->base = ioremap(base, size);
- if (!pmx_driver->base) {
- ret = -ENOMEM;
- goto pmx_fail;
- }
-
- ret = pmx_register(pmx_driver);
- iounmap(pmx_driver->base);
-
-pmx_fail:
- if (ret)
- printk(KERN_ERR "padmux: registration failed. err no: %d\n",
- ret);
-}
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index eb89540..b4f340b 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
#
# Common support
-obj-y := clock.o padmux.o time.o
+obj-y := clock.o time.o
-obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
+obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 04/62] ST SPEAr: Making clock functions more generic
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (2 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 03/62] ST SPEAr: Padmux code Updated Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 15:56 ` Russell King - ARM Linux
2011-01-18 7:11 ` [PATCH V4 05/62] ST SPEAr: Formalized timer support Viresh Kumar
` (57 subsequent siblings)
61 siblings, 1 reply; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Modifications include:
- Adding dummy clk_set_rate function. Required for compilation of few drivers
- Making function present in plat-spear/clock.c more generic over all platforms
- Added div_factor filed in struct clk for clks with .recalc = follow_parent
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear3xx/clock.c | 66 ++++++++++++++++++++++++++----
arch/arm/mach-spear6xx/clock.c | 67 ++++++++++++++++++++++++++----
arch/arm/plat-spear/clock.c | 59 ++++++++++++++++++--------
arch/arm/plat-spear/include/plat/clock.h | 64 ++++++++++++++++++++++++----
4 files changed, 212 insertions(+), 44 deletions(-)
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 18febf9..7ea8749 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -39,10 +39,25 @@ static struct clk rtc_clk = {
};
/* clock derived from 24 MHz osc clk */
+/* pll masks structure */
+static struct pll_clk_masks pll1_masks = {
+ .mode_mask = PLL_MODE_MASK,
+ .mode_shift = PLL_MODE_SHIFT,
+ .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
+ .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
+ .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
+ .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
+ .div_p_mask = PLL_DIV_P_MASK,
+ .div_p_shift = PLL_DIV_P_SHIFT,
+ .div_n_mask = PLL_DIV_N_MASK,
+ .div_n_shift = PLL_DIV_N_SHIFT,
+};
+
/* pll1 configuration structure */
static struct pll_clk_config pll1_config = {
.mode_reg = PLL1_CTR,
.cfg_reg = PLL1_FRQ,
+ .masks = &pll1_masks,
};
/* PLL1 clock */
@@ -50,7 +65,7 @@ static struct clk pll1_clk = {
.pclk = &osc_24m_clk,
.en_reg = PLL1_CTR,
.en_reg_bit = PLL_ENABLE,
- .recalc = &pll1_clk_recalc,
+ .recalc = &pll_clk_recalc,
.private_data = &pll1_config,
};
@@ -76,11 +91,16 @@ static struct clk cpu_clk = {
.recalc = &follow_parent,
};
+/* ahb masks structure */
+static struct bus_clk_masks ahb_masks = {
+ .mask = PLL_HCLK_RATIO_MASK,
+ .shift = PLL_HCLK_RATIO_SHIFT,
+};
+
/* ahb configuration structure */
static struct bus_clk_config ahb_config = {
.reg = CORE_CLK_CFG,
- .mask = PLL_HCLK_RATIO_MASK,
- .shift = PLL_HCLK_RATIO_SHIFT,
+ .masks = &ahb_masks,
};
/* ahb clock */
@@ -91,9 +111,22 @@ static struct clk ahb_clk = {
.private_data = &ahb_config,
};
+/* auxiliary synthesizers masks */
+static struct aux_clk_masks aux_masks = {
+ .eq_sel_mask = AUX_EQ_SEL_MASK,
+ .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+ .eq1_mask = AUX_EQ1_SEL,
+ .eq2_mask = AUX_EQ2_SEL,
+ .xscale_sel_mask = AUX_XSCALE_MASK,
+ .xscale_sel_shift = AUX_XSCALE_SHIFT,
+ .yscale_sel_mask = AUX_YSCALE_MASK,
+ .yscale_sel_shift = AUX_YSCALE_SHIFT,
+};
+
/* uart configurations */
static struct aux_clk_config uart_config = {
.synth_reg = UART_CLK_SYNT,
+ .masks = &aux_masks,
};
/* uart parents */
@@ -130,6 +163,7 @@ static struct clk uart_clk = {
/* firda configurations */
static struct aux_clk_config firda_config = {
.synth_reg = FIRDA_CLK_SYNT,
+ .masks = &aux_masks,
};
/* firda parents */
@@ -184,9 +218,18 @@ static struct pclk_sel gpt_pclk_sel = {
.pclk_sel_mask = GPT_CLK_MASK,
};
+/* gpt synthesizer masks */
+static struct gpt_clk_masks gpt_masks = {
+ .mscale_sel_mask = GPT_MSCALE_MASK,
+ .mscale_sel_shift = GPT_MSCALE_SHIFT,
+ .nscale_sel_mask = GPT_NSCALE_MASK,
+ .nscale_sel_shift = GPT_NSCALE_SHIFT,
+};
+
/* gpt0 configurations */
-static struct aux_clk_config gpt0_config = {
+static struct gpt_clk_config gpt0_config = {
.synth_reg = PRSC1_CLK_CFG,
+ .masks = &gpt_masks,
};
/* gpt0 timer clock */
@@ -199,8 +242,9 @@ static struct clk gpt0_clk = {
};
/* gpt1 configurations */
-static struct aux_clk_config gpt1_config = {
+static struct gpt_clk_config gpt1_config = {
.synth_reg = PRSC2_CLK_CFG,
+ .masks = &gpt_masks,
};
/* gpt1 timer clock */
@@ -214,8 +258,9 @@ static struct clk gpt1_clk = {
};
/* gpt2 configurations */
-static struct aux_clk_config gpt2_config = {
+static struct gpt_clk_config gpt2_config = {
.synth_reg = PRSC3_CLK_CFG,
+ .masks = &gpt_masks,
};
/* gpt2 timer clock */
@@ -253,11 +298,16 @@ static struct clk clcd_clk = {
};
/* clock derived from ahb clk */
+/* apb masks structure */
+static struct bus_clk_masks apb_masks = {
+ .mask = HCLK_PCLK_RATIO_MASK,
+ .shift = HCLK_PCLK_RATIO_SHIFT,
+};
+
/* apb configuration structure */
static struct bus_clk_config apb_config = {
.reg = CORE_CLK_CFG,
- .mask = HCLK_PCLK_RATIO_MASK,
- .shift = HCLK_PCLK_RATIO_SHIFT,
+ .masks = &apb_masks,
};
/* apb clock */
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 36ff056..ef88922 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -39,10 +39,25 @@ static struct clk rtc_clk = {
};
/* clock derived from 30 MHz osc clk */
+/* pll masks structure */
+static struct pll_clk_masks pll1_masks = {
+ .mode_mask = PLL_MODE_MASK,
+ .mode_shift = PLL_MODE_SHIFT,
+ .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
+ .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
+ .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
+ .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
+ .div_p_mask = PLL_DIV_P_MASK,
+ .div_p_shift = PLL_DIV_P_SHIFT,
+ .div_n_mask = PLL_DIV_N_MASK,
+ .div_n_shift = PLL_DIV_N_SHIFT,
+};
+
/* pll1 configuration structure */
static struct pll_clk_config pll1_config = {
.mode_reg = PLL1_CTR,
.cfg_reg = PLL1_FRQ,
+ .masks = &pll1_masks,
};
/* PLL1 clock */
@@ -50,7 +65,7 @@ static struct clk pll1_clk = {
.pclk = &osc_30m_clk,
.en_reg = PLL1_CTR,
.en_reg_bit = PLL_ENABLE,
- .recalc = &pll1_clk_recalc,
+ .recalc = &pll_clk_recalc,
.private_data = &pll1_config,
};
@@ -76,11 +91,16 @@ static struct clk cpu_clk = {
.recalc = &follow_parent,
};
+/* ahb masks structure */
+static struct bus_clk_masks ahb_masks = {
+ .mask = PLL_HCLK_RATIO_MASK,
+ .shift = PLL_HCLK_RATIO_SHIFT,
+};
+
/* ahb configuration structure */
static struct bus_clk_config ahb_config = {
.reg = CORE_CLK_CFG,
- .mask = PLL_HCLK_RATIO_MASK,
- .shift = PLL_HCLK_RATIO_SHIFT,
+ .masks = &ahb_masks,
};
/* ahb clock */
@@ -112,9 +132,22 @@ static struct pclk_sel uart_pclk_sel = {
.pclk_sel_mask = UART_CLK_MASK,
};
+/* auxiliary synthesizers masks */
+static struct aux_clk_masks aux_masks = {
+ .eq_sel_mask = AUX_EQ_SEL_MASK,
+ .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+ .eq1_mask = AUX_EQ1_SEL,
+ .eq2_mask = AUX_EQ2_SEL,
+ .xscale_sel_mask = AUX_XSCALE_MASK,
+ .xscale_sel_shift = AUX_XSCALE_SHIFT,
+ .yscale_sel_mask = AUX_YSCALE_MASK,
+ .yscale_sel_shift = AUX_YSCALE_SHIFT,
+};
+
/* uart configurations */
static struct aux_clk_config uart_config = {
.synth_reg = UART_CLK_SYNT,
+ .masks = &aux_masks,
};
/* uart0 clock */
@@ -140,6 +173,7 @@ static struct clk uart1_clk = {
/* firda configurations */
static struct aux_clk_config firda_config = {
.synth_reg = FIRDA_CLK_SYNT,
+ .masks = &aux_masks,
};
/* firda parents */
@@ -176,6 +210,7 @@ static struct clk firda_clk = {
/* clcd configurations */
static struct aux_clk_config clcd_config = {
.synth_reg = CLCD_CLK_SYNT,
+ .masks = &aux_masks,
};
/* clcd parents */
@@ -230,9 +265,18 @@ static struct pclk_sel gpt_pclk_sel = {
.pclk_sel_mask = GPT_CLK_MASK,
};
+/* gpt synthesizer masks */
+static struct gpt_clk_masks gpt_masks = {
+ .mscale_sel_mask = GPT_MSCALE_MASK,
+ .mscale_sel_shift = GPT_MSCALE_SHIFT,
+ .nscale_sel_mask = GPT_NSCALE_MASK,
+ .nscale_sel_shift = GPT_NSCALE_SHIFT,
+};
+
/* gpt0_1 configurations */
-static struct aux_clk_config gpt0_1_config = {
+static struct gpt_clk_config gpt0_1_config = {
.synth_reg = PRSC1_CLK_CFG,
+ .masks = &gpt_masks,
};
/* gpt0 ARM1 subsystem timer clock */
@@ -254,8 +298,9 @@ static struct clk gpt1_clk = {
};
/* gpt2 configurations */
-static struct aux_clk_config gpt2_config = {
+static struct gpt_clk_config gpt2_config = {
.synth_reg = PRSC2_CLK_CFG,
+ .masks = &gpt_masks,
};
/* gpt2 timer clock */
@@ -269,8 +314,9 @@ static struct clk gpt2_clk = {
};
/* gpt3 configurations */
-static struct aux_clk_config gpt3_config = {
+static struct gpt_clk_config gpt3_config = {
.synth_reg = PRSC3_CLK_CFG,
+ .masks = &gpt_masks,
};
/* gpt3 timer clock */
@@ -309,11 +355,16 @@ static struct clk usbd_clk = {
};
/* clock derived from ahb clk */
+/* apb masks structure */
+static struct bus_clk_masks apb_masks = {
+ .mask = HCLK_PCLK_RATIO_MASK,
+ .shift = HCLK_PCLK_RATIO_SHIFT,
+};
+
/* apb configuration structure */
static struct bus_clk_config apb_config = {
.reg = CORE_CLK_CFG,
- .mask = HCLK_PCLK_RATIO_MASK,
- .shift = HCLK_PCLK_RATIO_SHIFT,
+ .masks = &apb_masks,
};
/* apb clock */
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index ee4f90e..f1cf832 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -17,7 +17,6 @@
#include <linux/list.h>
#include <linux/module.h>
#include <linux/spinlock.h>
-#include <mach/misc_regs.h>
#include <plat/clock.h>
static DEFINE_SPINLOCK(clocks_lock);
@@ -187,6 +186,20 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
}
EXPORT_SYMBOL(clk_set_parent);
+/**
+ * clk_set_rate - set the clock rate for a clock source
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ /* TODO */
+ return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
/* registers clock in platform clock framework */
void clk_register(struct clk_lookup *cl)
{
@@ -212,6 +225,7 @@ void clk_register(struct clk_lookup *cl)
list_add(&clk->sibling, &clk->pclk->children);
} else {
/* add clocks with > 1 parent to 1st parent's children list */
+ clk->pclk = clk->pclk_sel->pclk_info[0].pclk;
list_add(&clk->sibling,
&clk->pclk_sel->pclk_info[0].pclk->children);
}
@@ -283,29 +297,31 @@ static void change_parent(struct clk *cclk, struct clk *pclk)
* In Dithered mode
* rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
*/
-void pll1_clk_recalc(struct clk *clk)
+void pll_clk_recalc(struct clk *clk)
{
struct pll_clk_config *config = clk->private_data;
unsigned int num = 2, den = 0, val, mode = 0;
unsigned long flags;
spin_lock_irqsave(&clocks_lock, flags);
- mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) &
- PLL_MODE_MASK;
+ mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
+ config->masks->mode_mask;
val = readl(config->cfg_reg);
/* calculate denominator */
- den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
+ den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
den = 1 << den;
- den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
+ den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
/* calculate numerator & denominator */
if (!mode) {
/* Normal mode */
- num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
+ num *= (val >> config->masks->norm_fdbk_m_shift) &
+ config->masks->norm_fdbk_m_mask;
} else {
/* Dithered mode */
- num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
+ num *= (val >> config->masks->dith_fdbk_m_shift) &
+ config->masks->dith_fdbk_m_mask;
den *= 256;
}
@@ -321,7 +337,8 @@ void bus_clk_recalc(struct clk *clk)
unsigned long flags;
spin_lock_irqsave(&clocks_lock, flags);
- div = ((readl(config->reg) >> config->shift) & config->mask) + 1;
+ div = ((readl(config->reg) >> config->masks->shift) &
+ config->masks->mask) + 1;
clk->rate = (unsigned long)clk->pclk->rate / div;
spin_unlock_irqrestore(&clocks_lock, flags);
}
@@ -359,15 +376,18 @@ void aux_clk_recalc(struct clk *clk)
if (pclk_info->scalable) {
val = readl(config->synth_reg);
- eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK;
- if (eqn == AUX_EQ1_SEL)
+ eqn = (val >> config->masks->eq_sel_shift) &
+ config->masks->eq_sel_mask;
+ if (eqn == config->masks->eq1_mask)
den *= 2;
/* calculate numerator */
- num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK;
+ num = (val >> config->masks->xscale_sel_shift) &
+ config->masks->xscale_sel_mask;
/* calculate denominator */
- den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK;
+ den *= (val >> config->masks->yscale_sel_shift) &
+ config->masks->yscale_sel_mask;
val = (((clk->pclk->rate/10000) * num) / den) * 10000;
} else
val = clk->pclk->rate;
@@ -383,7 +403,7 @@ void aux_clk_recalc(struct clk *clk)
*/
void gpt_clk_recalc(struct clk *clk)
{
- struct aux_clk_config *config = clk->private_data;
+ struct gpt_clk_config *config = clk->private_data;
struct pclk_info *pclk_info = NULL;
unsigned int div = 1, val;
unsigned long flags;
@@ -402,8 +422,10 @@ void gpt_clk_recalc(struct clk *clk)
spin_lock_irqsave(&clocks_lock, flags);
if (pclk_info->scalable) {
val = readl(config->synth_reg);
- div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK;
- div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
+ div += (val >> config->masks->mscale_sel_shift) &
+ config->masks->mscale_sel_mask;
+ div *= 1 << (((val >> config->masks->nscale_sel_shift) &
+ config->masks->nscale_sel_mask) + 1);
}
clk->rate = (unsigned long)clk->pclk->rate / div;
@@ -411,15 +433,16 @@ void gpt_clk_recalc(struct clk *clk)
}
/*
- * Used for clocks that always have same value as the parent clock divided by a
+ * Used for clocks that always have value as the parent clock divided by a
* fixed divisor
*/
void follow_parent(struct clk *clk)
{
unsigned long flags;
+ unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
spin_lock_irqsave(&clocks_lock, flags);
- clk->rate = clk->pclk->rate;
+ clk->rate = clk->pclk->rate/div_factor;
spin_unlock_irqrestore(&clocks_lock, flags);
}
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index 2572260..5f66333 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -67,6 +67,7 @@ struct pclk_sel {
* @en_reg_bit: clk enable/disable bit
* @ops: clk enable/disable ops - generic_clkops selected if NULL
* @recalc: pointer to clock rate recalculate function
+ * @div_factor: division factor to parent clock. Only for recalc = follow_parent
* @pclk: current parent clk
* @pclk_sel: pointer to parent selection structure
* @pclk_sel_shift: register shift for selecting parent of this clock
@@ -82,6 +83,7 @@ struct clk {
u8 en_reg_bit;
const struct clkops *ops;
void (*recalc) (struct clk *);
+ unsigned int div_factor;
struct clk *pclk;
struct pclk_sel *pclk_sel;
@@ -93,23 +95,65 @@ struct clk {
};
/* pll configuration structure */
+struct pll_clk_masks {
+ u32 mode_mask;
+ u32 mode_shift;
+
+ u32 norm_fdbk_m_mask;
+ u32 norm_fdbk_m_shift;
+ u32 dith_fdbk_m_mask;
+ u32 dith_fdbk_m_shift;
+ u32 div_p_mask;
+ u32 div_p_shift;
+ u32 div_n_mask;
+ u32 div_n_shift;
+};
+
struct pll_clk_config {
- unsigned int *mode_reg;
- unsigned int *cfg_reg;
+ u32 *mode_reg;
+ u32 *cfg_reg;
+ struct pll_clk_masks *masks;
};
/* ahb and apb bus configuration structure */
+struct bus_clk_masks {
+ u32 mask;
+ u32 shift;
+};
+
struct bus_clk_config {
- unsigned int *reg;
- unsigned int mask;
- unsigned int shift;
+ u32 *reg;
+ struct bus_clk_masks *masks;
+};
+
+/* Aux clk configuration structure: applicable to UART and FIRDA */
+struct aux_clk_masks {
+ u32 eq_sel_mask;
+ u32 eq_sel_shift;
+ u32 eq1_mask;
+ u32 eq2_mask;
+ u32 xscale_sel_mask;
+ u32 xscale_sel_shift;
+ u32 yscale_sel_mask;
+ u32 yscale_sel_shift;
};
-/*
- * Aux clk configuration structure: applicable to GPT, UART and FIRDA
- */
struct aux_clk_config {
- unsigned int *synth_reg;
+ u32 *synth_reg;
+ struct aux_clk_masks *masks;
+};
+
+/* GPT clk configuration structure */
+struct gpt_clk_masks {
+ u32 mscale_sel_mask;
+ u32 mscale_sel_shift;
+ u32 nscale_sel_mask;
+ u32 nscale_sel_shift;
+};
+
+struct gpt_clk_config {
+ u32 *synth_reg;
+ struct gpt_clk_masks *masks;
};
/* platform specific clock functions */
@@ -118,7 +162,7 @@ void recalc_root_clocks(void);
/* clock recalc functions */
void follow_parent(struct clk *clk);
-void pll1_clk_recalc(struct clk *clk);
+void pll_clk_recalc(struct clk *clk);
void bus_clk_recalc(struct clk *clk);
void gpt_clk_recalc(struct clk *clk);
void aux_clk_recalc(struct clk *clk);
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 05/62] ST SPEAr: Formalized timer support
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (3 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 04/62] ST SPEAr: Making clock functions more generic Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 23:50 ` Jamie Iles
2011-01-18 7:11 ` [PATCH V4 06/62] ST SPEAr13XX: Adding machine specific header files Viresh Kumar
` (56 subsequent siblings)
61 siblings, 1 reply; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Arch specific timer initialization code is moved into Arch specific file.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 3 +-
arch/arm/mach-spear3xx/spear300_evb.c | 2 +-
arch/arm/mach-spear3xx/spear310_evb.c | 2 +-
arch/arm/mach-spear3xx/spear320_evb.c | 2 +-
arch/arm/mach-spear3xx/spear3xx.c | 32 ++++++++++++++++++++++++-
arch/arm/mach-spear6xx/include/mach/generic.h | 3 +-
arch/arm/mach-spear6xx/spear600_evb.c | 3 +-
arch/arm/mach-spear6xx/spear6xx.c | 31 ++++++++++++++++++++++++
arch/arm/plat-spear/time.c | 21 ++++++----------
9 files changed, 79 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index c16d2f8..e7d2de8 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -33,10 +33,11 @@
/* Add spear3xx family device structure declarations here */
extern struct amba_device gpio_device;
extern struct amba_device uart_device;
-extern struct sys_timer spear_sys_timer;
+extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
void __init clk_init(void);
+void __init spear_setup_timer(void);
void __init spear3xx_map_io(void);
void __init spear3xx_init_irq(void);
void __init spear3xx_init(void);
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 2c90663..cd23c98 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -71,6 +71,6 @@ MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
.boot_params = 0x00000100,
.map_io = spear3xx_map_io,
.init_irq = spear3xx_init_irq,
- .timer = &spear_sys_timer,
+ .timer = &spear3xx_timer,
.init_machine = spear300_evb_init,
MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 4e55e55..3855431 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -78,6 +78,6 @@ MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
.boot_params = 0x00000100,
.map_io = spear3xx_map_io,
.init_irq = spear3xx_init_irq,
- .timer = &spear_sys_timer,
+ .timer = &spear3xx_timer,
.init_machine = spear310_evb_init,
MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 7083a06..4a7ce35 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -75,6 +75,6 @@ MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
.boot_params = 0x00000100,
.map_io = spear3xx_map_io,
.init_irq = spear3xx_init_irq,
- .timer = &spear_sys_timer,
+ .timer = &spear3xx_timer,
.init_machine = spear320_evb_init,
MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index faf8709..e281e0c 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -523,5 +523,35 @@ struct pmx_dev pmx_plgpio_45_46_49_50 = {
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
.enb_on_reset = 1,
};
+#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
-#endif
+static void __init spear3xx_timer_init(void)
+{
+ char pclk_name[] = "pll3_48m_clk";
+ struct clk *gpt_clk, *pclk;
+
+ /* get the system timer clock */
+ gpt_clk = clk_get_sys("gpt0", NULL);
+ if (!gpt_clk) {
+ pr_err("%s:couldn't get clk for gpt\n", __func__);
+ BUG();
+ }
+
+ /* get the suitable parent clock for timer*/
+ pclk = clk_get(NULL, pclk_name);
+ if (!pclk) {
+ pr_err("%s:couldn't get %s as parent for gpt\n",
+ __func__, pclk_name);
+ BUG();
+ }
+
+ clk_set_parent(gpt_clk, pclk);
+ clk_put(gpt_clk);
+ clk_put(pclk);
+
+ spear_setup_timer();
+}
+
+struct sys_timer spear3xx_timer = {
+ .init = spear3xx_timer_init,
+};
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 16205a5..e5967ed 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -31,9 +31,10 @@
/* Add spear6xx family device structure declarations here */
extern struct amba_device gpio_device[];
extern struct amba_device uart_device[];
-extern struct sys_timer spear_sys_timer;
+extern struct sys_timer spear6xx_timer;
/* Add spear6xx family function declarations here */
+void __init spear_setup_timer(void);
void __init spear6xx_map_io(void);
void __init spear6xx_init_irq(void);
void __init spear6xx_init(void);
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index daff8d0..bdd5b76 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -42,10 +42,11 @@ static void __init spear600_evb_init(void)
amba_device_register(amba_devs[i], &iomem_resource);
}
+
MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
.boot_params = 0x00000100,
.map_io = spear6xx_map_io,
.init_irq = spear6xx_init_irq,
- .timer = &spear_sys_timer,
+ .timer = &spear6xx_timer,
.init_machine = spear600_evb_init,
MACHINE_END
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index f2fe14e..ea4c356 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -155,3 +155,34 @@ void __init spear6xx_map_io(void)
/* This will initialize clock framework */
clk_init();
}
+
+static void __init spear6xx_timer_init(void)
+{
+ char pclk_name[] = "pll3_48m_clk";
+ struct clk *gpt_clk, *pclk;
+
+ /* get the system timer clock */
+ gpt_clk = clk_get_sys("gpt0", NULL);
+ if (!gpt_clk) {
+ pr_err("%s:couldn't get clk for gpt\n", __func__);
+ BUG();
+ }
+
+ /* get the suitable parent clock for timer*/
+ pclk = clk_get(NULL, pclk_name);
+ if (!pclk) {
+ pr_err("%s:couldn't get %s as parent for gpt\n",
+ __func__, pclk_name);
+ BUG();
+ }
+
+ clk_set_parent(gpt_clk, pclk);
+ clk_put(gpt_clk);
+ clk_put(pclk);
+
+ spear_setup_timer();
+}
+
+struct sys_timer spear6xx_timer = {
+ .init = spear6xx_timer_init,
+};
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index 839c88d..100672f 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -1,7 +1,7 @@
/*
* arch/arm/plat-spear/time.c
*
- * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2010 ST Microelectronics
* Shiraz Hashim<shiraz.hashim@st.com>
*
* This file is licensed under the terms of the GNU General Public
@@ -211,7 +211,7 @@ static void __init spear_clockevent_init(void)
void __init spear_setup_timer(void)
{
- struct clk *pll3_clk;
+ int ret;
if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
pr_err("%s:cannot get IO addr\n", __func__);
@@ -230,26 +230,21 @@ void __init spear_setup_timer(void)
goto err_iomap;
}
- pll3_clk = clk_get(NULL, "pll3_48m_clk");
- if (!pll3_clk) {
- pr_err("%s:couldn't get PLL3 as parent for gpt\n", __func__);
- goto err_iomap;
+ ret = clk_enable(gpt_clk);
+ if (ret < 0) {
+ pr_err("%s:couldn't enable gpt clock\n", __func__);
+ goto err_clk;
}
- clk_set_parent(gpt_clk, pll3_clk);
-
spear_clockevent_init();
spear_clocksource_init();
return;
+err_clk:
+ clk_put(gpt_clk);
err_iomap:
iounmap(gpt_base);
-
err_mem:
release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
}
-
-struct sys_timer spear_sys_timer = {
- .init = spear_setup_timer,
-};
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 06/62] ST SPEAr13XX: Adding machine specific header files
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (4 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 05/62] ST SPEAr: Formalized timer support Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 16:00 ` Russell King - ARM Linux
2011-01-18 7:11 ` [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files Viresh Kumar
` (55 subsequent siblings)
61 siblings, 1 reply; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/clkdev.h | 19 ++
arch/arm/mach-spear13xx/include/mach/debug-macro.S | 14 +
arch/arm/mach-spear13xx/include/mach/entry-macro.S | 22 ++
arch/arm/mach-spear13xx/include/mach/generic.h | 46 +++
arch/arm/mach-spear13xx/include/mach/gpio.h | 19 ++
arch/arm/mach-spear13xx/include/mach/hardware.h | 25 ++
arch/arm/mach-spear13xx/include/mach/io.h | 19 ++
arch/arm/mach-spear13xx/include/mach/irqs.h | 91 ++++++
arch/arm/mach-spear13xx/include/mach/memory.h | 19 ++
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 306 ++++++++++++++++++++
arch/arm/mach-spear13xx/include/mach/smp.h | 25 ++
arch/arm/mach-spear13xx/include/mach/spear.h | 93 ++++++
arch/arm/mach-spear13xx/include/mach/spear1300.h | 21 ++
arch/arm/mach-spear13xx/include/mach/system.h | 35 +++
arch/arm/mach-spear13xx/include/mach/timex.h | 19 ++
arch/arm/mach-spear13xx/include/mach/uncompress.h | 19 ++
arch/arm/mach-spear13xx/include/mach/vmalloc.h | 18 ++
17 files changed, 810 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/io.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/memory.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/smp.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1300.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/vmalloc.h
diff --git a/arch/arm/mach-spear13xx/include/mach/clkdev.h b/arch/arm/mach-spear13xx/include/mach/clkdev.h
new file mode 100644
index 0000000..effdb81
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/clkdev.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/clkdev.h
+ *
+ * Clock Dev framework definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#include <plat/clkdev.h>
+
+#endif /* __MACH_CLKDEV_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
new file mode 100644
index 0000000..3933edc
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header spear13xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/entry-macro.S b/arch/arm/mach-spear13xx/include/mach/entry-macro.S
new file mode 100644
index 0000000..93d1215
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/entry-macro.S
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * Copy of RealView platform implementation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <asm/hardware/entry-macro-gic.S>
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
new file mode 100644
index 0000000..5c0f042
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/generic.h
+ *
+ * spear13xx machine family generic header file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GENERIC_H
+#define __MACH_GENERIC_H
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+/*
+ * Each GPT has 2 timer channels
+ * Following GPT channels will be used as clock source and clockevent
+ */
+#define SPEAR_GPT0_BASE SPEAR13XX_GPT0_BASE
+#define SPEAR_GPT0_CHAN0_IRQ IRQ_GPT0_TMR0
+#define SPEAR_GPT0_CHAN1_IRQ IRQ_GPT0_TMR1
+
+/* Add spear13xx family device structure declarations here */
+extern struct amba_device spear13xx_uart_device;
+extern struct sys_timer spear13xx_timer;
+
+/* Add spear1300 machine device structure declarations here */
+
+/* Add spear13xx family function declarations here */
+void __init clk_init(void);
+void __init spear_setup_timer(void);
+void __init spear1300_init(void);
+void __init spear13xx_map_io(void);
+void __init spear13xx_init_irq(void);
+void __init spear13xx_init(void);
+void spear13xx_secondary_startup(void);
+
+#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
new file mode 100644
index 0000000..43fa541
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/gpio.h
+ *
+ * GPIO macros for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
new file mode 100644
index 0000000..0047d75
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/hardware.h
+ *
+ * Hardware definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#include <mach/spear.h>
+
+/* Vitual to physical translation of statically mapped space */
+#define IO_ADDRESS(x) (x | 0xF0000000)
+
+/* typesafe io address */
+#define __io_address(n) __io(IO_ADDRESS(n))
+
+#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/io.h b/arch/arm/mach-spear13xx/include/mach/io.h
new file mode 100644
index 0000000..2fe3503
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/io.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/io.h
+ *
+ * IO definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#include <plat/io.h>
+
+#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
new file mode 100644
index 0000000..036bfc6
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+/* IRQ definitions */
+/*
+ * SGI : ID0 - ID15
+ * PPI : ID16 - ID31
+ * SHPI : ID32 - ID224
+ */
+
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
+/* Shared Peripheral Interrupt (SHPI) */
+#define IRQ_SHPI_START 32
+
+#define IRQ_PLAY_I2S2 (IRQ_SHPI_START + 10)
+#define IRQ_REC_I2S2 (IRQ_SHPI_START + 11)
+#define IRQ_ADC (IRQ_SHPI_START + 12)
+#define IRQ_CLCD (IRQ_SHPI_START + 13)
+#define IRQ_DMAC0_FLAG_0 (IRQ_SHPI_START + 14)
+#define IRQ_DMAC0_FLAG_1 (IRQ_SHPI_START + 15)
+#define IRQ_DMAC0_FLAG_2 (IRQ_SHPI_START + 16)
+#define IRQ_DMAC0_FLAG_3 (IRQ_SHPI_START + 17)
+#define IRQ_DMAC0_FLAG_4 (IRQ_SHPI_START + 18)
+#define IRQ_DMAC0_COMBINED (IRQ_SHPI_START + 19)
+#define IRQ_FSMC0 (IRQ_SHPI_START + 20)
+#define IRQ_FSMC1 (IRQ_SHPI_START + 21)
+#define IRQ_FSMC2 (IRQ_SHPI_START + 22)
+#define IRQ_FSMC3 (IRQ_SHPI_START + 23)
+#define IRQ_GPIO0 (IRQ_SHPI_START + 24)
+#define IRQ_GPIO1 (IRQ_SHPI_START + 25)
+#define IRQ_PLAY_I2S1 (IRQ_SHPI_START + 26)
+#define IRQ_JPEG (IRQ_SHPI_START + 27)
+#define IRQ_SDHCI (IRQ_SHPI_START + 28)
+#define IRQ_CF (IRQ_SHPI_START + 29)
+#define IRQ_SMI (IRQ_SHPI_START + 30)
+#define IRQ_SSP (IRQ_SHPI_START + 31)
+#define IRQ_C3 (IRQ_SHPI_START + 32)
+#define IRQ_GMAC_1 (IRQ_SHPI_START + 33)
+#define IRQ_GMAC_2 (IRQ_SHPI_START + 34)
+#define IRQ_UART (IRQ_SHPI_START + 35)
+#define IRQ_RTC (IRQ_SHPI_START + 36)
+#define IRQ_GPT0_TMR0 (IRQ_SHPI_START + 37)
+#define IRQ_GPT0_TMR1 (IRQ_SHPI_START + 38)
+#define IRQ_GPT1_TMR0 (IRQ_SHPI_START + 39)
+#define IRQ_GPT1_TMR1 (IRQ_SHPI_START + 40)
+#define IRQ_I2C (IRQ_SHPI_START + 41)
+#define IRQ_GPT2_TMR0 (IRQ_SHPI_START + 42)
+#define IRQ_GPT2_TMR1 (IRQ_SHPI_START + 43)
+#define IRQ_GPT3_TMR0 (IRQ_SHPI_START + 44)
+#define IRQ_GPT3_TMR1 (IRQ_SHPI_START + 45)
+
+#define IRQ_JPEG_RME (IRQ_SHPI_START + 52)
+#define IRQ_KBD (IRQ_SHPI_START + 52)
+#define IRQ_REC_I2S1 (IRQ_SHPI_START + 53)
+#define IRQ_DMAC1_FLAG_0 (IRQ_SHPI_START + 54)
+#define IRQ_DMAC1_FLAG_1 (IRQ_SHPI_START + 55)
+#define IRQ_DMAC1_FLAG_2 (IRQ_SHPI_START + 56)
+#define IRQ_DMAC1_FLAG_3 (IRQ_SHPI_START + 57)
+#define IRQ_DMAC1_FLAG_4 (IRQ_SHPI_START + 58)
+#define IRQ_DMAC1_COMBINED (IRQ_SHPI_START + 59)
+
+#define IRQ_UDC (IRQ_SHPI_START + 62)
+#define IRQ_UPD (IRQ_SHPI_START + 63)
+#define IRQ_USBH_EHCI0 (IRQ_SHPI_START + 64)
+#define IRQ_USBH_OHCI0 (IRQ_SHPI_START + 65)
+#define IRQ_USBH_EHCI1 (IRQ_SHPI_START + 66)
+#define IRQ_USBH_OHCI1 (IRQ_SHPI_START + 67)
+#define IRQ_PCIE1 (IRQ_SHPI_START + 68)
+#define IRQ_PCIE2 (IRQ_SHPI_START + 69)
+#define IRQ_PCIE3 (IRQ_SHPI_START + 70)
+
+#define IRQ_GIC_END (IRQ_SHPI_START + 128)
+
+#define NR_IRQS IRQ_GIC_END
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/memory.h b/arch/arm/mach-spear13xx/include/mach/memory.h
new file mode 100644
index 0000000..200257c
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/memory.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/memory.h
+ *
+ * Memory map for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#include <plat/memory.h>
+
+#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
new file mode 100644
index 0000000..1f6028f
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -0,0 +1,306 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/misc_regs.h
+ *
+ * Miscellaneous registers definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MISC_REGS_H
+#define __MACH_MISC_REGS_H
+
+#include <mach/hardware.h>
+
+#define MISC_BASE VA_SPEAR13XX_MISC_BASE
+
+/* General Configuration */
+#define SOC_CFG ((unsigned int *)(MISC_BASE + 0x000))
+#define BOOTSTRAP_CFG ((unsigned int *)(MISC_BASE + 0x004))
+
+/* Power Management Registers */
+#define PCM_CFG ((unsigned int *)(MISC_BASE + 0x100))
+#define PCM_WKUP_CFG ((unsigned int *)(MISC_BASE + 0x104))
+#define SWITCH_CTR ((unsigned int *)(MISC_BASE + 0x108))
+#define SYS_CLK_CTRL ((unsigned int *)(MISC_BASE + 0x200))
+#define SYS_SW_RES ((unsigned int *)(MISC_BASE + 0x204))
+
+/* Clock Configuration Registers */
+#define SYS_CLK_PLLTIMER ((unsigned int *)(MISC_BASE + 0x208))
+#define SYS_CLK_OSCITIMER ((unsigned int *)(MISC_BASE + 0x20c))
+
+/* PLL related registers and bit values */
+#define PLL_CFG ((unsigned int *)(MISC_BASE + 0x210))
+ /* PLL_CFG bit values */
+ #define OSC_24M_MASK 0
+ #define OSC_25M_MASK 1
+ #define PLL_CLK_MASK 3
+ #define PLL1_CLK_SHIFT 20
+ #define PLL2_CLK_SHIFT 22
+ #define PLL3_CLK_SHIFT 24
+
+#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x214))
+#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x218))
+#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x21c))
+#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x220))
+#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x224))
+#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x228))
+#define PLL3_CTR ((unsigned int *)(MISC_BASE + 0x22c))
+#define PLL3_FRQ ((unsigned int *)(MISC_BASE + 0x230))
+#define PLL3_MOD ((unsigned int *)(MISC_BASE + 0x234))
+#define PLL4_CTR ((unsigned int *)(MISC_BASE + 0x238))
+ /* PLL_CTR register masks */
+ #define PLL_ENABLE 2
+ #define PLL_MODE_SHIFT 4
+ #define PLL_MODE_MASK 3
+ #define PLL_MODE_NORMAL 0
+ #define PLL_MODE_FRACTION 1
+ #define PLL_MODE_DITH_DSB 2
+ #define PLL_MODE_DITH_SSB 3
+
+#define PLL4_FRQ ((unsigned int *)(MISC_BASE + 0x23c))
+ /* PLL FRQ register masks */
+ #define PLL_DIV_N_SHIFT 0
+ #define PLL_DIV_N_MASK 0xFF
+ #define PLL_DIV_P_SHIFT 8
+ #define PLL_DIV_P_MASK 0x7
+ #define PLL_NORM_FDBK_M_SHIFT 24
+ #define PLL_NORM_FDBK_M_MASK 0xFF
+ #define PLL_DITH_FDBK_M_SHIFT 16
+ #define PLL_DITH_FDBK_M_MASK 0xFFFF
+
+#define PLL4_MOD ((unsigned int *)(MISC_BASE + 0x240))
+
+#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x244))
+ /* PERIP_CLK_CFG bit values */
+ #define GPT_OSC24_MASK 0
+ #define GPT_APB_MASK 1
+ #define GPT_CLK_MASK 1
+ #define GPT0_CLK_SHIFT 8
+ #define GPT1_CLK_SHIFT 9
+ #define GPT2_CLK_SHIFT 12
+ #define GPT3_CLK_SHIFT 13
+ #define AUX_CLK_PLL1_MASK 1
+ #define AUX_CLK_PLL5_MASK 0
+ #define UART_CLK_MASK 1
+ #define UART_CLK_SHIFT 4
+
+#define GMAC_CLK_CFG ((unsigned int *)(MISC_BASE + 0x248))
+#define C3_CLK_SYNTH ((unsigned int *)(MISC_BASE + 0x24c))
+#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x250))
+#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x254))
+#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x258))
+#define MCIF_SD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x25c))
+#define MCIF_CFXD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x260))
+#define RAS_CLK_SYNT0 ((unsigned int *)(MISC_BASE + 0x264))
+#define RAS_CLK_SYNT1 ((unsigned int *)(MISC_BASE + 0x268))
+#define RAS_CLK_SYNT2 ((unsigned int *)(MISC_BASE + 0x26c))
+#define RAS_CLK_SYNT3 ((unsigned int *)(MISC_BASE + 0x270))
+ /* aux clk synthesizer register masks */
+ #define AUX_EQ_SEL_SHIFT 30
+ #define AUX_EQ_SEL_MASK 1
+ #define AUX_EQ1_SEL 0
+ #define AUX_EQ2_SEL 1
+ #define AUX_XSCALE_SHIFT 16
+ #define AUX_XSCALE_MASK 0xFFF
+ #define AUX_YSCALE_SHIFT 0
+ #define AUX_YSCALE_MASK 0xFFF
+
+#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x274))
+ /* PERIP1_CLK_ENB register masks */
+ #define BUS_CLK_ENB 0
+ #define SYSROM_CLK_ENB 1
+ #define AORAM_CLK_ENB 2
+ #define SYSRAM_CLK_ENB 3
+ #define FSMC_CLK_ENB 4
+ #define SMI_CLK_ENB 5
+ #define SD_CLK_ENB 6
+ #define CF_XD_CLK_ENB 7
+ #define GETH_CLK_ENB 8
+ #define UHC0_CLK_ENB 9
+ #define UHC1_CLK_ENB 10
+ #define UDC_UPD_CLK_ENB 11
+ #define PCI0_CLK_ENB 12
+ #define PCI1_CLK_ENB 13
+ #define PCI2_CLK_ENB 14
+ #define UART_CLK_ENB 15
+ #define SSP_CLK_ENB 17
+ #define I2C_CLK_ENB 18
+ #define I2S_SLV_CLK_ENB 19
+ #define I2S_MST_CLK_ENB 20
+ #define GPT0_CLK_ENB 21
+ #define GPT1_CLK_ENB 22
+ #define GPIOA_CLK_ENB 23
+ #define GPIOB_CLK_ENB 24
+ #define DMA0_CLK_ENB 25
+ #define DMA1_CLK_ENB 26
+ #define CLCD_CLK_ENB 27
+ #define JPEGC_CLK_ENB 28
+ #define C3_CLK_ENB 29
+ #define ADC_CLK_ENB 30
+ #define RTC_CLK_ENB 31
+
+#define PERIP2_CLK_ENB ((unsigned int *)(MISC_BASE + 0x278))
+ /* PERIP2_CLK_ENB register masks */
+ #define DDR_CTRL_CLK_ENB 0
+ #define DDR_CORE_CLK_ENB 1
+ #define CPU_DBG_CLK_ENB 2
+ #define KBD_CLK_ENB 3
+ #define GPT2_CLK_ENB 4
+ #define GPT3_CLK_ENB 5
+ #define ACP_CLK_ENB 6
+ #define I2S_REFOUT_CLK_ENB 7
+ #define THSENS_CLK_ENB 8
+
+#define PERIP1_SW_RST ((unsigned int *)(MISC_BASE + 0x27c))
+ #define JPEG_SOF_RST 28
+#define PERIP2_SW_RST ((unsigned int *)(MISC_BASE + 0x280))
+#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x284))
+#define RAS_SW_RST ((unsigned int *)(MISC_BASE + 0x288))
+#define PLL1_SYNT ((unsigned int *)(MISC_BASE + 0x28c))
+#define I2S_CLK_CFG ((unsigned int *)(MISC_BASE + 0x290))
+
+/* Peripheral Configuration Registers */
+#define DMAC_HS_SEL ((unsigned int *)(MISC_BASE + 0x300))
+#define DMAC_SEL ((unsigned int *)(MISC_BASE + 0x304))
+#define DMAC_FLOW_SEL ((unsigned int *)(MISC_BASE + 0x308))
+#define DMAC_DIR_SEL ((unsigned int *)(MISC_BASE + 0x30c))
+#define DMAC_CFG ((unsigned int *)(MISC_BASE + 0x310))
+#define USBPHY_GEN_CFG ((unsigned int *)(MISC_BASE + 0x314))
+#define USBPHY_P1_CFG ((unsigned int *)(MISC_BASE + 0x318))
+#define USBPHY_P2_CFG ((unsigned int *)(MISC_BASE + 0x31c))
+#define USBPHY_P3_CFG ((unsigned int *)(MISC_BASE + 0x320))
+#define PCIE_CFG ((unsigned int *)(MISC_BASE + 0x324))
+#define PCIE_MIPHY_CFG ((unsigned int *)(MISC_BASE + 0x328))
+#define PERIP_CFG ((unsigned int *)(MISC_BASE + 0x32c))
+ #define MCIF_SEL_SHIFT 3
+ #define MCIF_SEL_MASK 0x3
+ #define SD_MMC_ACTIVE 0x1
+ #define CF_MMC_ACTIVE 0x2
+ #define XD_MMC_ACTIVE 0x3
+#define FSMC_CFG ((unsigned int *)(MISC_BASE + 0x330))
+#define MPMC_CTR_STS ((unsigned int *)(MISC_BASE + 0x334))
+
+/* Inter-Processor Communication Registers */
+#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x500))
+#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x504))
+#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x508))
+#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x51C))
+
+/* Pad Configuration Registers */
+#define PAD_PU_CFG_1 ((unsigned int *)(MISC_BASE + 0x600))
+#define PAD_PU_CFG_2 ((unsigned int *)(MISC_BASE + 0x604))
+#define PAD_PU_CFG_3 ((unsigned int *)(MISC_BASE + 0x608))
+#define PAD_PU_CFG_4 ((unsigned int *)(MISC_BASE + 0x60c))
+#define PAD_PU_CFG_5 ((unsigned int *)(MISC_BASE + 0x610))
+#define PAD_PU_CFG_6 ((unsigned int *)(MISC_BASE + 0x614))
+#define PAD_PU_CFG_7 ((unsigned int *)(MISC_BASE + 0x618))
+#define PAD_PU_CFG_8 ((unsigned int *)(MISC_BASE + 0x61c))
+#define PAD_PD_CFG_1 ((unsigned int *)(MISC_BASE + 0x620))
+#define PAD_PD_CFG_2 ((unsigned int *)(MISC_BASE + 0x624))
+#define PAD_PD_CFG_3 ((unsigned int *)(MISC_BASE + 0x628))
+#define PAD_PD_CFG_4 ((unsigned int *)(MISC_BASE + 0x62c))
+#define PAD_PD_CFG_5 ((unsigned int *)(MISC_BASE + 0x630))
+#define PAD_PD_CFG_6 ((unsigned int *)(MISC_BASE + 0x634))
+#define PAD_PD_CFG_7 ((unsigned int *)(MISC_BASE + 0x638))
+#define PAD_PD_CFG_8 ((unsigned int *)(MISC_BASE + 0x63c))
+#define PAD_SLEEP_CFG ((unsigned int *)(MISC_BASE + 0x640))
+#define PAD_HYST_CFG ((unsigned int *)(MISC_BASE + 0x644))
+#define PAD_DRV_CFG ((unsigned int *)(MISC_BASE + 0x648))
+#define PAD_SLEW_CFG ((unsigned int *)(MISC_BASE + 0x64c))
+#define PAD_FUNCTION_EN_1 ((unsigned int *)(MISC_BASE + 0x650))
+#define PAD_FUNCTION_EN_2 ((unsigned int *)(MISC_BASE + 0x654))
+#define PAD_FUNCTION_EN_3 ((unsigned int *)(MISC_BASE + 0x658))
+#define DDR_PAD_CFG ((unsigned int *)(MISC_BASE + 0x65c))
+#define THSENS_CFG ((unsigned int *)(MISC_BASE + 0x6c4))
+
+/* Compensation Configuration Registers */
+#define COMP_1V8_2V5_3V3__1_CFG ((unsigned int *)(MISC_BASE + 0x700))
+#define COMP_1V8_2V5_3V3__2_CFG ((unsigned int *)(MISC_BASE + 0x704))
+#define COMP_3V3_1_CFG ((unsigned int *)(MISC_BASE + 0x708))
+#define COMP_3V3_2_CFG ((unsigned int *)(MISC_BASE + 0x70c))
+#define COMP_DDR_CFG ((unsigned int *)(MISC_BASE + 0x710))
+
+/* OTP Programming Registers */
+#define OTP_PROG_CTR ((unsigned int *)(MISC_BASE + 0x800))
+#define OTP_WDATA1_1 ((unsigned int *)(MISC_BASE + 0x804))
+#define OTP_WDATA1_2 ((unsigned int *)(MISC_BASE + 0x808))
+#define OTP_WDATA1_3 ((unsigned int *)(MISC_BASE + 0x80c))
+#define OTP_WDATA1_4 ((unsigned int *)(MISC_BASE + 0x810))
+#define OTP_WDATA1_5 ((unsigned int *)(MISC_BASE + 0x814))
+#define OTP_WDATA1_6 ((unsigned int *)(MISC_BASE + 0x818))
+#define OTP_WDATA1_7 ((unsigned int *)(MISC_BASE + 0x81c))
+#define OTP_WDATA1_8 ((unsigned int *)(MISC_BASE + 0x820))
+#define OTP_WDATA2_1 ((unsigned int *)(MISC_BASE + 0x824))
+#define OTP_WDATA2_2 ((unsigned int *)(MISC_BASE + 0x828))
+#define OTP_WDATA2_3 ((unsigned int *)(MISC_BASE + 0x82c))
+#define OTP_WDATA2_4 ((unsigned int *)(MISC_BASE + 0x830))
+#define OTP_WDATA2_5 ((unsigned int *)(MISC_BASE + 0x834))
+#define OTP_WDATA2_6 ((unsigned int *)(MISC_BASE + 0x838))
+#define OTP_WDATA2_7 ((unsigned int *)(MISC_BASE + 0x83c))
+#define OTP_WDATA2_8 ((unsigned int *)(MISC_BASE + 0x840))
+#define OTP_MASK_1 ((unsigned int *)(MISC_BASE + 0x844))
+#define OTP_MASK_2 ((unsigned int *)(MISC_BASE + 0x848))
+#define OTP_MASK_3 ((unsigned int *)(MISC_BASE + 0x84c))
+#define OTP_MASK_4 ((unsigned int *)(MISC_BASE + 0x850))
+#define OTP_MASK_5 ((unsigned int *)(MISC_BASE + 0x854))
+#define OTP_MASK_6 ((unsigned int *)(MISC_BASE + 0x858))
+#define OTP_MASK_7 ((unsigned int *)(MISC_BASE + 0x85c))
+#define OTP_MASK_8 ((unsigned int *)(MISC_BASE + 0x860))
+#define OTP_RDATA1_1 ((unsigned int *)(MISC_BASE + 0x864))
+#define OTP_RDATA1_2 ((unsigned int *)(MISC_BASE + 0x868))
+#define OTP_RDATA1_3 ((unsigned int *)(MISC_BASE + 0x86c))
+#define OTP_RDATA1_4 ((unsigned int *)(MISC_BASE + 0x870))
+#define OTP_RDATA1_5 ((unsigned int *)(MISC_BASE + 0x874))
+#define OTP_RDATA1_6 ((unsigned int *)(MISC_BASE + 0x878))
+#define OTP_RDATA1_7 ((unsigned int *)(MISC_BASE + 0x87c))
+#define OTP_RDATA1_8 ((unsigned int *)(MISC_BASE + 0x880))
+#define OTP_RDATA2_1 ((unsigned int *)(MISC_BASE + 0x884))
+#define OTP_RDATA2_2 ((unsigned int *)(MISC_BASE + 0x888))
+#define OTP_RDATA2_3 ((unsigned int *)(MISC_BASE + 0x88c))
+#define OTP_RDATA2_4 ((unsigned int *)(MISC_BASE + 0x890))
+#define OTP_RDATA2_5 ((unsigned int *)(MISC_BASE + 0x894))
+#define OTP_RDATA2_6 ((unsigned int *)(MISC_BASE + 0x898))
+#define OTP_RDATA2_7 ((unsigned int *)(MISC_BASE + 0x89c))
+#define OTP_RDATA2_8 ((unsigned int *)(MISC_BASE + 0x8a0))
+#define OTP_RDATAM_1 ((unsigned int *)(MISC_BASE + 0x8a4))
+#define OTP_RDATAM_2 ((unsigned int *)(MISC_BASE + 0x8a8))
+#define OTP_RDATAM_3 ((unsigned int *)(MISC_BASE + 0x8ac))
+#define OTP_RDATAM_4 ((unsigned int *)(MISC_BASE + 0x8b0))
+#define OTP_RDATAM_5 ((unsigned int *)(MISC_BASE + 0x8b4))
+#define OTP_RDATAM_6 ((unsigned int *)(MISC_BASE + 0x8b8))
+#define OTP_RDATAM_7 ((unsigned int *)(MISC_BASE + 0x8bc))
+#define OTP_RDATAM_8 ((unsigned int *)(MISC_BASE + 0x8c0))
+
+/* A9SM Registers */
+#define A9SM_CLUSTERID ((unsigned int *)(MISC_BASE + 0x900))
+#define A9SM_STATUS ((unsigned int *)(MISC_BASE + 0x904))
+#define A9SM_DEBUG ((unsigned int *)(MISC_BASE + 0x908))
+#define A9SM_FILTER ((unsigned int *)(MISC_BASE + 0x90c))
+#define A9SM_PARITY_CFG ((unsigned int *)(MISC_BASE + 0x910))
+#define A9SM_PARITY_ERR ((unsigned int *)(MISC_BASE + 0x914))
+
+/* SOC ID Registers */
+#define DIE_ID_1 ((unsigned int *)(MISC_BASE + 0xa00))
+#define DIE_ID_2 ((unsigned int *)(MISC_BASE + 0xa04))
+#define DIE_ID_3 ((unsigned int *)(MISC_BASE + 0xa08))
+#define DIE_ID_4 ((unsigned int *)(MISC_BASE + 0xa0c))
+#define DIE_ID_VALID ((unsigned int *)(MISC_BASE + 0xa10))
+
+/* SOC TEST & DEBUG Registers */
+#define MIPHY_TEST ((unsigned int *)(MISC_BASE + 0x1000))
+#define PCIE_MSTR_P0 ((unsigned int *)(MISC_BASE + 0x1004))
+#define PCIE_AWMISC_P0 ((unsigned int *)(MISC_BASE + 0x1008))
+#define PCIE_ARMISC_P0 ((unsigned int *)(MISC_BASE + 0x100c))
+#define PCIE_MSTR_P1 ((unsigned int *)(MISC_BASE + 0x1010))
+#define PCIE_AWMISC_P1 ((unsigned int *)(MISC_BASE + 0x1014))
+#define PCIE_ARMISC_P1 ((unsigned int *)(MISC_BASE + 0x1018))
+#define PCIE_MSTR_P2 ((unsigned int *)(MISC_BASE + 0x101c))
+#define PCIE_AWMISC_P2 ((unsigned int *)(MISC_BASE + 0x1020))
+#define PCIE_ARMISC_P2 ((unsigned int *)(MISC_BASE + 0x1024))
+
+#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/smp.h b/arch/arm/mach-spear13xx/include/mach/smp.h
new file mode 100644
index 0000000..c1c4580
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/smp.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/smp.h
+ *
+ * Few SMP related definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+/* We use IRQ1 as the IPI */
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
+{
+ gic_raise_softirq(mask, ipi);
+}
+
+#endif
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
new file mode 100644
index 0000000..d4b11a4
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -0,0 +1,93 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear.h
+ *
+ * spear13xx Machine family specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR13XX_H
+#define __MACH_SPEAR13XX_H
+
+#include <mach/spear1300.h>
+
+#define SPEAR13XX_L2CC_BASE 0xED000000
+
+/* ARM9SMP peripheral base address */
+#define SPEAR13XX_A9SM_PERIP_BASE 0xEC800000
+#define VA_SPEAR13XX_A9SM_PERIP_BASE IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE)
+/* A9SM peripheral offsets */
+#define SPEAR13XX_SCU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x00)
+#define SPEAR13XX_GIC_CPU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x100)
+#define SPEAR13XX_GLOBAL_TMR_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x200)
+#define SPEAR13XX_LOCAL_TMR_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x600)
+#define SPEAR13XX_WDT_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x620)
+#define SPEAR13XX_GIC_DIST_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x1000)
+
+#define SPEAR13XX_UART_BASE 0xE0000000
+#define VA_SPEAR13XX_UART_BASE IO_ADDRESS(SPEAR13XX_UART_BASE)
+
+#define SPEAR13XX_ADC_BASE 0xE0080000
+#define SPEAR13XX_SSP_BASE 0xE0100000
+#define SPEAR13XX_I2S0_BASE 0xE0180000
+#define SPEAR13XX_I2S1_BASE 0xE0200000
+#define SPEAR13XX_I2C_BASE 0xE0280000
+#define SPEAR13XX_KBD_BASE 0xE0300000
+#define SPEAR13XX_GPT0_BASE 0xE0380000
+#define SPEAR13XX_GPT1_BASE 0xE0400000
+#define SPEAR13XX_GPT2_BASE 0xE0480000
+#define SPEAR13XX_GPT3_BASE 0xE0500000
+#define SPEAR13XX_RTC_BASE 0xE0580000
+#define SPEAR13XX_GPIOA_BASE 0xE0600000
+#define SPEAR13XX_GPIOB_BASE 0xE0680000
+#define SPEAR13XX_MISC_BASE 0xE0700000
+#define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
+
+#define SPEAR13XX_SYSRAM0_BASE 0xB3800000
+#define SPEAR13XX_SYSRAM0_SIZE 0x00800000
+
+/*
+ * The system location which is polled by secondary cpus to find the
+ * jump address
+ */
+#define SPEAR13XX_SYS_LOCATION (SPEAR13XX_SYSRAM0_BASE + 0x600)
+
+#define SPEAR13XX_SYSRAM1_BASE 0xE0800000
+#define SPEAR13XX_SYSRAM1_SIZE 0x00800000
+#define SPEAR13XX_CLCD_BASE 0xE1000000
+#define SPEAR13XX_C3_BASE 0xE1800000
+#define SPEAR13XX_GETH_BASE 0xE2000000
+#define SPEAR13XX_UPD_BASE 0xE2800000
+#define SPEAR13XX_UDC_BASE 0xE3800000
+#define SPEAR13XX_UHC0_OHCI_BASE 0xE4000000
+#define SPEAR13XX_UHC0_EHCI_BASE 0xE4800000
+#define SPEAR13XX_UHC1_OHCI_BASE 0xE5000000
+#define SPEAR13XX_UHC1_EHCI_BASE 0xE5800000
+#define SPEAR13XX_SMI_MEM_BASE 0xE6000000
+#define SPEAR13XX_SMI_CTRL_BASE 0xEA000000
+#define SPEAR13XX_DMAC0_BASE 0xEA800000
+#define SPEAR13XX_DMAC1_BASE 0xEB000000
+#define SPEAR13XX_MII_PHY_BASE 0xEB800000
+#define SPEAR13XX_MPMC_BASE 0xEC000000
+#define SPEAR13XX_PCIE0_BASE 0x80000000
+#define SPEAR13XX_PCIE1_BASE 0x90000000
+#define SPEAR13XX_PCIE2_BASE 0xC0000000
+#define SPEAR13XX_PCIE0_APP_BASE 0xB1000000
+#define SPEAR13XX_PCIE1_APP_BASE 0xB1800000
+#define SPEAR13XX_PCIE2_APP_BASE 0xB4000000
+#define SPEAR13XX_FSMC_MEM_BASE 0xA0000000
+#define SPEAR13XX_FSMC_BASE 0xB0000000
+#define SPEAR13XX_JPEG_BASE 0xB2000000
+#define SPEAR13XX_MCIF_CF_BASE 0xB2800000
+#define SPEAR13XX_MCIF_SDHCI_BASE 0xB3000000
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE SPEAR13XX_UART_BASE
+#define VA_SPEAR_DBG_UART_BASE VA_SPEAR13XX_UART_BASE
+
+#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1300.h b/arch/arm/mach-spear13xx/include/mach/spear1300.h
new file mode 100644
index 0000000..b3ba267
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1300.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear1300.h
+ *
+ * SPEAr1300 Machine specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR1300
+
+#ifndef __MACH_SPEAR1300_H
+#define __MACH_SPEAR1300_H
+
+#endif /* __MACH_SPEAR1300_H */
+
+#endif /* CONFIG_MACH_SPEAR1300 */
diff --git a/arch/arm/mach-spear13xx/include/mach/system.h b/arch/arm/mach-spear13xx/include/mach/system.h
new file mode 100644
index 0000000..a9b159d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/system.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/system.h
+ *
+ * spear13xx Machine family specific architecture functions
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/misc_regs.h>
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ writel(0x01, SYS_SW_RES);
+}
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
new file mode 100644
index 0000000..0a81490
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/timex.h
+ *
+ * spear13xx machine family specific timex definitions
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE 24000000
+
+#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
new file mode 100644
index 0000000..3c27f25
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/vmalloc.h b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
new file mode 100644
index 0000000..85ad57e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/vmalloc.h
+ *
+ * Defining Vmalloc area for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#include <plat/vmalloc.h>
+
+#endif /* __MACH_VMALLOC_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (5 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 06/62] ST SPEAr13XX: Adding machine specific header files Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 16:06 ` Russell King - ARM Linux
2011-01-18 7:11 ` [PATCH V4 08/62] ST SPEAr: Adding support for SPEAr13xx SoC in spear generic plat/ Viresh Kumar
` (54 subsequent siblings)
61 siblings, 1 reply; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/Kconfig | 21 ++
arch/arm/mach-spear13xx/Makefile | 14 ++
arch/arm/mach-spear13xx/Makefile.boot | 3 +
arch/arm/mach-spear13xx/clock.c | 353 +++++++++++++++++++++++++++++++
arch/arm/mach-spear13xx/headsmp.S | 96 +++++++++
arch/arm/mach-spear13xx/localtimer.c | 25 +++
arch/arm/mach-spear13xx/platsmp.c | 165 ++++++++++++++
arch/arm/mach-spear13xx/spear1300.c | 23 ++
arch/arm/mach-spear13xx/spear1300_evb.c | 48 +++++
arch/arm/mach-spear13xx/spear13xx.c | 121 +++++++++++
10 files changed, 869 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/Kconfig
create mode 100644 arch/arm/mach-spear13xx/Makefile
create mode 100644 arch/arm/mach-spear13xx/Makefile.boot
create mode 100644 arch/arm/mach-spear13xx/clock.c
create mode 100644 arch/arm/mach-spear13xx/headsmp.S
create mode 100644 arch/arm/mach-spear13xx/localtimer.c
create mode 100644 arch/arm/mach-spear13xx/platsmp.c
create mode 100644 arch/arm/mach-spear13xx/spear1300.c
create mode 100644 arch/arm/mach-spear13xx/spear1300_evb.c
create mode 100644 arch/arm/mach-spear13xx/spear13xx.c
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
new file mode 100644
index 0000000..3ea463d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -0,0 +1,21 @@
+#
+# SPEAr13XX Machine configuration file
+#
+
+if ARCH_SPEAR13XX
+
+menu "SPEAr13xx Implementations"
+config BOARD_SPEAR1300_EVB
+ bool "SPEAr1300 Evaluation Board"
+ select MACH_SPEAR1300
+ help
+ Supports ST SPEAr1300 Evaluation Board
+
+endmenu
+
+config MACH_SPEAR1300
+ bool "SPEAr1300"
+ help
+ Supports ST SPEAr1300 Machine
+
+endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
new file mode 100644
index 0000000..cb5ae9e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for SPEAr13XX machine series
+#
+
+# common files
+obj-y += spear13xx.o clock.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+
+# spear1300 specific files
+obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
+
+# spear1300 boards files
+obj-$(CONFIG_BOARD_SPEAR1300_EVB) += spear1300_evb.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
new file mode 100644
index 0000000..7a1f3c0
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
new file mode 100644
index 0000000..722f634
--- /dev/null
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -0,0 +1,353 @@
+/*
+ * arch/arm/mach-spear13xx/clock.c
+ *
+ * SPEAr13xx machines clock framework source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * shiraz hashim<shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <asm/mach-types.h>
+#include <plat/clock.h>
+#include <mach/hardware.h>
+#include <mach/misc_regs.h>
+
+/* root clks */
+/* 24 MHz oscillator clock */
+static struct clk osc1_24m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 24000000,
+};
+
+/* 32 KHz oscillator clock */
+static struct clk osc2_32k_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 32000,
+};
+
+/* 25 MHz MIPHY oscillator clock */
+static struct clk osc3_25m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 25000000,
+};
+
+/* clock derived from 32 KHz osc clk */
+/* rtc clock */
+static struct clk rtc_clk = {
+ .pclk = &osc2_32k_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = RTC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from osc1 or osc3 */
+/* pll[1-3] parents */
+static struct pclk_info pll_pclk_info[] = {
+ {
+ .pclk = &osc1_24m_clk,
+ .pclk_mask = OSC_24M_MASK,
+ }, {
+ .pclk = &osc3_25m_clk,
+ .pclk_mask = OSC_25M_MASK,
+ },
+};
+
+/* pll[1-3] parent select structure */
+static struct pclk_sel pll_pclk_sel = {
+ .pclk_info = pll_pclk_info,
+ .pclk_count = ARRAY_SIZE(pll_pclk_info),
+ .pclk_sel_reg = PLL_CFG,
+ .pclk_sel_mask = PLL_CLK_MASK,
+};
+
+/* pll masks structure */
+static struct pll_clk_masks pll_masks = {
+ .mode_mask = PLL_MODE_MASK,
+ .mode_shift = PLL_MODE_SHIFT,
+ .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
+ .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
+ .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
+ .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
+ .div_p_mask = PLL_DIV_P_MASK,
+ .div_p_shift = PLL_DIV_P_SHIFT,
+ .div_n_mask = PLL_DIV_N_MASK,
+ .div_n_shift = PLL_DIV_N_SHIFT,
+};
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+ .mode_reg = PLL1_CTR,
+ .cfg_reg = PLL1_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll1 clock */
+static struct clk pll1_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL1_CLK_SHIFT,
+ .en_reg = PLL1_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .recalc = &pll_clk_recalc,
+ .private_data = &pll1_config,
+};
+
+/* pll2 configuration structure */
+static struct pll_clk_config pll2_config = {
+ .mode_reg = PLL2_CTR,
+ .cfg_reg = PLL2_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll2 clock */
+static struct clk pll2_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL2_CLK_SHIFT,
+ .en_reg = PLL2_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .recalc = &pll_clk_recalc,
+ .private_data = &pll2_config,
+};
+
+/* pll3 configuration structure */
+static struct pll_clk_config pll3_config = {
+ .mode_reg = PLL3_CTR,
+ .cfg_reg = PLL3_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll3 clock */
+static struct clk pll3_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL3_CLK_SHIFT,
+ .en_reg = PLL3_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .recalc = &pll_clk_recalc,
+ .private_data = &pll3_config,
+};
+
+/* pll4 (DDR) configuration structure */
+static struct pll_clk_config pll4_config = {
+ .mode_reg = PLL4_CTR,
+ .cfg_reg = PLL4_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll4 (DDR) clock */
+static struct clk pll4_clk = {
+ .pclk = &osc1_24m_clk,
+ .en_reg = PLL4_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .recalc = &pll_clk_recalc,
+ .private_data = &pll4_config,
+};
+
+/* pll5 USB 48 MHz clock */
+static struct clk pll5_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc1_24m_clk,
+ .rate = 48000000,
+};
+
+/* pll6 (MIPHY) clock */
+static struct clk pll6_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc3_25m_clk,
+ .rate = 25000000,
+};
+
+/* clocks derived from pll1 clk */
+/* cpu clock */
+static struct clk cpu_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* ahb clock */
+static struct clk ahb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 6,
+ .recalc = &follow_parent,
+};
+
+/* apb clock */
+static struct clk apb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 12,
+ .recalc = &follow_parent,
+};
+
+/* clocks derived from osc1, ahb or apb */
+/* gpt[0-3] parents */
+static struct pclk_info gpt_pclk_info[] = {
+ {
+ .pclk = &osc1_24m_clk,
+ .pclk_mask = GPT_OSC24_MASK,
+ }, {
+ .pclk = &apb_clk,
+ .pclk_mask = GPT_APB_MASK,
+ },
+};
+
+/* gpt[0-3] parent select structure */
+static struct pclk_sel gpt_pclk_sel = {
+ .pclk_info = gpt_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt0 timer clock */
+static struct clk gpt0_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT0_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT0_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt1 timer clock */
+static struct clk gpt1_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT1_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT1_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt2 timer clock */
+static struct clk gpt2_clk = {
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = GPT2_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT2_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt3 timer clock */
+static struct clk gpt3_clk = {
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = GPT3_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT3_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* watch dog timer clock */
+static struct clk wdt_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* smi clock */
+static struct clk smi_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SMI_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* auxiliary synthesizers masks */
+static struct aux_clk_masks aux_masks = {
+ .eq_sel_mask = AUX_EQ_SEL_MASK,
+ .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+ .eq1_mask = AUX_EQ1_SEL,
+ .eq2_mask = AUX_EQ2_SEL,
+ .xscale_sel_mask = AUX_XSCALE_MASK,
+ .xscale_sel_shift = AUX_XSCALE_SHIFT,
+ .yscale_sel_mask = AUX_YSCALE_MASK,
+ .yscale_sel_shift = AUX_YSCALE_SHIFT,
+};
+
+/* uart configurations */
+static struct aux_clk_config uart_config = {
+ .synth_reg = UART_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* clocks derived from pll1 or pll5 */
+/* uart parents */
+static struct pclk_info uart_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_mask = AUX_CLK_PLL5_MASK,
+ }, {
+ .pclk = &pll1_clk,
+ .pclk_mask = AUX_CLK_PLL1_MASK,
+ .scalable = 1,
+ },
+};
+
+/* uart parent select structure */
+static struct pclk_sel uart_pclk_sel = {
+ .pclk_info = uart_pclk_info,
+ .pclk_count = ARRAY_SIZE(uart_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = UART_CLK_MASK,
+};
+
+/* uart clock */
+static struct clk uart_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UART_CLK_ENB,
+ .pclk_sel = &uart_pclk_sel,
+ .pclk_sel_shift = UART_CLK_SHIFT,
+ .recalc = &aux_clk_recalc,
+ .private_data = &uart_config,
+};
+
+/* array of all spear 13xx clock lookups */
+static struct clk_lookup spear_clk_lookups[] = {
+ /* root clks */
+ {.con_id = "osc1_24m_clk", .clk = &osc1_24m_clk},
+ {.con_id = "osc2_32k_clk", .clk = &osc2_32k_clk},
+ {.con_id = "osc3_25m_clk", .clk = &osc3_25m_clk},
+
+ /* clock derived from 32 KHz osc clk */
+ {.dev_id = "rtc", .clk = &rtc_clk},
+
+ /* clock derived from 24/25 MHz osc1/osc3 clk */
+ {.con_id = "pll1_clk", .clk = &pll1_clk},
+ {.con_id = "pll2_clk", .clk = &pll2_clk},
+ {.con_id = "pll3_clk", .clk = &pll3_clk},
+ {.con_id = "pll4_clk", .clk = &pll4_clk},
+ {.con_id = "pll5_clk", .clk = &pll5_clk},
+ {.con_id = "pll6_clk", .clk = &pll6_clk},
+
+ /* clock derived from pll1 clk */
+ {.con_id = "cpu_clk", .clk = &cpu_clk},
+ {.con_id = "ahb_clk", .clk = &ahb_clk},
+ { .con_id = "apb_clk", .clk = &apb_clk},
+
+ /* clocks having multiple parent source from above clocks */
+ {.dev_id = "uart", .clk = &uart_clk},
+ {.dev_id = "gpt0", .clk = &gpt0_clk},
+ {.dev_id = "gpt1", .clk = &gpt1_clk},
+ {.dev_id = "gpt2", .clk = &gpt2_clk},
+ {.dev_id = "gpt3", .clk = &gpt3_clk},
+
+ /* clock derived from ahb/apb clk */
+ { .dev_id = "smi", .clk = &smi_clk},
+ { .dev_id = "wdt", .clk = &wdt_clk},
+};
+
+void __init clk_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ recalc_root_clocks();
+}
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
new file mode 100644
index 0000000..30761d3
--- /dev/null
+++ b/arch/arm/mach-spear13xx/headsmp.S
@@ -0,0 +1,96 @@
+/*
+ * arch/arm/mach-spear13XX/headsmp.S
+ *
+ * Picked from realview
+ * Copyright (c) 2010 ST Microelectronics Limited
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+/*
+ * This one is picked from Tegra :-
+ *
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the ain
+ * processor. We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ */
+ENTRY(v7_invalidate_l1)
+ mov r0, #0
+ mcr p15, 2, r0, c0, c0, 0
+ mrc p15, 1, r0, c0, c0, 0
+
+ ldr r1, =0x7fff
+ and r2, r1, r0, lsr #13
+
+ ldr r1, =0x3ff
+
+ and r3, r1, r0, lsr #3 @ NumWays - 1
+ add r2, r2, #1 @ NumSets
+
+ and r0, r0, #0x7
+ add r0, r0, #4 @ SetShift
+
+ clz r1, r3 @ WayShift
+ add r4, r3, #1 @ NumWays
+1: sub r2, r2, #1 @ NumSets--
+ mov r3, r4 @ Temp = NumWays
+2: subs r3, r3, #1 @ Temp--
+ mov r5, r3, lsl r1
+ mov r6, r2, lsl r0
+ orr r5, r5, r6 @ Reg = Temp<<WayShift)|(NumSets<<SetShift)
+ mcr p15, 0, r5, c7, c6, 2
+ bgt 2b
+ cmp r2, #0
+ bgt 1b
+ dsb
+ isb
+ mov pc, lr
+ENDPROC(v7_invalidate_l1)
+
+/*
+ * spear13xx specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(spear13xx_secondary_startup)
+ /* If we don't do this then we have a crash */
+
+ /*
+ * Since now this is being called from xloader so removing it
+ * here
+ */
+#if 0
+ bl v7_invalidate_l1
+#endif
+
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+
+ .align
+1: .long .
+ .long pen_release
diff --git a/arch/arm/mach-spear13xx/localtimer.c b/arch/arm/mach-spear13xx/localtimer.c
new file mode 100644
index 0000000..816b08c
--- /dev/null
+++ b/arch/arm/mach-spear13xx/localtimer.c
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/localtimer.c
+ * Directly picked from realview
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/* Setup the local clock events for a CPU. */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+ evt->irq = IRQ_LOCALTIMER;
+ twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
new file mode 100644
index 0000000..8fa7379
--- /dev/null
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -0,0 +1,165 @@
+/*
+ * arch/arm/mach-spear13xx/platsmp.c
+ *
+ * based upon linux/arch/arm/mach-realview/platsmp.c
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/smp_scu.h>
+#include <asm/system.h>
+#include <asm/unified.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+static DEFINE_SPINLOCK(boot_lock);
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not. This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+ pen_release = val;
+ smp_wmb();
+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static void __iomem *scu_base_addr(void)
+{
+ return __io_address(SPEAR13XX_SCU_BASE);
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_secondary_init(0);
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ write_pen_release(-1);
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /*
+ * The secondary processor is waiting to be released from
+ * the holding pen - release it, then wait for it to flag
+ * that it has been released by resetting pen_release.
+ *
+ * Note that "pen_release" is the hardware CPU ID, whereas
+ * "cpu" is Linux's internal ID.
+ */
+ write_pen_release(cpu);
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+ void __iomem *scu_base = scu_base_addr();
+ unsigned int i, ncores;
+
+ ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+}
+
+static void __init wakeup_secondary(void)
+{
+ /* nobody is to be released from the pen yet */
+ pen_release = -1;
+
+ /*
+ * Write the address of secondary startup into the system-wide
+ * location (presently it is in SRAM). The BootMonitor waits
+ * for this register to become non-zero.
+ * We must also send an sev to wake it up
+ */
+ __raw_writel(BSYM(virt_to_phys(spear13xx_secondary_startup)),
+ __io_address(SPEAR13XX_SYS_LOCATION));
+
+ mb();
+
+ /*
+ * Send a 'sev' to wake the secondary core from WFE.
+ */
+ sev();
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ /*
+ * Initialise the present map, which describes the set of CPUs
+ * actually populated at the present time.
+ */
+ for (i = 0; i < max_cpus; i++)
+ set_cpu_present(i, true);
+
+ scu_enable(scu_base_addr());
+ wakeup_secondary();
+}
diff --git a/arch/arm/mach-spear13xx/spear1300.c b/arch/arm/mach-spear13xx/spear1300.c
new file mode 100644
index 0000000..c1b82f1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1300.c
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-spear13xx/spear1300.c
+ *
+ * SPEAr1300 machine source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Add spear1300 specific devices here */
+
+void __init spear1300_init(void)
+{
+ /* call spear13xx family common init function */
+ spear13xx_init();
+}
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
new file mode 100644
index 0000000..9a83d61
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-spear13xx/spear1300_evb.c
+ *
+ * SPEAr1300 evaluation board source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ &spear13xx_uart_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+};
+
+static void __init spear1300_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear1300 machine init function */
+ spear1300_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR1300, "ST-SPEAR1300-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear13xx_map_io,
+ .init_irq = spear13xx_init_irq,
+ .timer = &spear13xx_timer,
+ .init_machine = spear1300_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
new file mode 100644
index 0000000..6774b26
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -0,0 +1,121 @@
+/*
+ * arch/arm/mach-spear13xx/spear13xx.c
+ *
+ * SPEAr13XX machines common source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/io.h>
+#include <asm/hardware/gic.h>
+#include <asm/irq.h>
+#include <asm/localtimer.h>
+#include <asm/mach/arch.h>
+#include <asm/smp_twd.h>
+#include <mach/irqs.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* Add spear13xx machines common devices here */
+/* uart device registeration */
+struct amba_device spear13xx_uart_device = {
+ .dev = {
+ .init_name = "uart",
+ },
+ .res = {
+ .start = SPEAR13XX_UART_BASE,
+ .end = SPEAR13XX_UART_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART, NO_IRQ},
+};
+
+/* Do spear13xx familiy common initialization part here */
+void __init spear13xx_init(void)
+{
+ /* nothing to do for now */
+}
+
+/* This will initialize vic */
+void __init spear13xx_init_irq(void)
+{
+ gic_init(0, 29, __io_address(SPEAR13XX_GIC_DIST_BASE),
+ __io_address(SPEAR13XX_GIC_CPU_BASE));
+}
+
+/* Following will create static virtual/physical mappings */
+struct map_desc spear13xx_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(SPEAR13XX_UART_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_UART_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_A9SM_PERIP_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_MISC_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_MISC_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_SYSRAM0_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_SYSRAM0_BASE),
+ .length = SZ_32K,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear13xx_map_io(void)
+{
+ iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
+
+ /* This will initialize clock framework */
+ clk_init();
+}
+
+static void __init spear13xx_timer_init(void)
+{
+ char pclk_name[] = "osc1_24m_clk";
+ struct clk *gpt_clk, *pclk;
+
+#ifdef CONFIG_LOCAL_TIMERS
+ /* Setup the local timer base */
+ twd_base = __io_address(SPEAR13XX_LOCAL_TMR_BASE);
+#endif
+
+ /* get the system timer clock */
+ gpt_clk = clk_get_sys("gpt0", NULL);
+ if (!gpt_clk) {
+ pr_err("%s:couldn't get clk for gpt\n", __func__);
+ BUG();
+ }
+
+ /* get the suitable parent clock for timer*/
+ pclk = clk_get(NULL, pclk_name);
+ if (!pclk) {
+ pr_err("%s:couldn't get %s as parent for gpt\n",
+ __func__, pclk_name);
+ BUG();
+ }
+
+ clk_set_parent(gpt_clk, pclk);
+ clk_put(gpt_clk);
+ clk_put(pclk);
+
+ spear_setup_timer();
+}
+
+struct sys_timer spear13xx_timer = {
+ .init = spear13xx_timer_init,
+};
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 08/62] ST SPEAr: Adding support for SPEAr13xx SoC in spear generic plat/
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (6 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 09/62] ST SPEAr13XX: Added compilation support in arch/arm/ Viresh Kumar
` (53 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/plat-spear/Kconfig | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbc..29a25d2 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,6 +8,13 @@ choice
prompt "ST SPEAr Family"
default ARCH_SPEAR3XX
+config ARCH_SPEAR13XX
+ bool "SPEAr13XX"
+ select ARM_GIC
+ select CPU_V7
+ help
+ Supports for ARM's SPEAR13XX family
+
config ARCH_SPEAR3XX
bool "SPEAr3XX"
select ARM_VIC
@@ -25,6 +32,7 @@ config ARCH_SPEAR6XX
endchoice
# Adding SPEAr machine specific configuration files
+source "arch/arm/mach-spear13xx/Kconfig"
source "arch/arm/mach-spear3xx/Kconfig"
source "arch/arm/mach-spear6xx/Kconfig"
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 09/62] ST SPEAr13XX: Added compilation support in arch/arm/
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (7 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 08/62] ST SPEAr: Adding support for SPEAr13xx SoC in spear generic plat/ Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 10/62] ST SPEAr13xx: Adding default config file Viresh Kumar
` (52 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
This patch adds compilation support for ST Microelectronics SPEAr13xx machines.
SPEAr13xx SOC's are based on Arm CortexA9 CPUs.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/Kconfig | 4 ++--
arch/arm/Makefile | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..f3904ba 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1253,8 +1253,8 @@ config SMP
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
- ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
- ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+ ARCH_S5PV310 || ARCH_SPEAR13XX || ARCH_TEGRA || ARCH_U8500 || \
+ ARCH_VEXPRESS_CA9X4 || ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c22c1ad..51769cc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -193,6 +193,7 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
machine-$(CONFIG_FOOTBRIDGE) := footbridge
+machine-$(CONFIG_MACH_SPEAR1300) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 10/62] ST SPEAr13xx: Adding default config file
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (8 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 09/62] ST SPEAr13XX: Added compilation support in arch/arm/ Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 11/62] ST SPEAr: Adding support for CLCD on SPEAr3xx/6xx Viresh Kumar
` (51 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/configs/spear13xx_defconfig | 60 ++++++++++++++++++++++++++++++++++
1 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/configs/spear13xx_defconfig
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
new file mode 100644
index 0000000..10b1cf5
--- /dev/null
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -0,0 +1,60 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_BOARD_SPEAR1300_EVB=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_AEABI=y
+CONFIG_BINFMT_MISC=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+# CONFIG_HWMON is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 11/62] ST SPEAr: Adding support for CLCD on SPEAr3xx/6xx
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (9 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 10/62] ST SPEAr13xx: Adding default config file Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 12/62] ST SPEAr: Updating Clock Support Viresh Kumar
` (50 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipul-kumar Samar <vipulkumar.samar@st.com>
SPEAr 3xx and 6xx have ARM PL110 CLCD controller. This patch adds
supports for CLCD in these machines.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 6 ++
arch/arm/mach-spear3xx/spear300.c | 17 ++++
arch/arm/mach-spear3xx/spear300_evb.c | 1 +
arch/arm/mach-spear3xx/spear320.c | 16 ++++
arch/arm/mach-spear3xx/spear320_evb.c | 1 +
arch/arm/mach-spear6xx/include/mach/generic.h | 4 +
arch/arm/mach-spear6xx/spear600_evb.c | 1 +
arch/arm/mach-spear6xx/spear6xx.c | 17 ++++
arch/arm/plat-spear/Makefile | 2 +-
arch/arm/plat-spear/clcd.c | 114 +++++++++++++++++++++++++
drivers/video/Kconfig | 14 +++-
11 files changed, 191 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/plat-spear/clcd.c
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index e7d2de8..1c8f9f1 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -100,6 +100,7 @@ extern struct pmx_driver pmx_driver;
/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
/* Add spear300 machine device structure declarations here */
+extern struct amba_device clcd_device;
extern struct amba_device gpio1_device;
/* pad mux modes */
@@ -136,6 +137,8 @@ extern struct pmx_dev pmx_gpio1;
/* Add spear300 machine function declarations here */
void __init spear300_init(void);
+/* Add misc structure declarations here */
+extern struct clcd_board clcd_plat_data;
#endif /* CONFIG_MACH_SPEAR300 */
/* spear310 declarations */
@@ -160,6 +163,7 @@ void __init spear310_init(void);
/* spear320 declarations */
#ifdef CONFIG_MACH_SPEAR320
/* Add spear320 machine device structure declarations here */
+extern struct amba_device clcd_device;
/* pad mux modes */
extern struct pmx_mode auto_net_smii_mode;
@@ -194,6 +198,8 @@ extern struct pmx_dev pmx_i2c1;
/* Add spear320 machine function declarations here */
void __init spear320_init(void);
+/* Add misc structure declarations here */
+extern struct clcd_board clcd_plat_data;
#endif /* CONFIG_MACH_SPEAR320 */
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 7e01677..1921cf8 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -371,6 +371,23 @@ struct pmx_driver pmx_driver = {
};
/* Add spear300 specific devices here */
+
+/* CLCD device registration */
+struct amba_device clcd_device = {
+ .dev = {
+ .init_name = "clcd",
+ .coherent_dma_mask = ~0,
+ .platform_data = &clcd_plat_data,
+ },
+ .res = {
+ .start = SPEAR300_CLCD_BASE,
+ .end = SPEAR300_CLCD_BASE + SPEAR300_CLCD_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .dma_mask = ~0,
+ .irq = {IRQ_CLCD, NO_IRQ},
+};
+
/* arm gpio1 device registration */
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index cd23c98..3bb7fbc 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -38,6 +38,7 @@ static struct amba_device *amba_devs[] __initdata = {
&uart_device,
/* spear300 specific devices */
+ &clcd_device,
&gpio1_device,
};
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 456bb33..70f1db2 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -386,6 +386,22 @@ struct pmx_driver pmx_driver = {
/* Add spear320 specific devices here */
+/* CLCD device registration */
+struct amba_device clcd_device = {
+ .dev = {
+ .init_name = "clcd",
+ .coherent_dma_mask = ~0,
+ .platform_data = &clcd_plat_data,
+ },
+ .res = {
+ .start = SPEAR320_CLCD_BASE,
+ .end = SPEAR320_CLCD_BASE + SPEAR320_CLCD_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .dma_mask = ~0,
+ .irq = {VIRQ_CLCD, NO_IRQ},
+};
+
/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
{
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 4a7ce35..821e806 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -43,6 +43,7 @@ static struct amba_device *amba_devs[] __initdata = {
&uart_device,
/* spear320 specific devices */
+ &clcd_device,
};
static struct platform_device *plat_devs[] __initdata = {
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index e5967ed..d6a04f2 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -29,6 +29,7 @@
#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
/* Add spear6xx family device structure declarations here */
+extern struct amba_device clcd_device;
extern struct amba_device gpio_device[];
extern struct amba_device uart_device[];
extern struct sys_timer spear6xx_timer;
@@ -43,4 +44,7 @@ void __init clk_init(void);
/* Add spear600 machine device structure declarations here */
+/* Add misc structure declarations here */
+extern struct clcd_board clcd_plat_data;
+
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index bdd5b76..88e69f4 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -17,6 +17,7 @@
#include <mach/spear.h>
static struct amba_device *amba_devs[] __initdata = {
+ &clcd_device,
&gpio_device[0],
&gpio_device[1],
&gpio_device[2],
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index ea4c356..9b61430 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -23,6 +23,23 @@
#include <mach/spear.h>
/* Add spear6xx machines common devices here */
+
+/* CLCD device registration */
+struct amba_device clcd_device = {
+ .dev = {
+ .init_name = "clcd",
+ .coherent_dma_mask = ~0,
+ .platform_data = &clcd_plat_data,
+ },
+ .res = {
+ .start = SPEAR6XX_ICM3_CLCD_BASE,
+ .end = SPEAR6XX_ICM3_CLCD_BASE + SPEAR6XX_ICM3_CLCD_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .dma_mask = ~0,
+ .irq = {IRQ_BASIC_CLCD, NO_IRQ},
+};
+
/* uart device registration */
struct amba_device uart_device[] = {
{
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index b4f340b..01a4a91 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
#
# Common support
-obj-y := clock.o time.o
+obj-y := clcd.o clock.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
diff --git a/arch/arm/plat-spear/clcd.c b/arch/arm/plat-spear/clcd.c
new file mode 100644
index 0000000..d469b81
--- /dev/null
+++ b/arch/arm/plat-spear/clcd.c
@@ -0,0 +1,114 @@
+/*
+* arch/arm/plat-spear/clcd.c
+*
+* Copyright (C) 2009 ST Microelectronics
+* Shiraz Hashim<shiraz.hashim@st.com>
+* Ashish Priyadarshi<ashish.priyadarshi@st.com>
+*
+* This file is licensed under the terms of the GNU General Public
+* License version 2. This program is licensed "as is" without any
+* warranty of any kind, whether express or implied.
+*/
+
+#include <linux/dma-mapping.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+
+/* This is enough for the size of 800x480 (1.5 MB) */
+#define FRAMESIZE 0x00180000
+
+#ifdef CONFIG_FB_ARMCLCD_SHARP_LQ043T1DG01
+static struct clcd_panel sharp_LQ043T1DG01_in = {
+ .mode = {
+ .name = "Sharp LQ043T1DG01",
+ .refresh = 0,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = 48000,
+ .left_margin = 2,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .lower_margin = 2,
+ .hsync_len = 41,
+ .vsync_len = 11,
+ .sync = 0,/* FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT */
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ .width = -1,
+ .height = -1,
+ .tim2 = TIM2_IOE | TIM2_CLKSEL | 3,
+ .cntl = CNTL_LCDTFT | CNTL_BGR,
+ .bpp = 32,
+};
+#endif
+
+#ifdef CONFIG_FB_ARMCLCD_SAMSUNG_LMS700
+static struct clcd_panel samsung_LMS700_in = {
+ .mode = {
+ .name = "Samsung LMS700",
+ .refresh = 0,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 48000,
+ .left_margin = 16,
+ .right_margin = 8,
+ .upper_margin = 6,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ .width = -1,
+ .height = -1,
+ .tim2 = TIM2_CLKSEL,
+ .cntl = CNTL_LCDTFT | CNTL_BGR,
+ .bpp = 32,
+};
+#endif
+
+static int clcd_setup(struct clcd_fb *fb)
+{
+ dma_addr_t dma;
+
+ /* Detect which LCD panel is connected */
+#ifdef CONFIG_FB_ARMCLCD_SHARP_LQ043T1DG01
+ fb->panel = &sharp_LQ043T1DG01_in;
+#endif
+#ifdef CONFIG_FB_ARMCLCD_SAMSUNG_LMS700
+ fb->panel = &samsung_LMS700_in;
+#endif
+ fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, FRAMESIZE,
+ &dma, GFP_KERNEL);
+ if (!fb->fb.screen_base) {
+ printk(KERN_ERR "CLCD: unable to map framebuffer\n");
+ return -ENOMEM;
+ }
+ fb->fb.fix.smem_start = dma;
+ fb->fb.fix.smem_len = FRAMESIZE;
+
+ return 0;
+}
+
+static void clcd_remove(struct clcd_fb *fb)
+{
+ dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+ fb->fb.screen_base, fb->fb.fix.smem_start);
+}
+
+static int clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+ return dma_mmap_writecombine(&fb->dev->dev, vma,
+ fb->fb.screen_base,
+ fb->fb.fix.smem_start,
+ fb->fb.fix.smem_len);
+}
+
+struct clcd_board clcd_plat_data = {
+ .name = "spear-clcd",
+ .check = clcdfb_check,
+ .decode = clcdfb_decode,
+ .setup = clcd_setup,
+ .mmap = clcd_mmap,
+ .remove = clcd_remove,
+};
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d916ac0..bf6632d 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -324,10 +324,22 @@ config FB_ARMCLCD
choice
- depends on FB_ARMCLCD && (ARCH_LH7A40X || ARCH_LH7952X)
+ depends on FB_ARMCLCD && (ARCH_LH7A40X || ARCH_LH7952X || ARCH_SPEAR6XX || MACH_SPEAR300 || MACH_SPEAR320)
prompt "LCD Panel"
default FB_ARMCLCD_SHARP_LQ035Q7DB02
+config FB_ARMCLCD_SHARP_LQ043T1DG01
+ bool "SHARP LQ043T1DG01 CLCD 4.2\" TFT(480x272)"
+ help
+ This is an implementation of the Sharp LQ043T1DG01, a 4.2"
+ color TFT panel. The native resolution is 480x272.
+
+config FB_ARMCLCD_SAMSUNG_LMS700
+ bool "SAMSUNG CLCD 7\" TFT(800x480)"
+ help
+ This is an implementation of the Samsung LMS700, a 7"
+ color TFT panel. The native resolution is 800x480.
+
config FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
bool "LogicPD LCD 3.5\" QVGA w/HRTFT IC"
help
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 12/62] ST SPEAr: Updating Clock Support
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (10 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 11/62] ST SPEAr: Adding support for CLCD on SPEAr3xx/6xx Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 13/62] ST SPEAr: Adding Debugfs support on clock framework Viresh Kumar
` (49 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
- Adding support for divisor per parent clock
- Adding ENABLED_ON_INIT feature in clk
- Adding clk_set_rate
- Simplified clk_recalc functions
- Added/updating clock definitions
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear13xx/clock.c | 621 +++++++++++++++++++-
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 101 ++--
arch/arm/mach-spear3xx/clock.c | 431 ++++++++++++--
arch/arm/mach-spear3xx/include/mach/misc_regs.h | 5 +-
arch/arm/mach-spear6xx/clock.c | 331 ++++++++---
arch/arm/mach-spear6xx/include/mach/misc_regs.h | 5 +-
arch/arm/plat-spear/clock.c | 675 +++++++++++++++++-----
arch/arm/plat-spear/include/plat/clock.h | 94 +++-
8 files changed, 1888 insertions(+), 375 deletions(-)
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
index 722f634..c39389e 100644
--- a/arch/arm/mach-spear13xx/clock.c
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -53,10 +53,10 @@ static struct clk rtc_clk = {
static struct pclk_info pll_pclk_info[] = {
{
.pclk = &osc1_24m_clk,
- .pclk_mask = OSC_24M_MASK,
+ .pclk_val = OSC_24M_VAL,
}, {
.pclk = &osc3_25m_clk,
- .pclk_mask = OSC_25M_MASK,
+ .pclk_val = OSC_25M_VAL,
},
};
@@ -88,16 +88,45 @@ static struct pll_clk_config pll1_config = {
.masks = &pll_masks,
};
+/* pll rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll_rtbl[] = {
+ /* PCLK 24MHz */
+ {.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
+ {.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
+ {.mode = 0, .m = 0xFA, .n = 0x06, .p = 0x1}, /* 1000 MHz */
+};
+
/* pll1 clock */
static struct clk pll1_clk = {
+ .flags = ENABLED_ON_INIT,
.pclk_sel = &pll_pclk_sel,
.pclk_sel_shift = PLL1_CLK_SHIFT,
.en_reg = PLL1_CTR,
.en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
.private_data = &pll1_config,
};
+/* pll1div2 clock */
+static struct clk pll1div2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* pll1div4 clock */
+static struct clk pll1div4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 4,
+ .recalc = &follow_parent,
+};
+
/* pll2 configuration structure */
static struct pll_clk_config pll2_config = {
.mode_reg = PLL2_CTR,
@@ -111,7 +140,10 @@ static struct clk pll2_clk = {
.pclk_sel_shift = PLL2_CLK_SHIFT,
.en_reg = PLL2_CTR,
.en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
.private_data = &pll2_config,
};
@@ -128,7 +160,10 @@ static struct clk pll3_clk = {
.pclk_sel_shift = PLL3_CLK_SHIFT,
.en_reg = PLL3_CTR,
.en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
.private_data = &pll3_config,
};
@@ -139,12 +174,24 @@ static struct pll_clk_config pll4_config = {
.masks = &pll_masks,
};
+/* pll4 rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll4_rtbl[] = {
+ {.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
+ {.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
+ {.mode = 0, .m = 0xFA, .n = 0x06, .p = 0x1}, /* 1000 MHz */
+};
+
/* pll4 (DDR) clock */
static struct clk pll4_clk = {
+ .flags = ENABLED_ON_INIT,
.pclk = &osc1_24m_clk,
.en_reg = PLL4_CTR,
.en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll4_rtbl, ARRAY_SIZE(pll4_rtbl), 3},
.private_data = &pll4_config,
};
@@ -192,10 +239,10 @@ static struct clk apb_clk = {
static struct pclk_info gpt_pclk_info[] = {
{
.pclk = &osc1_24m_clk,
- .pclk_mask = GPT_OSC24_MASK,
+ .pclk_val = GPT_OSC24_VAL,
}, {
.pclk = &apb_clk,
- .pclk_mask = GPT_APB_MASK,
+ .pclk_val = GPT_APB_VAL,
},
};
@@ -246,15 +293,8 @@ static struct clk gpt3_clk = {
/* watch dog timer clock */
static struct clk wdt_clk = {
.flags = ALWAYS_ENABLED,
- .pclk = &apb_clk,
- .recalc = &follow_parent,
-};
-
-/* smi clock */
-static struct clk smi_clk = {
- .pclk = &ahb_clk,
- .en_reg = PERIP1_CLK_ENB,
- .en_reg_bit = SMI_CLK_ENB,
+ .pclk = &cpu_clk,
+ .div_factor = 2,
.recalc = &follow_parent,
};
@@ -270,22 +310,42 @@ static struct aux_clk_masks aux_masks = {
.yscale_sel_shift = AUX_YSCALE_SHIFT,
};
+/* clocks derived multiple parents (pll1, pll5, synthesizers or others) */
/* uart configurations */
-static struct aux_clk_config uart_config = {
+static struct aux_clk_config uart_synth_config = {
.synth_reg = UART_CLK_SYNT,
.masks = &aux_masks,
};
-/* clocks derived from pll1 or pll5 */
+/* aux rate configuration table, in ascending order of rates */
+struct aux_rate_tbl aux_rtbl[] = {
+ /* For PLL1div2 = 500 MHz */
+ {.xscale = 1, .yscale = 6, .eq = 1}, /* 83 MHz */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* 125 MHz */
+ {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
+};
+
+/* uart synth clock */
+static struct clk uart_synth_clk = {
+ .en_reg = UART_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .private_data = &uart_synth_config,
+};
+
/* uart parents */
static struct pclk_info uart_pclk_info[] = {
{
.pclk = &pll5_clk,
- .pclk_mask = AUX_CLK_PLL5_MASK,
+ .pclk_val = AUX_CLK_PLL5_VAL,
}, {
- .pclk = &pll1_clk,
- .pclk_mask = AUX_CLK_PLL1_MASK,
- .scalable = 1,
+ .pclk = &uart_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
},
};
@@ -303,10 +363,469 @@ static struct clk uart_clk = {
.en_reg_bit = UART_CLK_ENB,
.pclk_sel = &uart_pclk_sel,
.pclk_sel_shift = UART_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* sdhci configurations */
+static struct aux_clk_config sdhci_synth_config = {
+ .synth_reg = SDHCI_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* sdhci synth clock */
+static struct clk sdhci_synth_clk = {
+ .en_reg = SDHCI_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
+ .private_data = &sdhci_synth_config,
+};
+
+/* sdhci clock */
+static struct clk sdhci_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SDHCI_CLK_ENB,
+ .pclk = &sdhci_synth_clk,
+ .recalc = &follow_parent,
+};
+
+/* cfxd configurations */
+static struct aux_clk_config cfxd_synth_config = {
+ .synth_reg = CFXD_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* cfxd synth clock */
+static struct clk cfxd_synth_clk = {
+ .en_reg = CFXD_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
+ .private_data = &cfxd_synth_config,
+};
+
+/* cfxd clock */
+static struct clk cfxd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CFXD_CLK_ENB,
+ .pclk = &cfxd_synth_clk,
+ .recalc = &follow_parent,
+};
+
+/* C3 clk configurations */
+static struct aux_clk_config c3_synth_config = {
+ .synth_reg = C3_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* c3 synth clock */
+static struct clk c3_synth_clk = {
+ .en_reg = C3_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .private_data = &c3_synth_config,
+};
+
+/* c3 parents */
+static struct pclk_info c3_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &c3_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* c3 parent select structure */
+static struct pclk_sel c3_pclk_sel = {
+ .pclk_info = c3_pclk_info,
+ .pclk_count = ARRAY_SIZE(c3_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = C3_CLK_MASK,
+};
+
+/* c3 clock */
+static struct clk c3_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = C3_CLK_ENB,
+ .pclk_sel = &c3_pclk_sel,
+ .pclk_sel_shift = C3_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gmac phy clk configurations */
+static struct aux_clk_config gmac_phy_synth_config = {
+ .synth_reg = GMAC_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* gmii external pad clock for phy operation */
+static struct clk gmii_txclk125_pad = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 125000000,
+};
+
+/* gmac phy set of input clks*/
+static struct pclk_info gmac_phy_input_pclk_info[] = {
+ {
+ .pclk = &gmii_txclk125_pad,
+ .pclk_val = GMAC_PHY_PAD_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = GMAC_PHY_PLL2_VAL,
+ }, {
+ .pclk = &osc3_25m_clk,
+ .pclk_val = GMAC_PHY_OSC3_VAL,
+ },
+};
+
+static struct pclk_sel gmac_phy_input_pclk_sel = {
+ .pclk_info = gmac_phy_input_pclk_info,
+ .pclk_count = ARRAY_SIZE(gmac_phy_input_pclk_info),
+ .pclk_sel_reg = GMAC_CLK_CFG,
+ .pclk_sel_mask = GMAC_PHY_INPUT_CLK_MASK,
+};
+
+static struct clk gmac_phy_input_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gmac_phy_input_pclk_sel,
+ .pclk_sel_shift = GMAC_PHY_INPUT_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gmac rate configuration table, in ascending order of rates */
+struct aux_rate_tbl gmac_rtbl[] = {
+ /* For gmac phy input clk */
+ {.xscale = 1, .yscale = 6, .eq = 1}, /* divided by 6 */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* divided by 4 */
+ {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
+};
+
+static struct clk gmac_phy_synth_clk = {
+ .en_reg = GMAC_CLK_CFG,
+ .en_reg_bit = GMAC_PHY_SYNT_ENB,
+ .pclk = &gmac_phy_input_clk,
+ .calc_rate = &aux_calc_rate,
.recalc = &aux_clk_recalc,
- .private_data = &uart_config,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {gmac_rtbl, ARRAY_SIZE(gmac_rtbl), 0},
+ .private_data = &gmac_phy_synth_config,
+};
+
+/* gmac phy parents */
+static struct pclk_info gmac_phy_pclk_info[] = {
+ {
+ .pclk = &gmac_phy_input_clk,
+ .pclk_val = 0,
+ }, {
+ .pclk = &gmac_phy_synth_clk,
+ .pclk_val = 1,
+ }
+};
+
+/* gmac phy parent select structure */
+static struct pclk_sel gmac_phy_pclk_sel = {
+ .pclk_info = gmac_phy_pclk_info,
+ .pclk_count = ARRAY_SIZE(gmac_phy_pclk_info),
+ .pclk_sel_reg = GMAC_CLK_CFG,
+ .pclk_sel_mask = GMAC_PHY_CLK_MASK,
+};
+
+/* gmac phy clock */
+static struct clk gmac_phy_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gmac_phy_pclk_sel,
+ .pclk_sel_shift = GMAC_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* clcd synthesizers masks */
+static struct clcd_synth_masks clcd_masks = {
+ .div_factor_mask = CLCD_SYNT_DIV_FACTOR_MASK,
+ .div_factor_shift = CLCD_SYNT_DIV_FACTOR_SHIFT,
+};
+
+static struct clcd_clk_config clcd_synth_config = {
+ .synth_reg = CLCD_CLK_SYNT,
+ .masks = &clcd_masks,
+};
+
+/* clcd synth parents */
+static struct pclk_info clcd_synth_pclk_info[] = {
+ {
+ .pclk = &pll1div4_clk,
+ .pclk_val = CLCD_SYNT_PLL1_DIV4_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = CLCD_SYNT_PLL2_VAL,
+ },
+};
+
+/* clcd synth parent select structure */
+static struct pclk_sel clcd_synth_pclk_sel = {
+ .pclk_info = clcd_synth_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_synth_pclk_info),
+ .pclk_sel_reg = PLL_CFG,
+ .pclk_sel_mask = CLCD_SYNT_CLK_MASK,
+};
+
+/* clcd rate configuration table, in ascending order of rates */
+struct clcd_rate_tbl clcd_rtbl[] = {
+ /* For pll1div4 = 250 MHz */
+ {.div = 0x4000}, /* 62.5 MHz */
+ {.div = 0x2000}, /* 125 MHz */
+};
+
+/* clcd synth clock */
+static struct clk clcd_synth_clk = {
+ .en_reg = CLCD_CLK_SYNT,
+ .en_reg_bit = CLCD_SYNT_ENB,
+ .pclk_sel = &clcd_synth_pclk_sel,
+ .pclk_sel_shift = CLCD_SYNT_CLK_SHIFT,
+ .calc_rate = &clcd_calc_rate,
+ .recalc = &clcd_clk_recalc,
+ .set_rate = &clcd_clk_set_rate,
+ .rate_config = {clcd_rtbl, ARRAY_SIZE(clcd_rtbl), 1},
+ .private_data = &clcd_synth_config,
+};
+
+/* clcd clock parents */
+static struct pclk_info clcd_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &clcd_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* clcd parent select structure */
+static struct pclk_sel clcd_pclk_sel = {
+ .pclk_info = clcd_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = CLCD_CLK_MASK,
+};
+
+/* clcd clock */
+static struct clk clcd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CLCD_CLK_ENB,
+ .pclk_sel = &clcd_pclk_sel,
+ .pclk_sel_shift = CLCD_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from ahb clk */
+
+/* i2c clock */
+static struct clk i2c_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2C_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* dma clock */
+static struct clk dma0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk dma1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* jpeg clock */
+static struct clk jpeg_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = JPEG_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gmac clock */
+static struct clk gmac_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GMAC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* fsmc clock */
+static struct clk fsmc_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = FSMC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* smi clock */
+static struct clk smi_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SMI_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* uhc0 clock */
+static struct clk uhci0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UHC0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* uhc1 clock */
+static struct clk uhci1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UHC1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* usbd clock */
+static struct clk usbd_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* pci clocks */
+static struct clk pcie0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk pcie1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE1_CLK_ENB,
+ .recalc = &follow_parent,
};
+static struct clk pcie2_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* sysram clocks */
+static struct clk sysram0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SYSRAM0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk sysram1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SYSRAM1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from apb clk */
+/* adc clock */
+static struct clk adc_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = ADC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ssp clock */
+static struct clk ssp_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SSP_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* i2s0 clock */
+static struct clk i2s0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2S0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* i2s1 clock */
+static struct clk i2s1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2S1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* keyboard clock */
+static struct clk kbd_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = KBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* spear1300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1300
+
+#endif
+
+/* spear1310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1310
+/* can0 clock */
+static struct clk can0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* can1 clock */
+static struct clk can1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+#endif
+
/* array of all spear 13xx clock lookups */
static struct clk_lookup spear_clk_lookups[] = {
/* root clks */
@@ -315,7 +834,7 @@ static struct clk_lookup spear_clk_lookups[] = {
{.con_id = "osc3_25m_clk", .clk = &osc3_25m_clk},
/* clock derived from 32 KHz osc clk */
- {.dev_id = "rtc", .clk = &rtc_clk},
+ {.dev_id = "rtc-spear", .clk = &rtc_clk},
/* clock derived from 24/25 MHz osc1/osc3 clk */
{.con_id = "pll1_clk", .clk = &pll1_clk},
@@ -328,18 +847,68 @@ static struct clk_lookup spear_clk_lookups[] = {
/* clock derived from pll1 clk */
{.con_id = "cpu_clk", .clk = &cpu_clk},
{.con_id = "ahb_clk", .clk = &ahb_clk},
- { .con_id = "apb_clk", .clk = &apb_clk},
+ {.con_id = "apb_clk", .clk = &apb_clk},
+
+ /* synthesizers/prescaled clocks */
+ {.con_id = "pll1div2_clk", .clk = &pll1div2_clk},
+ {.con_id = "pll1div4_clk", .clk = &pll1div4_clk},
+ {.con_id = "c3_synth_clk", .clk = &c3_synth_clk},
+ {.con_id = "gmii_txclk123_pad_clk", .clk = &gmii_txclk125_pad},
+ {.con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
+ {.con_id = "uart_synth_clk", .clk = &uart_synth_clk},
+ {.con_id = "sdhci_synth_clk", .clk = &sdhci_synth_clk},
+ {.con_id = "cfxd_synth_clk", .clk = &cfxd_synth_clk},
+ {.con_id = "gmac_phy_input_clk", .clk = &gmac_phy_input_clk},
+ {.con_id = "gmac_phy_synth_clk", .clk = &gmac_phy_synth_clk},
+ {.con_id = "gmac_phy_clk", .clk = &gmac_phy_clk},
/* clocks having multiple parent source from above clocks */
- {.dev_id = "uart", .clk = &uart_clk},
+ {.dev_id = "clcd", .clk = &clcd_clk},
{.dev_id = "gpt0", .clk = &gpt0_clk},
{.dev_id = "gpt1", .clk = &gpt1_clk},
{.dev_id = "gpt2", .clk = &gpt2_clk},
{.dev_id = "gpt3", .clk = &gpt3_clk},
+ {.dev_id = "uart", .clk = &uart_clk},
- /* clock derived from ahb/apb clk */
- { .dev_id = "smi", .clk = &smi_clk},
- { .dev_id = "wdt", .clk = &wdt_clk},
+ /* clock derived from ahb clk */
+ {.dev_id = "smi", .clk = &smi_clk},
+ {.con_id = "usbh.0_clk", .clk = &uhci0_clk},
+ {.con_id = "usbh.1_clk", .clk = &uhci1_clk},
+ {.dev_id = "usbd", .clk = &usbd_clk},
+ {.dev_id = "i2c_designware.0", .clk = &i2c_clk},
+ {.dev_id = "dma0", .clk = &dma0_clk},
+ {.dev_id = "dma1", .clk = &dma1_clk},
+ {.dev_id = "jpeg", .clk = &jpeg_clk},
+ {.dev_id = "gmac", .clk = &gmac_clk},
+ {.dev_id = "c3", .clk = &c3_clk},
+ {.dev_id = "pcie0", .clk = &pcie0_clk},
+ {.dev_id = "pcie1", .clk = &pcie1_clk},
+ {.dev_id = "pcie2", .clk = &pcie2_clk},
+ {.dev_id = "cfxd", .clk = &cfxd_clk},
+ {.dev_id = "sdhci", .clk = &sdhci_clk},
+ {.con_id = "fsmc", .clk = &fsmc_clk},
+ {.dev_id = "sysram0", .clk = &sysram0_clk},
+ {.dev_id = "sysram1", .clk = &sysram1_clk},
+
+ /* clock derived from apb clk */
+ {.dev_id = "i2s0", .clk = &i2s0_clk},
+ {.dev_id = "i2s1", .clk = &i2s1_clk},
+ {.dev_id = "adc", .clk = &adc_clk},
+ {.dev_id = "ssp-pl022", .clk = &ssp_clk},
+ {.dev_id = "gpio0", .clk = &gpio0_clk},
+ {.dev_id = "gpio1", .clk = &gpio1_clk},
+ {.dev_id = "keyboard", .clk = &kbd_clk},
+ {.dev_id = "wdt", .clk = &wdt_clk},
+
+ /* spear1300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1300
+#endif
+
+ /* spear1310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1310
+ {.dev_id = "c_can_platform.0", .clk = &can0_clk},
+ {.dev_id = "c_can_platform.1", .clk = &can1_clk},
+#endif
};
void __init clk_init(void)
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
index 1f6028f..a8a1119 100644
--- a/arch/arm/mach-spear13xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -36,12 +36,16 @@
/* PLL related registers and bit values */
#define PLL_CFG ((unsigned int *)(MISC_BASE + 0x210))
/* PLL_CFG bit values */
- #define OSC_24M_MASK 0
- #define OSC_25M_MASK 1
- #define PLL_CLK_MASK 3
- #define PLL1_CLK_SHIFT 20
- #define PLL2_CLK_SHIFT 22
- #define PLL3_CLK_SHIFT 24
+ #define OSC_24M_VAL 0
+ #define OSC_25M_VAL 1
+ #define PLL_CLK_MASK 3
+ #define PLL1_CLK_SHIFT 20
+ #define PLL2_CLK_SHIFT 22
+ #define PLL3_CLK_SHIFT 24
+ #define CLCD_SYNT_PLL1_DIV4_VAL 0
+ #define CLCD_SYNT_PLL2_VAL 1
+ #define CLCD_SYNT_CLK_MASK 1
+ #define CLCD_SYNT_CLK_SHIFT 31
#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x214))
#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x218))
@@ -77,30 +81,53 @@
#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x244))
/* PERIP_CLK_CFG bit values */
- #define GPT_OSC24_MASK 0
- #define GPT_APB_MASK 1
- #define GPT_CLK_MASK 1
- #define GPT0_CLK_SHIFT 8
- #define GPT1_CLK_SHIFT 9
- #define GPT2_CLK_SHIFT 12
- #define GPT3_CLK_SHIFT 13
- #define AUX_CLK_PLL1_MASK 1
- #define AUX_CLK_PLL5_MASK 0
+ #define GPT_OSC24_VAL 0
+ #define GPT_APB_VAL 1
+ #define GPT_CLK_MASK 1
+ #define GPT0_CLK_SHIFT 8
+ #define GPT1_CLK_SHIFT 9
+ #define GPT2_CLK_SHIFT 12
+ #define GPT3_CLK_SHIFT 13
+ #define AUX_CLK_PLL5_VAL 0
+ #define AUX_CLK_SYNT_VAL 1
#define UART_CLK_MASK 1
#define UART_CLK_SHIFT 4
+ #define CLCD_PLL5_VAL 0
+ #define CLCD_SYNT_MASK 1
+ #define CLCD_CLK_MASK 3
+ #define CLCD_CLK_SHIFT 2
+ #define C3_CLK_MASK 1
+ #define C3_CLK_SHIFT 1
#define GMAC_CLK_CFG ((unsigned int *)(MISC_BASE + 0x248))
-#define C3_CLK_SYNTH ((unsigned int *)(MISC_BASE + 0x24c))
+
+ #define GMAC_PHY_PAD_VAL 0
+ #define GMAC_PHY_PLL2_VAL 1
+ #define GMAC_PHY_OSC3_VAL 2
+ #define GMAC_PHY_INPUT_CLK_MASK 3
+ #define GMAC_PHY_INPUT_CLK_SHIFT 1
+ #define GMAC_PHY_SYNT_ENB 3
+ #define GMAC_PHY_CLK_MASK 1
+ #define GMAC_PHY_CLK_SHIFT 3
+ #define GMAC_PHY_SYNT_ENB_VAL 4
+
+#define C3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x24c))
#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x250))
+ /* CLCD synth reg masks */
+ #define CLCD_SYNT_ENB 31
+ #define CLCD_SYNT_DIV_FACTOR_MASK 0x1ffff
+ #define CLCD_SYNT_DIV_FACTOR_SHIFT 0
+
#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x254))
#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x258))
-#define MCIF_SD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x25c))
-#define MCIF_CFXD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x260))
+#define SDHCI_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x25c))
+#define CFXD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x260))
#define RAS_CLK_SYNT0 ((unsigned int *)(MISC_BASE + 0x264))
#define RAS_CLK_SYNT1 ((unsigned int *)(MISC_BASE + 0x268))
#define RAS_CLK_SYNT2 ((unsigned int *)(MISC_BASE + 0x26c))
#define RAS_CLK_SYNT3 ((unsigned int *)(MISC_BASE + 0x270))
/* aux clk synthesizer register masks */
+ #define AUX_SYNT_ENB 31
#define AUX_EQ_SEL_SHIFT 30
#define AUX_EQ_SEL_MASK 1
#define AUX_EQ1_SEL 0
@@ -114,32 +141,32 @@
/* PERIP1_CLK_ENB register masks */
#define BUS_CLK_ENB 0
#define SYSROM_CLK_ENB 1
- #define AORAM_CLK_ENB 2
- #define SYSRAM_CLK_ENB 3
+ #define SYSRAM1_CLK_ENB 2
+ #define SYSRAM0_CLK_ENB 3
#define FSMC_CLK_ENB 4
#define SMI_CLK_ENB 5
- #define SD_CLK_ENB 6
- #define CF_XD_CLK_ENB 7
- #define GETH_CLK_ENB 8
+ #define SDHCI_CLK_ENB 6
+ #define CFXD_CLK_ENB 7
+ #define GMAC_CLK_ENB 8
#define UHC0_CLK_ENB 9
#define UHC1_CLK_ENB 10
- #define UDC_UPD_CLK_ENB 11
- #define PCI0_CLK_ENB 12
- #define PCI1_CLK_ENB 13
- #define PCI2_CLK_ENB 14
+ #define USBD_CLK_ENB 11
+ #define PCIE0_CLK_ENB 12
+ #define PCIE1_CLK_ENB 13
+ #define PCIE2_CLK_ENB 14
#define UART_CLK_ENB 15
#define SSP_CLK_ENB 17
#define I2C_CLK_ENB 18
- #define I2S_SLV_CLK_ENB 19
- #define I2S_MST_CLK_ENB 20
+ #define I2S0_CLK_ENB 19
+ #define I2S1_CLK_ENB 20
#define GPT0_CLK_ENB 21
#define GPT1_CLK_ENB 22
- #define GPIOA_CLK_ENB 23
- #define GPIOB_CLK_ENB 24
+ #define GPIO0_CLK_ENB 23
+ #define GPIO1_CLK_ENB 24
#define DMA0_CLK_ENB 25
#define DMA1_CLK_ENB 26
#define CLCD_CLK_ENB 27
- #define JPEGC_CLK_ENB 28
+ #define JPEG_CLK_ENB 28
#define C3_CLK_ENB 29
#define ADC_CLK_ENB 30
#define RTC_CLK_ENB 31
@@ -219,11 +246,11 @@
#define THSENS_CFG ((unsigned int *)(MISC_BASE + 0x6c4))
/* Compensation Configuration Registers */
-#define COMP_1V8_2V5_3V3__1_CFG ((unsigned int *)(MISC_BASE + 0x700))
-#define COMP_1V8_2V5_3V3__2_CFG ((unsigned int *)(MISC_BASE + 0x704))
-#define COMP_3V3_1_CFG ((unsigned int *)(MISC_BASE + 0x708))
-#define COMP_3V3_2_CFG ((unsigned int *)(MISC_BASE + 0x70c))
-#define COMP_DDR_CFG ((unsigned int *)(MISC_BASE + 0x710))
+#define COMP_1V8_2V5_3V3__1_CFG ((unsigned int *)(MISC_BASE + 0x700))
+#define COMP_1V8_2V5_3V3__2_CFG ((unsigned int *)(MISC_BASE + 0x704))
+#define COMP_3V3_1_CFG ((unsigned int *)(MISC_BASE + 0x708))
+#define COMP_3V3_2_CFG ((unsigned int *)(MISC_BASE + 0x70c))
+#define COMP_DDR_CFG ((unsigned int *)(MISC_BASE + 0x710))
/* OTP Programming Registers */
#define OTP_PROG_CTR ((unsigned int *)(MISC_BASE + 0x800))
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 7ea8749..8ae4ad0 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -60,12 +60,22 @@ static struct pll_clk_config pll1_config = {
.masks = &pll1_masks,
};
+/* pll rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll_rtbl[] = {
+ {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
+};
+
/* PLL1 clock */
static struct clk pll1_clk = {
+ .flags = ENABLED_ON_INIT,
.pclk = &osc_24m_clk,
.en_reg = PLL1_CTR,
.en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
.private_data = &pll1_config,
};
@@ -103,11 +113,22 @@ static struct bus_clk_config ahb_config = {
.masks = &ahb_masks,
};
+/* ahb rate configuration table, in ascending order of rates */
+struct bus_rate_tbl bus_rtbl[] = {
+ {.div = 3}, /* == parent divided by 4 */
+ {.div = 2}, /* == parent divided by 3 */
+ {.div = 1}, /* == parent divided by 2 */
+ {.div = 0}, /* == parent divided by 1 */
+};
+
/* ahb clock */
static struct clk ahb_clk = {
.flags = ALWAYS_ENABLED,
.pclk = &pll1_clk,
+ .calc_rate = &bus_calc_rate,
.recalc = &bus_clk_recalc,
+ .set_rate = &bus_clk_set_rate,
+ .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
.private_data = &ahb_config,
};
@@ -123,22 +144,40 @@ static struct aux_clk_masks aux_masks = {
.yscale_sel_shift = AUX_YSCALE_SHIFT,
};
-/* uart configurations */
-static struct aux_clk_config uart_config = {
+/* uart synth configurations */
+static struct aux_clk_config uart_synth_config = {
.synth_reg = UART_CLK_SYNT,
.masks = &aux_masks,
};
+/* aux rate configuration table, in ascending order of rates */
+struct aux_rate_tbl aux_rtbl[] = {
+ /* For PLL1 = 332 MHz */
+ {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
+};
+
+/* uart synth clock */
+static struct clk uart_synth_clk = {
+ .en_reg = UART_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+ .private_data = &uart_synth_config,
+};
+
/* uart parents */
static struct pclk_info uart_pclk_info[] = {
{
- .pclk = &pll1_clk,
- .pclk_mask = AUX_CLK_PLL1_MASK,
- .scalable = 1,
+ .pclk = &uart_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
}, {
.pclk = &pll3_48m_clk,
- .pclk_mask = AUX_CLK_PLL3_MASK,
- .scalable = 0,
+ .pclk_val = AUX_CLK_PLL3_VAL,
},
};
@@ -156,26 +195,35 @@ static struct clk uart_clk = {
.en_reg_bit = UART_CLK_ENB,
.pclk_sel = &uart_pclk_sel,
.pclk_sel_shift = UART_CLK_SHIFT,
- .recalc = &aux_clk_recalc,
- .private_data = &uart_config,
+ .recalc = &follow_parent,
};
/* firda configurations */
-static struct aux_clk_config firda_config = {
+static struct aux_clk_config firda_synth_config = {
.synth_reg = FIRDA_CLK_SYNT,
.masks = &aux_masks,
};
+/* firda synth clock */
+static struct clk firda_synth_clk = {
+ .en_reg = FIRDA_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+ .private_data = &firda_synth_config,
+};
+
/* firda parents */
static struct pclk_info firda_pclk_info[] = {
{
- .pclk = &pll1_clk,
- .pclk_mask = AUX_CLK_PLL1_MASK,
- .scalable = 1,
+ .pclk = &firda_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
}, {
.pclk = &pll3_48m_clk,
- .pclk_mask = AUX_CLK_PLL3_MASK,
- .scalable = 0,
+ .pclk_val = AUX_CLK_PLL3_VAL,
},
};
@@ -193,84 +241,155 @@ static struct clk firda_clk = {
.en_reg_bit = FIRDA_CLK_ENB,
.pclk_sel = &firda_pclk_sel,
.pclk_sel_shift = FIRDA_CLK_SHIFT,
- .recalc = &aux_clk_recalc,
- .private_data = &firda_config,
+ .recalc = &follow_parent,
+};
+
+/* gpt synthesizer masks */
+static struct gpt_clk_masks gpt_masks = {
+ .mscale_sel_mask = GPT_MSCALE_MASK,
+ .mscale_sel_shift = GPT_MSCALE_SHIFT,
+ .nscale_sel_mask = GPT_NSCALE_MASK,
+ .nscale_sel_shift = GPT_NSCALE_SHIFT,
+};
+
+/* gpt rate configuration table, in ascending order of rates */
+struct gpt_rate_tbl gpt_rtbl[] = {
+ /* For pll1 = 332 MHz */
+ {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
+ {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
+ {.mscale = 1, .nscale = 0}, /* 83 MHz */
+};
+
+/* gpt0 synth clk config*/
+static struct gpt_clk_config gpt0_synth_config = {
+ .synth_reg = PRSC1_CLK_CFG,
+ .masks = &gpt_masks,
+};
+
+/* gpt synth clock */
+static struct clk gpt0_synth_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .calc_rate = &gpt_calc_rate,
+ .recalc = &gpt_clk_recalc,
+ .set_rate = &gpt_clk_set_rate,
+ .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+ .private_data = &gpt0_synth_config,
};
/* gpt parents */
-static struct pclk_info gpt_pclk_info[] = {
+static struct pclk_info gpt0_pclk_info[] = {
{
- .pclk = &pll1_clk,
- .pclk_mask = AUX_CLK_PLL1_MASK,
- .scalable = 1,
+ .pclk = &gpt0_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
}, {
.pclk = &pll3_48m_clk,
- .pclk_mask = AUX_CLK_PLL3_MASK,
- .scalable = 0,
+ .pclk_val = AUX_CLK_PLL3_VAL,
},
};
/* gpt parent select structure */
-static struct pclk_sel gpt_pclk_sel = {
- .pclk_info = gpt_pclk_info,
- .pclk_count = ARRAY_SIZE(gpt_pclk_info),
+static struct pclk_sel gpt0_pclk_sel = {
+ .pclk_info = gpt0_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
.pclk_sel_reg = PERIP_CLK_CFG,
.pclk_sel_mask = GPT_CLK_MASK,
};
-/* gpt synthesizer masks */
-static struct gpt_clk_masks gpt_masks = {
- .mscale_sel_mask = GPT_MSCALE_MASK,
- .mscale_sel_shift = GPT_MSCALE_SHIFT,
- .nscale_sel_mask = GPT_NSCALE_MASK,
- .nscale_sel_shift = GPT_NSCALE_SHIFT,
+/* gpt0 timer clock */
+static struct clk gpt0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gpt0_pclk_sel,
+ .pclk_sel_shift = GPT0_CLK_SHIFT,
+ .recalc = &follow_parent,
};
-/* gpt0 configurations */
-static struct gpt_clk_config gpt0_config = {
- .synth_reg = PRSC1_CLK_CFG,
+/* gpt1 synth clk configurations */
+static struct gpt_clk_config gpt1_synth_config = {
+ .synth_reg = PRSC2_CLK_CFG,
.masks = &gpt_masks,
};
-/* gpt0 timer clock */
-static struct clk gpt0_clk = {
+/* gpt1 synth clock */
+static struct clk gpt1_synth_clk = {
.flags = ALWAYS_ENABLED,
- .pclk_sel = &gpt_pclk_sel,
- .pclk_sel_shift = GPT0_CLK_SHIFT,
+ .pclk = &pll1_clk,
+ .calc_rate = &gpt_calc_rate,
.recalc = &gpt_clk_recalc,
- .private_data = &gpt0_config,
+ .set_rate = &gpt_clk_set_rate,
+ .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+ .private_data = &gpt1_synth_config,
};
-/* gpt1 configurations */
-static struct gpt_clk_config gpt1_config = {
- .synth_reg = PRSC2_CLK_CFG,
- .masks = &gpt_masks,
+static struct pclk_info gpt1_pclk_info[] = {
+ {
+ .pclk = &gpt1_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_val = AUX_CLK_PLL3_VAL,
+ },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt1_pclk_sel = {
+ .pclk_info = gpt1_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
};
/* gpt1 timer clock */
static struct clk gpt1_clk = {
.en_reg = PERIP1_CLK_ENB,
.en_reg_bit = GPT1_CLK_ENB,
- .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel = &gpt1_pclk_sel,
.pclk_sel_shift = GPT1_CLK_SHIFT,
- .recalc = &gpt_clk_recalc,
- .private_data = &gpt1_config,
+ .recalc = &follow_parent,
};
-/* gpt2 configurations */
-static struct gpt_clk_config gpt2_config = {
+/* gpt2 synth clk configurations */
+static struct gpt_clk_config gpt2_synth_config = {
.synth_reg = PRSC3_CLK_CFG,
.masks = &gpt_masks,
};
+/* gpt1 synth clock */
+static struct clk gpt2_synth_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .calc_rate = &gpt_calc_rate,
+ .recalc = &gpt_clk_recalc,
+ .set_rate = &gpt_clk_set_rate,
+ .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+ .private_data = &gpt2_synth_config,
+};
+
+static struct pclk_info gpt2_pclk_info[] = {
+ {
+ .pclk = &gpt2_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_val = AUX_CLK_PLL3_VAL,
+ },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt2_pclk_sel = {
+ .pclk_info = gpt2_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
/* gpt2 timer clock */
static struct clk gpt2_clk = {
.en_reg = PERIP1_CLK_ENB,
.en_reg_bit = GPT2_CLK_ENB,
- .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel = &gpt2_pclk_sel,
.pclk_sel_shift = GPT2_CLK_SHIFT,
- .recalc = &gpt_clk_recalc,
- .private_data = &gpt2_config,
+ .recalc = &follow_parent,
};
/* clock derived from pll3 clk */
@@ -290,13 +409,6 @@ static struct clk usbd_clk = {
.recalc = &follow_parent,
};
-/* clcd clock */
-static struct clk clcd_clk = {
- .flags = ALWAYS_ENABLED,
- .pclk = &pll3_48m_clk,
- .recalc = &follow_parent,
-};
-
/* clock derived from ahb clk */
/* apb masks structure */
static struct bus_clk_masks apb_masks = {
@@ -314,7 +426,10 @@ static struct bus_clk_config apb_config = {
static struct clk apb_clk = {
.flags = ALWAYS_ENABLED,
.pclk = &ahb_clk,
+ .calc_rate = &bus_calc_rate,
.recalc = &bus_clk_recalc,
+ .set_rate = &bus_clk_set_rate,
+ .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
.private_data = &apb_config,
};
@@ -375,8 +490,17 @@ static struct clk adc_clk = {
.recalc = &follow_parent,
};
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+/* emi clock */
+static struct clk emi_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ahb_clk,
+ .recalc = &follow_parent,
+};
+#endif
+
/* ssp clock */
-static struct clk ssp_clk = {
+static struct clk ssp0_clk = {
.pclk = &apb_clk,
.en_reg = PERIP1_CLK_ENB,
.en_reg_bit = SSP_CLK_ENB,
@@ -393,6 +517,137 @@ static struct clk gpio_clk = {
static struct clk dummy_apb_pclk;
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
+ defined(CONFIG_MACH_SPEAR320)
+/* fsmc clock */
+static struct clk fsmc_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ahb_clk,
+ .recalc = &follow_parent,
+};
+#endif
+
+/* common clocks to spear310 and spear320 */
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+/* uart1 clock */
+static struct clk uart1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart2 clock */
+static struct clk uart2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+
+/* common clocks to spear300 and spear320 */
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
+/* clcd clock */
+static struct clk clcd_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll3_48m_clk,
+ .recalc = &follow_parent,
+};
+
+/* sdhci clock */
+static struct clk sdhci_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ahb_clk,
+ .recalc = &follow_parent,
+};
+#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
+
+/* spear300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR300
+/* gpio1 clock */
+static struct clk gpio1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* keyboard clock */
+static struct clk kbd_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+#endif
+
+/* spear310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR310
+/* uart3 clock */
+static struct clk uart3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart4 clock */
+static struct clk uart4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart5 clock */
+static struct clk uart5_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+#endif
+
+/* spear320 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR320
+/* can0 clock */
+static struct clk can0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* can1 clock */
+static struct clk can1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* i2c1 clock */
+static struct clk i2c1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ahb_clk,
+ .recalc = &follow_parent,
+};
+
+/* ssp1 clock */
+static struct clk ssp1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* ssp2 clock */
+static struct clk ssp2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* pwm clock */
+static struct clk pwm_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+#endif
+
/* array of all spear 3xx clock lookups */
static struct clk_lookup spear_clk_lookups[] = {
{ .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
@@ -400,7 +655,7 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
{ .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
/* clock derived from 32 KHz osc clk */
- { .dev_id = "rtc", .clk = &rtc_clk},
+ { .dev_id = "rtc-spear", .clk = &rtc_clk},
/* clock derived from 24 MHz osc clk */
{ .con_id = "pll1_clk", .clk = &pll1_clk},
{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
@@ -408,18 +663,22 @@ static struct clk_lookup spear_clk_lookups[] = {
/* clock derived from pll1 clk */
{ .con_id = "cpu_clk", .clk = &cpu_clk},
{ .con_id = "ahb_clk", .clk = &ahb_clk},
+ { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
+ { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
+ { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
+ { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk},
+ { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
{ .dev_id = "uart", .clk = &uart_clk},
{ .dev_id = "firda", .clk = &firda_clk},
{ .dev_id = "gpt0", .clk = &gpt0_clk},
{ .dev_id = "gpt1", .clk = &gpt1_clk},
{ .dev_id = "gpt2", .clk = &gpt2_clk},
/* clock derived from pll3 clk */
- { .dev_id = "usbh", .clk = &usbh_clk},
+ { .con_id = "usbh_clk", .clk = &usbh_clk},
{ .dev_id = "usbd", .clk = &usbd_clk},
- { .dev_id = "clcd", .clk = &clcd_clk},
/* clock derived from ahb clk */
{ .con_id = "apb_clk", .clk = &apb_clk},
- { .dev_id = "i2c", .clk = &i2c_clk},
+ { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
{ .dev_id = "dma", .clk = &dma_clk},
{ .dev_id = "jpeg", .clk = &jpeg_clk},
{ .dev_id = "gmac", .clk = &gmac_clk},
@@ -427,8 +686,50 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "c3", .clk = &c3_clk},
/* clock derived from apb clk */
{ .dev_id = "adc", .clk = &adc_clk},
- { .dev_id = "ssp", .clk = &ssp_clk},
+ { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
{ .dev_id = "gpio", .clk = &gpio_clk},
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+ { .dev_id = "physmap-flash", .clk = &emi_clk},
+#endif
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
+ defined(CONFIG_MACH_SPEAR320)
+ { .con_id = "fsmc", .clk = &fsmc_clk},
+#endif
+
+/* common clocks to spear310 and spear320 */
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+ { .dev_id = "uart1", .clk = &uart1_clk},
+ { .dev_id = "uart2", .clk = &uart2_clk},
+#endif
+
+ /* common clock to spear300 and spear320 */
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
+ { .dev_id = "clcd", .clk = &clcd_clk},
+ { .dev_id = "sdhci", .clk = &sdhci_clk},
+#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
+
+ /* spear300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR300
+ { .dev_id = "gpio1", .clk = &gpio1_clk},
+ { .dev_id = "keyboard", .clk = &kbd_clk},
+#endif
+
+ /* spear310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR310
+ { .dev_id = "uart3", .clk = &uart3_clk},
+ { .dev_id = "uart4", .clk = &uart4_clk},
+ { .dev_id = "uart5", .clk = &uart5_clk},
+
+#endif
+ /* spear320 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR320
+ { .dev_id = "c_can_platform.0", .clk = &can0_clk},
+ { .dev_id = "c_can_platform.1", .clk = &can1_clk},
+ { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
+ { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
+ { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
+ { .dev_id = "pwm", .clk = &pwm_clk},
+#endif
};
void __init clk_init(void)
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 38d767a..6cb4f3c 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -63,8 +63,8 @@
#define GPT1_CLK_SHIFT 11
#define GPT2_CLK_SHIFT 12
#define GPT_CLK_MASK 0x1
-#define AUX_CLK_PLL3_MASK 0
-#define AUX_CLK_PLL1_MASK 1
+#define AUX_CLK_PLL3_VAL 0
+#define AUX_CLK_PLL1_VAL 1
#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C))
/* PERIP1_CLK_ENB register masks */
@@ -113,6 +113,7 @@
#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074))
#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078))
/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB 31
#define AUX_EQ_SEL_SHIFT 30
#define AUX_EQ_SEL_MASK 1
#define AUX_EQ1_SEL 0
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index ef88922..9171952 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -60,12 +60,22 @@ static struct pll_clk_config pll1_config = {
.masks = &pll1_masks,
};
+/* pll rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll_rtbl[] = {
+ {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
+};
+
/* PLL1 clock */
static struct clk pll1_clk = {
+ .flags = ENABLED_ON_INIT,
.pclk = &osc_30m_clk,
.en_reg = PLL1_CTR,
.en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
.private_data = &pll1_config,
};
@@ -103,35 +113,25 @@ static struct bus_clk_config ahb_config = {
.masks = &ahb_masks,
};
+/* ahb rate configuration table, in ascending order of rates */
+struct bus_rate_tbl bus_rtbl[] = {
+ {.div = 3}, /* == parent divided by 4 */
+ {.div = 2}, /* == parent divided by 3 */
+ {.div = 1}, /* == parent divided by 2 */
+ {.div = 0}, /* == parent divided by 1 */
+};
+
/* ahb clock */
static struct clk ahb_clk = {
.flags = ALWAYS_ENABLED,
.pclk = &pll1_clk,
+ .calc_rate = &bus_calc_rate,
.recalc = &bus_clk_recalc,
+ .set_rate = &bus_clk_set_rate,
+ .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
.private_data = &ahb_config,
};
-/* uart parents */
-static struct pclk_info uart_pclk_info[] = {
- {
- .pclk = &pll1_clk,
- .pclk_mask = AUX_CLK_PLL1_MASK,
- .scalable = 1,
- }, {
- .pclk = &pll3_48m_clk,
- .pclk_mask = AUX_CLK_PLL3_MASK,
- .scalable = 0,
- },
-};
-
-/* uart parent select structure */
-static struct pclk_sel uart_pclk_sel = {
- .pclk_info = uart_pclk_info,
- .pclk_count = ARRAY_SIZE(uart_pclk_info),
- .pclk_sel_reg = PERIP_CLK_CFG,
- .pclk_sel_mask = UART_CLK_MASK,
-};
-
/* auxiliary synthesizers masks */
static struct aux_clk_masks aux_masks = {
.eq_sel_mask = AUX_EQ_SEL_MASK,
@@ -145,19 +145,57 @@ static struct aux_clk_masks aux_masks = {
};
/* uart configurations */
-static struct aux_clk_config uart_config = {
+static struct aux_clk_config uart_synth_config = {
.synth_reg = UART_CLK_SYNT,
.masks = &aux_masks,
};
+/* aux rate configuration table, in ascending order of rates */
+struct aux_rate_tbl aux_rtbl[] = {
+ /* For PLL1 = 332 MHz */
+ {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
+};
+
+/* uart synth clock */
+static struct clk uart_synth_clk = {
+ .en_reg = UART_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
+ .private_data = &uart_synth_config,
+};
+
+/* uart parents */
+static struct pclk_info uart_pclk_info[] = {
+ {
+ .pclk = &uart_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_val = AUX_CLK_PLL3_VAL,
+ },
+};
+
+/* uart parent select structure */
+static struct pclk_sel uart_pclk_sel = {
+ .pclk_info = uart_pclk_info,
+ .pclk_count = ARRAY_SIZE(uart_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = UART_CLK_MASK,
+};
+
/* uart0 clock */
static struct clk uart0_clk = {
.en_reg = PERIP1_CLK_ENB,
.en_reg_bit = UART0_CLK_ENB,
.pclk_sel = &uart_pclk_sel,
.pclk_sel_shift = UART_CLK_SHIFT,
- .recalc = &aux_clk_recalc,
- .private_data = &uart_config,
+ .recalc = &follow_parent,
};
/* uart1 clock */
@@ -166,26 +204,35 @@ static struct clk uart1_clk = {
.en_reg_bit = UART1_CLK_ENB,
.pclk_sel = &uart_pclk_sel,
.pclk_sel_shift = UART_CLK_SHIFT,
- .recalc = &aux_clk_recalc,
- .private_data = &uart_config,
+ .recalc = &follow_parent,
};
/* firda configurations */
-static struct aux_clk_config firda_config = {
+static struct aux_clk_config firda_synth_config = {
.synth_reg = FIRDA_CLK_SYNT,
.masks = &aux_masks,
};
+/* firda synth clock */
+static struct clk firda_synth_clk = {
+ .en_reg = FIRDA_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
+ .private_data = &firda_synth_config,
+};
+
/* firda parents */
static struct pclk_info firda_pclk_info[] = {
{
- .pclk = &pll1_clk,
- .pclk_mask = AUX_CLK_PLL1_MASK,
- .scalable = 1,
+ .pclk = &firda_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
}, {
.pclk = &pll3_48m_clk,
- .pclk_mask = AUX_CLK_PLL3_MASK,
- .scalable = 0,
+ .pclk_val = AUX_CLK_PLL3_VAL,
},
};
@@ -203,26 +250,35 @@ static struct clk firda_clk = {
.en_reg_bit = FIRDA_CLK_ENB,
.pclk_sel = &firda_pclk_sel,
.pclk_sel_shift = FIRDA_CLK_SHIFT,
- .recalc = &aux_clk_recalc,
- .private_data = &firda_config,
+ .recalc = &follow_parent,
};
/* clcd configurations */
-static struct aux_clk_config clcd_config = {
+static struct aux_clk_config clcd_synth_config = {
.synth_reg = CLCD_CLK_SYNT,
.masks = &aux_masks,
};
+/* firda synth clock */
+static struct clk clcd_synth_clk = {
+ .en_reg = CLCD_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
+ .private_data = &clcd_synth_config,
+};
+
/* clcd parents */
static struct pclk_info clcd_pclk_info[] = {
{
- .pclk = &pll1_clk,
- .pclk_mask = AUX_CLK_PLL1_MASK,
- .scalable = 1,
+ .pclk = &clcd_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
}, {
.pclk = &pll3_48m_clk,
- .pclk_mask = AUX_CLK_PLL3_MASK,
- .scalable = 0,
+ .pclk_val = AUX_CLK_PLL3_VAL,
},
};
@@ -240,29 +296,7 @@ static struct clk clcd_clk = {
.en_reg_bit = CLCD_CLK_ENB,
.pclk_sel = &clcd_pclk_sel,
.pclk_sel_shift = CLCD_CLK_SHIFT,
- .recalc = &aux_clk_recalc,
- .private_data = &clcd_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt_pclk_info[] = {
- {
- .pclk = &pll1_clk,
- .pclk_mask = AUX_CLK_PLL1_MASK,
- .scalable = 1,
- }, {
- .pclk = &pll3_48m_clk,
- .pclk_mask = AUX_CLK_PLL3_MASK,
- .scalable = 0,
- },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt_pclk_sel = {
- .pclk_info = gpt_pclk_info,
- .pclk_count = ARRAY_SIZE(gpt_pclk_info),
- .pclk_sel_reg = PERIP_CLK_CFG,
- .pclk_sel_mask = GPT_CLK_MASK,
+ .recalc = &follow_parent,
};
/* gpt synthesizer masks */
@@ -273,60 +307,162 @@ static struct gpt_clk_masks gpt_masks = {
.nscale_sel_shift = GPT_NSCALE_SHIFT,
};
-/* gpt0_1 configurations */
-static struct gpt_clk_config gpt0_1_config = {
+/* gpt rate configuration table, in ascending order of rates */
+struct gpt_rate_tbl gpt_rtbl[] = {
+ /* For pll1 = 332 MHz */
+ {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
+ {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
+ {.mscale = 1, .nscale = 0}, /* 83 MHz */
+};
+
+/* gpt0 synth clk config*/
+static struct gpt_clk_config gpt0_synth_config = {
.synth_reg = PRSC1_CLK_CFG,
.masks = &gpt_masks,
};
+/* gpt synth clock */
+static struct clk gpt0_synth_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .calc_rate = &gpt_calc_rate,
+ .recalc = &gpt_clk_recalc,
+ .set_rate = &gpt_clk_set_rate,
+ .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+ .private_data = &gpt0_synth_config,
+};
+
+/* gpt parents */
+static struct pclk_info gpt0_pclk_info[] = {
+ {
+ .pclk = &gpt0_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_val = AUX_CLK_PLL3_VAL,
+ },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt0_pclk_sel = {
+ .pclk_info = gpt0_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
/* gpt0 ARM1 subsystem timer clock */
static struct clk gpt0_clk = {
.flags = ALWAYS_ENABLED,
- .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel = &gpt0_pclk_sel,
.pclk_sel_shift = GPT0_CLK_SHIFT,
- .recalc = &gpt_clk_recalc,
- .private_data = &gpt0_1_config,
+ .recalc = &follow_parent,
+};
+
+
+/* Note: gpt0 and gpt1 share same parent clocks */
+/* gpt parent select structure */
+static struct pclk_sel gpt1_pclk_sel = {
+ .pclk_info = gpt0_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
};
/* gpt1 timer clock */
static struct clk gpt1_clk = {
.flags = ALWAYS_ENABLED,
- .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel = &gpt1_pclk_sel,
.pclk_sel_shift = GPT1_CLK_SHIFT,
- .recalc = &gpt_clk_recalc,
- .private_data = &gpt0_1_config,
+ .recalc = &follow_parent,
};
-/* gpt2 configurations */
-static struct gpt_clk_config gpt2_config = {
+/* gpt2 synth clk config*/
+static struct gpt_clk_config gpt2_synth_config = {
.synth_reg = PRSC2_CLK_CFG,
.masks = &gpt_masks,
};
+/* gpt synth clock */
+static struct clk gpt2_synth_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .calc_rate = &gpt_calc_rate,
+ .recalc = &gpt_clk_recalc,
+ .set_rate = &gpt_clk_set_rate,
+ .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+ .private_data = &gpt2_synth_config,
+};
+
+/* gpt parents */
+static struct pclk_info gpt2_pclk_info[] = {
+ {
+ .pclk = &gpt2_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_val = AUX_CLK_PLL3_VAL,
+ },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt2_pclk_sel = {
+ .pclk_info = gpt2_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
/* gpt2 timer clock */
static struct clk gpt2_clk = {
- .en_reg = PERIP1_CLK_ENB,
- .en_reg_bit = GPT2_CLK_ENB,
- .pclk_sel = &gpt_pclk_sel,
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gpt2_pclk_sel,
.pclk_sel_shift = GPT2_CLK_SHIFT,
- .recalc = &gpt_clk_recalc,
- .private_data = &gpt2_config,
+ .recalc = &follow_parent,
};
-/* gpt3 configurations */
-static struct gpt_clk_config gpt3_config = {
+/* gpt3 synth clk config*/
+static struct gpt_clk_config gpt3_synth_config = {
.synth_reg = PRSC3_CLK_CFG,
.masks = &gpt_masks,
};
+/* gpt synth clock */
+static struct clk gpt3_synth_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .calc_rate = &gpt_calc_rate,
+ .recalc = &gpt_clk_recalc,
+ .set_rate = &gpt_clk_set_rate,
+ .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+ .private_data = &gpt3_synth_config,
+};
+
+/* gpt parents */
+static struct pclk_info gpt3_pclk_info[] = {
+ {
+ .pclk = &gpt3_synth_clk,
+ .pclk_val = AUX_CLK_PLL1_VAL,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_val = AUX_CLK_PLL3_VAL,
+ },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt3_pclk_sel = {
+ .pclk_info = gpt3_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
/* gpt3 timer clock */
static struct clk gpt3_clk = {
- .en_reg = PERIP1_CLK_ENB,
- .en_reg_bit = GPT3_CLK_ENB,
- .pclk_sel = &gpt_pclk_sel,
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gpt3_pclk_sel,
.pclk_sel_shift = GPT3_CLK_SHIFT,
- .recalc = &gpt_clk_recalc,
- .private_data = &gpt3_config,
+ .recalc = &follow_parent,
};
/* clock derived from pll3 clk */
@@ -371,7 +507,10 @@ static struct bus_clk_config apb_config = {
static struct clk apb_clk = {
.flags = ALWAYS_ENABLED,
.pclk = &ahb_clk,
+ .calc_rate = &bus_calc_rate,
.recalc = &bus_clk_recalc,
+ .set_rate = &bus_clk_set_rate,
+ .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
.private_data = &apb_config,
};
@@ -488,7 +627,7 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
{ .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
/* clock derived from 32 KHz os clk */
- { .dev_id = "rtc", .clk = &rtc_clk},
+ { .dev_id = "rtc-spear", .clk = &rtc_clk},
/* clock derived from 30 MHz os clk */
{ .con_id = "pll1_clk", .clk = &pll1_clk},
{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
@@ -496,6 +635,12 @@ static struct clk_lookup spear_clk_lookups[] = {
/* clock derived from pll1 clk */
{ .con_id = "cpu_clk", .clk = &cpu_clk},
{ .con_id = "ahb_clk", .clk = &ahb_clk},
+ { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
+ { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
+ { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
+ { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
+ { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
+ { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk},
{ .dev_id = "uart0", .clk = &uart0_clk},
{ .dev_id = "uart1", .clk = &uart1_clk},
{ .dev_id = "firda", .clk = &firda_clk},
@@ -505,22 +650,22 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "gpt2", .clk = &gpt2_clk},
{ .dev_id = "gpt3", .clk = &gpt3_clk},
/* clock derived from pll3 clk */
- { .dev_id = "usbh0", .clk = &usbh0_clk},
- { .dev_id = "usbh1", .clk = &usbh1_clk},
+ { .con_id = "usbh.0_clk", .clk = &usbh0_clk},
+ { .con_id = "usbh.1_clk", .clk = &usbh1_clk},
{ .dev_id = "usbd", .clk = &usbd_clk},
/* clock derived from ahb clk */
{ .con_id = "apb_clk", .clk = &apb_clk},
- { .dev_id = "i2c", .clk = &i2c_clk},
+ { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
{ .dev_id = "dma", .clk = &dma_clk},
{ .dev_id = "jpeg", .clk = &jpeg_clk},
{ .dev_id = "gmac", .clk = &gmac_clk},
{ .dev_id = "smi", .clk = &smi_clk},
- { .dev_id = "fsmc", .clk = &fsmc_clk},
+ { .con_id = "fsmc", .clk = &fsmc_clk},
/* clock derived from apb clk */
{ .dev_id = "adc", .clk = &adc_clk},
- { .dev_id = "ssp0", .clk = &ssp0_clk},
- { .dev_id = "ssp1", .clk = &ssp1_clk},
- { .dev_id = "ssp2", .clk = &ssp2_clk},
+ { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
+ { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
+ { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
{ .dev_id = "gpio0", .clk = &gpio0_clk},
{ .dev_id = "gpio1", .clk = &gpio1_clk},
{ .dev_id = "gpio2", .clk = &gpio2_clk},
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 0390803..bd71e72 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -66,8 +66,8 @@
#define GPT2_CLK_SHIFT 11
#define GPT3_CLK_SHIFT 12
#define GPT_CLK_MASK 0x1
-#define AUX_CLK_PLL3_MASK 0
-#define AUX_CLK_PLL1_MASK 1
+#define AUX_CLK_PLL3_VAL 0
+#define AUX_CLK_PLL1_VAL 1
#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C))
/* PERIP1_CLK_ENB register masks */
@@ -123,6 +123,7 @@
#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074))
#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078))
/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB 31
#define AUX_EQ_SEL_SHIFT 30
#define AUX_EQ_SEL_MASK 1
#define AUX_EQ1_SEL 0
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index f1cf832..8de7cf6 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -12,6 +12,7 @@
*/
#include <linux/bug.h>
+#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/list.h>
@@ -22,7 +23,7 @@
static DEFINE_SPINLOCK(clocks_lock);
static LIST_HEAD(root_clks);
-static void propagate_rate(struct list_head *);
+static void propagate_rate(struct clk *, int on_init);
static int generic_clk_enable(struct clk *clk)
{
@@ -64,6 +65,100 @@ static struct clkops generic_clkops = {
.disable = generic_clk_disable,
};
+/* returns current programmed clocks clock info structure */
+static struct pclk_info *pclk_info_get(struct clk *clk)
+{
+ unsigned int val, i;
+ struct pclk_info *info = NULL;
+
+ val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
+ & clk->pclk_sel->pclk_sel_mask;
+
+ for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
+ if (clk->pclk_sel->pclk_info[i].pclk_val == val)
+ info = &clk->pclk_sel->pclk_info[i];
+ }
+
+ return info;
+}
+
+/*
+ * Set Update pclk, and pclk_info of clk and add clock sibling node to current
+ * parents children list
+ */
+static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ list_del(&clk->sibling);
+ list_add(&clk->sibling, &pclk_info->pclk->children);
+
+ clk->pclk = pclk_info->pclk;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+static void do_clk_disable(struct clk *clk)
+{
+ if (!clk)
+ return;
+
+ if (!clk->usage_count) {
+ WARN_ON(1);
+ return;
+ }
+
+ clk->usage_count--;
+
+ if (clk->usage_count == 0) {
+ /*
+ * Surely, there are no active childrens or direct users
+ * of this clock
+ */
+ if (clk->pclk)
+ do_clk_disable(clk->pclk);
+
+ if (clk->ops && clk->ops->disable)
+ clk->ops->disable(clk);
+ }
+}
+
+static int do_clk_enable(struct clk *clk)
+{
+ int ret = 0;
+
+ if (!clk)
+ return -EFAULT;
+
+ if (clk->usage_count == 0) {
+ if (clk->pclk) {
+ ret = do_clk_enable(clk->pclk);
+ if (ret)
+ goto err;
+ }
+ if (clk->ops && clk->ops->enable) {
+ ret = clk->ops->enable(clk);
+ if (ret) {
+ if (clk->pclk)
+ do_clk_disable(clk->pclk);
+ goto err;
+ }
+ }
+ /*
+ * Since the clock is going to be used for the first
+ * time please reclac
+ */
+ if (clk->recalc) {
+ ret = clk->recalc(clk);
+ if (ret)
+ goto err;
+ }
+ }
+ clk->usage_count++;
+err:
+ return ret;
+}
+
/*
* clk_enable - inform the system when the clock source should be running.
* @clk: clock source
@@ -77,17 +172,9 @@ int clk_enable(struct clk *clk)
unsigned long flags;
int ret = 0;
- if (!clk || IS_ERR(clk))
- return -EFAULT;
-
spin_lock_irqsave(&clocks_lock, flags);
- if (clk->usage_count == 0) {
- if (clk->ops && clk->ops->enable)
- ret = clk->ops->enable(clk);
- }
- clk->usage_count++;
+ ret = do_clk_enable(clk);
spin_unlock_irqrestore(&clocks_lock, flags);
-
return ret;
}
EXPORT_SYMBOL(clk_enable);
@@ -108,17 +195,8 @@ void clk_disable(struct clk *clk)
{
unsigned long flags;
- if (!clk || IS_ERR(clk))
- return;
-
- WARN_ON(clk->usage_count == 0);
-
spin_lock_irqsave(&clocks_lock, flags);
- clk->usage_count--;
- if (clk->usage_count == 0) {
- if (clk->ops && clk->ops->disable)
- clk->ops->disable(clk);
- }
+ do_clk_disable(clk);
spin_unlock_irqrestore(&clocks_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
@@ -152,15 +230,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
int i, found = 0, val = 0;
unsigned long flags;
- if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent))
+ if (!clk || !parent)
return -EFAULT;
- if (clk->usage_count)
- return -EBUSY;
- if (!clk->pclk_sel)
- return -EPERM;
if (clk->pclk == parent)
return 0;
+ if (!clk->pclk_sel)
+ return -EPERM;
+ /* check if requested parent is in clk parent list */
for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
if (clk->pclk_sel->pclk_info[i].pclk == parent) {
found = 1;
@@ -175,13 +252,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
/* reflect parent change in hardware */
val = readl(clk->pclk_sel->pclk_sel_reg);
val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
- val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift;
+ val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
writel(val, clk->pclk_sel->pclk_sel_reg);
spin_unlock_irqrestore(&clocks_lock, flags);
/* reflect parent change in software */
- clk->recalc(clk);
- propagate_rate(&clk->children);
+ clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
+
+ propagate_rate(clk, 0);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
@@ -195,19 +273,37 @@ EXPORT_SYMBOL(clk_set_parent);
*/
int clk_set_rate(struct clk *clk, unsigned long rate)
{
- /* TODO */
- return -EINVAL;
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ if (!clk || !rate)
+ return -EFAULT;
+
+ if (clk->set_rate) {
+ spin_lock_irqsave(&clocks_lock, flags);
+ ret = clk->set_rate(clk, rate);
+ if (!ret)
+ /* if successful -> propagate */
+ propagate_rate(clk, 0);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+ } else if (clk->pclk) {
+ u32 mult = clk->div_factor ? clk->div_factor : 1;
+ ret = clk_set_rate(clk->pclk, mult * rate);
+ }
+
+ return ret;
}
EXPORT_SYMBOL(clk_set_rate);
/* registers clock in platform clock framework */
void clk_register(struct clk_lookup *cl)
{
- struct clk *clk = cl->clk;
+ struct clk *clk;
unsigned long flags;
- if (!clk || IS_ERR(clk))
+ if (!cl || !cl->clk)
return;
+ clk = cl->clk;
spin_lock_irqsave(&clocks_lock, flags);
@@ -220,15 +316,24 @@ void clk_register(struct clk_lookup *cl)
/* root clock don't have any parents */
if (!clk->pclk && !clk->pclk_sel) {
list_add(&clk->sibling, &root_clks);
- /* add clocks with only one parent to parent's children list */
} else if (clk->pclk && !clk->pclk_sel) {
+ /* add clocks with only one parent to parent's children list */
list_add(&clk->sibling, &clk->pclk->children);
} else {
- /* add clocks with > 1 parent to 1st parent's children list */
- clk->pclk = clk->pclk_sel->pclk_info[0].pclk;
- list_add(&clk->sibling,
- &clk->pclk_sel->pclk_info[0].pclk->children);
+ /* clocks with more than one parent */
+ struct pclk_info *pclk_info;
+
+ pclk_info = pclk_info_get(clk);
+ if (!pclk_info) {
+ pr_err("CLKDEV: invalid pclk info of clk with"
+ " %s dev_id and %s con_id\n",
+ cl->dev_id, cl->con_id);
+ } else {
+ clk->pclk = pclk_info->pclk;
+ list_add(&clk->sibling, &pclk_info->pclk->children);
+ }
}
+
spin_unlock_irqrestore(&clocks_lock, flags);
/* add clock to arm clockdev framework */
@@ -236,56 +341,112 @@ void clk_register(struct clk_lookup *cl)
}
/**
- * propagate_rate - recalculate and propagate all clocks in list head
+ * propagate_rate - recalculate and propagate all clocks to children
+ * @pclk: parent clock required to be propogated
+ * @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
*
- * Recalculates all root clocks in list head, which if the clock's .recalc is
- * set correctly, should also propagate their rates.
+ * Recalculates all children clocks
*/
-static void propagate_rate(struct list_head *lhead)
+void propagate_rate(struct clk *pclk, int on_init)
{
- struct clk *clkp, *_temp;
+ struct clk *clk, *_temp;
+ int ret = 0;
+
+ list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
+ if (clk->recalc) {
+ ret = clk->recalc(clk);
+ /*
+ * recalc will return error if clk out is not programmed
+ * In this case configure default rate.
+ */
+ if (ret && clk->set_rate)
+ clk->set_rate(clk, 0);
+ }
+ propagate_rate(clk, on_init);
+
+ if (!on_init)
+ continue;
- list_for_each_entry_safe(clkp, _temp, lhead, sibling) {
- if (clkp->recalc)
- clkp->recalc(clkp);
- propagate_rate(&clkp->children);
+ /* Enable clks enabled on init, in software view */
+ if (clk->flags & ENABLED_ON_INIT)
+ do_clk_enable(clk);
}
}
-/* returns current programmed clocks clock info structure */
-static struct pclk_info *pclk_info_get(struct clk *clk)
+/**
+ * round_rate - Returns index of closest programmable rate in rate_config tbl
+ * @clk: ptr to clock structure
+ * @drate: desired rate
+ * @rate: final rate will be returned in this variable only.
+ *
+ * Finds index in rate_config for highest clk rate which is less than
+ * requested rate. If there is no clk rate lesser than requested rate then
+ * -EINVAL is returned. This routine assumes that rate_config is written
+ * in incrementing order of clk rates.
+ * If drate passed is zero then default rate is programmed.
+ */
+static int round_rate(struct clk *clk, unsigned long drate, unsigned long *rate)
{
- unsigned int mask, i;
- unsigned long flags;
- struct pclk_info *info = NULL;
+ unsigned long tmp = 0, prev_rate = 0;
+ int index;
- spin_lock_irqsave(&clocks_lock, flags);
- mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
- & clk->pclk_sel->pclk_sel_mask;
+ if (!clk->calc_rate)
+ return -EFAULT;
- for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
- if (clk->pclk_sel->pclk_info[i].pclk_mask == mask)
- info = &clk->pclk_sel->pclk_info[i];
+ /* Set default rate if desired rate is 0 */
+ if (!drate) {
+ index = clk->rate_config.default_index;
+ *rate = clk->calc_rate(clk, index);
+ return index;
}
- spin_unlock_irqrestore(&clocks_lock, flags);
- return info;
+ /*
+ * This loops ends on two conditions:
+ * - as soon as clk is found with rate greater than requested rate.
+ * - if all clks in rate_config are smaller than requested rate.
+ */
+ for (index = 0; index < clk->rate_config.count; index++) {
+ prev_rate = tmp;
+ tmp = clk->calc_rate(clk, index);
+ if (drate < tmp) {
+ index--;
+ break;
+ }
+ }
+ /* return if can't find suitable clock */
+ if (index < 0) {
+ index = -EINVAL;
+ *rate = 0;
+ } else if (index == clk->rate_config.count) {
+ /* program with highest clk rate possible */
+ index = clk->rate_config.count - 1;
+ *rate = tmp;
+ } else
+ *rate = prev_rate;
+
+ return index;
}
+/*All below functions are called with lock held */
+
/*
- * Set pclk as cclk's parent and add clock sibling node to current parents
- * children list
+ * Calculates pll clk rate for specific value of mode, m, n and p
+ *
+ * In normal mode
+ * rate = (2 * M[15:8] * Fin)/(N * 2^P)
+ *
+ * In Dithered mode
+ * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
*/
-static void change_parent(struct clk *cclk, struct clk *pclk)
+unsigned long pll_calc_rate(struct clk *clk, int index)
{
- unsigned long flags;
+ unsigned long rate = clk->pclk->rate;
+ struct pll_rate_tbl *tbls = clk->rate_config.tbls;
+ unsigned int mode;
- spin_lock_irqsave(&clocks_lock, flags);
- list_del(&cclk->sibling);
- list_add(&cclk->sibling, &pclk->children);
-
- cclk->pclk = pclk;
- spin_unlock_irqrestore(&clocks_lock, flags);
+ mode = tbls[index].mode ? 256 : 1;
+ return (((2 * rate / 10000) * tbls[index].m) /
+ (mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
}
/*
@@ -297,13 +458,11 @@ static void change_parent(struct clk *cclk, struct clk *pclk)
* In Dithered mode
* rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
*/
-void pll_clk_recalc(struct clk *clk)
+int pll_clk_recalc(struct clk *clk)
{
struct pll_clk_config *config = clk->private_data;
unsigned int num = 2, den = 0, val, mode = 0;
- unsigned long flags;
- spin_lock_irqsave(&clocks_lock, flags);
mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
config->masks->mode_mask;
@@ -325,22 +484,120 @@ void pll_clk_recalc(struct clk *clk)
den *= 256;
}
+ if (!den)
+ return -EINVAL;
+
clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
- spin_unlock_irqrestore(&clocks_lock, flags);
+ return 0;
+}
+
+/*
+ * Configures new clock rate of pll
+ */
+int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
+{
+ struct pll_rate_tbl *tbls = clk->rate_config.tbls;
+ struct pll_clk_config *config = clk->private_data;
+ unsigned long val, rate;
+ int i;
+
+ i = round_rate(clk, desired_rate, &rate);
+ if (i < 0)
+ return i;
+
+ val = readl(config->mode_reg) &
+ ~(config->masks->mode_mask << config->masks->mode_shift);
+ val |= (tbls[i].mode & config->masks->mode_mask) <<
+ config->masks->mode_shift;
+ writel(val, config->mode_reg);
+
+ val = readl(config->cfg_reg) &
+ ~(config->masks->div_p_mask << config->masks->div_p_shift);
+ val |= (tbls[i].p & config->masks->div_p_mask) <<
+ config->masks->div_p_shift;
+ val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
+ val |= (tbls[i].n & config->masks->div_n_mask) <<
+ config->masks->div_n_shift;
+ val &= ~(config->masks->dith_fdbk_m_mask <<
+ config->masks->dith_fdbk_m_shift);
+ if (tbls[i].mode)
+ val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
+ config->masks->dith_fdbk_m_shift;
+ else
+ val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
+ config->masks->norm_fdbk_m_shift;
+
+ writel(val, config->cfg_reg);
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+/*
+ * Calculates ahb, apb clk rate for specific value of div
+ */
+unsigned long bus_calc_rate(struct clk *clk, int index)
+{
+ unsigned long rate = clk->pclk->rate;
+ struct bus_rate_tbl *tbls = clk->rate_config.tbls;
+
+ return rate / (tbls[index].div + 1);
}
/* calculates current programmed rate of ahb or apb bus */
-void bus_clk_recalc(struct clk *clk)
+int bus_clk_recalc(struct clk *clk)
{
struct bus_clk_config *config = clk->private_data;
unsigned int div;
- unsigned long flags;
- spin_lock_irqsave(&clocks_lock, flags);
div = ((readl(config->reg) >> config->masks->shift) &
config->masks->mask) + 1;
+
+ if (!div)
+ return -EINVAL;
+
clk->rate = (unsigned long)clk->pclk->rate / div;
- spin_unlock_irqrestore(&clocks_lock, flags);
+ return 0;
+}
+
+/* Configures new clock rate of AHB OR APB bus */
+int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
+{
+ struct bus_rate_tbl *tbls = clk->rate_config.tbls;
+ struct bus_clk_config *config = clk->private_data;
+ unsigned long val, rate;
+ int i;
+
+ i = round_rate(clk, desired_rate, &rate);
+ if (i < 0)
+ return i;
+
+ val = readl(config->reg) &
+ ~(config->masks->mask << config->masks->shift);
+ val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
+ writel(val, config->reg);
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+/*
+ * gives rate for different values of eq, x and y
+ *
+ * Fout from synthesizer can be given from two equations:
+ * Fout1 = (Fin * X/Y)/2 EQ1
+ * Fout2 = Fin * X/Y EQ2
+ */
+unsigned long aux_calc_rate(struct clk *clk, int index)
+{
+ unsigned long rate = clk->pclk->rate;
+ struct aux_rate_tbl *tbls = clk->rate_config.tbls;
+ u8 eq = tbls[index].eq ? 1 : 2;
+
+ return (((rate/10000) * tbls[index].xscale) /
+ (tbls[index].yscale * eq)) * 10000;
}
/*
@@ -353,47 +610,76 @@ void bus_clk_recalc(struct clk *clk)
*
* Selection of eqn 1 or 2 is programmed in register
*/
-void aux_clk_recalc(struct clk *clk)
+int aux_clk_recalc(struct clk *clk)
{
struct aux_clk_config *config = clk->private_data;
- struct pclk_info *pclk_info = NULL;
unsigned int num = 1, den = 1, val, eqn;
- unsigned long flags;
- /* get current programmed parent */
- pclk_info = pclk_info_get(clk);
- if (!pclk_info) {
- spin_lock_irqsave(&clocks_lock, flags);
- clk->pclk = NULL;
- clk->rate = 0;
- spin_unlock_irqrestore(&clocks_lock, flags);
- return;
- }
+ val = readl(config->synth_reg);
- change_parent(clk, pclk_info->pclk);
+ eqn = (val >> config->masks->eq_sel_shift) &
+ config->masks->eq_sel_mask;
+ if (eqn == config->masks->eq1_mask)
+ den *= 2;
- spin_lock_irqsave(&clocks_lock, flags);
- if (pclk_info->scalable) {
- val = readl(config->synth_reg);
-
- eqn = (val >> config->masks->eq_sel_shift) &
- config->masks->eq_sel_mask;
- if (eqn == config->masks->eq1_mask)
- den *= 2;
-
- /* calculate numerator */
- num = (val >> config->masks->xscale_sel_shift) &
- config->masks->xscale_sel_mask;
-
- /* calculate denominator */
- den *= (val >> config->masks->yscale_sel_shift) &
- config->masks->yscale_sel_mask;
- val = (((clk->pclk->rate/10000) * num) / den) * 10000;
- } else
- val = clk->pclk->rate;
+ /* calculate numerator */
+ num = (val >> config->masks->xscale_sel_shift) &
+ config->masks->xscale_sel_mask;
- clk->rate = val;
- spin_unlock_irqrestore(&clocks_lock, flags);
+ /* calculate denominator */
+ den *= (val >> config->masks->yscale_sel_shift) &
+ config->masks->yscale_sel_mask;
+
+ if (!den)
+ return -EINVAL;
+
+ clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
+ return 0;
+}
+
+/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
+int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
+{
+ struct aux_rate_tbl *tbls = clk->rate_config.tbls;
+ struct aux_clk_config *config = clk->private_data;
+ unsigned long val, rate;
+ int i;
+
+ i = round_rate(clk, desired_rate, &rate);
+ if (i < 0)
+ return i;
+
+ val = readl(config->synth_reg) &
+ ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
+ val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
+ config->masks->eq_sel_shift;
+ val &= ~(config->masks->xscale_sel_mask <<
+ config->masks->xscale_sel_shift);
+ val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
+ config->masks->xscale_sel_shift;
+ val &= ~(config->masks->yscale_sel_mask <<
+ config->masks->yscale_sel_shift);
+ val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
+ config->masks->yscale_sel_shift;
+ writel(val, config->synth_reg);
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+/*
+ * Calculates gpt clk rate for different values of mscale and nscale
+ *
+ * Fout= Fin/((2 ^ (N+1)) * (M+1))
+ */
+unsigned long gpt_calc_rate(struct clk *clk, int index)
+{
+ unsigned long rate = clk->pclk->rate;
+ struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
+
+ return rate / ((1 << (tbls[index].nscale + 1)) *
+ (tbls[index].mscale + 1));
}
/*
@@ -401,49 +687,142 @@ void aux_clk_recalc(struct clk *clk)
* Fout from synthesizer can be given from below equations:
* Fout= Fin/((2 ^ (N+1)) * (M+1))
*/
-void gpt_clk_recalc(struct clk *clk)
+int gpt_clk_recalc(struct clk *clk)
{
struct gpt_clk_config *config = clk->private_data;
- struct pclk_info *pclk_info = NULL;
unsigned int div = 1, val;
- unsigned long flags;
-
- pclk_info = pclk_info_get(clk);
- if (!pclk_info) {
- spin_lock_irqsave(&clocks_lock, flags);
- clk->pclk = NULL;
- clk->rate = 0;
- spin_unlock_irqrestore(&clocks_lock, flags);
- return;
- }
- change_parent(clk, pclk_info->pclk);
+ val = readl(config->synth_reg);
+ div += (val >> config->masks->mscale_sel_shift) &
+ config->masks->mscale_sel_mask;
+ div *= 1 << (((val >> config->masks->nscale_sel_shift) &
+ config->masks->nscale_sel_mask) + 1);
- spin_lock_irqsave(&clocks_lock, flags);
- if (pclk_info->scalable) {
- val = readl(config->synth_reg);
- div += (val >> config->masks->mscale_sel_shift) &
- config->masks->mscale_sel_mask;
- div *= 1 << (((val >> config->masks->nscale_sel_shift) &
- config->masks->nscale_sel_mask) + 1);
- }
+ if (!div)
+ return -EINVAL;
clk->rate = (unsigned long)clk->pclk->rate / div;
- spin_unlock_irqrestore(&clocks_lock, flags);
+ return 0;
+}
+
+/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
+int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
+{
+ struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
+ struct gpt_clk_config *config = clk->private_data;
+ unsigned long val, rate;
+ int i;
+
+ i = round_rate(clk, desired_rate, &rate);
+ if (i < 0)
+ return i;
+
+ val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
+ config->masks->mscale_sel_shift);
+ val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
+ config->masks->mscale_sel_shift;
+ val &= ~(config->masks->nscale_sel_mask <<
+ config->masks->nscale_sel_shift);
+ val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
+ config->masks->nscale_sel_shift;
+ writel(val, config->synth_reg);
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+/*
+ * Calculates clcd clk rate for different values of div
+ *
+ * Fout from synthesizer can be given from below equation:
+ * Fout= Fin/2*div (division factor)
+ * div is 17 bits:-
+ * 0-13 (fractional part)
+ * 14-16 (integer part)
+ * To calculate Fout we left shift val by 14 bits and divide Fin by
+ * complete div (including fractional part) and then right shift the
+ * result by 14 places.
+ */
+unsigned long clcd_calc_rate(struct clk *clk, int index)
+{
+ unsigned long rate = clk->pclk->rate;
+ struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
+
+ rate /= 1000;
+ rate <<= 12;
+ rate /= (2 * tbls[index].div);
+ rate >>= 12;
+ rate *= 1000;
+
+ return rate;
+}
+
+/*
+ * calculates current programmed rate of clcd synthesizer
+ * Fout from synthesizer can be given from below equation:
+ * Fout= Fin/2*div (division factor)
+ * div is 17 bits:-
+ * 0-13 (fractional part)
+ * 14-16 (integer part)
+ * To calculate Fout we left shift val by 14 bits and divide Fin by
+ * complete div (including fractional part) and then right shift the
+ * result by 14 places.
+ */
+int clcd_clk_recalc(struct clk *clk)
+{
+ struct clcd_clk_config *config = clk->private_data;
+ unsigned int div = 1;
+ unsigned long prate;
+ unsigned int val;
+
+ val = readl(config->synth_reg);
+ div = (val >> config->masks->div_factor_shift) &
+ config->masks->div_factor_mask;
+
+ if (!div)
+ return -EINVAL;
+
+ prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
+
+ clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
+ clk->rate *= 1000;
+ return 0;
+}
+
+/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
+int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
+{
+ struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
+ struct clcd_clk_config *config = clk->private_data;
+ unsigned long val, rate;
+ int i;
+
+ i = round_rate(clk, desired_rate, &rate);
+ if (i < 0)
+ return i;
+
+ val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
+ config->masks->div_factor_shift);
+ val |= (tbls[i].div & config->masks->div_factor_mask) <<
+ config->masks->div_factor_shift;
+ writel(val, config->synth_reg);
+
+ clk->rate = rate;
+
+ return 0;
}
/*
* Used for clocks that always have value as the parent clock divided by a
* fixed divisor
*/
-void follow_parent(struct clk *clk)
+int follow_parent(struct clk *clk)
{
- unsigned long flags;
unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
- spin_lock_irqsave(&clocks_lock, flags);
clk->rate = clk->pclk->rate/div_factor;
- spin_unlock_irqrestore(&clocks_lock, flags);
+ return 0;
}
/**
@@ -454,5 +833,25 @@ void follow_parent(struct clk *clk)
*/
void recalc_root_clocks(void)
{
- propagate_rate(&root_clks);
+ struct clk *pclk;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ list_for_each_entry(pclk, &root_clks, sibling) {
+ if (pclk->recalc) {
+ ret = pclk->recalc(pclk);
+ /*
+ * recalc will return error if clk out is not programmed
+ * In this case configure default clock.
+ */
+ if (ret && pclk->set_rate)
+ pclk->set_rate(pclk, 0);
+ }
+ propagate_rate(pclk, 1);
+ /* Enable clks enabled on init, in software view */
+ if (pclk->flags & ENABLED_ON_INIT)
+ do_clk_enable(pclk);
+ }
+ spin_unlock_irqrestore(&clocks_lock, flags);
}
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index 5f66333..c9de151 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -21,6 +21,7 @@
/* clk structure flags */
#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
+#define ENABLED_ON_INIT (1 << 2) /* clocks enabled@init */
/**
* struct clkops - clock operations
@@ -35,13 +36,11 @@ struct clkops {
/**
* struct pclk_info - parents info
* @pclk: pointer to parent clk
- * @pclk_mask: value to be written for selecting this parent
- * @scalable: Is parent scalable (1 - YES, 0 - NO)
+ * @pclk_val: value to be written for selecting this parent
*/
struct pclk_info {
struct clk *pclk;
- u8 pclk_mask;
- u8 scalable;
+ u8 pclk_val;
};
/**
@@ -59,6 +58,18 @@ struct pclk_sel {
};
/**
+ * struct rate_config - clk rate configurations
+ * @tbls: array of device specific clk rate tables, in ascending order of rates
+ * @count: size of tbls array
+ * @default_index: default setting when originally disabled
+ */
+struct rate_config {
+ void *tbls;
+ u8 count;
+ u8 default_index;
+};
+
+/**
* struct clk - clock structure
* @usage_count: num of users who enabled this clock
* @flags: flags for clock properties
@@ -67,7 +78,10 @@ struct pclk_sel {
* @en_reg_bit: clk enable/disable bit
* @ops: clk enable/disable ops - generic_clkops selected if NULL
* @recalc: pointer to clock rate recalculate function
- * @div_factor: division factor to parent clock. Only for recalc = follow_parent
+ * @set_rate: pointer to clock set rate function
+ * @calc_rate: pointer to clock get rate function for index
+ * @rate_config: rate configuration information, used by set_rate
+ * @div_factor: division factor to parent clock.
* @pclk: current parent clk
* @pclk_sel: pointer to parent selection structure
* @pclk_sel_shift: register shift for selecting parent of this clock
@@ -82,7 +96,10 @@ struct clk {
unsigned int *en_reg;
u8 en_reg_bit;
const struct clkops *ops;
- void (*recalc) (struct clk *);
+ int (*recalc) (struct clk *);
+ int (*set_rate) (struct clk *, unsigned long rate);
+ unsigned long (*calc_rate)(struct clk *, int index);
+ struct rate_config rate_config;
unsigned int div_factor;
struct clk *pclk;
@@ -115,6 +132,14 @@ struct pll_clk_config {
struct pll_clk_masks *masks;
};
+/* pll clk rate config structure */
+struct pll_rate_tbl {
+ u8 mode;
+ u16 m;
+ u8 n;
+ u8 p;
+};
+
/* ahb and apb bus configuration structure */
struct bus_clk_masks {
u32 mask;
@@ -126,6 +151,11 @@ struct bus_clk_config {
struct bus_clk_masks *masks;
};
+/* ahb and apb clk bus rate config structure */
+struct bus_rate_tbl {
+ u8 div;
+};
+
/* Aux clk configuration structure: applicable to UART and FIRDA */
struct aux_clk_masks {
u32 eq_sel_mask;
@@ -143,6 +173,13 @@ struct aux_clk_config {
struct aux_clk_masks *masks;
};
+/* aux clk rate config structure */
+struct aux_rate_tbl {
+ u16 xscale;
+ u16 yscale;
+ u8 eq;
+};
+
/* GPT clk configuration structure */
struct gpt_clk_masks {
u32 mscale_sel_mask;
@@ -156,15 +193,48 @@ struct gpt_clk_config {
struct gpt_clk_masks *masks;
};
+/* gpt clk rate config structure */
+struct gpt_rate_tbl {
+ u16 mscale;
+ u16 nscale;
+};
+
+/* clcd clk configuration structure */
+struct clcd_synth_masks {
+ u32 div_factor_mask;
+ u32 div_factor_shift;
+};
+
+struct clcd_clk_config {
+ u32 *synth_reg;
+ struct clcd_synth_masks *masks;
+};
+
+/* clcd clk rate config structure */
+struct clcd_rate_tbl {
+ u16 div;
+};
+
/* platform specific clock functions */
void clk_register(struct clk_lookup *cl);
void recalc_root_clocks(void);
-/* clock recalc functions */
-void follow_parent(struct clk *clk);
-void pll_clk_recalc(struct clk *clk);
-void bus_clk_recalc(struct clk *clk);
-void gpt_clk_recalc(struct clk *clk);
-void aux_clk_recalc(struct clk *clk);
+/* clock recalc & set rate functions */
+int follow_parent(struct clk *clk);
+unsigned long pll_calc_rate(struct clk *clk, int index);
+int pll_clk_recalc(struct clk *clk);
+int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+unsigned long bus_calc_rate(struct clk *clk, int index);
+int bus_clk_recalc(struct clk *clk);
+int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+unsigned long gpt_calc_rate(struct clk *clk, int index);
+int gpt_clk_recalc(struct clk *clk);
+int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+unsigned long aux_calc_rate(struct clk *clk, int index);
+int aux_clk_recalc(struct clk *clk);
+int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+unsigned long clcd_calc_rate(struct clk *clk, int index);
+int clcd_clk_recalc(struct clk *clk);
+int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
#endif /* __PLAT_CLOCK_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 13/62] ST SPEAr: Adding Debugfs support on clock framework
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (11 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 12/62] ST SPEAr: Updating Clock Support Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 14/62] ST SPEAr: Correcting SOC Config base address for spear320 Viresh Kumar
` (48 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/plat-spear/clock.c | 116 ++++++++++++++++++++++++++++++
arch/arm/plat-spear/include/plat/clock.h | 8 ++
2 files changed, 124 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index 8de7cf6..7d3338f 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -13,6 +13,7 @@
#include <linux/bug.h>
#include <linux/clk.h>
+#include <linux/debugfs.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/list.h>
@@ -22,8 +23,14 @@
static DEFINE_SPINLOCK(clocks_lock);
static LIST_HEAD(root_clks);
+#ifdef CONFIG_DEBUG_FS
+static LIST_HEAD(clocks);
+#endif
static void propagate_rate(struct clk *, int on_init);
+#ifdef CONFIG_DEBUG_FS
+static int clk_debugfs_reparent(struct clk *);
+#endif
static int generic_clk_enable(struct clk *clk)
{
@@ -96,6 +103,10 @@ static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
clk->pclk = pclk_info->pclk;
spin_unlock_irqrestore(&clocks_lock, flags);
+
+#ifdef CONFIG_DEBUG_FS
+ clk_debugfs_reparent(clk);
+#endif
}
static void do_clk_disable(struct clk *clk)
@@ -336,6 +347,12 @@ void clk_register(struct clk_lookup *cl)
spin_unlock_irqrestore(&clocks_lock, flags);
+ /* debugfs specific */
+#ifdef CONFIG_DEBUG_FS
+ list_add(&clk->node, &clocks);
+ clk->cl = cl;
+#endif
+
/* add clock to arm clockdev framework */
clkdev_add(cl);
}
@@ -855,3 +872,102 @@ void recalc_root_clocks(void)
}
spin_unlock_irqrestore(&clocks_lock, flags);
}
+
+#ifdef CONFIG_DEBUG_FS
+/*
+ * debugfs support to trace clock tree hierarchy and attributes
+ */
+static struct dentry *clk_debugfs_root;
+static int clk_debugfs_register_one(struct clk *c)
+{
+ int err;
+ struct dentry *d, *child;
+ struct clk *pa = c->pclk;
+ char s[255];
+ char *p = s;
+
+ if (c) {
+ if (c->cl->con_id)
+ p += sprintf(p, "%s", c->cl->con_id);
+ if (c->cl->dev_id)
+ p += sprintf(p, "%s", c->cl->dev_id);
+ }
+ d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
+ if (!d)
+ return -ENOMEM;
+ c->dent = d;
+
+ d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
+ (u32 *)&c->usage_count);
+ if (!d) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+ d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+ if (!d) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+ d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+ if (!d) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+ return 0;
+
+err_out:
+ d = c->dent;
+ list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
+ debugfs_remove(child);
+ debugfs_remove(c->dent);
+ return err;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+ int err;
+ struct clk *pa = c->pclk;
+
+ if (pa && !pa->dent) {
+ err = clk_debugfs_register(pa);
+ if (err)
+ return err;
+ }
+
+ if (!c->dent) {
+ err = clk_debugfs_register_one(c);
+ if (err)
+ return err;
+ }
+ return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+ struct clk *c;
+ struct dentry *d;
+ int err;
+
+ d = debugfs_create_dir("clock", NULL);
+ if (!d)
+ return -ENOMEM;
+ clk_debugfs_root = d;
+
+ list_for_each_entry(c, &clocks, node) {
+ err = clk_debugfs_register(c);
+ if (err)
+ goto err_out;
+ }
+ return 0;
+err_out:
+ debugfs_remove_recursive(clk_debugfs_root);
+ return err;
+}
+late_initcall(clk_debugfs_init);
+
+static int clk_debugfs_reparent(struct clk *c)
+{
+ debugfs_remove(c->dent);
+ return clk_debugfs_register_one(c);
+}
+#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index c9de151..16aa0c9 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -88,6 +88,9 @@ struct rate_config {
* @children: list for childrens or this clock
* @sibling: node for list of clocks having same parents
* @private_data: clock specific private data
+ * @node: list to maintain clocks linearly
+ * @cl: clocklook up assoicated with this clock
+ * @dent: object for debugfs
*/
struct clk {
unsigned int usage_count;
@@ -109,6 +112,11 @@ struct clk {
struct list_head children;
struct list_head sibling;
void *private_data;
+#ifdef CONFIG_DEBUG_FS
+ struct list_head node;
+ struct clk_lookup *cl;
+ struct dentry *dent;
+#endif
};
/* pll configuration structure */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 14/62] ST SPEAr: Correcting SOC Config base address for spear320
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (12 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 13/62] ST SPEAr: Adding Debugfs support on clock framework Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 15/62] ST SPEAr: Adding PLGPIO driver for spear platform Viresh Kumar
` (47 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/spear320.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index cacf17a..53677e4 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -62,7 +62,7 @@
#define SPEAR320_SMII1_BASE 0xAB000000
#define SPEAR320_SMII1_SIZE 0x01000000
-#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
+#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 15/62] ST SPEAr: Adding PLGPIO driver for spear platform
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (13 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 14/62] ST SPEAr: Correcting SOC Config base address for spear320 Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 17/62] ST SPEAr: Adding machine support for rtc-spear Viresh Kumar
` (46 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Plgpio pads on few spear machines can be configured as gpios. This patch add
support for configuring these PLGPIOs.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 2 +
arch/arm/mach-spear3xx/include/mach/gpio.h | 141 ++++++++
arch/arm/mach-spear3xx/include/mach/irqs.h | 9 +-
arch/arm/mach-spear3xx/spear310.c | 69 ++++
arch/arm/mach-spear3xx/spear310_evb.c | 1 +
arch/arm/mach-spear3xx/spear320.c | 30 ++-
arch/arm/mach-spear3xx/spear320_evb.c | 1 +
arch/arm/mach-spear6xx/include/mach/gpio.h | 27 ++
arch/arm/plat-spear/Makefile | 2 +
arch/arm/plat-spear/include/plat/gpio.h | 35 ++
arch/arm/plat-spear/plgpio.c | 452 +++++++++++++++++++++++++
11 files changed, 764 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/plat-spear/plgpio.c
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 1c8f9f1..d76ee98 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -144,6 +144,7 @@ extern struct clcd_board clcd_plat_data;
/* spear310 declarations */
#ifdef CONFIG_MACH_SPEAR310
/* Add spear310 machine device structure declarations here */
+extern struct platform_device plgpio_device;
/* pad mux devices */
extern struct pmx_dev pmx_emi_cs_0_1_4_5;
@@ -164,6 +165,7 @@ void __init spear310_init(void);
#ifdef CONFIG_MACH_SPEAR320
/* Add spear320 machine device structure declarations here */
extern struct amba_device clcd_device;
+extern struct platform_device plgpio_device;
/* pad mux modes */
extern struct pmx_mode auto_net_smii_mode;
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
index 451b208..e531f6d 100644
--- a/arch/arm/mach-spear3xx/include/mach/gpio.h
+++ b/arch/arm/mach-spear3xx/include/mach/gpio.h
@@ -16,4 +16,145 @@
#include <plat/gpio.h>
+#ifdef CONFIG_MACH_SPEAR310
+#define PLGPIO_ENB 0x0010
+#define PLGPIO_WDATA 0x0020
+#define PLGPIO_DIR 0x0030
+#define PLGPIO_IE 0x0040
+#define PLGPIO_RDATA 0x0050
+#define PLGPIO_MIS 0x0060
+
+#elif defined(CONFIG_MACH_SPEAR320)
+#define PLGPIO_ENB 0x0024
+#define PLGPIO_WDATA 0x0034
+#define PLGPIO_DIR 0x0044
+#define PLGPIO_RDATA 0x0054
+#define PLGPIO_IE 0x0064
+#define PLGPIO_MIS 0x0074
+#endif
+
+#define BASIC_GPIO_0 0
+#define BASIC_GPIO_1 1
+#define BASIC_GPIO_2 2
+#define BASIC_GPIO_3 3
+#define BASIC_GPIO_4 4
+#define BASIC_GPIO_5 5
+#define BASIC_GPIO_6 6
+#define BASIC_GPIO_7 7
+
+#ifdef CONFIG_MACH_SPEAR300
+#define RAS_GPIO_0 8
+#define RAS_GPIO_1 9
+#define RAS_GPIO_2 10
+#define RAS_GPIO_3 11
+#define RAS_GPIO_4 12
+#define RAS_GPIO_5 13
+#define RAS_GPIO_6 14
+#define RAS_GPIO_7 15
+
+#elif defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#define PLGPIO_0 8
+#define PLGPIO_1 9
+#define PLGPIO_2 10
+#define PLGPIO_3 11
+#define PLGPIO_4 12
+#define PLGPIO_5 13
+#define PLGPIO_6 14
+#define PLGPIO_7 15
+#define PLGPIO_8 16
+#define PLGPIO_9 17
+#define PLGPIO_10 18
+#define PLGPIO_11 19
+#define PLGPIO_12 20
+#define PLGPIO_13 21
+#define PLGPIO_14 22
+#define PLGPIO_15 23
+#define PLGPIO_16 24
+#define PLGPIO_17 25
+#define PLGPIO_18 26
+#define PLGPIO_19 27
+#define PLGPIO_20 28
+#define PLGPIO_21 29
+#define PLGPIO_22 30
+#define PLGPIO_23 31
+#define PLGPIO_24 32
+#define PLGPIO_25 33
+#define PLGPIO_26 34
+#define PLGPIO_27 35
+#define PLGPIO_28 36
+#define PLGPIO_29 37
+#define PLGPIO_30 38
+#define PLGPIO_31 39
+#define PLGPIO_32 40
+#define PLGPIO_33 41
+#define PLGPIO_34 42
+#define PLGPIO_35 43
+#define PLGPIO_36 44
+#define PLGPIO_37 45
+#define PLGPIO_38 46
+#define PLGPIO_39 47
+#define PLGPIO_40 48
+#define PLGPIO_41 49
+#define PLGPIO_42 50
+#define PLGPIO_43 51
+#define PLGPIO_44 52
+#define PLGPIO_45 53
+#define PLGPIO_46 54
+#define PLGPIO_47 55
+#define PLGPIO_48 56
+#define PLGPIO_49 57
+#define PLGPIO_50 58
+#define PLGPIO_51 59
+#define PLGPIO_52 60
+#define PLGPIO_53 61
+#define PLGPIO_54 62
+#define PLGPIO_55 63
+#define PLGPIO_56 64
+#define PLGPIO_57 65
+#define PLGPIO_58 66
+#define PLGPIO_59 67
+#define PLGPIO_60 68
+#define PLGPIO_61 69
+#define PLGPIO_62 70
+#define PLGPIO_63 71
+#define PLGPIO_64 72
+#define PLGPIO_65 73
+#define PLGPIO_66 74
+#define PLGPIO_67 75
+#define PLGPIO_68 76
+#define PLGPIO_69 77
+#define PLGPIO_70 78
+#define PLGPIO_71 79
+#define PLGPIO_72 80
+#define PLGPIO_73 81
+#define PLGPIO_74 82
+#define PLGPIO_75 83
+#define PLGPIO_76 84
+#define PLGPIO_77 85
+#define PLGPIO_78 86
+#define PLGPIO_79 87
+#define PLGPIO_80 88
+#define PLGPIO_81 89
+#define PLGPIO_82 90
+#define PLGPIO_83 91
+#define PLGPIO_84 92
+#define PLGPIO_85 93
+#define PLGPIO_86 94
+#define PLGPIO_87 95
+#define PLGPIO_88 96
+#define PLGPIO_89 97
+#define PLGPIO_90 98
+#define PLGPIO_91 99
+#define PLGPIO_92 100
+#define PLGPIO_93 101
+#define PLGPIO_94 102
+#define PLGPIO_95 103
+#define PLGPIO_96 104
+#define PLGPIO_97 105
+#define PLGPIO_98 106
+#define PLGPIO_99 107
+#define PLGPIO_100 108
+#define PLGPIO_101 109
+#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+
#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 7f940b8..f1175b9 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -141,12 +141,13 @@
#endif
/* PLGPIO Virtual IRQs */
+#define SPEAR_PLGPIO_COUNT 102
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102)
+#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
+#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + SPEAR_PLGPIO_COUNT)
#endif
-#define VIRQ_END SPEAR_GPIO_INT_END
-#define NR_IRQS VIRQ_END
+#define VIRQ_END SPEAR_GPIO_INT_END
+#define NR_IRQS VIRQ_END
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index f38eb21..3a3acea 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -15,6 +15,7 @@
#include <asm/irq.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <plat/gpio.h>
#include <plat/shirq.h>
/* pad multiplexing support */
@@ -140,6 +141,74 @@ struct pmx_driver pmx_driver = {
};
/* Add spear310 specific devices here */
+/* plgpio device registeration */
+/*
+ * pin to offset and offset to pin converter functions
+ *
+ * In spear310 there is inconsistency among bit positions in plgpio regiseters,
+ * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
+ * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
+ */
+static int spear300_p2o(int pin)
+{
+ int offset = pin;
+
+ if (pin <= 27)
+ offset += 4;
+ else if (pin <= 33)
+ offset = -1;
+ else if (pin <= 97)
+ offset -= 2;
+ else if (pin <= 101)
+ offset = 101 - pin;
+ else
+ offset = -1;
+
+ return offset;
+}
+
+int spear300_o2p(int offset)
+{
+ if (offset <= 3)
+ return 101 - offset;
+ else if (offset <= 31)
+ return offset - 4;
+ else
+ return offset + 2;
+}
+
+static struct plgpio_platform_data plgpio_plat_data = {
+ .gpio_base = 8,
+ .irq_base = SPEAR_PLGPIO_INT_BASE,
+ .gpio_count = SPEAR_PLGPIO_COUNT,
+ .p2o = spear300_p2o,
+ .o2p = spear300_o2p,
+ /* list of registers with inconsistency */
+ .p2o_regs = PTO_RDATA_REG | PTO_WDATA_REG | PTO_DIR_REG |
+ PTO_IE_REG | PTO_RDATA_REG | PTO_MIS_REG,
+};
+
+static struct resource plgpio_resources[] = {
+ {
+ .start = SPEAR310_SOC_CONFIG_BASE,
+ .end = SPEAR310_SOC_CONFIG_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = VIRQ_PLGPIO,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device plgpio_device = {
+ .name = "plgpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &plgpio_plat_data,
+ },
+ .num_resources = ARRAY_SIZE(plgpio_resources),
+ .resource = plgpio_resources,
+};
+
/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 3855431..7dd93bd 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -52,6 +52,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
/* spear310 specific devices */
+ &plgpio_device,
};
static void __init spear310_evb_init(void)
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 70f1db2..d5e5969 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -15,6 +15,7 @@
#include <asm/irq.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <plat/gpio.h>
#include <plat/shirq.h>
/* pad multiplexing support */
@@ -385,7 +386,6 @@ struct pmx_driver pmx_driver = {
};
/* Add spear320 specific devices here */
-
/* CLCD device registration */
struct amba_device clcd_device = {
.dev = {
@@ -402,6 +402,34 @@ struct amba_device clcd_device = {
.irq = {VIRQ_CLCD, NO_IRQ},
};
+/* plgpio device registeration */
+static struct plgpio_platform_data plgpio_plat_data = {
+ .gpio_base = 8,
+ .irq_base = SPEAR_PLGPIO_INT_BASE,
+ .gpio_count = SPEAR_PLGPIO_COUNT,
+};
+
+static struct resource plgpio_resources[] = {
+ {
+ .start = SPEAR320_SOC_CONFIG_BASE,
+ .end = SPEAR320_SOC_CONFIG_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = VIRQ_PLGPIO,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device plgpio_device = {
+ .name = "plgpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &plgpio_plat_data,
+ },
+ .num_resources = ARRAY_SIZE(plgpio_resources),
+ .resource = plgpio_resources,
+};
+
/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
{
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 821e806..82f4e76 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -50,6 +50,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
/* spear320 specific devices */
+ &plgpio_device,
};
static void __init spear320_evb_init(void)
diff --git a/arch/arm/mach-spear6xx/include/mach/gpio.h b/arch/arm/mach-spear6xx/include/mach/gpio.h
index 3a789db..465b2e7 100644
--- a/arch/arm/mach-spear6xx/include/mach/gpio.h
+++ b/arch/arm/mach-spear6xx/include/mach/gpio.h
@@ -16,4 +16,31 @@
#include <plat/gpio.h>
+#define CPU_GPIO_0 0
+#define CPU_GPIO_1 1
+#define CPU_GPIO_2 2
+#define CPU_GPIO_3 3
+#define CPU_GPIO_4 4
+#define CPU_GPIO_5 5
+#define CPU_GPIO_6 6
+#define CPU_GPIO_7 7
+
+#define BASIC_GPIO_0 8
+#define BASIC_GPIO_1 9
+#define BASIC_GPIO_2 10
+#define BASIC_GPIO_3 11
+#define BASIC_GPIO_4 12
+#define BASIC_GPIO_5 13
+#define BASIC_GPIO_6 14
+#define BASIC_GPIO_7 15
+
+#define APPL_GPIO_0 16
+#define APPL_GPIO_1 17
+#define APPL_GPIO_2 18
+#define APPL_GPIO_3 19
+#define APPL_GPIO_4 20
+#define APPL_GPIO_5 21
+#define APPL_GPIO_6 22
+#define APPL_GPIO_7 23
+
#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 01a4a91..e66bc5f 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -6,3 +6,5 @@
obj-y := clcd.o clock.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
+obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
+obj-$(CONFIG_MACH_SPEAR320) += plgpio.o
diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h
index b857c91..450671e 100644
--- a/arch/arm/plat-spear/include/plat/gpio.h
+++ b/arch/arm/plat-spear/include/plat/gpio.h
@@ -21,4 +21,39 @@
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
+/* plgpio driver declarations */
+/*
+ * plgpio pins in all machines are not one to one mapped, bitwise with
+ * registers bits. These set of macros define register masks for which below
+ * functions (pin_to_offset and offset_to_pin) are required to be called.
+ */
+#define PTO_ENB_REG 0x001
+#define PTO_WDATA_REG 0x002
+#define PTO_DIR_REG 0x004
+#define PTO_IE_REG 0x008
+#define PTO_RDATA_REG 0x010
+#define PTO_MIS_REG 0x020
+
+/* functions for converting pin to correct offset in register and vice versa */
+/**
+ * struct plgpio_platform_data: plgpio driver platform data
+ *
+ * gpio_base: gpio start number of plgpios
+ * irq_base: irq number of plgpio0
+ * gpio_count: total count of plgpios
+ * p2o: function ptr for pin to offset conversion. This is required only for
+ * machines where mapping b/w pin and offset is not 1-to-1.
+ * o2p: function ptr for offset to pin conversion. This is required only for
+ * machines where mapping b/w pin and offset is not 1-to-1.
+ * p2o_regs: mask of registers for which p2o and o2p are applicable
+ */
+struct plgpio_platform_data {
+ u32 gpio_base;
+ u32 irq_base;
+ u32 gpio_count;
+ int (*p2o)(int pin); /* pin_to_offset */
+ int (*o2p)(int offset); /* offset_to_pin */
+ u32 p2o_regs;
+};
+
#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-spear/plgpio.c b/arch/arm/plat-spear/plgpio.c
new file mode 100644
index 0000000..3080178
--- /dev/null
+++ b/arch/arm/plat-spear/plgpio.c
@@ -0,0 +1,452 @@
+/*
+ * arch/arm/plat-spear/plgpio.c
+ *
+ * SPEAr platform PLGPIO driver source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#define MAX_GPIO_PER_REG 32
+#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
+#define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG)\
+ * sizeof(int *))
+
+/*
+ * struct plgpio: plgpio driver specific structure
+ *
+ * lock: lock for guarding gpio registers
+ * base: base address of plgpio block
+ * irq_base: irq number of plgpio0
+ * chip: gpio framework specific chip information structure
+ * p2o: function ptr for pin to offset conversion. This is required only for
+ * machines where mapping b/w pin and offset is not 1-to-1.
+ * o2p: function ptr for offset to pin conversion. This is required only for
+ * machines where mapping b/w pin and offset is not 1-to-1.
+ * p2o_regs: mask of registers for which p2o and o2p are applicable
+ */
+struct plgpio {
+ spinlock_t lock;
+ void __iomem *base;
+ unsigned irq_base;
+ struct gpio_chip chip;
+ int (*p2o)(int pin); /* pin_to_offset */
+ int (*o2p)(int offset); /* offset_to_pin */
+ u32 p2o_regs;
+};
+
+/* register manipulation inline functions */
+static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
+{
+ u32 offset = PIN_OFFSET(pin);
+ void __iomem *reg_off = REG_OFFSET(base, reg, pin);
+ u32 val = readl(reg_off);
+
+ return val & (1 << offset);
+}
+
+static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
+{
+ u32 offset = PIN_OFFSET(pin);
+ void __iomem *reg_off = REG_OFFSET(base, reg, pin);
+ u32 val = readl(reg_off);
+
+ writel(val | (1 << offset), reg_off);
+}
+
+static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
+{
+ u32 offset = PIN_OFFSET(pin);
+ void __iomem *reg_off = REG_OFFSET(base, reg, pin);
+ u32 val = readl(reg_off);
+
+ writel(val & ~(1 << offset), reg_off);
+}
+
+/* gpio framework specific routines */
+static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+ unsigned long flags;
+
+ if (offset >= chip->ngpio)
+ return -EINVAL;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_set(plgpio->base, offset, PLGPIO_DIR);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+
+ return 0;
+}
+
+static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+ unsigned long flags;
+ unsigned dir_offset = offset, wdata_offset = offset, tmp;
+
+ if (offset >= chip->ngpio)
+ return -EINVAL;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
+ tmp = plgpio->p2o(offset);
+ if (tmp == -1)
+ return -EINVAL;
+
+ if (plgpio->p2o_regs & PTO_DIR_REG)
+ dir_offset = tmp;
+ if (plgpio->p2o_regs & PTO_WDATA_REG)
+ wdata_offset = tmp;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_reset(plgpio->base, dir_offset, PLGPIO_DIR);
+ if (value)
+ plgpio_reg_set(plgpio->base, wdata_offset, PLGPIO_WDATA);
+ else
+ plgpio_reg_reset(plgpio->base, wdata_offset, PLGPIO_WDATA);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+
+ return 0;
+}
+
+static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+
+ if (offset >= chip->ngpio)
+ return -EINVAL;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return -EINVAL;
+ }
+
+ return is_plgpio_set(plgpio->base, offset, PLGPIO_RDATA);
+}
+
+static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+
+ if (offset >= chip->ngpio)
+ return;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return;
+ }
+
+ if (value)
+ plgpio_reg_set(plgpio->base, offset, PLGPIO_WDATA);
+ else
+ plgpio_reg_reset(plgpio->base, offset, PLGPIO_WDATA);
+}
+
+static int plgpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+ unsigned long flags;
+ int ret = 0;
+
+ if (offset >= chip->ngpio)
+ return -EINVAL;
+
+ /*
+ * put gpio in IN mode before enabling it. This make enabling gpio safe
+ */
+ ret = plgpio_direction_input(chip, offset);
+ if (ret)
+ return ret;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_set(plgpio->base, offset, PLGPIO_ENB);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+
+ return 0;
+}
+
+static void plgpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+ unsigned long flags;
+
+ if (offset >= chip->ngpio)
+ return;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_reset(plgpio->base, offset, PLGPIO_ENB);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+}
+
+static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+
+ if (plgpio->irq_base == (unsigned) -1)
+ return -EINVAL;
+
+ return plgpio->irq_base + offset;
+}
+
+/* PLGPIO IRQ */
+static void plgpio_irq_mask(unsigned irq)
+{
+ struct plgpio *plgpio = get_irq_chip_data(irq);
+ int offset = irq - plgpio->irq_base;
+ unsigned long flags;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_set(plgpio->base, offset, PLGPIO_IE);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+}
+
+static void plgpio_irq_unmask(unsigned irq)
+{
+ struct plgpio *plgpio = get_irq_chip_data(irq);
+ int offset = irq - plgpio->irq_base;
+ unsigned long flags;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_reset(plgpio->base, offset, PLGPIO_IE);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+}
+
+static int plgpio_irq_type(unsigned irq, unsigned trigger)
+{
+ struct plgpio *plgpio = get_irq_chip_data(irq);
+ int offset = irq - plgpio->irq_base;
+
+ if (offset >= plgpio->chip.ngpio)
+ return -EINVAL;
+
+ if (trigger != IRQ_TYPE_LEVEL_HIGH)
+ return -EINVAL;
+ return 0;
+}
+
+static struct irq_chip plgpio_irqchip = {
+ .name = "PLGPIO",
+ .mask = plgpio_irq_mask,
+ .unmask = plgpio_irq_unmask,
+ .set_type = plgpio_irq_type,
+};
+
+static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+ struct plgpio *plgpio = get_irq_data(irq);
+ unsigned long pending;
+ int regs_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
+ count, pin, offset, i = 0;
+
+ /* check all plgpio MIS registers for a possible interrupt */
+ for (; i < regs_count; i++) {
+ pending = readl(plgpio->base + PLGPIO_MIS + i * sizeof(int *));
+ if (!pending)
+ continue;
+
+ /*
+ * clear extra bits in last register having gpios < MAX/REG
+ * ex: Suppose there are max 102 plgpios. then last register
+ * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
+ * so, we must not take other 28 bits into consideration for
+ * checking interrupt. so clear those bits.
+ */
+ count = plgpio->chip.ngpio - i * MAX_GPIO_PER_REG;
+ if (count < MAX_GPIO_PER_REG)
+ pending &= (1 << count) - 1;
+
+ for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
+ /* get correct pin for "offset" */
+ if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
+ pin = plgpio->o2p(offset);
+ if (pin == -1)
+ continue;
+ } else
+ pin = offset;
+
+ generic_handle_irq(plgpio_to_irq(&plgpio->chip,
+ i * MAX_GPIO_PER_REG + pin));
+ }
+ }
+}
+
+static int __devinit plgpio_probe(struct platform_device *pdev)
+{
+ struct plgpio_platform_data *pdata;
+ struct plgpio *plgpio;
+ int ret, irq, i;
+ struct resource *res;
+
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "invalid platform data\n");
+ goto fail;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ret = -EBUSY;
+ dev_dbg(&pdev->dev, "invalid IORESOURCE_MEM\n");
+ goto fail;
+ }
+
+ if (!request_mem_region(res->start, resource_size(res), "plgpio")) {
+ ret = -EBUSY;
+ dev_dbg(&pdev->dev, "request mem region fail\n");
+ goto fail;
+ }
+
+ plgpio = kzalloc(sizeof(*plgpio), GFP_KERNEL);
+ if (!plgpio) {
+ ret = -ENOMEM;
+ dev_dbg(&pdev->dev, "memory allocation fail\n");
+ goto release_region;
+ }
+
+ plgpio->base = ioremap(res->start, resource_size(res));
+ if (!plgpio->base) {
+ ret = -ENOMEM;
+ dev_dbg(&pdev->dev, "ioremap fail\n");
+ goto kfree;
+ }
+
+ spin_lock_init(&plgpio->lock);
+
+ plgpio->chip.request = plgpio_request;
+ plgpio->chip.free = plgpio_free;
+ plgpio->chip.direction_input = plgpio_direction_input;
+ plgpio->chip.direction_output = plgpio_direction_output;
+ plgpio->chip.get = plgpio_get_value;
+ plgpio->chip.set = plgpio_set_value;
+ plgpio->chip.to_irq = plgpio_to_irq;
+ plgpio->chip.base = pdata->gpio_base;
+ plgpio->chip.ngpio = pdata->gpio_count;
+ plgpio->chip.label = dev_name(&pdev->dev);
+ plgpio->chip.dev = &pdev->dev;
+ plgpio->chip.owner = THIS_MODULE;
+ plgpio->irq_base = pdata->irq_base;
+ plgpio->p2o = pdata->p2o;
+ plgpio->o2p = pdata->o2p;
+ plgpio->p2o_regs = pdata->p2o_regs;
+
+ ret = gpiochip_add(&plgpio->chip);
+ if (ret) {
+ dev_dbg(&pdev->dev, "unable to add gpio chip\n");
+ goto iounmap;
+ }
+
+ /* irq_chip support */
+ if (pdata->irq_base == (unsigned) -1) {
+ dev_info(&pdev->dev, "Initialization successful\n");
+ return 0;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "invalid irq number\n");
+ goto remove_gpiochip;
+ }
+
+ set_irq_chained_handler(irq, plgpio_irq_handler);
+ for (i = 0; i < pdata->gpio_count; i++) {
+ set_irq_chip(i+plgpio->irq_base, &plgpio_irqchip);
+ set_irq_handler(i+plgpio->irq_base, handle_simple_irq);
+ set_irq_flags(i+plgpio->irq_base, IRQF_VALID);
+ set_irq_chip_data(i+plgpio->irq_base, plgpio);
+ }
+ set_irq_data(irq, plgpio);
+ dev_info(&pdev->dev, "Initialization successful\n");
+
+ return 0;
+
+remove_gpiochip:
+ if (gpiochip_remove(&plgpio->chip))
+ dev_dbg(&pdev->dev, "unable to remove gpiochip\n");
+iounmap:
+ iounmap(plgpio->base);
+kfree:
+ kfree(plgpio);
+release_region:
+ release_mem_region(res->start, resource_size(res));
+fail:
+ dev_err(&pdev->dev, "probe fail: %d\n", ret);
+ return ret;
+}
+
+static struct platform_driver plgpio_driver = {
+ .probe = plgpio_probe,
+ .driver = {
+ .name = "plgpio",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init plgpio_init(void)
+{
+ return platform_driver_register(&plgpio_driver);
+}
+subsys_initcall(plgpio_init);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("SPEAr PLGPIO driver");
+MODULE_LICENSE("GPL");
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 17/62] ST SPEAr: Adding machine support for rtc-spear
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (14 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 15/62] ST SPEAr: Adding PLGPIO driver for spear platform Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 18/62] ST SPEAr: adding support for synopsis i2c designware Viresh Kumar
` (45 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 1 +
arch/arm/mach-spear13xx/spear1300_evb.c | 1 +
arch/arm/mach-spear13xx/spear13xx.c | 19 +++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/generic.h | 1 +
arch/arm/mach-spear3xx/spear300_evb.c | 1 +
arch/arm/mach-spear3xx/spear310_evb.c | 1 +
arch/arm/mach-spear3xx/spear320_evb.c | 1 +
arch/arm/mach-spear3xx/spear3xx.c | 19 +++++++++++++++++++
arch/arm/mach-spear6xx/include/mach/generic.h | 1 +
arch/arm/mach-spear6xx/spear600_evb.c | 1 +
arch/arm/mach-spear6xx/spear6xx.c | 19 +++++++++++++++++++
11 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 5c0f042..bf032f6 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -30,6 +30,7 @@
/* Add spear13xx family device structure declarations here */
extern struct amba_device spear13xx_uart_device;
+extern struct platform_device spear13xx_rtc_device;
extern struct sys_timer spear13xx_timer;
/* Add spear1300 machine device structure declarations here */
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 9a83d61..2fce2ec 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -22,6 +22,7 @@ static struct amba_device *amba_devs[] __initdata = {
};
static struct platform_device *plat_devs[] __initdata = {
+ &spear13xx_rtc_device,
};
static void __init spear1300_evb_init(void)
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 6774b26..d924dc9 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -37,6 +37,25 @@ struct amba_device spear13xx_uart_device = {
.irq = {IRQ_UART, NO_IRQ},
};
+/* rtc device registration */
+static struct resource rtc_resources[] = {
+ {
+ .start = SPEAR13XX_RTC_BASE,
+ .end = SPEAR13XX_RTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear13xx_rtc_device = {
+ .name = "rtc-spear",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(rtc_resources),
+ .resource = rtc_resources,
+};
+
/* Do spear13xx familiy common initialization part here */
void __init spear13xx_init(void)
{
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index d76ee98..408bb8d 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -33,6 +33,7 @@
/* Add spear3xx family device structure declarations here */
extern struct amba_device gpio_device;
extern struct amba_device uart_device;
+extern struct platform_device rtc_device;
extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 3bb7fbc..392ee4a 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -44,6 +44,7 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &rtc_device,
/* spear300 specific devices */
};
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 7dd93bd..15ca8fc 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -50,6 +50,7 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &rtc_device,
/* spear310 specific devices */
&plgpio_device,
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 82f4e76..48155cc 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -48,6 +48,7 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &rtc_device,
/* spear320 specific devices */
&plgpio_device,
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index e281e0c..8582b02 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -54,6 +54,25 @@ struct amba_device uart_device = {
.irq = {IRQ_UART, NO_IRQ},
};
+/* rtc device registration */
+static struct resource rtc_resources[] = {
+ {
+ .start = SPEAR3XX_ICM3_RTC_BASE,
+ .end = SPEAR3XX_ICM3_RTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_BASIC_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device rtc_device = {
+ .name = "rtc-spear",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(rtc_resources),
+ .resource = rtc_resources,
+};
+
/* Do spear3xx familiy common initialization part here */
void __init spear3xx_init(void)
{
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index d6a04f2..674b16c 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -32,6 +32,7 @@
extern struct amba_device clcd_device;
extern struct amba_device gpio_device[];
extern struct amba_device uart_device[];
+extern struct platform_device rtc_device;
extern struct sys_timer spear6xx_timer;
/* Add spear6xx family function declarations here */
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index 88e69f4..861e83d 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -26,6 +26,7 @@ static struct amba_device *amba_devs[] __initdata = {
};
static struct platform_device *plat_devs[] __initdata = {
+ &rtc_device,
};
static void __init spear600_evb_init(void)
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 9b61430..c95d2bf 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -121,6 +121,25 @@ struct amba_device gpio_device[] = {
}
};
+/* rtc device registration */
+static struct resource rtc_resources[] = {
+ {
+ .start = SPEAR6XX_ICM3_RTC_BASE,
+ .end = SPEAR6XX_ICM3_RTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_BASIC_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device rtc_device = {
+ .name = "rtc-spear",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(rtc_resources),
+ .resource = rtc_resources,
+};
+
/* This will add devices, and do machine specific tasks */
void __init spear6xx_init(void)
{
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 18/62] ST SPEAr: adding support for synopsis i2c designware
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (15 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 17/62] ST SPEAr: Adding machine support for rtc-spear Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 19/62] ST SPEAr: Adding machine support for USB host Viresh Kumar
` (44 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 2 +
arch/arm/mach-spear13xx/spear1300_evb.c | 4 +++
arch/arm/mach-spear13xx/spear13xx.c | 23 +++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/generic.h | 3 ++
arch/arm/mach-spear3xx/include/mach/irqs.h | 2 +-
arch/arm/mach-spear3xx/spear300_evb.c | 4 +++
arch/arm/mach-spear3xx/spear310_evb.c | 4 +++
arch/arm/mach-spear3xx/spear320.c | 24 +++++++++++++++++++-
arch/arm/mach-spear3xx/spear320_evb.c | 5 ++++
arch/arm/mach-spear3xx/spear3xx.c | 22 ++++++++++++++++++
arch/arm/mach-spear6xx/include/mach/generic.h | 2 +
arch/arm/mach-spear6xx/spear600_evb.c | 4 +++
arch/arm/mach-spear6xx/spear6xx.c | 22 ++++++++++++++++++
arch/arm/plat-spear/Makefile | 6 +++++
arch/arm/plat-spear/i2c_eval_board.c | 29 ++++++++++++++++++++++++
15 files changed, 154 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/plat-spear/i2c_eval_board.c
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index bf032f6..c8db271 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -30,6 +30,7 @@
/* Add spear13xx family device structure declarations here */
extern struct amba_device spear13xx_uart_device;
+extern struct platform_device spear13xx_i2c_device;
extern struct platform_device spear13xx_rtc_device;
extern struct sys_timer spear13xx_timer;
@@ -37,6 +38,7 @@ extern struct sys_timer spear13xx_timer;
/* Add spear13xx family function declarations here */
void __init clk_init(void);
+void __init i2c_register_default_devices(void);
void __init spear_setup_timer(void);
void __init spear1300_init(void);
void __init spear13xx_map_io(void);
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 2fce2ec..8df2a6c 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -22,6 +22,7 @@ static struct amba_device *amba_devs[] __initdata = {
};
static struct platform_device *plat_devs[] __initdata = {
+ &spear13xx_i2c_device,
&spear13xx_rtc_device,
};
@@ -32,6 +33,9 @@ static void __init spear1300_evb_init(void)
/* call spear1300 machine init function */
spear1300_init();
+ /* Register slave devices on the I2C buses */
+ i2c_register_default_devices();
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index d924dc9..e76153b 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -24,6 +24,7 @@
#include <mach/hardware.h>
/* Add spear13xx machines common devices here */
+
/* uart device registeration */
struct amba_device spear13xx_uart_device = {
.dev = {
@@ -37,6 +38,28 @@ struct amba_device spear13xx_uart_device = {
.irq = {IRQ_UART, NO_IRQ},
};
+/* i2c device registeration */
+static struct resource i2c_resources[] = {
+ {
+ .start = SPEAR13XX_I2C_BASE,
+ .end = SPEAR13XX_I2C_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear13xx_i2c_device = {
+ .name = "i2c_designware",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ },
+ .num_resources = ARRAY_SIZE(i2c_resources),
+ .resource = i2c_resources,
+};
+
/* rtc device registration */
static struct resource rtc_resources[] = {
{
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 408bb8d..2933b39 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -33,11 +33,13 @@
/* Add spear3xx family device structure declarations here */
extern struct amba_device gpio_device;
extern struct amba_device uart_device;
+extern struct platform_device i2c_device;
extern struct platform_device rtc_device;
extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
void __init clk_init(void);
+void __init i2c_register_default_devices(void);
void __init spear_setup_timer(void);
void __init spear3xx_map_io(void);
void __init spear3xx_init_irq(void);
@@ -166,6 +168,7 @@ void __init spear310_init(void);
#ifdef CONFIG_MACH_SPEAR320
/* Add spear320 machine device structure declarations here */
extern struct amba_device clcd_device;
+extern struct platform_device i2c1_device;
extern struct platform_device plgpio_device;
/* pad mux modes */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index f1175b9..5ad7574 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -133,7 +133,7 @@
#define VIRQ_MII1_SMII1 (VIRQ_START + 13)
#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14)
#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15)
-#define VIRQ_I2C (VIRQ_START + 16)
+#define VIRQ_I2C1 (VIRQ_START + 16)
/* GPIO pins virtual irqs */
#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17)
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 392ee4a..7c079ae 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -44,6 +44,7 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &i2c_device,
&rtc_device,
/* spear300 specific devices */
@@ -61,6 +62,9 @@ static void __init spear300_evb_init(void)
/* call spear300 machine init function */
spear300_init();
+ /* Register slave devices on the I2C buses */
+ i2c_register_default_devices();
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 15ca8fc..cbe6f42 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -50,6 +50,7 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &i2c_device,
&rtc_device,
/* spear310 specific devices */
@@ -68,6 +69,9 @@ static void __init spear310_evb_init(void)
/* call spear310 machine init function */
spear310_init();
+ /* Register slave devices on the I2C buses */
+ i2c_register_default_devices();
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index d5e5969..689b27a 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -402,6 +402,28 @@ struct amba_device clcd_device = {
.irq = {VIRQ_CLCD, NO_IRQ},
};
+/* i2c1 device registeration */
+static struct resource i2c1_resources[] = {
+ {
+ .start = SPEAR320_I2C_BASE,
+ .end = SPEAR320_I2C_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = VIRQ_I2C1 ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device i2c1_device = {
+ .name = "i2c_designware",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ },
+ .num_resources = ARRAY_SIZE(i2c1_resources),
+ .resource = i2c1_resources,
+};
+
/* plgpio device registeration */
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
@@ -535,7 +557,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
.status_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
.clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_I2C,
+ .virq = VIRQ_I2C1,
.status_mask = I2C1_IRQ_MASK,
.clear_mask = I2C1_IRQ_MASK,
},
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 48155cc..2c8d32c 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -48,9 +48,11 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &i2c_device,
&rtc_device,
/* spear320 specific devices */
+ &i2c1_device,
&plgpio_device,
};
@@ -66,6 +68,9 @@ static void __init spear320_evb_init(void)
/* call spear320 machine init function */
spear320_init();
+ /* Register slave devices on the I2C buses */
+ i2c_register_default_devices();
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 8582b02..14027a5 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -54,6 +54,28 @@ struct amba_device uart_device = {
.irq = {IRQ_UART, NO_IRQ},
};
+/* i2c device registeration */
+static struct resource i2c_resources[] = {
+ {
+ .start = SPEAR3XX_ICM1_I2C_BASE,
+ .end = SPEAR3XX_ICM1_I2C_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device i2c_device = {
+ .name = "i2c_designware",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ },
+ .num_resources = ARRAY_SIZE(i2c_resources),
+ .resource = i2c_resources,
+};
+
/* rtc device registration */
static struct resource rtc_resources[] = {
{
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 674b16c..3c04487 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -32,10 +32,12 @@
extern struct amba_device clcd_device;
extern struct amba_device gpio_device[];
extern struct amba_device uart_device[];
+extern struct platform_device i2c_device;
extern struct platform_device rtc_device;
extern struct sys_timer spear6xx_timer;
/* Add spear6xx family function declarations here */
+void __init i2c_register_default_devices(void);
void __init spear_setup_timer(void);
void __init spear6xx_map_io(void);
void __init spear6xx_init_irq(void);
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index 861e83d..cd75d16 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -26,6 +26,7 @@ static struct amba_device *amba_devs[] __initdata = {
};
static struct platform_device *plat_devs[] __initdata = {
+ &i2c_device,
&rtc_device,
};
@@ -36,6 +37,9 @@ static void __init spear600_evb_init(void)
/* call spear600 machine init function */
spear600_init();
+ /* Register slave devices on the I2C buses */
+ i2c_register_default_devices();
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index c95d2bf..591bfbb 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -121,6 +121,28 @@ struct amba_device gpio_device[] = {
}
};
+/* i2c device registeration */
+static struct resource i2c_resources[] = {
+ {
+ .start = SPEAR6XX_ICM1_I2C_BASE,
+ .end = SPEAR6XX_ICM1_I2C_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device i2c_device = {
+ .name = "i2c_designware",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ },
+ .num_resources = ARRAY_SIZE(i2c_resources),
+ .resource = i2c_resources,
+};
+
/* rtc device registration */
static struct resource rtc_resources[] = {
{
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e66bc5f..c31892a 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -8,3 +8,9 @@ obj-y := clcd.o clock.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
obj-$(CONFIG_MACH_SPEAR320) += plgpio.o
+
+obj-$(CONFIG_BOARD_SPEAR1300_EVB) += i2c_eval_board.o
+obj-$(CONFIG_BOARD_SPEAR300_EVB) += i2c_eval_board.o
+obj-$(CONFIG_BOARD_SPEAR310_EVB) += i2c_eval_board.o
+obj-$(CONFIG_BOARD_SPEAR320_EVB) += i2c_eval_board.o
+obj-$(CONFIG_BOARD_SPEAR600_EVB) += i2c_eval_board.o
diff --git a/arch/arm/plat-spear/i2c_eval_board.c b/arch/arm/plat-spear/i2c_eval_board.c
new file mode 100644
index 0000000..869d9c9
--- /dev/null
+++ b/arch/arm/plat-spear/i2c_eval_board.c
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/plat-spear/i2c_eval_board.c
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+
+static struct i2c_board_info __initdata i2c_board_info[] = {
+ {
+ .type = "eeprom",
+ .addr = 0x50,
+ }, {
+ .type = "eeprom",
+ .addr = 0x51,
+ },
+};
+
+void __init i2c_register_default_devices(void)
+{
+ i2c_register_board_info(0, i2c_board_info,
+ ARRAY_SIZE(i2c_board_info));
+}
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 19/62] ST SPEAr: Adding machine support for USB host
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (16 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 18/62] ST SPEAr: adding support for synopsis i2c designware Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 20/62] ST SPEAr: Adding machine support for keyboard Viresh Kumar
` (43 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 4 +
arch/arm/mach-spear13xx/spear1300_evb.c | 4 +
arch/arm/mach-spear13xx/spear13xx.c | 106 +++++++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/generic.h | 3 +
arch/arm/mach-spear3xx/spear300_evb.c | 3 +
arch/arm/mach-spear3xx/spear310_evb.c | 3 +
arch/arm/mach-spear3xx/spear320_evb.c | 3 +
arch/arm/mach-spear3xx/spear3xx.c | 80 +++++++++++++++++
arch/arm/mach-spear6xx/include/mach/generic.h | 4 +
arch/arm/mach-spear6xx/spear600_evb.c | 4 +
arch/arm/mach-spear6xx/spear6xx.c | 108 ++++++++++++++++++++++++
11 files changed, 322 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index c8db271..6473316 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -30,7 +30,11 @@
/* Add spear13xx family device structure declarations here */
extern struct amba_device spear13xx_uart_device;
+extern struct platform_device spear13xx_ehci0_device;
+extern struct platform_device spear13xx_ehci1_device;
extern struct platform_device spear13xx_i2c_device;
+extern struct platform_device spear13xx_ohci0_device;
+extern struct platform_device spear13xx_ohci1_device;
extern struct platform_device spear13xx_rtc_device;
extern struct sys_timer spear13xx_timer;
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 8df2a6c..1518044 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -22,7 +22,11 @@ static struct amba_device *amba_devs[] __initdata = {
};
static struct platform_device *plat_devs[] __initdata = {
+ &spear13xx_ehci0_device,
+ &spear13xx_ehci1_device,
&spear13xx_i2c_device,
+ &spear13xx_ohci0_device,
+ &spear13xx_ohci1_device,
&spear13xx_rtc_device,
};
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index e76153b..dc595a3 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -60,6 +60,112 @@ struct platform_device spear13xx_i2c_device = {
.resource = i2c_resources,
};
+/* usb host device registeration */
+static struct resource ehci0_resources[] = {
+ [0] = {
+ .start = SPEAR13XX_UHC0_EHCI_BASE,
+ .end = SPEAR13XX_UHC0_EHCI_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USBH_EHCI0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource ehci1_resources[] = {
+ [0] = {
+ .start = SPEAR13XX_UHC1_EHCI_BASE,
+ .end = SPEAR13XX_UHC1_EHCI_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USBH_EHCI1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource ohci0_resources[] = {
+ [0] = {
+ .start = SPEAR13XX_UHC0_OHCI_BASE,
+ .end = SPEAR13XX_UHC0_OHCI_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USBH_OHCI0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct resource ohci1_resources[] = {
+ [0] = {
+ .start = SPEAR13XX_UHC1_OHCI_BASE,
+ .end = SPEAR13XX_UHC1_OHCI_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USBH_OHCI1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* usbh0_id defaults to 0, being static variable */
+static int usbh0_id;
+static int usbh1_id = 1;
+static u64 ehci0_dmamask = ~0;
+
+struct platform_device spear13xx_ehci0_device = {
+ .name = "spear-ehci",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ehci0_dmamask,
+ .platform_data = &usbh0_id,
+ },
+ .num_resources = ARRAY_SIZE(ehci0_resources),
+ .resource = ehci0_resources,
+};
+
+static u64 ehci1_dmamask = ~0;
+
+struct platform_device spear13xx_ehci1_device = {
+ .name = "spear-ehci",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ehci1_dmamask,
+ .platform_data = &usbh1_id,
+ },
+ .num_resources = ARRAY_SIZE(ehci1_resources),
+ .resource = ehci1_resources,
+};
+
+static u64 ohci0_dmamask = ~0;
+
+struct platform_device spear13xx_ohci0_device = {
+ .name = "spear-ohci",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ohci0_dmamask,
+ .platform_data = &usbh0_id,
+ },
+ .num_resources = ARRAY_SIZE(ohci0_resources),
+ .resource = ohci0_resources,
+};
+
+static u64 ohci1_dmamask = ~0;
+struct platform_device spear13xx_ohci1_device = {
+ .name = "spear-ohci",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ohci1_dmamask,
+ .platform_data = &usbh1_id,
+ },
+ .num_resources = ARRAY_SIZE(ohci1_resources),
+ .resource = ohci1_resources,
+};
+
/* rtc device registration */
static struct resource rtc_resources[] = {
{
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 2933b39..b65a884 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -33,7 +33,10 @@
/* Add spear3xx family device structure declarations here */
extern struct amba_device gpio_device;
extern struct amba_device uart_device;
+extern struct platform_device ehci_device;
extern struct platform_device i2c_device;
+extern struct platform_device ohci0_device;
+extern struct platform_device ohci1_device;
extern struct platform_device rtc_device;
extern struct sys_timer spear3xx_timer;
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 7c079ae..caa7000 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -44,7 +44,10 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &ehci_device,
&i2c_device,
+ &ohci0_device,
+ &ohci1_device,
&rtc_device,
/* spear300 specific devices */
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index cbe6f42..7b7a236 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -50,7 +50,10 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &ehci_device,
&i2c_device,
+ &ohci0_device,
+ &ohci1_device,
&rtc_device,
/* spear310 specific devices */
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 2c8d32c..7bfe609 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -48,7 +48,10 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
+ &ehci_device,
&i2c_device,
+ &ohci0_device,
+ &ohci1_device,
&rtc_device,
/* spear320 specific devices */
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 14027a5..568f365 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -76,6 +76,86 @@ struct platform_device i2c_device = {
.resource = i2c_resources,
};
+/* usb host device registeration */
+static struct resource ehci_resources[] = {
+ [0] = {
+ .start = SPEAR3XX_ICM4_USB_EHCI0_1_BASE,
+ .end = SPEAR3XX_ICM4_USB_EHCI0_1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB_H_EHCI_0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource ohci0_resources[] = {
+ [0] = {
+ .start = SPEAR3XX_ICM4_USB_OHCI0_BASE,
+ .end = SPEAR3XX_ICM4_USB_OHCI0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB_H_OHCI_0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource ohci1_resources[] = {
+ [0] = {
+ .start = SPEAR3XX_ICM4_USB_OHCI1_BASE,
+ .end = SPEAR3XX_ICM4_USB_OHCI1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB_H_OHCI_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 ehci_dmamask = ~0;
+static int usbh_id = -1;
+
+struct platform_device ehci_device = {
+ .name = "spear-ehci",
+ .id = -1,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ehci_dmamask,
+ .platform_data = &usbh_id,
+ },
+ .num_resources = ARRAY_SIZE(ehci_resources),
+ .resource = ehci_resources,
+};
+
+static u64 ohci0_dmamask = ~0;
+
+struct platform_device ohci0_device = {
+ .name = "spear-ohci",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ohci0_dmamask,
+ .platform_data = &usbh_id,
+ },
+ .num_resources = ARRAY_SIZE(ohci0_resources),
+ .resource = ohci0_resources,
+};
+
+static u64 ohci1_dmamask = ~0;
+
+struct platform_device ohci1_device = {
+ .name = "spear-ohci",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ohci1_dmamask,
+ .platform_data = &usbh_id,
+ },
+ .num_resources = ARRAY_SIZE(ohci1_resources),
+ .resource = ohci1_resources,
+};
+
/* rtc device registration */
static struct resource rtc_resources[] = {
{
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 3c04487..ed1dbfc 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -32,7 +32,11 @@
extern struct amba_device clcd_device;
extern struct amba_device gpio_device[];
extern struct amba_device uart_device[];
+extern struct platform_device ehci0_device;
+extern struct platform_device ehci1_device;
extern struct platform_device i2c_device;
+extern struct platform_device ohci0_device;
+extern struct platform_device ohci1_device;
extern struct platform_device rtc_device;
extern struct sys_timer spear6xx_timer;
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index cd75d16..be4e5c9 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -26,7 +26,11 @@ static struct amba_device *amba_devs[] __initdata = {
};
static struct platform_device *plat_devs[] __initdata = {
+ &ehci0_device,
+ &ehci1_device,
&i2c_device,
+ &ohci0_device,
+ &ohci1_device,
&rtc_device,
};
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 591bfbb..5a9763f 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -143,6 +143,114 @@ struct platform_device i2c_device = {
.resource = i2c_resources,
};
+/* usb host device registeration */
+static struct resource ehci0_resources[] = {
+ [0] = {
+ .start = SPEAR6XX_ICM4_USB_EHCI0_BASE,
+ .end = SPEAR6XX_ICM4_USB_EHCI0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB_H_EHCI_0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource ehci1_resources[] = {
+ [0] = {
+ .start = SPEAR6XX_ICM4_USB_EHCI1_BASE,
+ .end = SPEAR6XX_ICM4_USB_EHCI1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB_H_EHCI_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource ohci0_resources[] = {
+ [0] = {
+ .start = SPEAR6XX_ICM4_USB_OHCI0_BASE,
+ .end = SPEAR6XX_ICM4_USB_OHCI0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB_H_OHCI_0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource ohci1_resources[] = {
+ [0] = {
+ .start = SPEAR6XX_ICM4_USB_OHCI1_BASE,
+ .end = SPEAR6XX_ICM4_USB_OHCI1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB_H_OHCI_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* usbh0_id defaults to 0, being static variable */
+static int usbh0_id;
+static int usbh1_id = 1;
+static u64 ehci0_dmamask = ~0;
+
+struct platform_device ehci0_device = {
+ .name = "spear-ehci",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ehci0_dmamask,
+ .platform_data = &usbh0_id,
+ },
+ .num_resources = ARRAY_SIZE(ehci0_resources),
+ .resource = ehci0_resources,
+};
+
+static u64 ehci1_dmamask = ~0;
+
+struct platform_device ehci1_device = {
+ .name = "spear-ehci",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ehci1_dmamask,
+ .platform_data = &usbh1_id,
+ },
+ .num_resources = ARRAY_SIZE(ehci1_resources),
+ .resource = ehci1_resources,
+};
+
+static u64 ohci0_dmamask = ~0;
+
+struct platform_device ohci0_device = {
+ .name = "spear-ohci",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ohci0_dmamask,
+ .platform_data = &usbh0_id,
+ },
+ .num_resources = ARRAY_SIZE(ohci0_resources),
+ .resource = ohci0_resources,
+};
+
+static u64 ohci1_dmamask = ~0;
+
+struct platform_device ohci1_device = {
+ .name = "spear-ohci",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .dma_mask = &ohci1_dmamask,
+ .platform_data = &usbh1_id,
+ },
+ .num_resources = ARRAY_SIZE(ohci1_resources),
+ .resource = ohci1_resources,
+};
+
/* rtc device registration */
static struct resource rtc_resources[] = {
{
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 20/62] ST SPEAr: Adding machine support for keyboard
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (17 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 19/62] ST SPEAr: Adding machine support for USB host Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 21/62] ST SPEAr: Added ARM PL061 GPIO Support on SPEAr13xx and modified resource size Viresh Kumar
` (42 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 1 +
arch/arm/mach-spear13xx/spear1300_evb.c | 17 +++++++++++++++++
arch/arm/mach-spear13xx/spear13xx.c | 19 +++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/generic.h | 1 +
arch/arm/mach-spear3xx/spear300.c | 19 +++++++++++++++++++
arch/arm/mach-spear3xx/spear300_evb.c | 17 +++++++++++++++++
6 files changed, 74 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 6473316..0d21b79 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -33,6 +33,7 @@ extern struct amba_device spear13xx_uart_device;
extern struct platform_device spear13xx_ehci0_device;
extern struct platform_device spear13xx_ehci1_device;
extern struct platform_device spear13xx_i2c_device;
+extern struct platform_device spear13xx_kbd_device;
extern struct platform_device spear13xx_ohci0_device;
extern struct platform_device spear13xx_ohci1_device;
extern struct platform_device spear13xx_rtc_device;
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 1518044..2d4b4cf 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -16,6 +16,7 @@
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <plat/keyboard.h>
static struct amba_device *amba_devs[] __initdata = {
&spear13xx_uart_device,
@@ -25,15 +26,31 @@ static struct platform_device *plat_devs[] __initdata = {
&spear13xx_ehci0_device,
&spear13xx_ehci1_device,
&spear13xx_i2c_device,
+ &spear13xx_kbd_device,
&spear13xx_ohci0_device,
&spear13xx_ohci1_device,
&spear13xx_rtc_device,
};
+/* keyboard specific platform data */
+static DECLARE_KEYMAP(keymap);
+static struct matrix_keymap_data keymap_data = {
+ .keymap = keymap,
+ .keymap_size = ARRAY_SIZE(keymap),
+};
+
+static struct kbd_platform_data kbd_data = {
+ .keymap = &keymap_data,
+ .rep = 1,
+};
+
static void __init spear1300_evb_init(void)
{
unsigned int i;
+ /* set keyboard plat data */
+ kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
+
/* call spear1300 machine init function */
spear1300_init();
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index dc595a3..7357f0b 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -166,6 +166,25 @@ struct platform_device spear13xx_ohci1_device = {
.resource = ohci1_resources,
};
+/* keyboard device registration */
+static struct resource kbd_resources[] = {
+ {
+ .start = SPEAR13XX_KBD_BASE,
+ .end = SPEAR13XX_KBD_BASE + SZ_1K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_KBD,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear13xx_kbd_device = {
+ .name = "keyboard",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(kbd_resources),
+ .resource = kbd_resources,
+};
+
/* rtc device registration */
static struct resource rtc_resources[] = {
{
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index b65a884..e82a900 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -108,6 +108,7 @@ extern struct pmx_driver pmx_driver;
/* Add spear300 machine device structure declarations here */
extern struct amba_device clcd_device;
extern struct amba_device gpio1_device;
+extern struct platform_device kbd_device;
/* pad mux modes */
extern struct pmx_mode nand_mode;
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 1921cf8..fab998c 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -407,6 +407,25 @@ struct amba_device gpio1_device = {
.irq = {VIRQ_GPIO1, NO_IRQ},
};
+/* keyboard device registration */
+static struct resource kbd_resources[] = {
+ {
+ .start = SPEAR300_KEYBOARD_BASE,
+ .end = SPEAR300_KEYBOARD_BASE + SZ_1K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = VIRQ_KEYBOARD,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device kbd_device = {
+ .name = "keyboard",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(kbd_resources),
+ .resource = kbd_resources,
+};
+
/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
{
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index caa7000..330b677 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -15,6 +15,7 @@
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <plat/keyboard.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
@@ -51,6 +52,19 @@ static struct platform_device *plat_devs[] __initdata = {
&rtc_device,
/* spear300 specific devices */
+ &kbd_device,
+};
+
+/* keyboard specific platform data */
+static DECLARE_KEYMAP(keymap);
+static struct matrix_keymap_data keymap_data = {
+ .keymap = keymap,
+ .keymap_size = ARRAY_SIZE(keymap),
+};
+
+static struct kbd_platform_data kbd_data = {
+ .keymap = &keymap_data,
+ .rep = 1,
};
static void __init spear300_evb_init(void)
@@ -62,6 +76,9 @@ static void __init spear300_evb_init(void)
pmx_driver.devs = pmx_devs;
pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
+ /* set keyboard plat data */
+ kbd_set_plat_data(&kbd_device, &kbd_data);
+
/* call spear300 machine init function */
spear300_init();
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 21/62] ST SPEAr: Added ARM PL061 GPIO Support on SPEAr13xx and modified resource size
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (18 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 20/62] ST SPEAr: Adding machine support for keyboard Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 22/62] ST SPEAr: Adding support for ST's PWM IP Viresh Kumar
` (41 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 1 +
arch/arm/mach-spear13xx/include/mach/gpio.h | 18 +++++++++++
arch/arm/mach-spear13xx/include/mach/irqs.h | 10 ++++++-
arch/arm/mach-spear13xx/include/mach/spear.h | 4 +-
arch/arm/mach-spear13xx/spear1300_evb.c | 2 +
arch/arm/mach-spear13xx/spear13xx.c | 37 ++++++++++++++++++++++++
arch/arm/mach-spear3xx/spear300.c | 2 +-
arch/arm/mach-spear3xx/spear3xx.c | 2 +-
arch/arm/mach-spear6xx/spear6xx.c | 9 ++----
9 files changed, 74 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 0d21b79..2fc34f5 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -29,6 +29,7 @@
#define SPEAR_GPT0_CHAN1_IRQ IRQ_GPT0_TMR1
/* Add spear13xx family device structure declarations here */
+extern struct amba_device spear13xx_gpio_device[];
extern struct amba_device spear13xx_uart_device;
extern struct platform_device spear13xx_ehci0_device;
extern struct platform_device spear13xx_ehci1_device;
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
index 43fa541..2f8ad23 100644
--- a/arch/arm/mach-spear13xx/include/mach/gpio.h
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -16,4 +16,22 @@
#include <plat/gpio.h>
+#define GPIO0_0 0
+#define GPIO0_1 1
+#define GPIO0_2 2
+#define GPIO0_3 3
+#define GPIO0_4 4
+#define GPIO0_5 5
+#define GPIO0_6 6
+#define GPIO0_7 7
+
+#define GPIO1_0 8
+#define GPIO1_1 9
+#define GPIO1_2 10
+#define GPIO1_3 11
+#define GPIO1_4 12
+#define GPIO1_5 13
+#define GPIO1_6 14
+#define GPIO1_7 15
+
#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
index 036bfc6..10b64c1 100644
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -86,6 +86,14 @@
#define IRQ_GIC_END (IRQ_SHPI_START + 128)
-#define NR_IRQS IRQ_GIC_END
+#define VIRQ_START IRQ_GIC_END
+
+/* GPIO pins virtual irqs */
+#define SPEAR_GPIO0_INT_BASE (VIRQ_START + 0)
+#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
+#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
+
+#define VIRQ_END SPEAR_GPIO_INT_END
+#define NR_IRQS VIRQ_END
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index d4b11a4..282ef2f 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -43,8 +43,8 @@
#define SPEAR13XX_GPT2_BASE 0xE0480000
#define SPEAR13XX_GPT3_BASE 0xE0500000
#define SPEAR13XX_RTC_BASE 0xE0580000
-#define SPEAR13XX_GPIOA_BASE 0xE0600000
-#define SPEAR13XX_GPIOB_BASE 0xE0680000
+#define SPEAR13XX_GPIO0_BASE 0xE0600000
+#define SPEAR13XX_GPIO1_BASE 0xE0680000
#define SPEAR13XX_MISC_BASE 0xE0700000
#define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 2d4b4cf..f2449ef 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -19,6 +19,8 @@
#include <plat/keyboard.h>
static struct amba_device *amba_devs[] __initdata = {
+ &spear13xx_gpio_device[0],
+ &spear13xx_gpio_device[1],
&spear13xx_uart_device,
};
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 7357f0b..c333a1d 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -12,6 +12,7 @@
*/
#include <linux/types.h>
+#include <linux/amba/pl061.h>
#include <linux/ptrace.h>
#include <linux/io.h>
#include <asm/hardware/gic.h>
@@ -24,6 +25,42 @@
#include <mach/hardware.h>
/* Add spear13xx machines common devices here */
+/* gpio device registeration */
+static struct pl061_platform_data gpio_plat_data[] = {
+ {
+ .gpio_base = 0,
+ .irq_base = SPEAR_GPIO0_INT_BASE,
+ }, {
+ .gpio_base = 8,
+ .irq_base = SPEAR_GPIO1_INT_BASE,
+ },
+};
+
+struct amba_device spear13xx_gpio_device[] = {
+ {
+ .dev = {
+ .init_name = "gpio0",
+ .platform_data = &gpio_plat_data[0],
+ },
+ .res = {
+ .start = SPEAR13XX_GPIO0_BASE,
+ .end = SPEAR13XX_GPIO0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_GPIO0, NO_IRQ},
+ }, {
+ .dev = {
+ .init_name = "gpio1",
+ .platform_data = &gpio_plat_data[1],
+ },
+ .res = {
+ .start = SPEAR13XX_GPIO1_BASE,
+ .end = SPEAR13XX_GPIO1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_GPIO1, NO_IRQ},
+ }
+};
/* uart device registeration */
struct amba_device spear13xx_uart_device = {
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index fab998c..95946b3 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -401,7 +401,7 @@ struct amba_device gpio1_device = {
},
.res = {
.start = SPEAR300_GPIO_BASE,
- .end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1,
+ .end = SPEAR300_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.irq = {VIRQ_GPIO1, NO_IRQ},
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 568f365..93be834 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -35,7 +35,7 @@ struct amba_device gpio_device = {
},
.res = {
.start = SPEAR3XX_ICM3_GPIO_BASE,
- .end = SPEAR3XX_ICM3_GPIO_BASE + SPEAR3XX_ICM3_GPIO_SIZE - 1,
+ .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.irq = {IRQ_BASIC_GPIO, NO_IRQ},
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 5a9763f..c6c9dfb 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -89,8 +89,7 @@ struct amba_device gpio_device[] = {
},
.res = {
.start = SPEAR6XX_CPU_GPIO_BASE,
- .end = SPEAR6XX_CPU_GPIO_BASE +
- SPEAR6XX_CPU_GPIO_SIZE - 1,
+ .end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.irq = {IRQ_LOCAL_GPIO, NO_IRQ},
@@ -101,8 +100,7 @@ struct amba_device gpio_device[] = {
},
.res = {
.start = SPEAR6XX_ICM3_GPIO_BASE,
- .end = SPEAR6XX_ICM3_GPIO_BASE +
- SPEAR6XX_ICM3_GPIO_SIZE - 1,
+ .end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.irq = {IRQ_BASIC_GPIO, NO_IRQ},
@@ -113,8 +111,7 @@ struct amba_device gpio_device[] = {
},
.res = {
.start = SPEAR6XX_ICM2_GPIO_BASE,
- .end = SPEAR6XX_ICM2_GPIO_BASE +
- SPEAR6XX_ICM2_GPIO_SIZE - 1,
+ .end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.irq = {IRQ_APPL_GPIO, NO_IRQ},
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 22/62] ST SPEAr: Adding support for ST's PWM IP
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (19 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 21/62] ST SPEAr: Added ARM PL061 GPIO Support on SPEAr13xx and modified resource size Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 23/62] ST SPEAr: Adding Watchdog support Viresh Kumar
` (40 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 1 +
arch/arm/mach-spear3xx/spear320.c | 17 +
arch/arm/mach-spear3xx/spear320_evb.c | 1 +
arch/arm/plat-spear/Kconfig | 7 +
arch/arm/plat-spear/Makefile | 1 +
arch/arm/plat-spear/pwm.c | 484 +++++++++++++++++++++++++
6 files changed, 511 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-spear/pwm.c
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index e82a900..21a4ac0 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -174,6 +174,7 @@ void __init spear310_init(void);
extern struct amba_device clcd_device;
extern struct platform_device i2c1_device;
extern struct platform_device plgpio_device;
+extern struct platform_device pwm_device;
/* pad mux modes */
extern struct pmx_mode auto_net_smii_mode;
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 689b27a..46c9769 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -452,6 +452,23 @@ struct platform_device plgpio_device = {
.resource = plgpio_resources,
};
+/* pwm device registeration */
+static struct resource pwm_resources[] = {
+ {
+ .start = SPEAR320_PWM_BASE,
+ .end = SPEAR320_PWM_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device pwm_device = {
+ .name = "pwm",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(pwm_resources),
+ .resource = pwm_resources,
+};
+
+
/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
{
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 7bfe609..eedcdd7 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -57,6 +57,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear320 specific devices */
&i2c1_device,
&plgpio_device,
+ &pwm_device,
};
static void __init spear320_evb_init(void)
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 29a25d2..80f402b 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -36,4 +36,11 @@ source "arch/arm/mach-spear13xx/Kconfig"
source "arch/arm/mach-spear3xx/Kconfig"
source "arch/arm/mach-spear6xx/Kconfig"
+config SPEAR_PWM
+ tristate "SPEAr Pulse Width Modulator"
+ depends on MACH_SPEAR320
+ default y
+ help
+ Support for ST Microelectronics Pulse Width Modulator present on SPEAr Platform.
+
endif
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index c31892a..0e29587 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -8,6 +8,7 @@ obj-y := clcd.o clock.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
obj-$(CONFIG_MACH_SPEAR320) += plgpio.o
+obj-$(CONFIG_SPEAR_PWM) += pwm.o
obj-$(CONFIG_BOARD_SPEAR1300_EVB) += i2c_eval_board.o
obj-$(CONFIG_BOARD_SPEAR300_EVB) += i2c_eval_board.o
diff --git a/arch/arm/plat-spear/pwm.c b/arch/arm/plat-spear/pwm.c
new file mode 100644
index 0000000..307c725
--- /dev/null
+++ b/arch/arm/plat-spear/pwm.c
@@ -0,0 +1,484 @@
+/*
+ * arch/arm/plat-spear/pwm.c
+ *
+ * ST Microelectronics SPEAr Pulse Width Modulator driver
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+/* PWM registers and bits definitions */
+#define PWMCR 0x00
+#define PWMDCR 0x04
+#define PWMPCR 0x08
+
+#define PWM_EN_MASK 0x1
+#define MIN_PRESCALE 0x00
+#define MAX_PRESCALE 0x3FFF
+#define PRESCALE_SHIFT 2
+#define MIN_DUTY 0x0001
+#define MAX_DUTY 0xFFFF
+#define MAX_PERIOD 0xFFFF
+#define MIN_PERIOD 0x0001
+
+#define PWM_DEVICE_PER_IP 4
+#define PWM_DEVICE_OFFSET 0x10
+
+/* lock for pwm_list */
+static DEFINE_SPINLOCK(list_lock);
+/* list of all pwm ips available in system */
+static LIST_HEAD(pwm_list);
+
+/**
+ * struct pwm_device: struct representing pwm device/channel
+ *
+ * pwmd_id: id of pwm device
+ * pwm: pointer to parent pwm ip
+ * label: used for storing label passed in pwm_request
+ * offset: base address offset from parent pwm mmio_base
+ * busy: represents usage status of a pwm device
+ * lock: lock specific to a pwm device
+ * node: node for adding device to parent pwm's devices list
+ *
+ * Each pwm IP contains four independent pwm device/channels. Some or all of
+ * which may be present in our configuration.
+ */
+struct pwm_device {
+ unsigned pwmd_id;
+ struct pwm *pwm;
+ const char *label;
+ unsigned offset;
+ unsigned busy;
+ spinlock_t lock;
+ struct list_head node;
+};
+
+/**
+ * struct pwm: struct representing pwm ip
+ *
+ * id: id of pwm ip
+ * mmio_base: base address of pwm
+ * clk: pointer to clk structure of pwm ip
+ * clk_enabled: clock enable status
+ * pdev: pointer to pdev structure of pwm
+ * lock: lock specific to current pwm ip
+ * devices: list of devices/childrens of pwm ip
+ * node: node for adding pwm to global list of all pwm ips
+ */
+struct pwm {
+ unsigned id;
+ void __iomem *mmio_base;
+ struct clk *clk;
+ int clk_enabled;
+ struct platform_device *pdev;
+ spinlock_t lock;
+ struct list_head devices;
+ struct list_head node;
+};
+
+/*
+ * period_ns = 10^9 * (PRESCALE + 1) * PV / PWM_CLK_RATE
+ * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
+ *
+ * PV = (PWM_CLK_RATE * period_ns)/ (10^9 * (PRESCALE + 1))
+ * DC = (PWM_CLK_RATE * duty_ns)/ (10^9 * (PRESCALE + 1))
+ */
+int pwm_config(struct pwm_device *pwmd, int duty_ns, int period_ns)
+{
+ u64 val, div, clk_rate;
+ unsigned long prescale = MIN_PRESCALE, pv, dc;
+ int ret = 0;
+
+ if (!pwmd) {
+ pr_err("pwm: config - NULL pwm device pointer\n");
+ return -EFAULT;
+ }
+
+ if (period_ns == 0 || duty_ns > period_ns) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* TODO: Need to optimize this loop */
+ while (1) {
+ div = 1000000000;
+ div *= 1 + prescale;
+ clk_rate = clk_get_rate(pwmd->pwm->clk);
+ val = clk_rate * period_ns;
+ pv = div64_u64(val, div);
+ val = clk_rate * duty_ns;
+ dc = div64_u64(val, div);
+
+ if ((pv == 0) || (dc == 0)) {
+ ret = -EINVAL;
+ goto err;
+ }
+ if ((pv > MAX_PERIOD) || (dc > MAX_DUTY)) {
+ prescale++;
+ if (prescale > MAX_PRESCALE) {
+ ret = -EINVAL;
+ goto err;
+ }
+ continue;
+ }
+ if ((pv < MIN_PERIOD) || (dc < MIN_DUTY)) {
+ ret = -EINVAL;
+ goto err;
+ }
+ break;
+ }
+
+ /*
+ * NOTE: the clock to PWM has to be enabled first
+ * before writing to the registers
+ */
+ spin_lock(&pwmd->pwm->lock);
+ ret = clk_enable(pwmd->pwm->clk);
+ if (ret) {
+ spin_unlock(&pwmd->pwm->lock);
+ goto err;
+ }
+
+ spin_lock(&pwmd->lock);
+ writel(prescale << PRESCALE_SHIFT, pwmd->pwm->mmio_base +
+ pwmd->offset + PWMCR);
+ writel(dc, pwmd->pwm->mmio_base + pwmd->offset + PWMDCR);
+ writel(pv, pwmd->pwm->mmio_base + pwmd->offset + PWMPCR);
+ spin_unlock(&pwmd->lock);
+ clk_disable(pwmd->pwm->clk);
+ spin_unlock(&pwmd->pwm->lock);
+
+ return 0;
+err:
+ dev_err(&pwmd->pwm->pdev->dev, "pwm config fail\n");
+ return ret;
+}
+EXPORT_SYMBOL(pwm_config);
+
+int pwm_enable(struct pwm_device *pwmd)
+{
+ int ret = 0;
+ u32 val = 0;
+
+ if (!pwmd) {
+ pr_err("pwm: enable - NULL pwm device pointer\n");
+ return -EFAULT;
+ }
+
+ spin_lock(&pwmd->pwm->lock);
+ ret = clk_enable(pwmd->pwm->clk);
+ if (!ret)
+ pwmd->pwm->clk_enabled++;
+ else {
+ spin_unlock(&pwmd->pwm->lock);
+ goto err;
+ }
+
+ spin_lock(&pwmd->lock);
+ val = readl(pwmd->pwm->mmio_base + pwmd->offset + PWMCR);
+ writel(val | PWM_EN_MASK, pwmd->pwm->mmio_base + pwmd->offset + PWMCR);
+ spin_unlock(&pwmd->lock);
+ spin_unlock(&pwmd->pwm->lock);
+ return 0;
+err:
+ dev_err(&pwmd->pwm->pdev->dev, "pwm enable fail\n");
+ return ret;
+}
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwmd)
+{
+ if (!pwmd) {
+ pr_err("pwm: disable - NULL pwm device pointer\n");
+ return;
+ }
+
+ spin_lock(&pwmd->pwm->lock);
+ spin_lock(&pwmd->lock);
+ writel(0, pwmd->pwm->mmio_base + pwmd->offset + PWMCR);
+ if (pwmd->pwm->clk_enabled) {
+ clk_disable(pwmd->pwm->clk);
+ pwmd->pwm->clk_enabled--;
+ }
+ spin_unlock(&pwmd->lock);
+ spin_unlock(&pwmd->pwm->lock);
+}
+EXPORT_SYMBOL(pwm_disable);
+
+struct pwm_device *pwm_request(int pwmd_id, const char *label)
+{
+ int found = 0;
+ struct pwm *pwm;
+ struct pwm_device *pwmd = NULL;
+
+ spin_lock(&list_lock);
+ list_for_each_entry(pwm, &pwm_list, node) {
+ spin_lock(&pwm->lock);
+ list_for_each_entry(pwmd, &pwm->devices, node) {
+ if (pwmd->pwmd_id == pwmd_id) {
+ found = 1;
+ break;
+ }
+ }
+ spin_unlock(&pwm->lock);
+ if (found)
+ break;
+ }
+ spin_unlock(&list_lock);
+
+ if (found) {
+ spin_lock(&pwmd->lock);
+ if (pwmd->busy == 0) {
+ pwmd->busy++;
+ pwmd->label = label;
+ } else
+ pwmd = ERR_PTR(-EBUSY);
+ spin_unlock(&pwmd->lock);
+ } else
+ pwmd = ERR_PTR(-ENOENT);
+
+ if (IS_ERR(pwmd))
+ pr_err("pwm: request fail\n");
+
+ return pwmd;
+}
+EXPORT_SYMBOL(pwm_request);
+
+void pwm_free(struct pwm_device *pwmd)
+{
+ if (!pwmd) {
+ pr_err("pwm: disable - NULL pwm device pointer\n");
+ return;
+ }
+
+ spin_lock(&pwmd->lock);
+ if (pwmd->busy) {
+ pwmd->busy--;
+ pwmd->label = NULL;
+ } else {
+ spin_unlock(&pwmd->lock);
+ dev_warn(&pwmd->pwm->pdev->dev, "pwm device already freed\n");
+ return;
+ }
+
+ spin_unlock(&pwmd->lock);
+}
+EXPORT_SYMBOL(pwm_free);
+
+/* creates and add pwmd device to parent pwm's devices list */
+static int add_pwm_device(unsigned int pwmd_id, struct pwm *pwm)
+{
+ struct pwm_device *pwmd;
+
+ pwmd = kzalloc(sizeof(*pwmd), GFP_KERNEL);
+ if (!pwmd)
+ return -ENOMEM;
+
+ pwmd->pwm = pwm;
+ pwmd->busy = 0;
+ pwmd->pwmd_id = pwmd_id + pwm->id * PWM_DEVICE_PER_IP;
+ pwmd->offset = pwmd_id * PWM_DEVICE_OFFSET;
+ spin_lock_init(&pwmd->lock);
+
+ spin_lock(&pwm->lock);
+ list_add_tail(&pwmd->node, &pwm->devices);
+ spin_unlock(&pwm->lock);
+
+ return 0;
+}
+
+/* removes all pwmd devices from parent pwm's devices list */
+static void remove_pwm_devices(struct pwm *pwm)
+{
+ struct pwm_device *pwmd;
+
+ spin_lock(&pwm->lock);
+ list_for_each_entry(pwmd, &pwm->devices, node) {
+ list_del(&pwmd->node);
+ kfree(pwmd);
+ }
+ spin_unlock(&pwm->lock);
+}
+
+static int __devinit spear_pwm_probe(struct platform_device *pdev)
+{
+ struct pwm *pwm = NULL;
+ struct resource *res;
+ int ret = 0, pwmd_id = 0;
+
+ pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
+ if (!pwm) {
+ ret = -ENOMEM;
+ dev_dbg(&pdev->dev, "failed to allocate memory\n");
+ goto err;
+ }
+
+ pwm->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {
+ ret = PTR_ERR(pwm->clk);
+ dev_dbg(&pdev->dev, "Error getting clock\n");
+ goto err_free;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "no memory resource defined\n");
+ goto err_free_clk;
+ }
+
+ if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+ ret = -EBUSY;
+ dev_dbg(&pdev->dev, "failed to request memory resource\n");
+ goto err_free_clk;
+ }
+
+ pwm->mmio_base = ioremap(res->start, resource_size(res));
+ if (!pwm->mmio_base) {
+ ret = -ENOMEM;
+ dev_dbg(&pdev->dev, "failed to ioremap\n");
+ goto err_free_mem;
+ }
+
+ /* initialize pwm structure */
+ pwm->clk_enabled = 0;
+ pwm->pdev = pdev;
+ /* if pdev->id is -1, only one pwm ip is present */
+ if (pdev->id == -1)
+ pwm->id = 0;
+ else
+ pwm->id = pdev->id;
+
+ spin_lock_init(&pwm->lock);
+ INIT_LIST_HEAD(&pwm->devices);
+ platform_set_drvdata(pdev, pwm);
+
+ /* add pwm to pwm list */
+ spin_lock(&list_lock);
+ list_add_tail(&pwm->node, &pwm_list);
+ spin_unlock(&list_lock);
+
+ /* add pwm devices */
+ for (pwmd_id = 0; pwmd_id < PWM_DEVICE_PER_IP; pwmd_id++) {
+ ret = add_pwm_device(pwmd_id, pwm);
+ if (!ret)
+ continue;
+ dev_err(&pdev->dev, "Add device fail for pwm device id: %d\n",
+ pwmd_id);
+ }
+
+ if (list_empty(&pwm->node))
+ goto err_remove_pwm;
+
+ dev_info(&pdev->dev, "Initialization successful\n");
+ return 0;
+
+err_remove_pwm:
+ spin_lock(&list_lock);
+ list_del(&pwm->node);
+ spin_unlock(&list_lock);
+
+ platform_set_drvdata(pdev, NULL);
+ iounmap(pwm->mmio_base);
+err_free_mem:
+ release_mem_region(res->start, resource_size(res));
+err_free_clk:
+ clk_put(pwm->clk);
+err_free:
+ kfree(pwm);
+err:
+ dev_err(&pdev->dev, "Initialization Fail. Error: %d\n", ret);
+
+ return ret;
+}
+
+static int __devexit spear_pwm_remove(struct platform_device *pdev)
+{
+ struct pwm *pwm;
+ struct resource *res;
+ int ret = 0;
+
+ pwm = platform_get_drvdata(pdev);
+ if (pwm == NULL) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "Remove: get_drvdata fail\n");
+ goto err;
+ }
+ platform_set_drvdata(pdev, NULL);
+
+ /* remove pwm devices */
+ remove_pwm_devices(pwm);
+
+ /* remove pwm from pwm_list */
+ spin_lock(&list_lock);
+ list_del(&pwm->node);
+ spin_unlock(&list_lock);
+
+ iounmap(pwm->mmio_base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "Remove: get_resource fail\n");
+ goto err;
+ }
+ release_mem_region(res->start, resource_size(res));
+
+ if (pwm->clk_enabled)
+ clk_disable(pwm->clk);
+ clk_put(pwm->clk);
+
+ kfree(pwm);
+ return 0;
+
+err:
+ dev_err(&pdev->dev, "Remove: Fail - %d\n", ret);
+ return ret;
+}
+
+static struct platform_driver spear_pwm_driver = {
+ .driver = {
+ .name = "pwm",
+ .bus = &platform_bus_type,
+ .owner = THIS_MODULE,
+ },
+ .probe = spear_pwm_probe,
+ .remove = __devexit_p(spear_pwm_remove)
+};
+
+static int __init spear_pwm_init(void)
+{
+ int ret = 0;
+
+ ret = platform_driver_register(&spear_pwm_driver);
+ if (ret)
+ pr_err("failed to register spear_pwm_driver\n");
+
+ return ret;
+}
+module_init(spear_pwm_init);
+
+static void __exit spear_pwm_exit(void)
+{
+ platform_driver_unregister(&spear_pwm_driver);
+}
+module_exit(spear_pwm_exit);
+
+MODULE_AUTHOR("Viresh Kumar");
+MODULE_DESCRIPTION("SPEAr PWM Driver");
+MODULE_LICENSE("GPL");
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 23/62] ST SPEAr: Adding Watchdog support
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (20 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 22/62] ST SPEAr: Adding support for ST's PWM IP Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 24/62] ST SPEAr: Adding machine support for nand Viresh Kumar
` (39 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 1 +
arch/arm/mach-spear3xx/spear300_evb.c | 1 +
arch/arm/mach-spear3xx/spear310_evb.c | 1 +
arch/arm/mach-spear3xx/spear320_evb.c | 1 +
arch/arm/mach-spear3xx/spear3xx.c | 12 ++++++++++++
arch/arm/mach-spear6xx/include/mach/generic.h | 1 +
arch/arm/mach-spear6xx/spear600_evb.c | 1 +
arch/arm/mach-spear6xx/spear6xx.c | 12 ++++++++++++
8 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 21a4ac0..3400ecd 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -33,6 +33,7 @@
/* Add spear3xx family device structure declarations here */
extern struct amba_device gpio_device;
extern struct amba_device uart_device;
+extern struct amba_device wdt_device;
extern struct platform_device ehci_device;
extern struct platform_device i2c_device;
extern struct platform_device ohci0_device;
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 330b677..abbc802 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -37,6 +37,7 @@ static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&gpio_device,
&uart_device,
+ &wdt_device,
/* spear300 specific devices */
&clcd_device,
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 7b7a236..6c00695 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -44,6 +44,7 @@ static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&gpio_device,
&uart_device,
+ &wdt_device,
/* spear310 specific devices */
};
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index eedcdd7..d371b31 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -41,6 +41,7 @@ static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&gpio_device,
&uart_device,
+ &wdt_device,
/* spear320 specific devices */
&clcd_device,
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 93be834..561949d 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -54,6 +54,18 @@ struct amba_device uart_device = {
.irq = {IRQ_UART, NO_IRQ},
};
+/* watchdog device registeration */
+struct amba_device wdt_device = {
+ .dev = {
+ .init_name = "wdt",
+ },
+ .res = {
+ .start = SPEAR3XX_ICM3_WDT_BASE,
+ .end = SPEAR3XX_ICM3_WDT_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
/* i2c device registeration */
static struct resource i2c_resources[] = {
{
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index ed1dbfc..112cc9b 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -32,6 +32,7 @@
extern struct amba_device clcd_device;
extern struct amba_device gpio_device[];
extern struct amba_device uart_device[];
+extern struct amba_device wdt_device;
extern struct platform_device ehci0_device;
extern struct platform_device ehci1_device;
extern struct platform_device i2c_device;
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index be4e5c9..7ec09b6 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -23,6 +23,7 @@ static struct amba_device *amba_devs[] __initdata = {
&gpio_device[2],
&uart_device[0],
&uart_device[1],
+ &wdt_device,
};
static struct platform_device *plat_devs[] __initdata = {
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index c6c9dfb..4801fc7 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -118,6 +118,18 @@ struct amba_device gpio_device[] = {
}
};
+/* watchdog device registeration */
+struct amba_device wdt_device = {
+ .dev = {
+ .init_name = "wdt",
+ },
+ .res = {
+ .start = SPEAR6XX_ICM3_WDT_BASE,
+ .end = SPEAR6XX_ICM3_WDT_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
/* i2c device registeration */
static struct resource i2c_resources[] = {
{
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 24/62] ST SPEAr: Adding machine support for nand
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (21 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 23/62] ST SPEAr: Adding Watchdog support Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 25/62] ST SPEAr: Added PCIE host controller base driver support Viresh Kumar
` (38 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 2 +
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 10 ++
arch/arm/mach-spear13xx/spear1300_evb.c | 9 ++
arch/arm/mach-spear13xx/spear13xx.c | 58 +++++++++++++
arch/arm/mach-spear3xx/include/mach/generic.h | 15 ++--
arch/arm/mach-spear3xx/include/mach/spear320.h | 3 +
arch/arm/mach-spear3xx/spear300.c | 98 ++++++++++++++++++++++
arch/arm/mach-spear3xx/spear300_evb.c | 8 ++
arch/arm/mach-spear3xx/spear310.c | 26 ++++++
arch/arm/mach-spear3xx/spear310_evb.c | 8 ++
arch/arm/mach-spear3xx/spear320.c | 26 ++++++
arch/arm/mach-spear3xx/spear320_evb.c | 8 ++
arch/arm/mach-spear6xx/include/mach/generic.h | 1 +
arch/arm/mach-spear6xx/spear600_evb.c | 8 ++
arch/arm/mach-spear6xx/spear6xx.c | 26 ++++++
arch/arm/plat-spear/include/plat/fsmc.h | 36 ++++++++
16 files changed, 336 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/plat-spear/include/plat/fsmc.h
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 2fc34f5..77b3c15 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -35,6 +35,7 @@ extern struct platform_device spear13xx_ehci0_device;
extern struct platform_device spear13xx_ehci1_device;
extern struct platform_device spear13xx_i2c_device;
extern struct platform_device spear13xx_kbd_device;
+extern struct platform_device spear13xx_nand_device;
extern struct platform_device spear13xx_ohci0_device;
extern struct platform_device spear13xx_ohci1_device;
extern struct platform_device spear13xx_rtc_device;
@@ -50,6 +51,7 @@ void __init spear1300_init(void);
void __init spear13xx_map_io(void);
void __init spear13xx_init_irq(void);
void __init spear13xx_init(void);
+void __init nand_mach_init(u32 busw);
void spear13xx_secondary_startup(void);
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
index a8a1119..e6823db 100644
--- a/arch/arm/mach-spear13xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -210,6 +210,16 @@
#define CF_MMC_ACTIVE 0x2
#define XD_MMC_ACTIVE 0x3
#define FSMC_CFG ((unsigned int *)(MISC_BASE + 0x330))
+ /* FSMC_CFG register masks */
+ #define FSMC_MEMSEL_MASK 0x3
+ #define FSMC_MEMSEL_SHIFT 0
+ #define FSMC_MEM_NOR 0
+ #define FSMC_MEM_NAND 1
+ #define FSMC_MEM_SRAM 2
+ #define NAND_BANK_MASK 0x3
+ #define NAND_BANK_SHIFT 2
+ #define NAND_DEV_WIDTH16 4
+
#define MPMC_CTR_STS ((unsigned int *)(MISC_BASE + 0x334))
/* Inter-Processor Communication Registers */
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index f2449ef..df063e9 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -12,11 +12,14 @@
*/
#include <linux/types.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/spear.h>
#include <plat/keyboard.h>
+#include <plat/fsmc.h>
static struct amba_device *amba_devs[] __initdata = {
&spear13xx_gpio_device[0],
@@ -29,6 +32,7 @@ static struct platform_device *plat_devs[] __initdata = {
&spear13xx_ehci1_device,
&spear13xx_i2c_device,
&spear13xx_kbd_device,
+ &spear13xx_nand_device,
&spear13xx_ohci0_device,
&spear13xx_ohci1_device,
&spear13xx_rtc_device,
@@ -53,6 +57,11 @@ static void __init spear1300_evb_init(void)
/* set keyboard plat data */
kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
+ /* set nand device's plat data */
+ fsmc_nand_set_plat_data(&spear13xx_nand_device, NULL, 0,
+ NAND_SKIP_BBTSCAN, FSMC_NAND_BW8);
+ nand_mach_init(FSMC_NAND_BW8);
+
/* call spear1300 machine init function */
spear1300_init();
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index c333a1d..6352d88 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -15,6 +15,7 @@
#include <linux/amba/pl061.h>
#include <linux/ptrace.h>
#include <linux/io.h>
+#include <linux/mtd/fsmc.h>
#include <asm/hardware/gic.h>
#include <asm/irq.h>
#include <asm/localtimer.h>
@@ -23,6 +24,7 @@
#include <mach/irqs.h>
#include <mach/generic.h>
#include <mach/hardware.h>
+#include <mach/misc_regs.h>
/* Add spear13xx machines common devices here */
/* gpio device registeration */
@@ -97,6 +99,62 @@ struct platform_device spear13xx_i2c_device = {
.resource = i2c_resources,
};
+/* nand device registeration */
+void __init nand_mach_init(u32 busw)
+{
+ u32 fsmc_cfg = readl(FSMC_CFG);
+ fsmc_cfg &= ~(FSMC_MEMSEL_MASK << FSMC_MEMSEL_SHIFT);
+ fsmc_cfg |= (FSMC_MEM_NAND << FSMC_MEMSEL_SHIFT);
+
+ if (busw == FSMC_NAND_BW16)
+ fsmc_cfg |= 1 << NAND_DEV_WIDTH16;
+ else
+ fsmc_cfg &= ~(1 << NAND_DEV_WIDTH16);
+
+ writel(fsmc_cfg, FSMC_CFG);
+}
+
+static void nand_select_bank(u32 bank, u32 busw)
+{
+ u32 fsmc_cfg = readl(FSMC_CFG);
+
+ fsmc_cfg &= ~(NAND_BANK_MASK << NAND_BANK_SHIFT);
+ fsmc_cfg |= (bank << NAND_BANK_SHIFT);
+
+ if (busw)
+ fsmc_cfg |= 1 << NAND_DEV_WIDTH16;
+ else
+ fsmc_cfg &= ~(1 << NAND_DEV_WIDTH16);
+
+ writel(fsmc_cfg, FSMC_CFG);
+}
+
+static struct fsmc_nand_platform_data nand_platform_data = {
+ .select_bank = nand_select_bank,
+};
+
+static struct resource nand_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR13XX_FSMC_MEM_BASE,
+ .end = SPEAR13XX_FSMC_MEM_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR13XX_FSMC_BASE,
+ .end = SPEAR13XX_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device spear13xx_nand_device = {
+ .name = "nand",
+ .id = -1,
+ .resource = nand_resources,
+ .num_resources = ARRAY_SIZE(nand_resources),
+ .dev.platform_data = &nand_platform_data,
+};
+
/* usb host device registeration */
static struct resource ehci0_resources[] = {
[0] = {
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 3400ecd..2e5ecbf 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -110,6 +110,10 @@ extern struct pmx_driver pmx_driver;
extern struct amba_device clcd_device;
extern struct amba_device gpio1_device;
extern struct platform_device kbd_device;
+extern struct platform_device nand0_device;
+extern struct platform_device nand1_device;
+extern struct platform_device nand2_device;
+extern struct platform_device nand3_device;
/* pad mux modes */
extern struct pmx_mode nand_mode;
@@ -147,12 +151,12 @@ void __init spear300_init(void);
/* Add misc structure declarations here */
extern struct clcd_board clcd_plat_data;
-#endif /* CONFIG_MACH_SPEAR300 */
/* spear310 declarations */
-#ifdef CONFIG_MACH_SPEAR310
+#elif defined(CONFIG_MACH_SPEAR310)
/* Add spear310 machine device structure declarations here */
extern struct platform_device plgpio_device;
+extern struct platform_device nand_device;
/* pad mux devices */
extern struct pmx_dev pmx_emi_cs_0_1_4_5;
@@ -167,13 +171,12 @@ extern struct pmx_dev pmx_tdm0;
/* Add spear310 machine function declarations here */
void __init spear310_init(void);
-#endif /* CONFIG_MACH_SPEAR310 */
-
/* spear320 declarations */
-#ifdef CONFIG_MACH_SPEAR320
+#elif defined(CONFIG_MACH_SPEAR320)
/* Add spear320 machine device structure declarations here */
extern struct amba_device clcd_device;
extern struct platform_device i2c1_device;
+extern struct platform_device nand_device;
extern struct platform_device plgpio_device;
extern struct platform_device pwm_device;
@@ -212,6 +215,6 @@ void __init spear320_init(void);
/* Add misc structure declarations here */
extern struct clcd_board clcd_plat_data;
-#endif /* CONFIG_MACH_SPEAR320 */
+#endif
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 53677e4..aa6727c 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -22,6 +22,9 @@
#define SPEAR320_FSMC_BASE 0x4C000000
#define SPEAR320_FSMC_SIZE 0x01000000
+#define SPEAR320_NAND_BASE 0x50000000
+#define SPEAR320_NAND_SIZE 0x04000000
+
#define SPEAR320_I2S_BASE 0x60000000
#define SPEAR320_I2S_SIZE 0x10000000
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 95946b3..58b3e44 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -14,6 +14,7 @@
#include <linux/types.h>
#include <linux/amba/pl061.h>
#include <linux/ptrace.h>
+#include <linux/mtd/fsmc.h>
#include <asm/irq.h>
#include <mach/generic.h>
#include <mach/spear.h>
@@ -426,6 +427,103 @@ struct platform_device kbd_device = {
.resource = kbd_resources,
};
+/* nand device registeration */
+static struct fsmc_nand_platform_data nand0_platform_data;
+
+static struct resource nand0_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR300_NAND_0_BASE,
+ .end = SPEAR300_NAND_0_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR300_FSMC_BASE,
+ .end = SPEAR300_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device nand0_device = {
+ .name = "nand",
+ .id = 0,
+ .resource = nand0_resources,
+ .num_resources = ARRAY_SIZE(nand0_resources),
+ .dev.platform_data = &nand0_platform_data,
+};
+
+static struct fsmc_nand_platform_data nand1_platform_data;
+
+static struct resource nand1_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR300_NAND_1_BASE,
+ .end = SPEAR300_NAND_1_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR300_FSMC_BASE,
+ .end = SPEAR300_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device nand1_device = {
+ .name = "nand",
+ .id = 1,
+ .resource = nand1_resources,
+ .num_resources = ARRAY_SIZE(nand1_resources),
+ .dev.platform_data = &nand1_platform_data,
+};
+
+static struct fsmc_nand_platform_data nand2_platform_data;
+
+static struct resource nand2_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR300_NAND_2_BASE,
+ .end = SPEAR300_NAND_2_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR300_FSMC_BASE,
+ .end = SPEAR300_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device nand2_device = {
+ .name = "nand",
+ .id = 2,
+ .resource = nand2_resources,
+ .num_resources = ARRAY_SIZE(nand2_resources),
+ .dev.platform_data = &nand2_platform_data,
+};
+
+static struct fsmc_nand_platform_data nand3_platform_data;
+
+static struct resource nand3_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR300_NAND_3_BASE,
+ .end = SPEAR300_NAND_3_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR300_FSMC_BASE,
+ .end = SPEAR300_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device nand3_device = {
+ .name = "nand",
+ .id = 3,
+ .resource = nand3_resources,
+ .num_resources = ARRAY_SIZE(nand3_resources),
+ .dev.platform_data = &nand3_platform_data,
+};
+
/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
{
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index abbc802..c219691 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -11,10 +11,13 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <plat/fsmc.h>
#include <plat/keyboard.h>
/* padmux devices to enable */
@@ -48,6 +51,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
&ehci_device,
&i2c_device,
+ &nand0_device,
&ohci0_device,
&ohci1_device,
&rtc_device,
@@ -80,6 +84,10 @@ static void __init spear300_evb_init(void)
/* set keyboard plat data */
kbd_set_plat_data(&kbd_device, &kbd_data);
+ /* set nand0 device's plat data */
+ fsmc_nand_set_plat_data(&nand0_device, NULL, 0, NAND_SKIP_BBTSCAN,
+ FSMC_NAND_BW8);
+
/* call spear300 machine init function */
spear300_init();
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 3a3acea..bb9ff7c 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -12,6 +12,7 @@
*/
#include <linux/ptrace.h>
+#include <linux/mtd/fsmc.h>
#include <asm/irq.h>
#include <mach/generic.h>
#include <mach/spear.h>
@@ -177,6 +178,31 @@ int spear300_o2p(int offset)
return offset + 2;
}
+/* nand device registeration */
+static struct fsmc_nand_platform_data nand_platform_data;
+
+static struct resource nand_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR310_NAND_BASE,
+ .end = SPEAR310_NAND_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR310_FSMC_BASE,
+ .end = SPEAR310_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device nand_device = {
+ .name = "nand",
+ .id = -1,
+ .resource = nand_resources,
+ .num_resources = ARRAY_SIZE(nand_resources),
+ .dev.platform_data = &nand_platform_data,
+};
+
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
.irq_base = SPEAR_PLGPIO_INT_BASE,
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 6c00695..d216c94 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -11,10 +11,13 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <plat/fsmc.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
@@ -53,6 +56,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
&ehci_device,
&i2c_device,
+ &nand_device,
&ohci0_device,
&ohci1_device,
&rtc_device,
@@ -70,6 +74,10 @@ static void __init spear310_evb_init(void)
pmx_driver.devs = pmx_devs;
pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
+ /* set nand device's plat data */
+ fsmc_nand_set_plat_data(&nand_device, NULL, 0, NAND_SKIP_BBTSCAN,
+ FSMC_NAND_BW8);
+
/* call spear310 machine init function */
spear310_init();
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 46c9769..1fb6a83 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -12,6 +12,7 @@
*/
#include <linux/ptrace.h>
+#include <linux/mtd/fsmc.h>
#include <asm/irq.h>
#include <mach/generic.h>
#include <mach/spear.h>
@@ -424,6 +425,31 @@ struct platform_device i2c1_device = {
.resource = i2c1_resources,
};
+/* nand device registeration */
+static struct fsmc_nand_platform_data nand_platform_data;
+
+static struct resource nand_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR320_NAND_BASE,
+ .end = SPEAR320_NAND_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR320_FSMC_BASE,
+ .end = SPEAR320_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device nand_device = {
+ .name = "nand",
+ .id = -1,
+ .resource = nand_resources,
+ .num_resources = ARRAY_SIZE(nand_resources),
+ .dev.platform_data = &nand_platform_data,
+};
+
/* plgpio device registeration */
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index d371b31..15db267 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -11,10 +11,13 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <plat/fsmc.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
@@ -51,6 +54,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
&ehci_device,
&i2c_device,
+ &nand_device,
&ohci0_device,
&ohci1_device,
&rtc_device,
@@ -70,6 +74,10 @@ static void __init spear320_evb_init(void)
pmx_driver.devs = pmx_devs;
pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
+ /* set nand device's plat data */
+ fsmc_nand_set_plat_data(&nand_device, NULL, 0, NAND_SKIP_BBTSCAN,
+ FSMC_NAND_BW8);
+
/* call spear320 machine init function */
spear320_init();
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 112cc9b..80695d69 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -36,6 +36,7 @@ extern struct amba_device wdt_device;
extern struct platform_device ehci0_device;
extern struct platform_device ehci1_device;
extern struct platform_device i2c_device;
+extern struct platform_device nand_device;
extern struct platform_device ohci0_device;
extern struct platform_device ohci1_device;
extern struct platform_device rtc_device;
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index 7ec09b6..32d3855 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -11,10 +11,13 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <plat/fsmc.h>
static struct amba_device *amba_devs[] __initdata = {
&clcd_device,
@@ -32,6 +35,7 @@ static struct platform_device *plat_devs[] __initdata = {
&i2c_device,
&ohci0_device,
&ohci1_device,
+ &nand_device,
&rtc_device,
};
@@ -39,6 +43,10 @@ static void __init spear600_evb_init(void)
{
unsigned int i;
+ /* set nand device's plat data */
+ fsmc_nand_set_plat_data(&nand_device, NULL, 0, NAND_SKIP_BBTSCAN,
+ FSMC_NAND_BW8);
+
/* call spear600 machine init function */
spear600_init();
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 4801fc7..1832361 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -15,6 +15,7 @@
#include <linux/amba/pl061.h>
#include <linux/ptrace.h>
#include <linux/io.h>
+#include <linux/mtd/fsmc.h>
#include <asm/hardware/vic.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
@@ -152,6 +153,31 @@ struct platform_device i2c_device = {
.resource = i2c_resources,
};
+/* nand device registeration */
+static struct fsmc_nand_platform_data nand_platform_data;
+
+static struct resource nand_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR6XX_ICM1_NAND_BASE,
+ .end = SPEAR6XX_ICM1_NAND_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR6XX_ICM1_FSMC_BASE,
+ .end = SPEAR6XX_ICM1_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device nand_device = {
+ .name = "nand",
+ .id = -1,
+ .resource = nand_resources,
+ .num_resources = ARRAY_SIZE(nand_resources),
+ .dev.platform_data = &nand_platform_data,
+};
+
/* usb host device registeration */
static struct resource ehci0_resources[] = {
[0] = {
diff --git a/arch/arm/plat-spear/include/plat/fsmc.h b/arch/arm/plat-spear/include/plat/fsmc.h
new file mode 100644
index 0000000..364a79b
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/fsmc.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/plat-spear/include/plat/fsmc.h
+ *
+ * FSMC definitions for SPEAr platform
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Vipin Kumar <vipin.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_FSMC_H
+#define __PLAT_FSMC_H
+
+#include <linux/mtd/fsmc.h>
+
+/* This function is used to set platform data field of pdev->dev */
+static inline void fsmc_nand_set_plat_data(struct platform_device *pdev,
+ struct mtd_partition *partitions, unsigned int nr_partitions,
+ unsigned int options, unsigned int width)
+{
+ struct fsmc_nand_platform_data *plat_data;
+ plat_data = dev_get_platdata(&pdev->dev);
+
+ if (partitions) {
+ plat_data->partitions = partitions;
+ plat_data->nr_partitions = nr_partitions;
+ }
+
+ plat_data->options = options;
+ plat_data->width = width;
+}
+
+#endif /* __PLAT_FSMC_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 25/62] ST SPEAr: Added PCIE host controller base driver support.
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (22 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 24/62] ST SPEAr: Adding machine support for nand Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-19 0:05 ` Russell King - ARM Linux
2011-01-18 7:11 ` [PATCH V4 26/62] ST SPEAr: Adding support for SSP PL022 Viresh Kumar
` (37 subsequent siblings)
61 siblings, 1 reply; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr13xx family contains Synopsys designware PCIE version 3.30a. This
patch adds support for this PCIE module for spear platform.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-spear13xx/Makefile | 1 +
arch/arm/mach-spear13xx/include/mach/hardware.h | 7 +
arch/arm/mach-spear13xx/include/mach/irqs.h | 25 +-
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 20 +
arch/arm/mach-spear13xx/include/mach/pcie.h | 170 +++++
arch/arm/mach-spear13xx/pcie.c | 861 ++++++++++++++++++++++
arch/arm/mach-spear13xx/spear1300_evb.c | 31 +
arch/arm/mach-spear13xx/spear13xx.c | 28 +
arch/arm/plat-spear/Kconfig | 2 +
10 files changed, 1142 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/pcie.h
create mode 100644 arch/arm/mach-spear13xx/pcie.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f3904ba..957d320 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1238,6 +1238,7 @@ config PCI_HOST_ITE8152
select DMABOUNCE
source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
source "drivers/pcmcia/Kconfig"
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index cb5ae9e..4f1cbc5 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -6,6 +6,7 @@
obj-y += spear13xx.o clock.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+obj-$(CONFIG_PCIEPORTBUS) += pcie.o
# spear1300 specific files
obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
index 0047d75..4abc2c0 100644
--- a/arch/arm/mach-spear13xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -22,4 +22,11 @@
/* typesafe io address */
#define __io_address(n) __io(IO_ADDRESS(n))
+#if defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO 0
+#define PCIBIOS_MIN_MEM 0
+#define pcibios_assign_all_busses() 0
+#endif
+
+
#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
index 10b64c1..d2bfbb1 100644
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -80,9 +80,9 @@
#define IRQ_USBH_OHCI0 (IRQ_SHPI_START + 65)
#define IRQ_USBH_EHCI1 (IRQ_SHPI_START + 66)
#define IRQ_USBH_OHCI1 (IRQ_SHPI_START + 67)
-#define IRQ_PCIE1 (IRQ_SHPI_START + 68)
-#define IRQ_PCIE2 (IRQ_SHPI_START + 69)
-#define IRQ_PCIE3 (IRQ_SHPI_START + 70)
+#define IRQ_PCIE0 (IRQ_SHPI_START + 68)
+#define IRQ_PCIE1 (IRQ_SHPI_START + 69)
+#define IRQ_PCIE2 (IRQ_SHPI_START + 70)
#define IRQ_GIC_END (IRQ_SHPI_START + 128)
@@ -93,7 +93,24 @@
#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
-#define VIRQ_END SPEAR_GPIO_INT_END
+/* PCIE MSI virtual irqs */
+#define SPEAR_NUM_MSI_IRQS 64
+#define SPEAR_MSI0_INT_BASE (SPEAR_GPIO_INT_END + 0)
+#define SPEAR_MSI0_INT_END (SPEAR_MSI0_INT_BASE + SPEAR_NUM_MSI_IRQS)
+#define SPEAR_MSI1_INT_BASE (SPEAR_MSI0_INT_END + 0)
+#define SPEAR_MSI1_INT_END (SPEAR_MSI1_INT_BASE + SPEAR_NUM_MSI_IRQS)
+#define SPEAR_MSI2_INT_BASE (SPEAR_MSI1_INT_END + 0)
+#define SPEAR_MSI2_INT_END (SPEAR_MSI2_INT_BASE + SPEAR_NUM_MSI_IRQS)
+
+#define SPEAR_NUM_INTX_IRQS 4
+#define SPEAR_INTX0_BASE (SPEAR_MSI2_INT_END + 0)
+#define SPEAR_INTX0_END (SPEAR_INTX0_BASE + SPEAR_NUM_INTX_IRQS)
+#define SPEAR_INTX1_BASE (SPEAR_INTX0_END + 0)
+#define SPEAR_INTX1_END (SPEAR_INTX1_BASE + SPEAR_NUM_INTX_IRQS)
+#define SPEAR_INTX2_BASE (SPEAR_INTX1_END + 0)
+#define SPEAR_INTX2_END (SPEAR_INTX2_BASE + SPEAR_NUM_INTX_IRQS)
+
+#define VIRQ_END SPEAR_INTX2_END
#define NR_IRQS VIRQ_END
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
index e6823db..a7ba6cb 100644
--- a/arch/arm/mach-spear13xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -202,6 +202,26 @@
#define USBPHY_P2_CFG ((unsigned int *)(MISC_BASE + 0x31c))
#define USBPHY_P3_CFG ((unsigned int *)(MISC_BASE + 0x320))
#define PCIE_CFG ((unsigned int *)(MISC_BASE + 0x324))
+ /* PCIE CFG MASks */
+ #define PCIE2_CFG_AUX_CLK (1 << 0)
+ #define PCIE1_CFG_AUX_CLK (1 << 1)
+ #define PCIE0_CFG_AUX_CLK (1 << 2)
+ #define PCIE2_CFG_CORE_CLK (1 << 3)
+ #define PCIE1_CFG_CORE_CLK (1 << 4)
+ #define PCIE0_CFG_CORE_CLK (1 << 5)
+ #define PCIE2_CFG_POWERUP_RESET (1 << 6)
+ #define PCIE1_CFG_POWERUP_RESET (1 << 7)
+ #define PCIE0_CFG_POWERUP_RESET (1 << 8)
+ #define PCIE2_CFG_DEVICE_PRESENT (1 << 9)
+ #define PCIE1_CFG_DEVICE_PRESENT (1 << 10)
+ #define PCIE0_CFG_DEVICE_PRESENT (1 << 11)
+ #define PCIE0_CFG_VAL (PCIE0_CFG_AUX_CLK | PCIE0_CFG_CORE_CLK \
+ | PCIE0_CFG_POWERUP_RESET | PCIE0_CFG_DEVICE_PRESENT)
+ #define PCIE1_CFG_VAL (PCIE1_CFG_AUX_CLK | PCIE1_CFG_CORE_CLK \
+ | PCIE1_CFG_POWERUP_RESET | PCIE1_CFG_DEVICE_PRESENT)
+ #define PCIE2_CFG_VAL (PCIE2_CFG_AUX_CLK | PCIE2_CFG_CORE_CLK \
+ | PCIE2_CFG_POWERUP_RESET | PCIE2_CFG_DEVICE_PRESENT)
+
#define PCIE_MIPHY_CFG ((unsigned int *)(MISC_BASE + 0x328))
#define PERIP_CFG ((unsigned int *)(MISC_BASE + 0x32c))
#define MCIF_SEL_SHIFT 3
diff --git a/arch/arm/mach-spear13xx/include/mach/pcie.h b/arch/arm/mach-spear13xx/include/mach/pcie.h
new file mode 100644
index 0000000..fa302e5
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/pcie.h
@@ -0,0 +1,170 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/pcie.h
+ *
+ * Spear SoC PCIe handling.
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_PCIE_H
+#define __MACH_PCIE_H
+
+extern int (*pcie_port_is_host)(int port);
+extern int enable_pcie0_clk(void);
+
+
+struct pcie_port {
+ u8 port;
+ u8 root_bus_nr;
+ void __iomem *base;
+ void __iomem *app_base;
+ void __iomem *va_app_base;
+ void __iomem *va_dbi_base;
+ void __iomem *va_cfg0_base;
+ spinlock_t conf_lock;
+ char mem_space_name[16];
+ char io_space_name[16];
+ struct resource res[2];
+};
+
+struct pcie_app_reg {
+ u32 app_ctrl_0; /*cr0*/
+ u32 app_ctrl_1; /*cr1*/
+ u32 app_status_0; /*cr2*/
+ u32 app_status_1; /*cr3*/
+ u32 msg_status; /*cr4*/
+ u32 msg_payload; /*cr5*/
+ u32 int_sts; /*cr6*/
+ u32 int_clr; /*cr7*/
+ u32 int_mask; /*cr8*/
+ u32 mst_bmisc; /*cr9*/
+ u32 phy_ctrl; /*cr10*/
+ u32 phy_status; /*cr11*/
+ u32 cxpl_debug_info_0; /*cr12*/
+ u32 cxpl_debug_info_1; /*cr13*/
+ u32 ven_msg_ctrl_0; /*cr14*/
+ u32 ven_msg_ctrl_1; /*cr15*/
+ u32 ven_msg_data_0; /*cr16*/
+ u32 ven_msg_data_1; /*cr17*/
+ u32 ven_msi_0; /*cr18*/
+ u32 ven_msi_1; /*cr19*/
+ u32 mst_rmisc; /*cr 20*/
+ u32 slv_awmisc; /*cr 21*/
+ u32 slv_armisc; /*cr 22*/
+ u32 pom0_mem_addr_start; /*cr23*/
+ u32 pom1_mem_addr_start; /*cr24*/
+ u32 pom_io_addr_start; /*cr25*/
+ u32 pom_cfg0_addr_start; /*cr26*/
+ u32 pom_cfg1_addr_start; /*cr27*/
+ u32 in0_mem_addr_start; /*cr28*/
+ u32 in1_mem_addr_start; /*cr29*/
+ u32 in_io_addr_start; /*cr30*/
+ u32 in_cfg0_addr_start; /*cr31*/
+ u32 in_cfg1_addr_start; /*cr32*/
+ u32 in_msg_addr_start; /*cr33*/
+ u32 in0_mem_addr_limit; /*cr34*/
+ u32 in1_mem_addr_limit; /*cr35*/
+ u32 in_io_addr_limit; /*cr36*/
+ u32 in_cfg0_addr_limit; /*cr37*/
+ u32 in_cfg1_addr_limit; /*cr38*/
+ u32 in_msg_addr_limit; /*cr39*/
+ u32 mem0_addr_offset_limit; /*cr40*/
+ u32 pim0_mem_addr_start; /*cr41*/
+ u32 pim1_mem_addr_start; /*cr42*/
+ u32 pim_io_addr_start; /*cr43*/
+ u32 pim_rom_addr_start; /*cr44*/
+};
+
+/*CR0 ID*/
+#define RX_LANE_FLIP_EN_ID 0
+#define TX_LANE_FLIP_EN_ID 1
+#define SYS_AUX_PWR_DET_ID 2
+#define APP_LTSSM_ENABLE_ID 3
+#define SYS_ATTEN_BUTTON_PRESSED_ID 4
+#define SYS_MRL_SENSOR_STATE_ID 5
+#define SYS_PWR_FAULT_DET_ID 6
+#define SYS_MRL_SENSOR_CHGED_ID 7
+#define SYS_PRE_DET_CHGED_ID 8
+#define SYS_CMD_CPLED_INT_ID 9
+#define APP_INIT_RST_0_ID 11
+#define APP_REQ_ENTR_L1_ID 12
+#define APP_READY_ENTR_L23_ID 13
+#define APP_REQ_EXIT_L1_ID 14
+#define DEVICE_TYPE_EP (0 << 25)
+#define DEVICE_TYPE_LEP (1 << 25)
+#define DEVICE_TYPE_RC (4 << 25)
+#define SYS_INT_ID 29
+#define MISCTRL_EN_ID 30
+#define REG_TRANSLATION_ENABLE 31
+
+/*CR1 ID*/
+#define APPS_PM_XMT_TURNOFF_ID 2
+#define APPS_PM_XMT_PME_ID 5
+
+/*CR3 ID*/
+#define XMLH_LTSSM_STATE_ID 0
+#define XMLH_LTSSM_STATE_L0 ((u32)0x11 << XMLH_LTSSM_STATE_ID)
+#define XMLH_LTSSM_STATE_MASK ((u32)0x1F << XMLH_LTSSM_STATE_ID)
+#define XMLH_LINK_UP_ID 5
+
+/*CR4 ID*/
+#define CFG_MSI_EN_ID 18
+
+/*CR6*/
+#define INTA_CTRL_INT (1 << 7)
+#define INTB_CTRL_INT (1 << 8)
+#define INTC_CTRL_INT (1 << 9)
+#define INTD_CTRL_INT (1 << 10)
+#define MSI_CTRL_INT (1 << 26)
+
+/*CR19 ID*/
+#define VEN_MSI_REQ_ID 11
+#define VEN_MSI_FUN_NUM_ID 8
+#define VEN_MSI_TC_ID 5
+#define VEN_MSI_VECTOR_ID 0
+#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
+#endif
+
+/*CE21-22 ID*/
+/*ID definitio of ARMISC*/
+#define AXI_OP_TYPE_ID 0
+#define AXI_OP_BCM_ID 5
+#define AXI_OP_EP_ID 6
+#define AXI_OP_TD_ID 7
+#define AXI_OP_ATTRIBUTE_ID 8
+#define AXI_OP_TC_ID 10
+#define AXI_OP_MSG_CODE_ID 13
+#define AXI_OP_DBI_ACCESS_ID 21
+#define AXI_OP_TYPE_MASK 0x1F
+#define AXI_OP_TYPE_MEM_RDRW 0
+#define AXI_OP_TYPE_MEM_RDRW_LOCKED 1
+#define AXI_OP_TYPE_IO_RDRW 2
+#define AXI_OP_TYPE_CONFIG_RDRW_TYPE0 4
+#define AXI_OP_TYPE_CONFIG_RDRW_TYPE1 5
+#define AXI_OP_TYPE_MSG_REQ 16
+#define AXI_OP_TYPE_COMPLETION 10
+#define AXI_OP_TYPE_COMPLETION_LOCKED 11
+#define AXI_OP_TYPE_DBI_ELBI_ENABLE 1
+
+/* synopsis specific PCIE configuration registers*/
+#define PCIE_MSI_ADDR_LO 0x820 /* 32 bits */
+#define PCIE_MSI_ADDR_HI 0x824 /* 32 bits */
+#define PCIE_MSI_INTR0_ENABLE 0x828 /* 32 bits */
+#define PCIE_MSI_INTR0_MASK 0x82C /* 32 bits */
+#define PCIE_MSI_INTR0_STATUS 0x830 /* 32 bits */
+
+/*BAR MASK registers*/
+#define PCIE_BAR0_MASK_REG 0x1010
+
+static inline void pcie_init(int (*fptr)(int port))
+{
+ pcie_port_is_host = fptr;
+}
diff --git a/arch/arm/mach-spear13xx/pcie.c b/arch/arm/mach-spear13xx/pcie.c
new file mode 100644
index 0000000..869175e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/pcie.c
@@ -0,0 +1,861 @@
+/*
+ * arch/arm/mach-spear13xx/pcie.c
+ *
+ * PCIe functions for SPEAr 13xx SoCs
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/msi.h>
+#include <linux/mbus.h>
+#include <linux/sched.h>
+#include <asm/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach/irq.h>
+#include <mach/pcie.h>
+#include <mach/irqs.h>
+#include <mach/misc_regs.h>
+
+#define NUM_PCIE_PORTS 3
+
+/* Sum of all these space can maximum be 256MB*/
+#define IN0_MEM_SIZE (200 * 1024 * 1024 - 1)
+/* In current implementation address translation is done using IN0 only.
+ * So IN1 start address and IN0 end address has been kept same
+*/
+#define IN1_MEM_SIZE (0 * 1024 * 1024 - 1)
+#define IN_IO_SIZE (20 * 1024 * 1024 - 1)
+#define IN_CFG0_SIZE (1 * 1024 * 1024 - 1)
+#define IN_CFG1_SIZE (1 * 1024 * 1024 - 1)
+#define IN_MSG_SIZE (1 * 1024 * 1024 - 1)
+
+#define MAX_LINK_UP_WAIT_JIFFIES 10
+
+int (*pcie_port_is_host)(int port);
+static struct pcie_port pcie_port[NUM_PCIE_PORTS];
+static u32 spr_pcie_base[NUM_PCIE_PORTS] = {
+ SPEAR13XX_PCIE0_BASE,
+ SPEAR13XX_PCIE1_BASE,
+ SPEAR13XX_PCIE2_BASE,
+};
+static u32 spr_pcie_app_base[NUM_PCIE_PORTS] = {
+ SPEAR13XX_PCIE0_APP_BASE,
+ SPEAR13XX_PCIE1_APP_BASE,
+ SPEAR13XX_PCIE2_APP_BASE,
+};
+
+/* Keeping all DDR area of 256MB accesible for inbound transaction */
+#define INBOUND_ADDR_MASK 0xFFFFFFF
+
+#ifdef CONFIG_PCI_MSI
+static DECLARE_BITMAP(msi_irq_in_use[NUM_PCIE_PORTS], SPEAR_NUM_MSI_IRQS);
+static unsigned int spear_msi_data[NUM_PCIE_PORTS];
+
+static void spear13xx_msi_init(struct pcie_port *pp);
+#endif
+
+static void spear_pcie_int_handler(unsigned int irq, struct irq_desc *desc);
+
+static void enable_dbi_access(struct pcie_app_reg *app_reg)
+{
+ /* Enable DBI access */
+ writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID),
+ &app_reg->slv_armisc);
+ writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID),
+ &app_reg->slv_awmisc);
+
+}
+
+static void disable_dbi_access(struct pcie_app_reg *app_reg)
+{
+ /* disable DBI access */
+ writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),
+ &app_reg->slv_armisc);
+ writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),
+ &app_reg->slv_awmisc);
+
+}
+
+static void spear_dbi_read_reg(struct pcie_port *pp, int where, int size,
+ u32 *val)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) pp->va_app_base;
+ u32 va_address;
+
+ /* Enable DBI access */
+ enable_dbi_access(app_reg);
+
+ va_address = (u32)pp->va_dbi_base + (where & ~0x3);
+
+ *val = readl(va_address);
+
+ if (size == 1)
+ *val = (*val >> (8 * (where & 3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+ /* Disable DBI access */
+ disable_dbi_access(app_reg);
+}
+
+static void spear_dbi_write_reg(struct pcie_port *pp, int where, int size,
+ u32 val)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) pp->va_app_base;
+ u32 va_address;
+
+ /* Enable DBI access */
+ enable_dbi_access(app_reg);
+
+ va_address = (u32)pp->va_dbi_base + (where & ~0x3);
+
+ if (size == 4)
+ writel(val, va_address);
+ else if (size == 2)
+ writew(val, va_address + (where & 2));
+ else if (size == 1)
+ writeb(val, va_address + (where & 3));
+
+ /* Disable DBI access */
+ disable_dbi_access(app_reg);
+}
+
+static int spear13xx_pcie_link_up(void __iomem *va_app_base)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) va_app_base;
+ unsigned long deadline = jiffies + MAX_LINK_UP_WAIT_JIFFIES;
+
+ do {
+ if (readl(&app_reg->app_status_1) &
+ ((u32)1 << XMLH_LINK_UP_ID))
+ return 1;
+
+ cond_resched();
+ } while (!time_after_eq(jiffies, deadline));
+
+ return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+
+ /*setup registers for outbound translation */
+
+ writel(pp->base, &app_reg->in0_mem_addr_start);
+ writel(app_reg->in0_mem_addr_start + IN0_MEM_SIZE,
+ &app_reg->in0_mem_addr_limit);
+ writel(app_reg->in0_mem_addr_limit + 1, &app_reg->in1_mem_addr_start);
+ writel(app_reg->in1_mem_addr_start + IN1_MEM_SIZE,
+ &app_reg->in1_mem_addr_limit);
+ writel(app_reg->in1_mem_addr_limit + 1, &app_reg->in_io_addr_start);
+ writel(app_reg->in_io_addr_start + IN_IO_SIZE,
+ &app_reg->in_io_addr_limit);
+ writel(app_reg->in_io_addr_limit + 1, &app_reg->in_cfg0_addr_start);
+ writel(app_reg->in_cfg0_addr_start + IN_CFG0_SIZE,
+ &app_reg->in_cfg0_addr_limit);
+ writel(app_reg->in_cfg0_addr_limit + 1, &app_reg->in_cfg1_addr_start);
+ writel(app_reg->in_cfg1_addr_start + IN_CFG1_SIZE,
+ &app_reg->in_cfg1_addr_limit);
+ writel(app_reg->in_cfg1_addr_limit + 1, &app_reg->in_msg_addr_start);
+ writel(app_reg->in_msg_addr_start + IN_MSG_SIZE,
+ &app_reg->in_msg_addr_limit);
+
+ writel(app_reg->in0_mem_addr_start, &app_reg->pom0_mem_addr_start);
+ writel(app_reg->in1_mem_addr_start, &app_reg->pom1_mem_addr_start);
+ writel(app_reg->in_io_addr_start, &app_reg->pom_io_addr_start);
+
+ /*setup registers for inbound translation */
+
+ writel(INBOUND_ADDR_MASK + 1, &app_reg->mem0_addr_offset_limit);
+ writel(0, &app_reg->pim0_mem_addr_start);
+ writel(0, &app_reg->pim1_mem_addr_start);
+ spear_dbi_write_reg(pp, PCIE_BAR0_MASK_REG, 4, INBOUND_ADDR_MASK);
+ spear_dbi_write_reg(pp, PCI_BASE_ADDRESS_0, 4, 0);
+
+ writel(0x0, &app_reg->pim_io_addr_start);
+ writel(0x0, &app_reg->pim_io_addr_start);
+ writel(0x0, &app_reg->pim_rom_addr_start);
+
+ writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+ | (1 << APP_LTSSM_ENABLE_ID)
+ | ((u32)1 << REG_TRANSLATION_ENABLE),
+ &app_reg->app_ctrl_0);
+}
+
+static void __init spear13xx_pcie_preinit(void)
+{
+ int i;
+ struct pcie_port *pp;
+ struct pcie_app_reg *app_reg;
+
+ for (i = 0; i < NUM_PCIE_PORTS; i++) {
+ pp = pcie_port + i;
+ app_reg = (struct pcie_app_reg *) (pp->va_app_base);
+
+ if (!(*pcie_port_is_host)(i))
+ continue;
+ snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+ "PCIe %d MEM", pp->port);
+ pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+ pp->res[0].name = pp->mem_space_name;
+ pp->res[0].start = app_reg->in0_mem_addr_start;
+ pp->res[0].end = app_reg->in0_mem_addr_limit;
+ pp->res[0].flags = IORESOURCE_MEM;
+
+ snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+ "PCIe %d I/O", pp->port);
+ pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+ pp->res[1].name = pp->io_space_name;
+ pp->res[1].start = app_reg->in_io_addr_start;
+ pp->res[1].end = app_reg->in_io_addr_limit;
+ pp->res[1].flags = IORESOURCE_IO;
+
+ if (request_resource(&iomem_resource, &pp->res[0]))
+ panic("can't allocate PCIe I/O space");
+ if (request_resource(&iomem_resource, &pp->res[1]))
+ panic("can't allocate PCIe MEM space");
+ }
+}
+
+static int __init spear13xx_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+ struct pcie_port *pp;
+ u32 val = 0;
+
+ if (nr >= NUM_PCIE_PORTS)
+ return 0;
+
+ if (!(*pcie_port_is_host)(nr))
+ return 0;
+
+ pp = &pcie_port[nr];
+ if (!spear13xx_pcie_link_up((void __iomem *)pp->va_app_base))
+ return 0;
+ pp->root_bus_nr = sys->busnr;
+
+ /* Generic PCIe unit setup.*/
+
+ /* Enable own BME. It is necessary to enable own BME to do a
+ * memory transaction on a downstream device
+ */
+ spear_dbi_read_reg(pp, PCI_COMMAND, 2, &val);
+ val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
+ spear_dbi_write_reg(pp, PCI_COMMAND, 2, val);
+
+ /* Need to come back here*/
+
+ sys->resource[0] = &pp->res[0];
+ sys->resource[1] = &pp->res[1];
+ sys->resource[2] = NULL;
+
+ return 1;
+}
+
+static struct pcie_port *bus_to_port(int bus)
+{
+ int i;
+
+ for (i = NUM_PCIE_PORTS - 1; i >= 0; i--) {
+ int rbus = pcie_port[i].root_bus_nr;
+ if (!(*pcie_port_is_host)(i))
+ continue;
+ if (rbus != -1 && rbus <= bus)
+ break;
+ }
+
+ return i >= 0 ? pcie_port + i : NULL;
+}
+
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
+{
+ /*If there is no link, then there is no device*/
+ if (!spear13xx_pcie_link_up((void __iomem *)pp->va_app_base))
+ return 0;
+ /*
+ * Don't go out when trying to access nonexisting devices
+ * on the local bus.
+ * we have only one slot on each root port.
+ */
+ if (bus == pp->root_bus_nr && dev > 0)
+ return 0;
+ return 1;
+}
+
+static int spear13xx_pcie_rd_conf(struct pcie_port *pp, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) pp->va_app_base;
+ u32 address = (u32)pp->va_cfg0_base | (PCI_FUNC(devfn) << 16)
+ | (where & 0xFFFC);
+
+ writel((bus->number << 24) | (PCI_SLOT(devfn) << 19),
+ &app_reg->pom_cfg0_addr_start);
+ writel(readl(&app_reg->slv_armisc) & ~(AXI_OP_TYPE_MASK),
+ &app_reg->slv_armisc);
+ writel(readl(&app_reg->slv_armisc) | AXI_OP_TYPE_CONFIG_RDRW_TYPE0,
+ &app_reg->slv_armisc);
+
+ *val = readl(address);
+ if (size == 1)
+ *val = (*val >> (8 * (where & 3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+ writel(readl(&app_reg->slv_armisc) & ~(AXI_OP_TYPE_MASK),
+ &app_reg->slv_armisc);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+ struct pcie_port *pp = bus_to_port(bus->number);
+ unsigned long flags;
+ int ret;
+
+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
+ *val = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ spin_lock_irqsave(&pp->conf_lock, flags);
+ ret = spear13xx_pcie_rd_conf(pp, bus, devfn, where, size, val);
+ spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+ return ret;
+}
+
+static int spear13xx_pcie_wr_conf(struct pcie_port *pp, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 val)
+{
+ int ret = PCIBIOS_SUCCESSFUL;
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) pp->va_app_base;
+ u32 address = (u32)pp->va_cfg0_base | (PCI_FUNC(devfn) << 16)
+ | (where & 0xFFFC);
+
+ writel((bus->number << 24) | (PCI_SLOT(devfn) << 19),
+ &app_reg->pom_cfg0_addr_start);
+ writel(readl(&app_reg->slv_awmisc) & ~(AXI_OP_TYPE_MASK),
+ &app_reg->slv_awmisc);
+ writel(readl(&app_reg->slv_awmisc) | AXI_OP_TYPE_CONFIG_RDRW_TYPE0,
+ &app_reg->slv_awmisc);
+ if (size == 4)
+ writel(val, address);
+ else if (size == 2)
+ writew(val, address + (where & 2));
+ else if (size == 1)
+ writeb(val, address + (where & 3));
+ else
+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
+ writel(readl(&app_reg->slv_awmisc) & ~(AXI_OP_TYPE_MASK),
+ &app_reg->slv_awmisc);
+ return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+ int where, int size, u32 val)
+{
+ struct pcie_port *pp = bus_to_port(bus->number);
+ unsigned long flags;
+ int ret;
+
+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ spin_lock_irqsave(&pp->conf_lock, flags);
+ ret = spear13xx_pcie_wr_conf(pp, bus, devfn, where, size, val);
+ spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+ return ret;
+}
+
+static struct pci_ops pcie_ops = {
+ .read = pcie_rd_conf,
+ .write = pcie_wr_conf,
+};
+
+static struct pci_bus __init *
+spear13xx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+ struct pci_bus *bus;
+
+ if ((nr < NUM_PCIE_PORTS) && (*pcie_port_is_host)(nr)) {
+ bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+ } else {
+ bus = NULL;
+ BUG();
+ }
+
+ return bus;
+}
+
+static int __init spear13xx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ struct pcie_port *pp = bus_to_port(dev->bus->number);
+ int irq = (SPEAR_INTX0_BASE + pp->port * SPEAR_NUM_INTX_IRQS + pin - 1);
+
+ return irq;
+}
+
+static struct hw_pci spear13xx_pci __initdata = {
+ .nr_controllers = NUM_PCIE_PORTS,
+ .preinit = spear13xx_pcie_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = spear13xx_pcie_setup,
+ .scan = spear13xx_pcie_scan_bus,
+ .map_irq = spear13xx_pcie_map_irq,
+};
+
+void mask_intx_irq(unsigned int irq)
+{
+ int irq_offset = (irq - SPEAR_INTX0_BASE) % SPEAR_NUM_INTX_IRQS;
+ int port = (irq - SPEAR_INTX0_BASE) / SPEAR_NUM_INTX_IRQS;
+ struct pcie_port *pp = &pcie_port[port];
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+
+ switch (irq_offset) {
+ case 0:
+ writel(readl(&app_reg->int_mask) & ~INTA_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 1:
+ writel(readl(&app_reg->int_mask) & ~INTB_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 2:
+ writel(readl(&app_reg->int_mask) & ~INTC_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 3:
+ writel(readl(&app_reg->int_mask) & ~INTD_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ }
+}
+
+void unmask_intx_irq(unsigned int irq)
+{
+ int irq_offset = (irq - SPEAR_INTX0_BASE) % SPEAR_NUM_INTX_IRQS;
+ int port = (irq - SPEAR_INTX0_BASE) / SPEAR_NUM_INTX_IRQS;
+ struct pcie_port *pp = &pcie_port[port];
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+
+ switch (irq_offset) {
+ case 0:
+ writel(readl(&app_reg->int_mask) | INTA_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 1:
+ writel(readl(&app_reg->int_mask) | INTB_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 2:
+ writel(readl(&app_reg->int_mask) | INTC_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 3:
+ writel(readl(&app_reg->int_mask) | INTD_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ }
+}
+
+static struct irq_chip spear13xx_intx_chip = {
+ .name = "PCI-INTX",
+ .mask = mask_intx_irq,
+ .unmask = unmask_intx_irq,
+};
+
+static void spear13xx_int_init(struct pcie_port *pp)
+{
+ int i, irq;
+ struct pcie_app_reg *app_reg;
+
+ set_irq_chained_handler(IRQ_PCIE0 + pp->port, spear_pcie_int_handler);
+
+#ifdef CONFIG_PCI_MSI
+ spear13xx_msi_init(pp);
+#endif
+ /* Enbale INTX interrupt*/
+ app_reg = (struct pcie_app_reg *)pp->va_app_base;
+ writel(readl(&app_reg->int_mask) | INTA_CTRL_INT
+ | INTB_CTRL_INT | INTC_CTRL_INT
+ | INTD_CTRL_INT, &app_reg->int_mask);
+
+ /* initilize INTX chip here only. MSI chip will be
+ * initilized dynamically.*/
+ irq = (SPEAR_INTX0_BASE + pp->port * SPEAR_NUM_INTX_IRQS);
+ for (i = 0; i < SPEAR_NUM_INTX_IRQS; i++) {
+ set_irq_chip_and_handler(irq + i, &spear13xx_intx_chip,
+ handle_simple_irq);
+ set_irq_flags(irq + i, IRQF_VALID);
+ }
+}
+
+static void __init add_pcie_port(int port, u32 base, u32 app_base)
+{
+ struct pcie_port *pp = &pcie_port[port];
+ struct pcie_app_reg *app_reg;
+
+ pp->port = port;
+ pp->root_bus_nr = -1;
+ pp->base = (void __iomem *)base;
+ pp->app_base = (void __iomem *)app_base;
+ pp->va_app_base = (void __iomem *) ioremap(app_base, 0x200);
+ if (!pp->va_app_base) {
+ pr_err("error with ioremap in function %s\n", __func__);
+ return;
+ }
+ pp->va_dbi_base = (void __iomem *) ioremap(base, 0x2000);
+ if (!pp->va_dbi_base) {
+ pr_err("error with ioremap in function %s\n", __func__);
+ return;
+ }
+ spin_lock_init(&pp->conf_lock);
+ memset(pp->res, 0, sizeof(pp->res));
+ pr_info("spear13xx PCIe port %d\n", port);
+ if (spear13xx_pcie_link_up((void __iomem *)pp->va_app_base)) {
+ pr_info("link up in bios\n");
+ } else {
+ pr_info("link down in bios\n");
+ spear13xx_pcie_host_init(pp);
+ spear13xx_int_init(pp);
+ app_reg = (struct pcie_app_reg *)pp->va_app_base;
+ pp->va_cfg0_base = (void __iomem *)
+ ioremap(app_reg->in_cfg0_addr_start, IN_CFG0_SIZE);
+ if (!pp->va_cfg0_base) {
+ pr_err("error with ioremap in function %s\n", __func__);
+ return;
+ }
+
+ }
+}
+
+static int __init spear13xx_pcie_init(void)
+{
+ int port;
+ struct clk *clk;
+
+ for (port = 0; port < NUM_PCIE_PORTS; port++) {
+ /* do not enable clock if it is PCIE0. Ideally , all controller
+ * should have been independent from others with respect to
+ * clock. But PCIE1 and 2 depends on PCIE0.So PCIE0 clk
+ * is provided during board init.*/
+ if (port == 1) {
+ /* Ideally CFG Clock should have been also enabled
+ * here. But it is done currently during board
+ * init routne*/
+ clk = clk_get_sys("pcie1", NULL);
+ if (!clk) {
+ pr_err("%s:couldn't get clk for pcie1\n",
+ __func__);
+ continue;
+ }
+ if (clk_enable(clk)) {
+ pr_err("%s:couldn't enable clk for pcie1\n",
+ __func__);
+ continue;
+ }
+ } else if (port == 2) {
+ /* Ideally CFG Clock should have been also enabled
+ * here. But it is done currently during board
+ * init routne*/
+ clk = clk_get_sys("pcie2", NULL);
+ if (!clk) {
+ pr_err("%s:couldn't get clk for pcie2\n",
+ __func__);
+ continue;
+ }
+ if (clk_enable(clk)) {
+ pr_err("%s:couldn't enable clk for pcie2\n",
+ __func__);
+ continue;
+ }
+ }
+
+ if ((*pcie_port_is_host)(port))
+ add_pcie_port(port, spr_pcie_base[port],
+ spr_pcie_app_base[port]);
+ }
+
+ pci_common_init(&spear13xx_pci);
+
+ return 0;
+}
+subsys_initcall(spear13xx_pcie_init);
+
+#ifdef CONFIG_PCI_MSI
+/* MSI int handler
+ */
+static void handle_msi(struct pcie_port *pp)
+{
+ unsigned long val;
+ int i, pos;
+
+ for (i = 0; i < 8; i++) {
+ spear_dbi_read_reg(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
+ (u32 *)&val);
+ if (val) {
+ pos = 0;
+ while ((pos = find_next_bit(&val, 32, pos)) != 32) {
+ generic_handle_irq(SPEAR_MSI0_INT_BASE
+ + pp->port * SPEAR_NUM_MSI_IRQS
+ + (i * 32) + pos);
+ pos++;
+ }
+ }
+ spear_dbi_write_reg(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
+ }
+}
+#else
+static void handle_msi(struct pcie_port *pp)
+{
+}
+#endif
+
+static void spear_pcie_int_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct pcie_port *pp = &pcie_port[irq - IRQ_PCIE0];
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+ unsigned int status;
+
+ status = readl(&app_reg->int_sts);
+
+ desc->chip->ack(irq);
+
+ if (status & MSI_CTRL_INT) {
+ handle_msi(pp);
+ writel(MSI_CTRL_INT, &app_reg->int_clr);
+ } else if (status & INTA_CTRL_INT)
+ generic_handle_irq(SPEAR_INTX0_BASE
+ + pp->port * SPEAR_NUM_INTX_IRQS);
+ else if (status & INTB_CTRL_INT)
+ generic_handle_irq(SPEAR_INTX0_BASE
+ + pp->port * SPEAR_NUM_INTX_IRQS + 1);
+ else if (status & INTC_CTRL_INT)
+ generic_handle_irq(SPEAR_INTX0_BASE
+ + pp->port * SPEAR_NUM_INTX_IRQS + 2);
+ else if (status & INTD_CTRL_INT)
+ generic_handle_irq(SPEAR_INTX0_BASE
+ + pp->port * SPEAR_NUM_INTX_IRQS + 3);
+ else
+ writel(status, &app_reg->int_clr);
+
+ desc->chip->unmask(irq);
+}
+
+#ifdef CONFIG_PCI_MSI
+static int find_valid_pos0(int port, int nvec, int pos, int *pos0)
+{
+ int flag = 1;
+ do {
+ pos = find_next_zero_bit(msi_irq_in_use[port],
+ SPEAR_NUM_MSI_IRQS, pos);
+ /*if you have reached to the end then get out from here.*/
+ if (pos == SPEAR_NUM_MSI_IRQS)
+ return -ENOSPC;
+ /* Check if this position is at correct offset.nvec is always a
+ * power of two. pos0 must be nvec bit alligned.
+ */
+ if (pos % nvec)
+ pos += nvec - (pos % nvec);
+ else
+ flag = 0;
+ } while (flag);
+
+ *pos0 = pos;
+ return 0;
+}
+
+static void spear13xx_msi_nop(unsigned int irq)
+{
+ return;
+}
+
+static struct irq_chip spear13xx_msi_chip = {
+ .name = "PCI-MSI",
+ .ack = spear13xx_msi_nop,
+ .irq_enable = unmask_msi_irq,
+ .irq_disable = mask_msi_irq,
+ .irq_mask = mask_msi_irq,
+ .irq_unmask = unmask_msi_irq,
+};
+
+/*
+ * Dynamic irq allocate and deallocation
+ */
+static int get_irq(int nvec, struct msi_desc *desc, int *pos)
+{
+ int res, bit, irq, pos0, pos1, i;
+ u32 val;
+ struct pcie_port *pp = bus_to_port(desc->dev->bus->number);
+
+ pos0 = find_first_zero_bit(msi_irq_in_use[pp->port],
+ SPEAR_NUM_MSI_IRQS);
+ if (pos0 % nvec) {
+ if (find_valid_pos0(pp->port, nvec, pos0, &pos0))
+ goto no_valid_irq;
+ }
+ if (nvec > 1) {
+ pos1 = find_next_bit(msi_irq_in_use[pp->port],
+ SPEAR_NUM_MSI_IRQS, pos0);
+ /* there must be nvec number of consecutive free bits */
+ while ((pos1 - pos0) < nvec) {
+ if (find_valid_pos0(pp->port, nvec, pos1, &pos0))
+ goto no_valid_irq;
+ pos1 = find_next_bit(msi_irq_in_use[pp->port],
+ SPEAR_NUM_MSI_IRQS, pos0);
+ }
+ }
+
+ irq = (SPEAR_MSI0_INT_BASE + (pp->port * SPEAR_NUM_MSI_IRQS)) + pos0;;
+
+ if ((irq + nvec) > (SPEAR_MSI0_INT_END
+ + (pp->port * SPEAR_NUM_MSI_IRQS)))
+ goto no_valid_irq;
+
+ i = 0;
+ while (i < nvec) {
+ set_bit(pos0 + i, msi_irq_in_use[pp->port]);
+ dynamic_irq_init(irq + i);
+ set_irq_msi(irq + i, desc);
+ set_irq_chip_and_handler(irq + i, &spear13xx_msi_chip,
+ handle_simple_irq);
+
+ /* Enable corresponding interrupt on MSI interrupt
+ * controller.
+ */
+ res = ((pos0 + i) / 32) * 12;
+ bit = (pos0 + i) % 32;
+ spear_dbi_read_reg(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
+ val |= 1 << bit;
+ spear_dbi_write_reg(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+
+ i++;
+ }
+
+ *pos = pos0;
+ return irq;
+no_valid_irq:
+ *pos = pos0;
+ return -ENOSPC;
+}
+
+static void clean_irq(unsigned int irq)
+{
+ int res, bit, val, pos;
+ struct irq_desc *desc = irq_to_desc(irq);
+ struct pcie_port *pp = bus_to_port(desc->msi_desc->dev->bus->number);
+
+ pos = irq - (SPEAR_MSI0_INT_BASE + (pp->port * SPEAR_NUM_MSI_IRQS));
+
+ dynamic_irq_cleanup(irq);
+
+ clear_bit(pos, msi_irq_in_use[pp->port]);
+
+ /* Disable corresponding interrupt on MSI interrupt
+ * controller.
+ */
+ res = (pos / 32) * 12;
+ bit = pos % 32;
+ spear_dbi_read_reg(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
+ val &= ~(1 << bit);
+ spear_dbi_write_reg(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+
+}
+
+int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
+{
+ int cvec, rvec, irq, pos;
+ struct msi_msg msg;
+ uint16_t control;
+ struct pcie_port *pp = bus_to_port(pdev->bus->number);
+
+ /*
+ * Read the MSI config to figure out how many IRQs this device
+ * wants.Most devices only want 1, which will give
+ * configured_private_bits and request_private_bits equal 0.
+ */
+ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
+ &control);
+
+ /*
+ * If the number of private bits has been configured then use
+ * that value instead of the requested number. This gives the
+ * driver the chance to override the number of interrupts
+ * before calling pci_enable_msi().
+ */
+
+ cvec = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
+
+ if (cvec == 0) {
+ /* Nothing is configured, so use the hardware requested size */
+ rvec = (control & PCI_MSI_FLAGS_QMASK) >> 1;
+ } else {
+ /*
+ * Use the number of configured bits, assuming the
+ * driver wanted to override the hardware request
+ * value.
+ */
+ rvec = cvec;
+ }
+
+ /*
+ * The PCI 2.3 spec mandates that there are at most 32
+ * interrupts. If this device asks for more, only give it one.
+ */
+ if (rvec > 5)
+ rvec = 0;
+
+ irq = get_irq((1 << rvec), desc, &pos);
+
+ if (irq < 0)
+ return irq;
+
+ /* Update the number of IRQs the device has available to it */
+ control &= ~PCI_MSI_FLAGS_QSIZE;
+ control |= rvec << 4;
+ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
+ control);
+ desc->msi_attrib.multiple = rvec;
+
+ /* An EP will modify lower 8 bits(max) of msi data while
+ * sending any msi interrupt
+ */
+ msg.address_hi = 0x0;
+ msg.address_lo = __virt_to_phys((u32)(&spear_msi_data[pp->port]));
+ msg.data = pos;
+ write_msi_msg(irq, &msg);
+
+ return 0;
+}
+
+void arch_teardown_msi_irq(unsigned int irq)
+{
+ clean_irq(irq);
+}
+
+static void spear13xx_msi_init(struct pcie_port *pp)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+
+ spear_dbi_write_reg(pp, PCIE_MSI_ADDR_LO, 4,
+ __virt_to_phys((u32)(&spear_msi_data[pp->port])));
+ spear_dbi_write_reg(pp, PCIE_MSI_ADDR_HI, 4, 0);
+ /* Enbale MSI interrupt*/
+ writel(readl(&app_reg->int_mask) | MSI_CTRL_INT,
+ &app_reg->int_mask);
+}
+#endif
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index df063e9..ad1c6a0 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -18,6 +18,7 @@
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/spear.h>
+#include <mach/pcie.h>
#include <plat/keyboard.h>
#include <plat/fsmc.h>
@@ -50,6 +51,30 @@ static struct kbd_platform_data kbd_data = {
.rep = 1,
};
+#ifdef CONFIG_PCIEPORTBUS
+/* this function is needed for PCIE host and device driver. Same
+ * controller can not be programmed as host as well as device. So host
+ * driver must call this function and if this function returns 1 then
+ * only host should add that particular port as RC.
+ * A port to be added as device, one must also add device's information
+ * in plat_devs array defined in this file.
+ * it is the responsibility of calling function to not send port number
+ * greter than max no of controller(3)
+ */
+static int spear1300_pcie_port_is_host(int port)
+{
+ switch (port) {
+ case 0:
+ return 0;
+ case 1:
+ return 1;
+ case 2:
+ return 1;
+ }
+ return -EINVAL;
+}
+#endif
+
static void __init spear1300_evb_init(void)
{
unsigned int i;
@@ -68,6 +93,12 @@ static void __init spear1300_evb_init(void)
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
+#ifdef CONFIG_PCIEPORTBUS
+ /* Enable PCIE0 clk */
+ enable_pcie0_clk();
+ pcie_init(&spear1300_pcie_port_is_host);
+#endif
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 6352d88..86b4f98 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -299,6 +299,34 @@ struct platform_device spear13xx_rtc_device = {
.resource = rtc_resources,
};
+#ifdef CONFIG_PCIEPORTBUS
+/* PCIE0 clock always needs to be enabled if any of the three PCIE port
+ * have to be used. So call this function from the board initilization
+ * file. Ideally , all controller should have been independent from
+ * others with respect to clock.
+ */
+int enable_pcie0_clk(void)
+{
+ struct clk *clk;
+ /*Enable all CLK in CFG registers here only. Idealy only PCIE0
+ * should have been enabled. But Controler does not work
+ * properly if PCIE1 and PCIE2's CFG CLK is enabled in stages.
+ */
+ writel(PCIE0_CFG_VAL | PCIE1_CFG_VAL | PCIE2_CFG_VAL, PCIE_CFG);
+ clk = clk_get_sys("pcie0", NULL);
+ if (!clk) {
+ pr_err("%s:couldn't get clk for pcie0\n", __func__);
+ return -ENODEV;
+ }
+ if (clk_enable(clk)) {
+ pr_err("%s:couldn't enable clk for pcie0\n", __func__);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+#endif
+
/* Do spear13xx familiy common initialization part here */
void __init spear13xx_init(void)
{
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 80f402b..21f31cd 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -12,6 +12,8 @@ config ARCH_SPEAR13XX
bool "SPEAr13XX"
select ARM_GIC
select CPU_V7
+ select ARCH_SUPPORTS_MSI
+ select MIGHT_HAVE_PCI
help
Supports for ARM's SPEAR13XX family
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 26/62] ST SPEAr: Adding support for SSP PL022
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (23 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 25/62] ST SPEAr: Added PCIE host controller base driver support Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 16:18 ` Russell King - ARM Linux
2011-01-18 7:11 ` [PATCH V4 27/62] ST SPEAr: Adding support for SDHCI (SDIO) Viresh Kumar
` (36 subsequent siblings)
61 siblings, 1 reply; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 1 +
arch/arm/mach-spear13xx/spear1300_evb.c | 10 +++
arch/arm/mach-spear13xx/spear13xx.c | 31 ++++++++++
arch/arm/mach-spear3xx/include/mach/generic.h | 2 +
arch/arm/mach-spear3xx/spear300_evb.c | 25 ++++++++
arch/arm/mach-spear3xx/spear310_evb.c | 37 ++++++++++++
arch/arm/mach-spear3xx/spear320.c | 42 +++++++++++++
arch/arm/mach-spear3xx/spear320_evb.c | 9 +++
arch/arm/mach-spear3xx/spear3xx.c | 31 ++++++++++
arch/arm/mach-spear6xx/include/mach/generic.h | 1 +
arch/arm/mach-spear6xx/include/mach/spear.h | 4 +-
arch/arm/mach-spear6xx/spear600_evb.c | 13 ++++
arch/arm/mach-spear6xx/spear6xx.c | 68 ++++++++++++++++++++++
arch/arm/plat-spear/include/plat/spi.h | 74 ++++++++++++++++++++++++
14 files changed, 346 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/plat-spear/include/plat/spi.h
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 77b3c15..47e90df 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -30,6 +30,7 @@
/* Add spear13xx family device structure declarations here */
extern struct amba_device spear13xx_gpio_device[];
+extern struct amba_device spear13xx_ssp_device;
extern struct amba_device spear13xx_uart_device;
extern struct platform_device spear13xx_ehci0_device;
extern struct platform_device spear13xx_ehci1_device;
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index ad1c6a0..088bf52 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -12,7 +12,10 @@
*/
#include <linux/types.h>
+#include <linux/gpio.h>
#include <linux/mtd/nand.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -21,10 +24,12 @@
#include <mach/pcie.h>
#include <plat/keyboard.h>
#include <plat/fsmc.h>
+#include <plat/spi.h>
static struct amba_device *amba_devs[] __initdata = {
&spear13xx_gpio_device[0],
&spear13xx_gpio_device[1],
+ &spear13xx_ssp_device,
&spear13xx_uart_device,
};
@@ -51,6 +56,9 @@ static struct kbd_platform_data kbd_data = {
.rep = 1,
};
+static struct spi_board_info __initdata spi_board_info[] = {
+};
+
#ifdef CONFIG_PCIEPORTBUS
/* this function is needed for PCIE host and device driver. Same
* controller can not be programmed as host as well as device. So host
@@ -105,6 +113,8 @@ static void __init spear1300_evb_init(void)
/* Add Amba Devices */
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
amba_device_register(amba_devs[i], &iomem_resource);
+
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}
MACHINE_START(SPEAR1300, "ST-SPEAR1300-EVB")
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 86b4f98..3cb305a 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -12,6 +12,7 @@
*/
#include <linux/types.h>
+#include <linux/amba/pl022.h>
#include <linux/amba/pl061.h>
#include <linux/ptrace.h>
#include <linux/io.h>
@@ -64,6 +65,36 @@ struct amba_device spear13xx_gpio_device[] = {
}
};
+/* ssp device registeration */
+static struct pl022_ssp_controller ssp_platform_data = {
+ .bus_id = 0,
+ .enable_dma = 0,
+ /*
+ * This is number of spi devices that can be connected to spi. There are
+ * two type of chipselects on which slave devices can work. One is chip
+ * select provided by spi masters other is controlled through external
+ * gpio's. We can't use chipselect provided from spi master (because as
+ * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+ * this number now depends on number of gpios available for spi. each
+ * slave on each master requires a separate gpio pin.
+ */
+ .num_chipselect = 2,
+};
+
+struct amba_device spear13xx_ssp_device = {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .init_name = "ssp-pl022",
+ .platform_data = &ssp_platform_data,
+ },
+ .res = {
+ .start = SPEAR13XX_SSP_BASE,
+ .end = SPEAR13XX_SSP_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SSP, NO_IRQ},
+};
+
/* uart device registeration */
struct amba_device spear13xx_uart_device = {
.dev = {
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 2e5ecbf..2141393 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -32,6 +32,7 @@
/* Add spear3xx family device structure declarations here */
extern struct amba_device gpio_device;
+extern struct amba_device ssp0_device;
extern struct amba_device uart_device;
extern struct amba_device wdt_device;
extern struct platform_device ehci_device;
@@ -175,6 +176,7 @@ void __init spear310_init(void);
#elif defined(CONFIG_MACH_SPEAR320)
/* Add spear320 machine device structure declarations here */
extern struct amba_device clcd_device;
+extern struct amba_device ssp_device[];
extern struct platform_device i2c1_device;
extern struct platform_device nand_device;
extern struct platform_device plgpio_device;
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index c219691..0e3d8f3 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -15,10 +15,14 @@
#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
#include <mach/generic.h>
+#include <mach/gpio.h>
#include <mach/spear.h>
#include <plat/fsmc.h>
#include <plat/keyboard.h>
+#include <plat/spi.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
@@ -39,6 +43,7 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&gpio_device,
+ &ssp0_device,
&uart_device,
&wdt_device,
@@ -72,6 +77,24 @@ static struct kbd_platform_data kbd_data = {
.rep = 1,
};
+/* spi board information */
+/* spi0 flash Chip Select Control function, controlled by gpio pin mentioned */
+DECLARE_SPI_CS_CONTROL(0, flash, RAS_GPIO_3);
+/* spi0 flash Chip Info structure */
+DECLARE_SPI_CHIP_INFO(0, flash, spi0_flash_cs_control);
+
+static struct spi_board_info __initdata spi_board_info[] = {
+ /* spi0 board info */
+ {
+ .modalias = "m25p80",
+ .controller_data = &spi0_flash_chip_info,
+ .max_speed_hz = 25000000,
+ .bus_num = 0,
+ .chip_select = 1,
+ .mode = SPI_MODE_1,
+ }
+};
+
static void __init spear300_evb_init(void)
{
unsigned int i;
@@ -100,6 +123,8 @@ static void __init spear300_evb_init(void)
/* Add Amba Devices */
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
amba_device_register(amba_devs[i], &iomem_resource);
+
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}
MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index d216c94..6daacbb 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -15,9 +15,13 @@
#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
#include <mach/generic.h>
+#include <mach/gpio.h>
#include <mach/spear.h>
#include <plat/fsmc.h>
+#include <plat/spi.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
@@ -46,6 +50,7 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&gpio_device,
+ &ssp0_device,
&uart_device,
&wdt_device,
@@ -65,6 +70,36 @@ static struct platform_device *plat_devs[] __initdata = {
&plgpio_device,
};
+/* spi board information */
+/* spi0 flash Chip Select Control function, controlled by gpio pin mentioned */
+DECLARE_SPI_CS_CONTROL(0, flash, BASIC_GPIO_3);
+/* spi0 flash Chip Info structure */
+DECLARE_SPI_CHIP_INFO(0, flash, spi0_flash_cs_control);
+
+/* spi0 spidev Chip Select Control function, controlled by gpio pin mentioned */
+DECLARE_SPI_CS_CONTROL(0, dev, BASIC_GPIO_4);
+/* spi0 spidev Chip Info structure */
+DECLARE_SPI_CHIP_INFO(0, dev, spi0_dev_cs_control);
+
+static struct spi_board_info __initdata spi_board_info[] = {
+ /* spi0 board info */
+ {
+ .modalias = "spidev",
+ .controller_data = &spi0_dev_chip_info,
+ .max_speed_hz = 25000000,
+ .bus_num = 0,
+ .chip_select = 0,
+ .mode = SPI_MODE_1,
+ }, {
+ .modalias = "m25p80",
+ .controller_data = &spi0_flash_chip_info,
+ .max_speed_hz = 25000000,
+ .bus_num = 0,
+ .chip_select = 1,
+ .mode = SPI_MODE_1,
+ }
+};
+
static void __init spear310_evb_init(void)
{
unsigned int i;
@@ -90,6 +125,8 @@ static void __init spear310_evb_init(void)
/* Add Amba Devices */
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
amba_device_register(amba_devs[i], &iomem_resource);
+
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}
MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 1fb6a83..8c970dc 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/amba/pl022.h>
#include <linux/ptrace.h>
#include <linux/mtd/fsmc.h>
#include <asm/irq.h>
@@ -403,6 +404,47 @@ struct amba_device clcd_device = {
.irq = {VIRQ_CLCD, NO_IRQ},
};
+/* ssp device registeration */
+static struct pl022_ssp_controller ssp_platform_data[] = {
+ {
+ .bus_id = 1,
+ .enable_dma = 0,
+ .num_chipselect = 2,
+ }, {
+ .bus_id = 2,
+ .enable_dma = 0,
+ .num_chipselect = 2,
+ }
+};
+
+struct amba_device ssp_device[] = {
+ {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .init_name = "ssp-pl022.1",
+ .platform_data = &ssp_platform_data[0],
+ },
+ .res = {
+ .start = SPEAR320_SSP0_BASE,
+ .end = SPEAR320_SSP0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_SSP1, NO_IRQ},
+ }, {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .init_name = "ssp-pl022.2",
+ .platform_data = &ssp_platform_data[1],
+ },
+ .res = {
+ .start = SPEAR320_SSP1_BASE,
+ .end = SPEAR320_SSP1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_SSP2, NO_IRQ},
+ }
+};
+
/* i2c1 device registeration */
static struct resource i2c1_resources[] = {
{
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 15db267..baa4574 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -15,9 +15,13 @@
#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
#include <mach/generic.h>
+#include <mach/gpio.h>
#include <mach/spear.h>
#include <plat/fsmc.h>
+#include <plat/spi.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
@@ -65,6 +69,9 @@ static struct platform_device *plat_devs[] __initdata = {
&pwm_device,
};
+static struct spi_board_info __initdata spi_board_info[] = {
+};
+
static void __init spear320_evb_init(void)
{
unsigned int i;
@@ -90,6 +97,8 @@ static void __init spear320_evb_init(void)
/* Add Amba Devices */
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
amba_device_register(amba_devs[i], &iomem_resource);
+
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}
MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 561949d..d8efad2 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -12,6 +12,7 @@
*/
#include <linux/types.h>
+#include <linux/amba/pl022.h>
#include <linux/amba/pl061.h>
#include <linux/ptrace.h>
#include <linux/io.h>
@@ -41,6 +42,36 @@ struct amba_device gpio_device = {
.irq = {IRQ_BASIC_GPIO, NO_IRQ},
};
+/* ssp device registration */
+static struct pl022_ssp_controller ssp_platform_data = {
+ .bus_id = 0,
+ .enable_dma = 0,
+ /*
+ * This is number of spi devices that can be connected to spi. There are
+ * two type of chipselects on which slave devices can work. One is chip
+ * select provided by spi masters other is controlled through external
+ * gpio's. We can't use chipselect provided from spi master (because as
+ * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+ * this number now depends on number of gpios available for spi. each
+ * slave on each master requires a separate gpio pin.
+ */
+ .num_chipselect = 2,
+};
+
+struct amba_device ssp0_device = {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .init_name = "ssp-pl022.0",
+ .platform_data = &ssp_platform_data,
+ },
+ .res = {
+ .start = SPEAR3XX_ICM1_SSP_BASE,
+ .end = SPEAR3XX_ICM1_SSP_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SSP, NO_IRQ},
+};
+
/* uart device registration */
struct amba_device uart_device = {
.dev = {
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 80695d69..1394e45 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -31,6 +31,7 @@
/* Add spear6xx family device structure declarations here */
extern struct amba_device clcd_device;
extern struct amba_device gpio_device[];
+extern struct amba_device ssp_device[];
extern struct amba_device uart_device[];
extern struct amba_device wdt_device;
extern struct platform_device ehci0_device;
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index a835f5b..31486e5 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -68,8 +68,8 @@
#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000
#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000
-#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000
-#define SPEAR6XX_ICM2_SPI2_SIZE 0x00080000
+#define SPEAR6XX_ICM2_SSP2_BASE 0xD8180000
+#define SPEAR6XX_ICM2_SSP2_SIZE 0x00080000
#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000
#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index 32d3855..fe9a8c8 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -15,15 +15,23 @@
#include <linux/mtd/fsmc.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <linux/gpio.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
#include <mach/generic.h>
+#include <mach/gpio.h>
#include <mach/spear.h>
#include <plat/fsmc.h>
+#include <plat/spi.h>
static struct amba_device *amba_devs[] __initdata = {
&clcd_device,
&gpio_device[0],
&gpio_device[1],
&gpio_device[2],
+ &ssp_device[0],
+ &ssp_device[1],
+ &ssp_device[2],
&uart_device[0],
&uart_device[1],
&wdt_device,
@@ -39,6 +47,9 @@ static struct platform_device *plat_devs[] __initdata = {
&rtc_device,
};
+static struct spi_board_info __initdata spi_board_info[] = {
+};
+
static void __init spear600_evb_init(void)
{
unsigned int i;
@@ -59,6 +70,8 @@ static void __init spear600_evb_init(void)
/* Add Amba Devices */
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
amba_device_register(amba_devs[i], &iomem_resource);
+
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 1832361..58f1a15 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -12,6 +12,7 @@
*/
#include <linux/types.h>
+#include <linux/amba/pl022.h>
#include <linux/amba/pl061.h>
#include <linux/ptrace.h>
#include <linux/io.h>
@@ -41,6 +42,73 @@ struct amba_device clcd_device = {
.irq = {IRQ_BASIC_CLCD, NO_IRQ},
};
+/* ssp device registration */
+static struct pl022_ssp_controller ssp_platform_data[] = {
+ {
+ .bus_id = 0,
+ .enable_dma = 0,
+ /*
+ * This is number of spi devices that can be connected to spi.
+ * There are two type of chipselects on which slave devices can
+ * work. One is chip select provided by spi masters other is
+ * controlled through external gpio's. We can't use chipselect
+ * provided from spi master (because as soon as FIFO becomes
+ * empty, CS is disabled and transfer ends). So this number now
+ * depends on number of gpios available for spi. each slave on
+ * each master requires a separate gpio pin.
+ */
+ .num_chipselect = 2,
+ }, {
+ .bus_id = 1,
+ .enable_dma = 0,
+ .num_chipselect = 2,
+ }, {
+ .bus_id = 2,
+ .enable_dma = 0,
+ .num_chipselect = 2,
+ }
+};
+
+struct amba_device ssp_device[] = {
+ {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .init_name = "ssp-pl022.0",
+ .platform_data = &ssp_platform_data[0],
+ },
+ .res = {
+ .start = SPEAR6XX_ICM1_SSP0_BASE,
+ .end = SPEAR6XX_ICM1_SSP0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SSP_1, NO_IRQ},
+ }, {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .init_name = "ssp-pl022.1",
+ .platform_data = &ssp_platform_data[1],
+ },
+ .res = {
+ .start = SPEAR6XX_ICM1_SSP1_BASE,
+ .end = SPEAR6XX_ICM1_SSP1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SSP_2, NO_IRQ},
+ }, {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .init_name = "ssp-pl022.2",
+ .platform_data = &ssp_platform_data[2],
+ },
+ .res = {
+ .start = SPEAR6XX_ICM2_SSP2_BASE,
+ .end = SPEAR6XX_ICM2_SSP2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_APPL_SSP, NO_IRQ},
+ }
+};
+
/* uart device registration */
struct amba_device uart_device[] = {
{
diff --git a/arch/arm/plat-spear/include/plat/spi.h b/arch/arm/plat-spear/include/plat/spi.h
new file mode 100644
index 0000000..24d57e1
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/spi.h
@@ -0,0 +1,74 @@
+/*
+ * arch/arm/plat-spear/include/plat/spi.h
+ *
+ * SPI board specific definitions common to multiple boards on multiple
+ * machines.
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_SPI_H
+#define __PLAT_SPI_H
+
+#include <linux/amba/pl022.h>
+#include <linux/gpio.h>
+
+/* spi board information */
+static inline int spi_cs_gpio_request(u32 gpio_pin)
+{
+ int ret;
+
+ ret = gpio_request(gpio_pin, "SPI_CS");
+ if (ret < 0) {
+ printk(KERN_ERR "SPI: gpio:%d request fail\n", gpio_pin);
+ return ret;
+ } else {
+ ret = gpio_direction_output(gpio_pin, 1);
+ if (ret) {
+ printk(KERN_ERR "SPI: gpio:%d direction set fail\n",
+ gpio_pin);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+/* This will define cs_control function for a specific spi slave */
+#define DECLARE_SPI_CS_CONTROL(id, type, gpio) \
+static void spi##id##_##type##_cs_control(u32 control) \
+{ \
+ static int count, ret; \
+ \
+ if (unlikely(!count)) { \
+ count++; \
+ ret = spi_cs_gpio_request(gpio); \
+ } \
+ \
+ if (!ret) \
+ gpio_set_value(gpio, control); \
+}
+
+/* This will define CHIP_INFO structure for a specific spi slave */
+#define DECLARE_SPI_CHIP_INFO(id, type, chip_select_control) \
+static struct pl022_config_chip spi##id##_##type##_chip_info = {\
+ .iface = SSP_INTERFACE_MOTOROLA_SPI, \
+ .hierarchy = SSP_MASTER, \
+ .slave_tx_disable = 0, \
+ .com_mode = INTERRUPT_TRANSFER, \
+ .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, \
+ .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, \
+ .ctrl_len = SSP_BITS_12, \
+ .wait_state = SSP_MWIRE_WAIT_ZERO, \
+ .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, \
+ .cs_control = chip_select_control, \
+};
+
+#define DECLARE_SPI_CHIP_INFO_NULL_ID(chip_select_control) \
+DECLARE_SPI_CHIP_INFO(, chip_select_control)
+
+#endif /* __PLAT_SPI_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 27/62] ST SPEAr: Adding support for SDHCI (SDIO)
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (24 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 26/62] ST SPEAr: Adding support for SSP PL022 Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 28/62] ST SPEAr: Changing resource size of amba devices to SZ_4K Viresh Kumar
` (35 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 1 +
arch/arm/mach-spear13xx/spear1300_evb.c | 1 +
arch/arm/mach-spear13xx/spear13xx.c | 34 +++++++++++++-
arch/arm/mach-spear3xx/include/mach/generic.h | 13 ++++--
arch/arm/mach-spear3xx/include/mach/irqs.h | 4 +-
arch/arm/mach-spear3xx/include/mach/spear300.h | 4 +-
arch/arm/mach-spear3xx/include/mach/spear320.h | 6 +-
arch/arm/mach-spear3xx/spear300.c | 62 ++++++++++++++++++++----
arch/arm/mach-spear3xx/spear300_evb.c | 18 +++++++-
arch/arm/mach-spear3xx/spear320.c | 43 +++++++++++++----
arch/arm/mach-spear3xx/spear320_evb.c | 15 +++++-
11 files changed, 167 insertions(+), 34 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 47e90df..e6fe7b3 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -40,6 +40,7 @@ extern struct platform_device spear13xx_nand_device;
extern struct platform_device spear13xx_ohci0_device;
extern struct platform_device spear13xx_ohci1_device;
extern struct platform_device spear13xx_rtc_device;
+extern struct platform_device spear13xx_sdhci_device;
extern struct sys_timer spear13xx_timer;
/* Add spear1300 machine device structure declarations here */
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 088bf52..ef30ffd 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -42,6 +42,7 @@ static struct platform_device *plat_devs[] __initdata = {
&spear13xx_ohci0_device,
&spear13xx_ohci1_device,
&spear13xx_rtc_device,
+ &spear13xx_sdhci_device,
};
/* keyboard specific platform data */
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 3cb305a..f7ff7d7 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -330,6 +330,16 @@ struct platform_device spear13xx_rtc_device = {
.resource = rtc_resources,
};
+static void sdhci_enable(void)
+{
+ unsigned val = readl(PERIP_CFG);
+
+ /* This function enables SD/MMC interface out of SD/MMC, CF, XD */
+ val &= ~(MCIF_SEL_MASK << MCIF_SEL_SHIFT);
+ val |= SD_MMC_ACTIVE << MCIF_SEL_SHIFT;
+ writel(val, PERIP_CFG);
+}
+
#ifdef CONFIG_PCIEPORTBUS
/* PCIE0 clock always needs to be enabled if any of the three PCIE port
* have to be used. So call this function from the board initilization
@@ -358,10 +368,32 @@ int enable_pcie0_clk(void)
}
#endif
+/* sdhci (sdio) device declaration */
+static struct resource sdhci_resources[] = {
+ {
+ .start = SPEAR13XX_MCIF_SDHCI_BASE,
+ .end = SPEAR13XX_MCIF_SDHCI_BASE + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_SDHCI,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device spear13xx_sdhci_device = {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ },
+ .name = "sdhci",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(sdhci_resources),
+ .resource = sdhci_resources,
+};
+
/* Do spear13xx familiy common initialization part here */
void __init spear13xx_init(void)
{
- /* nothing to do for now */
+ sdhci_enable();
}
/* This will initialize vic */
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 2141393..12af694 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -115,6 +115,7 @@ extern struct platform_device nand0_device;
extern struct platform_device nand1_device;
extern struct platform_device nand2_device;
extern struct platform_device nand3_device;
+extern struct platform_device sdhci_device;
/* pad mux modes */
extern struct pmx_mode nand_mode;
@@ -143,12 +144,15 @@ extern struct pmx_dev pmx_telecom_camera;
extern struct pmx_dev pmx_telecom_dac;
extern struct pmx_dev pmx_telecom_i2s;
extern struct pmx_dev pmx_telecom_boot_pins;
-extern struct pmx_dev pmx_telecom_sdio_4bit;
-extern struct pmx_dev pmx_telecom_sdio_8bit;
+extern struct pmx_dev pmx_telecom_sdhci_4bit;
+extern struct pmx_dev pmx_telecom_sdhci_8bit;
extern struct pmx_dev pmx_gpio1;
/* Add spear300 machine function declarations here */
void __init spear300_init(void);
+#define SDHCI_MEM_ENB 0x1
+#define I2S_MEM_ENB 0x2
+void sdhci_i2s_mem_enable(u8 mask);
/* Add misc structure declarations here */
extern struct clcd_board clcd_plat_data;
@@ -181,6 +185,7 @@ extern struct platform_device i2c1_device;
extern struct platform_device nand_device;
extern struct platform_device plgpio_device;
extern struct platform_device pwm_device;
+extern struct platform_device sdhci_device;
/* pad mux modes */
extern struct pmx_mode auto_net_smii_mode;
@@ -193,14 +198,14 @@ extern struct pmx_dev pmx_clcd;
extern struct pmx_dev pmx_emi;
extern struct pmx_dev pmx_fsmc;
extern struct pmx_dev pmx_spp;
-extern struct pmx_dev pmx_sdio;
+extern struct pmx_dev pmx_sdhci;
extern struct pmx_dev pmx_i2s;
extern struct pmx_dev pmx_uart1;
extern struct pmx_dev pmx_uart1_modem;
extern struct pmx_dev pmx_uart2;
extern struct pmx_dev pmx_touchscreen;
extern struct pmx_dev pmx_can;
-extern struct pmx_dev pmx_sdio_led;
+extern struct pmx_dev pmx_sdhci_led;
extern struct pmx_dev pmx_pwm0;
extern struct pmx_dev pmx_pwm1;
extern struct pmx_dev pmx_pwm2;
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 5ad7574..df0c1f3 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -69,7 +69,7 @@
#define IRQ_CLCD IRQ_GEN_RAS_3
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define IRQ_SDIO IRQ_INTRCOMM_RAS_ARM
+#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM
/* GPIO pins virtual irqs */
#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9)
@@ -115,7 +115,7 @@
#define VIRQ_SPP (VIRQ_START + 2)
/* IRQs sharing IRQ_GEN_RAS_2 */
-#define IRQ_SDIO IRQ_GEN_RAS_2
+#define IRQ_SDHCI IRQ_GEN_RAS_2
/* IRQs sharing IRQ_GEN_RAS_3 */
#define VIRQ_PLGPIO (VIRQ_START + 3)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index ccaa765..1059d5a 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -39,8 +39,8 @@
#define SPEAR300_CLCD_BASE 0x60000000
#define SPEAR300_CLCD_SIZE 0x10000000
-#define SPEAR300_SDIO_BASE 0x70000000
-#define SPEAR300_SDIO_SIZE 0x10000000
+#define SPEAR300_SDHCI_BASE 0x70000000
+#define SPEAR300_SDHCI_SIZE 0x10000000
#define SPEAR300_NAND_0_BASE 0x80000000
#define SPEAR300_NAND_0_SIZE 0x04000000
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index aa6727c..89f5bfb 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -28,8 +28,8 @@
#define SPEAR320_I2S_BASE 0x60000000
#define SPEAR320_I2S_SIZE 0x10000000
-#define SPEAR320_SDIO_BASE 0x70000000
-#define SPEAR320_SDIO_SIZE 0x10000000
+#define SPEAR320_SDHCI_BASE 0x70000000
+#define SPEAR320_SDHCI_SIZE 0x10000000
#define SPEAR320_CLCD_BASE 0x90000000
#define SPEAR320_CLCD_SIZE 0x10000000
@@ -77,7 +77,7 @@
#define EMI_IRQ_MASK (1 << 7)
#define CLCD_IRQ_MASK (1 << 8)
#define SPP_IRQ_MASK (1 << 9)
-#define SDIO_IRQ_MASK (1 << 10)
+#define SDHCI_IRQ_MASK (1 << 10)
#define CAN_U_IRQ_MASK (1 << 11)
#define CAN_L_IRQ_MASK (1 << 12)
#define UART1_IRQ_MASK (1 << 13)
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 58b3e44..fceb71f 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -311,7 +311,7 @@ struct pmx_dev pmx_telecom_boot_pins = {
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
+struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
{
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -324,14 +324,14 @@ struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
},
};
-struct pmx_dev pmx_telecom_sdio_4bit = {
- .name = "telecom_sdio_4bit",
- .modes = pmx_telecom_sdio_4bit_modes,
- .mode_count = ARRAY_SIZE(pmx_telecom_sdio_4bit_modes),
+struct pmx_dev pmx_telecom_sdhci_4bit = {
+ .name = "telecom_sdhci_4bit",
+ .modes = pmx_telecom_sdhci_4bit_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
+struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
{
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -343,10 +343,10 @@ struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
},
};
-struct pmx_dev pmx_telecom_sdio_8bit = {
- .name = "telecom_sdio_8bit",
- .modes = pmx_telecom_sdio_8bit_modes,
- .mode_count = ARRAY_SIZE(pmx_telecom_sdio_8bit_modes),
+struct pmx_dev pmx_telecom_sdhci_8bit = {
+ .name = "telecom_sdhci_8bit",
+ .modes = pmx_telecom_sdhci_8bit_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
.enb_on_reset = 1,
};
@@ -524,6 +524,28 @@ struct platform_device nand3_device = {
.dev.platform_data = &nand3_platform_data,
};
+/* sdhci (sdio) device declaration */
+static struct resource sdhci_resources[] = {
+ {
+ .start = SPEAR300_SDHCI_BASE,
+ .end = SPEAR300_SDHCI_BASE + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_SDHCI,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device sdhci_device = {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ },
+ .name = "sdhci",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(sdhci_resources),
+ .resource = sdhci_resources,
+};
+
/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
{
@@ -577,6 +599,26 @@ struct spear_shirq shirq_ras1 = {
},
};
+/* Function handling sdhci and i2s memory sharing */
+#define SDHCI_MEM_SELECT 0x20000000
+void sdhci_i2s_mem_enable(u8 mask)
+{
+ u32 val;
+ void __iomem *base = ioremap(SPEAR300_SOC_CONFIG_BASE,
+ SPEAR300_SOC_CONFIG_SIZE);
+ if (!base) {
+ pr_debug("sdhci_i2s_enb: ioremap fail\n");
+ return;
+ }
+
+ val = readl(base + MODE_CONFIG_REG);
+ if (mask == SDHCI_MEM_ENB)
+ val |= SDHCI_MEM_SELECT;
+ else
+ val &= ~SDHCI_MEM_SELECT;
+ writel(val, base + MODE_CONFIG_REG);
+}
+
/* spear300 routines */
void __init spear300_init(void)
{
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 0e3d8f3..8e6fff0 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -17,6 +17,7 @@
#include <asm/mach-types.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
+#include <linux/mmc/sdhci-spear.h>
#include <mach/generic.h>
#include <mach/gpio.h>
#include <mach/spear.h>
@@ -36,7 +37,7 @@ static struct pmx_dev *pmx_devs[] = {
/* spear300 specific devices */
&pmx_fsmc_2_chips,
&pmx_clcd,
- &pmx_telecom_sdio_4bit,
+ &pmx_telecom_sdhci_4bit,
&pmx_gpio1,
};
@@ -63,6 +64,15 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear300 specific devices */
&kbd_device,
+ &sdhci_device,
+};
+
+/* sdhci board specific information */
+static struct sdhci_plat_data sdhci_plat_data = {
+ .card_power_gpio = RAS_GPIO_2,
+ .power_active_high = 0,
+ .power_always_enb = 0,
+ .card_int_gpio = RAS_GPIO_0,
};
/* keyboard specific platform data */
@@ -111,6 +121,12 @@ static void __init spear300_evb_init(void)
fsmc_nand_set_plat_data(&nand0_device, NULL, 0, NAND_SKIP_BBTSCAN,
FSMC_NAND_BW8);
+ /* set sdhci device platform data */
+ sdhci_set_plat_data(&sdhci_device, &sdhci_plat_data);
+
+ /* Enable sdhci memory */
+ sdhci_i2s_mem_enable(SDHCI_MEM_ENB);
+
/* call spear300 machine init function */
spear300_init();
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 8c970dc..6ab35db 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -13,6 +13,8 @@
#include <linux/amba/pl022.h>
#include <linux/ptrace.h>
+#include <linux/types.h>
+#include <linux/mmc/sdhci-spear.h>
#include <linux/mtd/fsmc.h>
#include <asm/irq.h>
#include <mach/generic.h>
@@ -113,7 +115,7 @@ struct pmx_dev pmx_spp = {
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_sdio_modes[] = {
+struct pmx_dev_mode pmx_sdhci_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
SMALL_PRINTERS_MODE,
@@ -121,10 +123,10 @@ struct pmx_dev_mode pmx_sdio_modes[] = {
},
};
-struct pmx_dev pmx_sdio = {
- .name = "sdio",
- .modes = pmx_sdio_modes,
- .mode_count = ARRAY_SIZE(pmx_sdio_modes),
+struct pmx_dev pmx_sdhci = {
+ .name = "sdhci",
+ .modes = pmx_sdhci_modes,
+ .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
.enb_on_reset = 1,
};
@@ -218,17 +220,17 @@ struct pmx_dev pmx_can = {
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_sdio_led_modes[] = {
+struct pmx_dev_mode pmx_sdhci_led_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
.mask = PMX_SSP_CS_MASK,
},
};
-struct pmx_dev pmx_sdio_led = {
- .name = "sdio_led",
- .modes = pmx_sdio_led_modes,
- .mode_count = ARRAY_SIZE(pmx_sdio_led_modes),
+struct pmx_dev pmx_sdhci_led = {
+ .name = "sdhci_led",
+ .modes = pmx_sdhci_led_modes,
+ .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
.enb_on_reset = 1,
};
@@ -536,6 +538,27 @@ struct platform_device pwm_device = {
.resource = pwm_resources,
};
+/* sdhci (sdio) device registeration */
+static struct resource sdhci_resources[] = {
+ {
+ .start = SPEAR320_SDHCI_BASE,
+ .end = SPEAR320_SDHCI_BASE + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_SDHCI,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device sdhci_device = {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ },
+ .name = "sdhci",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(sdhci_resources),
+ .resource = sdhci_resources,
+};
/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index baa4574..9dc8dc1 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -16,6 +16,7 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <linux/spi/flash.h>
+#include <linux/mmc/sdhci-spear.h>
#include <linux/spi/spi.h>
#include <mach/generic.h>
#include <mach/gpio.h>
@@ -33,7 +34,7 @@ static struct pmx_dev *pmx_devs[] = {
/* spear320 specific devices */
&pmx_fsmc,
- &pmx_sdio,
+ &pmx_sdhci,
&pmx_i2s,
&pmx_uart1,
&pmx_uart2,
@@ -67,6 +68,15 @@ static struct platform_device *plat_devs[] __initdata = {
&i2c1_device,
&plgpio_device,
&pwm_device,
+ &sdhci_device,
+};
+
+/* sdhci board specific information */
+static struct sdhci_plat_data sdhci_plat_data = {
+ .card_power_gpio = PLGPIO_61,
+ .power_active_high = 0,
+ .power_always_enb = 1,
+ .card_int_gpio = -1,
};
static struct spi_board_info __initdata spi_board_info[] = {
@@ -76,6 +86,9 @@ static void __init spear320_evb_init(void)
{
unsigned int i;
+ /* set sdhci device platform data */
+ sdhci_set_plat_data(&sdhci_device, &sdhci_plat_data);
+
/* padmux initialization, must be done before spear320_init */
pmx_driver.mode = &auto_net_mii_mode;
pmx_driver.devs = pmx_devs;
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 28/62] ST SPEAr: Changing resource size of amba devices to SZ_4K
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (25 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 27/62] ST SPEAr: Adding support for SDHCI (SDIO) Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 29/62] ST SPEAr: Replacing SIZE macro's with actual required size Viresh Kumar
` (34 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear3xx/spear300.c | 2 +-
arch/arm/mach-spear3xx/spear320.c | 2 +-
arch/arm/mach-spear3xx/spear3xx.c | 2 +-
arch/arm/mach-spear6xx/spear6xx.c | 8 +++-----
4 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index fceb71f..6989407 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -382,7 +382,7 @@ struct amba_device clcd_device = {
},
.res = {
.start = SPEAR300_CLCD_BASE,
- .end = SPEAR300_CLCD_BASE + SPEAR300_CLCD_SIZE - 1,
+ .end = SPEAR300_CLCD_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.dma_mask = ~0,
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 6ab35db..ab4ad8e 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -399,7 +399,7 @@ struct amba_device clcd_device = {
},
.res = {
.start = SPEAR320_CLCD_BASE,
- .end = SPEAR320_CLCD_BASE + SPEAR320_CLCD_SIZE - 1,
+ .end = SPEAR320_CLCD_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.dma_mask = ~0,
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index d8efad2..61db0b2f 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -79,7 +79,7 @@ struct amba_device uart_device = {
},
.res = {
.start = SPEAR3XX_ICM1_UART_BASE,
- .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1,
+ .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.irq = {IRQ_UART, NO_IRQ},
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 58f1a15..d00b581 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -35,7 +35,7 @@ struct amba_device clcd_device = {
},
.res = {
.start = SPEAR6XX_ICM3_CLCD_BASE,
- .end = SPEAR6XX_ICM3_CLCD_BASE + SPEAR6XX_ICM3_CLCD_SIZE - 1,
+ .end = SPEAR6XX_ICM3_CLCD_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.dma_mask = ~0,
@@ -117,8 +117,7 @@ struct amba_device uart_device[] = {
},
.res = {
.start = SPEAR6XX_ICM1_UART0_BASE,
- .end = SPEAR6XX_ICM1_UART0_BASE +
- SPEAR6XX_ICM1_UART0_SIZE - 1,
+ .end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.irq = {IRQ_UART_0, NO_IRQ},
@@ -128,8 +127,7 @@ struct amba_device uart_device[] = {
},
.res = {
.start = SPEAR6XX_ICM1_UART1_BASE,
- .end = SPEAR6XX_ICM1_UART1_BASE +
- SPEAR6XX_ICM1_UART1_SIZE - 1,
+ .end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.irq = {IRQ_UART_1, NO_IRQ},
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 29/62] ST SPEAr: Replacing SIZE macro's with actual required size
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (26 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 28/62] ST SPEAr: Changing resource size of amba devices to SZ_4K Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 30/62] SPEAr: defines base addresses as ulong Viresh Kumar
` (33 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
In arch specific files SIZE macro's were defined which were used for
creating memory/io mappings for sepecific devices. These macro's are
coming straight from h/w user manual and are much greated than required
sizes. Replacing these macros by actual required size.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/spear300.c | 9 +++------
arch/arm/mach-spear3xx/spear310.c | 2 +-
arch/arm/mach-spear3xx/spear320.c | 2 +-
arch/arm/mach-spear3xx/spear3xx.c | 8 ++++----
arch/arm/mach-spear6xx/spear6xx.c | 10 +++++-----
5 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 6989407..30e893f 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -604,8 +604,7 @@ struct spear_shirq shirq_ras1 = {
void sdhci_i2s_mem_enable(u8 mask)
{
u32 val;
- void __iomem *base = ioremap(SPEAR300_SOC_CONFIG_BASE,
- SPEAR300_SOC_CONFIG_SIZE);
+ void __iomem *base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
if (!base) {
pr_debug("sdhci_i2s_enb: ioremap fail\n");
return;
@@ -628,8 +627,7 @@ void __init spear300_init(void)
spear3xx_init();
/* shared irq registration */
- shirq_ras1.regs.base =
- ioremap(SPEAR300_TELECOM_BASE, SPEAR300_TELECOM_REG_SIZE);
+ shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
if (shirq_ras1.regs.base) {
ret = spear_shirq_register(&shirq_ras1);
if (ret)
@@ -637,8 +635,7 @@ void __init spear300_init(void)
}
/* pmx initialization */
- pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE,
- SPEAR300_SOC_CONFIG_SIZE);
+ pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
if (pmx_driver.base) {
ret = pmx_register(&pmx_driver);
if (ret)
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index bb9ff7c..ffc1f63 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -362,7 +362,7 @@ void __init spear310_init(void)
spear3xx_init();
/* shared irq registration */
- base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
+ base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
if (base) {
/* shirq 1 */
shirq_ras1.regs.base = base;
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index ab4ad8e..ac4f80b 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -694,7 +694,7 @@ void __init spear320_init(void)
spear3xx_init();
/* shared irq registration */
- base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE);
+ base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
if (base) {
/* shirq 1 */
shirq_ras1.regs.base = base;
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 61db0b2f..e98cdca 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -235,22 +235,22 @@ struct map_desc spear3xx_io_desc[] __initdata = {
{
.virtual = VA_SPEAR3XX_ICM1_UART_BASE,
.pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
- .length = SPEAR3XX_ICM1_UART_SIZE,
+ .length = SZ_4K,
.type = MT_DEVICE
}, {
.virtual = VA_SPEAR3XX_ML1_VIC_BASE,
.pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
- .length = SPEAR3XX_ML1_VIC_SIZE,
+ .length = SZ_4K,
.type = MT_DEVICE
}, {
.virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
- .length = SPEAR3XX_ICM3_SYS_CTRL_SIZE,
+ .length = SZ_4K,
.type = MT_DEVICE
}, {
.virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
- .length = SPEAR3XX_ICM3_MISC_REG_SIZE,
+ .length = SZ_4K,
.type = MT_DEVICE
},
};
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index d00b581..69287bf 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -389,27 +389,27 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
{
.virtual = VA_SPEAR6XX_ICM1_UART0_BASE,
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
- .length = SPEAR6XX_ICM1_UART0_SIZE,
+ .length = SZ_4K,
.type = MT_DEVICE
}, {
.virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
- .length = SPEAR6XX_CPU_VIC_PRI_SIZE,
+ .length = SZ_4K,
.type = MT_DEVICE
}, {
.virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
- .length = SPEAR6XX_CPU_VIC_SEC_SIZE,
+ .length = SZ_4K,
.type = MT_DEVICE
}, {
.virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
- .length = SPEAR6XX_ICM3_MISC_REG_BASE,
+ .length = SZ_4K,
.type = MT_DEVICE
}, {
.virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
- .length = SPEAR6XX_ICM3_MISC_REG_SIZE,
+ .length = SZ_4K,
.type = MT_DEVICE
},
};
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 30/62] SPEAr: defines base addresses as ulong.
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (27 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 29/62] ST SPEAr: Replacing SIZE macro's with actual required size Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 31/62] ST SPEAr: Adding miscellaneous devices Viresh Kumar
` (32 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
This patch defines base addresses as ulong.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/spear.h | 91 ++++++------
arch/arm/mach-spear3xx/include/mach/spear.h | 134 +++++-------------
arch/arm/mach-spear3xx/include/mach/spear300.h | 59 ++------
arch/arm/mach-spear3xx/include/mach/spear310.h | 34 ++---
arch/arm/mach-spear3xx/include/mach/spear320.h | 68 +++-------
arch/arm/mach-spear6xx/include/mach/spear.h | 174 ++++++-----------------
6 files changed, 172 insertions(+), 388 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 282ef2f..1a1af72 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -14,12 +14,13 @@
#ifndef __MACH_SPEAR13XX_H
#define __MACH_SPEAR13XX_H
+#include <asm/memory.h>
#include <mach/spear1300.h>
-#define SPEAR13XX_L2CC_BASE 0xED000000
+#define SPEAR13XX_L2CC_BASE UL(0xED000000)
/* ARM9SMP peripheral base address */
-#define SPEAR13XX_A9SM_PERIP_BASE 0xEC800000
+#define SPEAR13XX_A9SM_PERIP_BASE UL(0xEC800000)
#define VA_SPEAR13XX_A9SM_PERIP_BASE IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE)
/* A9SM peripheral offsets */
#define SPEAR13XX_SCU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x00)
@@ -29,26 +30,26 @@
#define SPEAR13XX_WDT_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x620)
#define SPEAR13XX_GIC_DIST_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x1000)
-#define SPEAR13XX_UART_BASE 0xE0000000
+#define SPEAR13XX_UART_BASE UL(0xE0000000)
#define VA_SPEAR13XX_UART_BASE IO_ADDRESS(SPEAR13XX_UART_BASE)
-#define SPEAR13XX_ADC_BASE 0xE0080000
-#define SPEAR13XX_SSP_BASE 0xE0100000
-#define SPEAR13XX_I2S0_BASE 0xE0180000
-#define SPEAR13XX_I2S1_BASE 0xE0200000
-#define SPEAR13XX_I2C_BASE 0xE0280000
-#define SPEAR13XX_KBD_BASE 0xE0300000
-#define SPEAR13XX_GPT0_BASE 0xE0380000
-#define SPEAR13XX_GPT1_BASE 0xE0400000
-#define SPEAR13XX_GPT2_BASE 0xE0480000
-#define SPEAR13XX_GPT3_BASE 0xE0500000
-#define SPEAR13XX_RTC_BASE 0xE0580000
-#define SPEAR13XX_GPIO0_BASE 0xE0600000
-#define SPEAR13XX_GPIO1_BASE 0xE0680000
-#define SPEAR13XX_MISC_BASE 0xE0700000
+#define SPEAR13XX_ADC_BASE UL(0xE0080000)
+#define SPEAR13XX_SSP_BASE UL(0xE0100000)
+#define SPEAR13XX_I2S0_BASE UL(0xE0180000)
+#define SPEAR13XX_I2S1_BASE UL(0xE0200000)
+#define SPEAR13XX_I2C_BASE UL(0xE0280000)
+#define SPEAR13XX_KBD_BASE UL(0xE0300000)
+#define SPEAR13XX_GPT0_BASE UL(0xE0380000)
+#define SPEAR13XX_GPT1_BASE UL(0xE0400000)
+#define SPEAR13XX_GPT2_BASE UL(0xE0480000)
+#define SPEAR13XX_GPT3_BASE UL(0xE0500000)
+#define SPEAR13XX_RTC_BASE UL(0xE0580000)
+#define SPEAR13XX_GPIO0_BASE UL(0xE0600000)
+#define SPEAR13XX_GPIO1_BASE UL(0xE0680000)
+#define SPEAR13XX_MISC_BASE UL(0xE0700000)
#define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
-#define SPEAR13XX_SYSRAM0_BASE 0xB3800000
+#define SPEAR13XX_SYSRAM0_BASE UL(0xB3800000)
#define SPEAR13XX_SYSRAM0_SIZE 0x00800000
/*
@@ -57,34 +58,34 @@
*/
#define SPEAR13XX_SYS_LOCATION (SPEAR13XX_SYSRAM0_BASE + 0x600)
-#define SPEAR13XX_SYSRAM1_BASE 0xE0800000
+#define SPEAR13XX_SYSRAM1_BASE UL(0xE0800000)
#define SPEAR13XX_SYSRAM1_SIZE 0x00800000
-#define SPEAR13XX_CLCD_BASE 0xE1000000
-#define SPEAR13XX_C3_BASE 0xE1800000
-#define SPEAR13XX_GETH_BASE 0xE2000000
-#define SPEAR13XX_UPD_BASE 0xE2800000
-#define SPEAR13XX_UDC_BASE 0xE3800000
-#define SPEAR13XX_UHC0_OHCI_BASE 0xE4000000
-#define SPEAR13XX_UHC0_EHCI_BASE 0xE4800000
-#define SPEAR13XX_UHC1_OHCI_BASE 0xE5000000
-#define SPEAR13XX_UHC1_EHCI_BASE 0xE5800000
-#define SPEAR13XX_SMI_MEM_BASE 0xE6000000
-#define SPEAR13XX_SMI_CTRL_BASE 0xEA000000
-#define SPEAR13XX_DMAC0_BASE 0xEA800000
-#define SPEAR13XX_DMAC1_BASE 0xEB000000
-#define SPEAR13XX_MII_PHY_BASE 0xEB800000
-#define SPEAR13XX_MPMC_BASE 0xEC000000
-#define SPEAR13XX_PCIE0_BASE 0x80000000
-#define SPEAR13XX_PCIE1_BASE 0x90000000
-#define SPEAR13XX_PCIE2_BASE 0xC0000000
-#define SPEAR13XX_PCIE0_APP_BASE 0xB1000000
-#define SPEAR13XX_PCIE1_APP_BASE 0xB1800000
-#define SPEAR13XX_PCIE2_APP_BASE 0xB4000000
-#define SPEAR13XX_FSMC_MEM_BASE 0xA0000000
-#define SPEAR13XX_FSMC_BASE 0xB0000000
-#define SPEAR13XX_JPEG_BASE 0xB2000000
-#define SPEAR13XX_MCIF_CF_BASE 0xB2800000
-#define SPEAR13XX_MCIF_SDHCI_BASE 0xB3000000
+#define SPEAR13XX_CLCD_BASE UL(0xE1000000)
+#define SPEAR13XX_C3_BASE UL(0xE1800000)
+#define SPEAR13XX_GETH_BASE UL(0xE2000000)
+#define SPEAR13XX_UPD_BASE UL(0xE2800000)
+#define SPEAR13XX_UDC_BASE UL(0xE3800000)
+#define SPEAR13XX_UHC0_OHCI_BASE UL(0xE4000000)
+#define SPEAR13XX_UHC0_EHCI_BASE UL(0xE4800000)
+#define SPEAR13XX_UHC1_OHCI_BASE UL(0xE5000000)
+#define SPEAR13XX_UHC1_EHCI_BASE UL(0xE5800000)
+#define SPEAR13XX_SMI_MEM_BASE UL(0xE6000000)
+#define SPEAR13XX_SMI_CTRL_BASE UL(0xEA000000)
+#define SPEAR13XX_DMAC0_BASE UL(0xEA800000)
+#define SPEAR13XX_DMAC1_BASE UL(0xEB000000)
+#define SPEAR13XX_MII_PHY_BASE UL(0xEB800000)
+#define SPEAR13XX_MPMC_BASE UL(0xEC000000)
+#define SPEAR13XX_PCIE0_BASE UL(0x80000000)
+#define SPEAR13XX_PCIE1_BASE UL(0x90000000)
+#define SPEAR13XX_PCIE2_BASE UL(0xC0000000)
+#define SPEAR13XX_PCIE0_APP_BASE UL(0xB1000000)
+#define SPEAR13XX_PCIE1_APP_BASE UL(0xB1800000)
+#define SPEAR13XX_PCIE2_APP_BASE UL(0xB4000000)
+#define SPEAR13XX_FSMC_MEM_BASE UL(0xA0000000)
+#define SPEAR13XX_FSMC_BASE UL(0xB0000000)
+#define SPEAR13XX_JPEG_BASE UL(0xB2000000)
+#define SPEAR13XX_MCIF_CF_BASE UL(0xB2800000)
+#define SPEAR13XX_MCIF_SDHCI_BASE UL(0xB3000000)
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR13XX_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index dcca856..00828bb8 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -14,124 +14,62 @@
#ifndef __MACH_SPEAR3XX_H
#define __MACH_SPEAR3XX_H
+#include <asm/memory.h>
#include <mach/hardware.h>
#include <mach/spear300.h>
#include <mach/spear310.h>
#include <mach/spear320.h>
-#define SPEAR3XX_ML_SDRAM_BASE 0x00000000
-#define SPEAR3XX_ML_SDRAM_SIZE 0x40000000
+#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
-#define SPEAR3XX_ICM9_BASE 0xC0000000
-#define SPEAR3XX_ICM9_SIZE 0x10000000
+#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
/* ICM1 - Low speed connection */
-#define SPEAR3XX_ICM1_2_BASE 0xD0000000
-#define SPEAR3XX_ICM1_2_SIZE 0x10000000
-
-#define SPEAR3XX_ICM1_UART_BASE 0xD0000000
+#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
+#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_UART_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000
-#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000
-#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000
-#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000
-#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000
-
-#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000
-#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000
-#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000
+#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
+#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
+#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
+#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
+#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
+#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
/* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000
-#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000
-
-#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000
-#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000
+#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
+#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
/* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE 0xE0000000
-#define SPEAR3XX_ICM4_SIZE 0x08000000
-
-#define SPEAR3XX_ICM4_MII_BASE 0xE0800000
-#define SPEAR3XX_ICM4_MII_SIZE 0x00800000
-
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000
-#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000
-#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000
-#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000
-#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000
-#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000
-#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000
-#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000
+#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
+#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
+#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
+#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
+#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
+#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
+#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
+#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
+#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
/* ML1 - Multi Layer CPU Subsystem */
-#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000
-#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000
-
-#define SPEAR3XX_ML1_TMR_BASE 0xF0000000
-#define SPEAR3XX_ML1_TMR_SIZE 0x00100000
-
-#define SPEAR3XX_ML1_VIC_BASE 0xF1100000
+#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
+#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
+#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
-#define SPEAR3XX_ML1_VIC_SIZE 0x00100000
/* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000
-#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000
-
-#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000
-#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000
-
-#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000
-#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000
-
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
-#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
-
-#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000
-#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000
-#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000
-#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000
-#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000
+#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
+#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
+#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
+#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
+#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
+#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
+#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
+#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
+#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000
+#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000
-#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000
+#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index 1059d5a..c723515 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -17,11 +17,9 @@
#define __MACH_SPEAR300_H
/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE 0x50000000
-#define SPEAR300_TELECOM_SIZE 0x10000000
+#define SPEAR300_TELECOM_BASE UL(0x50000000)
/* Interrupt registers offsets and masks */
-#define SPEAR300_TELECOM_REG_SIZE 0x00010000
#define INT_ENB_MASK_REG 0x54
#define INT_STS_MASK_REG 0x58
#define IT_PERS_S_IRQ_MASK (1 << 0)
@@ -36,47 +34,20 @@
#define SHIRQ_RAS1_MASK 0x1FF
-#define SPEAR300_CLCD_BASE 0x60000000
-#define SPEAR300_CLCD_SIZE 0x10000000
-
-#define SPEAR300_SDHCI_BASE 0x70000000
-#define SPEAR300_SDHCI_SIZE 0x10000000
-
-#define SPEAR300_NAND_0_BASE 0x80000000
-#define SPEAR300_NAND_0_SIZE 0x04000000
-
-#define SPEAR300_NAND_1_BASE 0x84000000
-#define SPEAR300_NAND_1_SIZE 0x04000000
-
-#define SPEAR300_NAND_2_BASE 0x88000000
-#define SPEAR300_NAND_2_SIZE 0x04000000
-
-#define SPEAR300_NAND_3_BASE 0x8c000000
-#define SPEAR300_NAND_3_SIZE 0x04000000
-
-#define SPEAR300_NOR_0_BASE 0x90000000
-#define SPEAR300_NOR_0_SIZE 0x01000000
-
-#define SPEAR300_NOR_1_BASE 0x91000000
-#define SPEAR300_NOR_1_SIZE 0x01000000
-
-#define SPEAR300_NOR_2_BASE 0x92000000
-#define SPEAR300_NOR_2_SIZE 0x01000000
-
-#define SPEAR300_NOR_3_BASE 0x93000000
-#define SPEAR300_NOR_3_SIZE 0x01000000
-
-#define SPEAR300_FSMC_BASE 0x94000000
-#define SPEAR300_FSMC_SIZE 0x05000000
-
-#define SPEAR300_SOC_CONFIG_BASE 0x99000000
-#define SPEAR300_SOC_CONFIG_SIZE 0x00000008
-
-#define SPEAR300_KEYBOARD_BASE 0xA0000000
-#define SPEAR300_KEYBOARD_SIZE 0x09000000
-
-#define SPEAR300_GPIO_BASE 0xA9000000
-#define SPEAR300_GPIO_SIZE 0x07000000
+#define SPEAR300_CLCD_BASE UL(0x60000000)
+#define SPEAR300_SDHCI_BASE UL(0x70000000)
+#define SPEAR300_NAND_0_BASE UL(0x80000000)
+#define SPEAR300_NAND_1_BASE UL(0x84000000)
+#define SPEAR300_NAND_2_BASE UL(0x88000000)
+#define SPEAR300_NAND_3_BASE UL(0x8c000000)
+#define SPEAR300_NOR_0_BASE UL(0x90000000)
+#define SPEAR300_NOR_1_BASE UL(0x91000000)
+#define SPEAR300_NOR_2_BASE UL(0x92000000)
+#define SPEAR300_NOR_3_BASE UL(0x93000000)
+#define SPEAR300_FSMC_BASE UL(0x94000000)
+#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
+#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
+#define SPEAR300_GPIO_BASE UL(0xA9000000)
#endif /* __MACH_SPEAR300_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index b27bb8a..1e85347 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -16,30 +16,18 @@
#ifndef __MACH_SPEAR310_H
#define __MACH_SPEAR310_H
-#define SPEAR310_NAND_BASE 0x40000000
-#define SPEAR310_NAND_SIZE 0x04000000
+#define SPEAR310_NAND_BASE UL(0x40000000)
+#define SPEAR310_FSMC_BASE UL(0x44000000)
+#define SPEAR310_UART1_BASE UL(0xB2000000)
+#define SPEAR310_UART2_BASE UL(0xB2080000)
+#define SPEAR310_UART3_BASE UL(0xB2100000)
+#define SPEAR310_UART4_BASE UL(0xB2180000)
+#define SPEAR310_UART5_BASE UL(0xB2200000)
+#define SPEAR310_HDLC_BASE UL(0xB2800000)
+#define SPEAR310_RS485_0_BASE UL(0xB3000000)
+#define SPEAR310_RS485_1_BASE UL(0xB3800000)
+#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
-#define SPEAR310_FSMC_BASE 0x44000000
-#define SPEAR310_FSMC_SIZE 0x01000000
-
-#define SPEAR310_UART1_BASE 0xB2000000
-#define SPEAR310_UART2_BASE 0xB2080000
-#define SPEAR310_UART3_BASE 0xB2100000
-#define SPEAR310_UART4_BASE 0xB2180000
-#define SPEAR310_UART5_BASE 0xB2200000
-#define SPEAR310_UART_SIZE 0x00080000
-
-#define SPEAR310_HDLC_BASE 0xB2800000
-#define SPEAR310_HDLC_SIZE 0x00800000
-
-#define SPEAR310_RS485_0_BASE 0xB3000000
-#define SPEAR310_RS485_0_SIZE 0x00800000
-
-#define SPEAR310_RS485_1_BASE 0xB3800000
-#define SPEAR310_RS485_1_SIZE 0x00800000
-
-#define SPEAR310_SOC_CONFIG_BASE 0xB4000000
-#define SPEAR310_SOC_CONFIG_SIZE 0x00000070
/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04
#define SMII0_IRQ_MASK (1 << 0)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 89f5bfb..940f0d8 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -16,57 +16,25 @@
#ifndef __MACH_SPEAR320_H
#define __MACH_SPEAR320_H
-#define SPEAR320_EMI_CTRL_BASE 0x40000000
-#define SPEAR320_EMI_CTRL_SIZE 0x08000000
+#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
+#define SPEAR320_FSMC_BASE UL(0x4C000000)
+#define SPEAR320_NAND_BASE UL(0x50000000)
+#define SPEAR320_I2S_BASE UL(0x60000000)
+#define SPEAR320_SDHCI_BASE UL(0x70000000)
+#define SPEAR320_CLCD_BASE UL(0x90000000)
+#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
+#define SPEAR320_CAN0_BASE UL(0xA1000000)
+#define SPEAR320_CAN1_BASE UL(0xA2000000)
+#define SPEAR320_UART1_BASE UL(0xA3000000)
+#define SPEAR320_UART2_BASE UL(0xA4000000)
+#define SPEAR320_SSP0_BASE UL(0xA5000000)
+#define SPEAR320_SSP1_BASE UL(0xA6000000)
+#define SPEAR320_I2C_BASE UL(0xA7000000)
+#define SPEAR320_PWM_BASE UL(0xA8000000)
+#define SPEAR320_SMII0_BASE UL(0xAA000000)
+#define SPEAR320_SMII1_BASE UL(0xAB000000)
+#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
-#define SPEAR320_FSMC_BASE 0x4C000000
-#define SPEAR320_FSMC_SIZE 0x01000000
-
-#define SPEAR320_NAND_BASE 0x50000000
-#define SPEAR320_NAND_SIZE 0x04000000
-
-#define SPEAR320_I2S_BASE 0x60000000
-#define SPEAR320_I2S_SIZE 0x10000000
-
-#define SPEAR320_SDHCI_BASE 0x70000000
-#define SPEAR320_SDHCI_SIZE 0x10000000
-
-#define SPEAR320_CLCD_BASE 0x90000000
-#define SPEAR320_CLCD_SIZE 0x10000000
-
-#define SPEAR320_PAR_PORT_BASE 0xA0000000
-#define SPEAR320_PAR_PORT_SIZE 0x01000000
-
-#define SPEAR320_CAN0_BASE 0xA1000000
-#define SPEAR320_CAN0_SIZE 0x01000000
-
-#define SPEAR320_CAN1_BASE 0xA2000000
-#define SPEAR320_CAN1_SIZE 0x01000000
-
-#define SPEAR320_UART1_BASE 0xA3000000
-#define SPEAR320_UART2_BASE 0xA4000000
-#define SPEAR320_UART_SIZE 0x01000000
-
-#define SPEAR320_SSP0_BASE 0xA5000000
-#define SPEAR320_SSP0_SIZE 0x01000000
-
-#define SPEAR320_SSP1_BASE 0xA6000000
-#define SPEAR320_SSP1_SIZE 0x01000000
-
-#define SPEAR320_I2C_BASE 0xA7000000
-#define SPEAR320_I2C_SIZE 0x01000000
-
-#define SPEAR320_PWM_BASE 0xA8000000
-#define SPEAR320_PWM_SIZE 0x01000000
-
-#define SPEAR320_SMII0_BASE 0xAA000000
-#define SPEAR320_SMII0_SIZE 0x01000000
-
-#define SPEAR320_SMII1_BASE 0xAB000000
-#define SPEAR320_SMII1_SIZE 0x01000000
-
-#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
-#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04
#define INT_CLR_MASK_REG 0x04
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 31486e5..4a2ecc7 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -14,153 +14,71 @@
#ifndef __MACH_SPEAR6XX_H
#define __MACH_SPEAR6XX_H
+#include <asm/memory.h>
#include <mach/hardware.h>
#include <mach/spear600.h>
-#define SPEAR6XX_ML_SDRAM_BASE 0x00000000
-#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000
-
+#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
/* ICM1 - Low speed connection */
-#define SPEAR6XX_ICM1_BASE 0xD0000000
-#define SPEAR6XX_ICM1_SIZE 0x08000000
+#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
-#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000
+#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000
-
-#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000
-#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000
-
-#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000
-#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000
-
-#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000
-#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000
-
-#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000
-#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000
-#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000
-#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000
-
-#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000
-#define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000
-
-#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000
-#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000
-
-#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000
-#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000
-
-#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000
-#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000
+#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
+#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
+#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
+#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
+#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
+#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
+#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
+#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
+#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
/* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE 0xD8000000
-#define SPEAR6XX_ICM2_SIZE 0x08000000
-
-#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000
-#define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000
-
-#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000
-#define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000
-
-#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000
-#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000
-
-#define SPEAR6XX_ICM2_SSP2_BASE 0xD8180000
-#define SPEAR6XX_ICM2_SSP2_SIZE 0x00080000
-
-#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000
-#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000
+#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
+#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
+#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
+#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
+#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
+#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
/* ML-1, 2 - Multi Layer CPU Subsystem */
-#define SPEAR6XX_ML_CPU_BASE 0xF0000000
-#define SPEAR6XX_ML_CPU_SIZE 0x08000000
-
-#define SPEAR6XX_CPU_TMR_BASE 0xF0000000
-#define SPEAR6XX_CPU_TMR_SIZE 0x00100000
-
-#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000
-#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000
-
-#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000
+#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
+#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
+#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
+#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000
-
-#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000
+#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000
/* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE 0xF8000000
-#define SPEAR6XX_ICM3_SIZE 0x08000000
-
-#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000
-#define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000
-
-#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000
-#define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000
-
-#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000
-#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000
-
-#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000
-#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000
-
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
-#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
-
-#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000
-#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000
-#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000
-#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000
-#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000
+#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
+#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
+#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
+#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
+#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
+#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
+#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
+#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
+#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
+#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
+#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000
+#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
-#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000
/* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE 0xE0000000
-#define SPEAR6XX_ICM4_SIZE 0x08000000
-
-#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000
-#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000
-
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000
-#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000
-#define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000
-#define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000
-#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000
-#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000
-#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000
-#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000
-#define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000
+#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
+#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
+#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
+#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
+#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
+#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
+#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
+#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
+#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
+#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 31/62] ST SPEAr: Adding miscellaneous devices
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (28 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 30/62] SPEAr: defines base addresses as ulong Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310 Viresh Kumar
` (31 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 7 ++
arch/arm/mach-spear3xx/spear310.c | 115 +++++++++++++++++++------
arch/arm/mach-spear3xx/spear320.c | 26 ++++++
3 files changed, 123 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 12af694..b45b85a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -160,6 +160,11 @@ extern struct clcd_board clcd_plat_data;
/* spear310 declarations */
#elif defined(CONFIG_MACH_SPEAR310)
/* Add spear310 machine device structure declarations here */
+extern struct amba_device uart1_device;
+extern struct amba_device uart2_device;
+extern struct amba_device uart3_device;
+extern struct amba_device uart4_device;
+extern struct amba_device uart5_device;
extern struct platform_device plgpio_device;
extern struct platform_device nand_device;
@@ -181,6 +186,8 @@ void __init spear310_init(void);
/* Add spear320 machine device structure declarations here */
extern struct amba_device clcd_device;
extern struct amba_device ssp_device[];
+extern struct amba_device uart1_device;
+extern struct amba_device uart2_device;
extern struct platform_device i2c1_device;
extern struct platform_device nand_device;
extern struct platform_device plgpio_device;
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index ffc1f63..673874a 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -142,6 +142,96 @@ struct pmx_driver pmx_driver = {
};
/* Add spear310 specific devices here */
+/* uart1 device registeration */
+struct amba_device uart1_device = {
+ .dev = {
+ .init_name = "uart1",
+ },
+ .res = {
+ .start = SPEAR310_UART1_BASE,
+ .end = SPEAR310_UART1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_UART1, NO_IRQ},
+};
+
+/* uart2 device registeration */
+struct amba_device uart2_device = {
+ .dev = {
+ .init_name = "uart2",
+ },
+ .res = {
+ .start = SPEAR310_UART2_BASE,
+ .end = SPEAR310_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_UART2, NO_IRQ},
+};
+
+/* uart3 device registeration */
+struct amba_device uart3_device = {
+ .dev = {
+ .init_name = "uart3",
+ },
+ .res = {
+ .start = SPEAR310_UART3_BASE,
+ .end = SPEAR310_UART3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_UART3, NO_IRQ},
+};
+
+/* uart4 device registeration */
+struct amba_device uart4_device = {
+ .dev = {
+ .init_name = "uart4",
+ },
+ .res = {
+ .start = SPEAR310_UART4_BASE,
+ .end = SPEAR310_UART4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_UART4, NO_IRQ},
+};
+
+/* uart5 device registeration */
+struct amba_device uart5_device = {
+ .dev = {
+ .init_name = "uart5",
+ },
+ .res = {
+ .start = SPEAR310_UART5_BASE,
+ .end = SPEAR310_UART5_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_UART5, NO_IRQ},
+};
+
+/* nand device registeration */
+static struct fsmc_nand_platform_data nand_platform_data;
+
+static struct resource nand_resources[] = {
+ {
+ .name = "nand_data",
+ .start = SPEAR310_NAND_BASE,
+ .end = SPEAR310_NAND_BASE + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "fsmc_regs",
+ .start = SPEAR310_FSMC_BASE,
+ .end = SPEAR310_FSMC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device nand_device = {
+ .name = "nand",
+ .id = -1,
+ .resource = nand_resources,
+ .num_resources = ARRAY_SIZE(nand_resources),
+ .dev.platform_data = &nand_platform_data,
+};
+
/* plgpio device registeration */
/*
* pin to offset and offset to pin converter functions
@@ -178,31 +268,6 @@ int spear300_o2p(int offset)
return offset + 2;
}
-/* nand device registeration */
-static struct fsmc_nand_platform_data nand_platform_data;
-
-static struct resource nand_resources[] = {
- {
- .name = "nand_data",
- .start = SPEAR310_NAND_BASE,
- .end = SPEAR310_NAND_BASE + SZ_16 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "fsmc_regs",
- .start = SPEAR310_FSMC_BASE,
- .end = SPEAR310_FSMC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device nand_device = {
- .name = "nand",
- .id = -1,
- .resource = nand_resources,
- .num_resources = ARRAY_SIZE(nand_resources),
- .dev.platform_data = &nand_platform_data,
-};
-
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
.irq_base = SPEAR_PLGPIO_INT_BASE,
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index ac4f80b..e506203 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -447,6 +447,32 @@ struct amba_device ssp_device[] = {
}
};
+/* uart1 device registeration */
+struct amba_device uart1_device = {
+ .dev = {
+ .init_name = "uart1",
+ },
+ .res = {
+ .start = SPEAR320_UART1_BASE,
+ .end = SPEAR320_UART1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_UART1, NO_IRQ},
+};
+
+/* uart2 device registeration */
+struct amba_device uart2_device = {
+ .dev = {
+ .init_name = "uart2",
+ },
+ .res = {
+ .start = SPEAR320_UART2_BASE,
+ .end = SPEAR320_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {VIRQ_UART2, NO_IRQ},
+};
+
/* i2c1 device registeration */
static struct resource i2c1_resources[] = {
{
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (29 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 31/62] ST SPEAr: Adding miscellaneous devices Viresh Kumar
@ 2011-01-18 7:11 ` Viresh Kumar
2011-01-19 0:09 ` Jamie Iles
2011-01-18 7:12 ` [PATCH V4 33/62] SPEAr320: Adding support for CAN Viresh Kumar
` (30 subsequent siblings)
61 siblings, 1 reply; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Bhupesh Sharma <bhupesh.sharma@st.com>
This patch adds support for SPEAr1310 Machine and evaluation board
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/Makefile | 1 +
arch/arm/configs/spear13xx_defconfig | 1 +
arch/arm/mach-spear13xx/Kconfig | 11 ++
arch/arm/mach-spear13xx/Makefile | 6 +
arch/arm/mach-spear13xx/include/mach/generic.h | 21 +++-
arch/arm/mach-spear13xx/include/mach/irqs.h | 37 ++++++
arch/arm/mach-spear13xx/include/mach/spear.h | 1 +
arch/arm/mach-spear13xx/include/mach/spear1310.h | 31 +++++
arch/arm/mach-spear13xx/spear1310.c | 62 ++++++++++
arch/arm/mach-spear13xx/spear1310_evb.c | 133 ++++++++++++++++++++++
arch/arm/plat-spear/Makefile | 1 +
11 files changed, 302 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1310.h
create mode 100644 arch/arm/mach-spear13xx/spear1310.c
create mode 100644 arch/arm/mach-spear13xx/spear1310_evb.c
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 51769cc..f3d42be 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -194,6 +194,7 @@ machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_MACH_SPEAR1300) := spear13xx
+machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 10b1cf5..9f3baf8 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -9,6 +9,7 @@ CONFIG_MODVERSIONS=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR13XX=y
CONFIG_BOARD_SPEAR1300_EVB=y
+CONFIG_BOARD_SPEAR1310_EVB=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_AEABI=y
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
index 3ea463d..229ef93 100644
--- a/arch/arm/mach-spear13xx/Kconfig
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -11,6 +11,12 @@ config BOARD_SPEAR1300_EVB
help
Supports ST SPEAr1300 Evaluation Board
+config BOARD_SPEAR1310_EVB
+ bool "SPEAr1310 Evaluation Board"
+ select MACH_SPEAR1310
+ help
+ Supports ST SPEAr1310 Evaluation Board
+
endmenu
config MACH_SPEAR1300
@@ -18,4 +24,9 @@ config MACH_SPEAR1300
help
Supports ST SPEAr1300 Machine
+config MACH_SPEAR1310
+ bool "SPEAr1310"
+ help
+ Supports ST SPEAr1310 Machine
+
endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index 4f1cbc5..838405a 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -13,3 +13,9 @@ obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
# spear1300 boards files
obj-$(CONFIG_BOARD_SPEAR1300_EVB) += spear1300_evb.o
+
+# spear1310 specific files
+obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
+
+# spear1310 boards files
+obj-$(CONFIG_BOARD_SPEAR1310_EVB) += spear1310_evb.o
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index e6fe7b3..9f25a85 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -43,17 +43,32 @@ extern struct platform_device spear13xx_rtc_device;
extern struct platform_device spear13xx_sdhci_device;
extern struct sys_timer spear13xx_timer;
-/* Add spear1300 machine device structure declarations here */
-
/* Add spear13xx family function declarations here */
void __init clk_init(void);
void __init i2c_register_default_devices(void);
void __init spear_setup_timer(void);
-void __init spear1300_init(void);
void __init spear13xx_map_io(void);
void __init spear13xx_init_irq(void);
void __init spear13xx_init(void);
void __init nand_mach_init(u32 busw);
void spear13xx_secondary_startup(void);
+/* spear1300 declarations */
+#ifdef CONFIG_MACH_SPEAR1300
+/* Add spear1300 machine function declarations here */
+void __init spear1300_init(void);
+
+#endif /* CONFIG_MACH_SPEAR1300 */
+
+/* spear1310 declarations */
+#ifdef CONFIG_MACH_SPEAR1310
+/* Add spear1310 machine device structure declarations here */
+extern struct platform_device spear1310_can0_device;
+extern struct platform_device spear1310_can1_device;
+
+/* Add spear1310 machine function declarations here */
+void __init spear1310_init(void);
+
+#endif /* CONFIG_MACH_SPEAR1310 */
+
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
index d2bfbb1..1ca70a6 100644
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -5,6 +5,7 @@
*
* Copyright (C) 2010 ST Microelectronics
* Shiraz Hashim <shiraz.hashim@st.com>
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
@@ -84,6 +85,42 @@
#define IRQ_PCIE1 (IRQ_SHPI_START + 69)
#define IRQ_PCIE2 (IRQ_SHPI_START + 70)
+/* Add spear1310 specific IRQs here */
+#ifdef CONFIG_MACH_SPEAR1310
+#define IRQ_FSMC_PC1 (IRQ_SHPI_START + 76)
+#define IRQ_FSMC_PC2 (IRQ_SHPI_START + 77)
+#define IRQ_FSMC_PC3 (IRQ_SHPI_START + 78)
+#define IRQ_FSMC_PC4 (IRQ_SHPI_START + 79)
+#define IRQ_RS4850 (IRQ_SHPI_START + 80)
+#define IRQ_RS4851 (IRQ_SHPI_START + 81)
+#define IRQ_CCAN0 (IRQ_SHPI_START + 82)
+#define IRQ_CCAN1 (IRQ_SHPI_START + 83)
+#define IRQ_TDM0 (IRQ_SHPI_START + 84)
+#define IRQ_TDM1 (IRQ_SHPI_START + 85)
+#define IRQ_UART0 (IRQ_SHPI_START + 86)
+#define IRQ_UART1 (IRQ_SHPI_START + 87)
+#define IRQ_UART2 (IRQ_SHPI_START + 88)
+#define IRQ_UART3 (IRQ_SHPI_START + 89)
+#define IRQ_UART4 (IRQ_SHPI_START + 90)
+#define IRQ_I2C_CNTR (IRQ_SHPI_START + 91)
+#define IRQ_GMAC0_SBD (IRQ_SHPI_START + 92)
+#define IRQ_GMAC0_PMT (IRQ_SHPI_START + 93)
+#define IRQ_GMAC1_SBD (IRQ_SHPI_START + 94)
+#define IRQ_GMAC1_PMT (IRQ_SHPI_START + 95)
+#define IRQ_GMAC2_SBD (IRQ_SHPI_START + 96)
+#define IRQ_GMAC2_PMT (IRQ_SHPI_START + 97)
+#define IRQ_GMAC3_SBD (IRQ_SHPI_START + 98)
+#define IRQ_GMAC3_PMT (IRQ_SHPI_START + 99)
+#define IRQ_GPIO (IRQ_SHPI_START + 100)
+#define IRQ_PCI_BRDG_HOST_FATAL (IRQ_SHPI_START + 101)
+#define IRQ_PCI_INTA (IRQ_SHPI_START + 102)
+#define IRQ_PCI_INTB (IRQ_SHPI_START + 103)
+#define IRQ_PCI_INTC (IRQ_SHPI_START + 104)
+#define IRQ_PCI_INTD (IRQ_SHPI_START + 105)
+#define IRQ_PCI_ME_TO_ARM (IRQ_SHPI_START + 106)
+#define IRQ_PCI_SERR_TO_ARM (IRQ_SHPI_START + 107)
+#endif /* CONFIG_MACH_SPEAR1310 */
+
#define IRQ_GIC_END (IRQ_SHPI_START + 128)
#define VIRQ_START IRQ_GIC_END
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 1a1af72..cf25eb5 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -16,6 +16,7 @@
#include <asm/memory.h>
#include <mach/spear1300.h>
+#include <mach/spear1310.h>
#define SPEAR13XX_L2CC_BASE UL(0xED000000)
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310.h b/arch/arm/mach-spear13xx/include/mach/spear1310.h
new file mode 100644
index 0000000..e57c99a
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1310.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear1310.h
+ *
+ * SPEAr1310 Machine specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR1310
+
+#ifndef __MACH_SPEAR1310_H
+#define __MACH_SPEAR1310_H
+
+#define SPEAR1310_CAN0_BASE UL(0x6DA00000)
+#define SPEAR1310_CAN1_BASE UL(0x6DB00000)
+#define SPEAR1310_RAS_BASE UL(0x6C800000)
+
+/* RAS Area Control Register */
+#define SPEAR1310_RAS_CTRL_REG0 (SPEAR1310_RAS_BASE + 0x0)
+#define SPEAR1310_RAS_CTRL_REG1 (SPEAR1310_RAS_BASE + 0x4)
+#define SPEAR1310_PHY_CLK_MASK 0xF
+#define SPEAR1310_PHY_CLK_SHIFT 0
+
+#endif /* __MACH_SPEAR1310_H */
+
+#endif /* CONFIG_MACH_SPEAR1310 */
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
new file mode 100644
index 0000000..561f68b
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310.c
+ *
+ * SPEAr1310 machine source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/ptrace.h>
+#include <asm/irq.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* Add spear1310 specific devices here */
+
+/* CAN device registeration */
+static struct resource can0_resources[] = {
+ {
+ .start = SPEAR1310_CAN0_BASE,
+ .end = SPEAR1310_CAN0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_CCAN0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear1310_can0_device = {
+ .name = "c_can_platform",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(can0_resources),
+ .resource = can0_resources,
+};
+
+static struct resource can1_resources[] = {
+ {
+ .start = SPEAR1310_CAN1_BASE,
+ .end = SPEAR1310_CAN1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_CCAN1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear1310_can1_device = {
+ .name = "c_can_platform",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(can1_resources),
+ .resource = can1_resources,
+};
+
+void __init spear1310_init(void)
+{
+ /* call spear13xx family common init function */
+ spear13xx_init();
+}
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
new file mode 100644
index 0000000..1270b4d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -0,0 +1,133 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310_evb.c
+ *
+ * SPEAr1310 evaluation board source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <plat/fsmc.h>
+#include <plat/keyboard.h>
+#include <plat/spi.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+#include <mach/pcie.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ /* spear13xx specific devices */
+ &spear13xx_gpio_device[0],
+ &spear13xx_gpio_device[1],
+ &spear13xx_ssp_device,
+ &spear13xx_uart_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+ /* spear13xx specific devices */
+ &spear13xx_ehci0_device,
+ &spear13xx_ehci1_device,
+ &spear13xx_i2c_device,
+ &spear13xx_kbd_device,
+ &spear13xx_nand_device,
+ &spear13xx_ohci0_device,
+ &spear13xx_ohci1_device,
+ &spear13xx_rtc_device,
+ &spear13xx_sdhci_device,
+
+ /* spear1310 specific devices */
+ &spear1310_can0_device,
+ &spear1310_can1_device,
+};
+
+/* keyboard specific platform data */
+static DECLARE_KEYMAP(keymap);
+static struct matrix_keymap_data keymap_data = {
+ .keymap = keymap,
+ .keymap_size = ARRAY_SIZE(keymap),
+};
+
+static struct kbd_platform_data kbd_data = {
+ .keymap = &keymap_data,
+ .rep = 1,
+};
+
+static struct spi_board_info __initdata spi_board_info[] = {
+};
+
+#ifdef CONFIG_PCIEPORTBUS
+/* this function is needed for PCIE host and device driver. Same
+ * controller can not be programmed as host as well as device. So host
+ * driver must call this function and if this function returns 1 then
+ * only host should add that particular port as RC.
+ * A port to be added as device, one must also add device's information
+ * in plat_devs array defined in this file.
+ * it is the responsibility of calling function to not send port number
+ * greter than max no of controller(3)
+ */
+int spear1310_pcie_port_is_host(int port)
+{
+ switch (port) {
+ case 0:
+ return 0;
+ case 1:
+ return 1;
+ case 2:
+ return 1;
+ }
+ return -EINVAL;
+}
+#endif
+
+static void __init spear1310_evb_init(void)
+{
+ unsigned int i;
+
+ /* set keyboard plat data */
+ kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
+
+ /* set nand device's plat data */
+ fsmc_nand_set_plat_data(&spear13xx_nand_device, NULL, 0,
+ NAND_SKIP_BBTSCAN, FSMC_NAND_BW8);
+ nand_mach_init(FSMC_NAND_BW8);
+
+ /* call spear1310 machine init function */
+ spear1310_init();
+
+ /* Register slave devices on the I2C buses */
+ i2c_register_default_devices();
+
+#ifdef CONFIG_PCIEPORTBUS
+ /* Enable PCIE0 clk */
+ enable_pcie0_clk();
+ pcie_init(&spear1310_pcie_port_is_host);
+#endif
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+}
+
+MACHINE_START(SPEAR1310, "ST-SPEAR1310-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear13xx_map_io,
+ .init_irq = spear13xx_init_irq,
+ .timer = &spear13xx_timer,
+ .init_machine = spear1310_evb_init,
+MACHINE_END
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 0e29587..37a61cc 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
obj-$(CONFIG_MACH_SPEAR320) += plgpio.o
obj-$(CONFIG_SPEAR_PWM) += pwm.o
+obj-$(CONFIG_BOARD_SPEAR1310_EVB) += i2c_eval_board.o
obj-$(CONFIG_BOARD_SPEAR1300_EVB) += i2c_eval_board.o
obj-$(CONFIG_BOARD_SPEAR300_EVB) += i2c_eval_board.o
obj-$(CONFIG_BOARD_SPEAR310_EVB) += i2c_eval_board.o
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 33/62] SPEAr320: Adding support for CAN
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (30 preceding siblings ...)
2011-01-18 7:11 ` [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310 Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 34/62] ST SPEAr: Adding support for DDR in clock framework Viresh Kumar
` (29 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 2 +
arch/arm/mach-spear3xx/spear320.c | 37 +++++++++++++++++++++++++
arch/arm/mach-spear3xx/spear320_evb.c | 2 +
3 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index b45b85a..c373f6d 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -188,6 +188,8 @@ extern struct amba_device clcd_device;
extern struct amba_device ssp_device[];
extern struct amba_device uart1_device;
extern struct amba_device uart2_device;
+extern struct platform_device can0_device;
+extern struct platform_device can1_device;
extern struct platform_device i2c1_device;
extern struct platform_device nand_device;
extern struct platform_device plgpio_device;
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index e506203..3c90d47 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -473,6 +473,43 @@ struct amba_device uart2_device = {
.irq = {VIRQ_UART2, NO_IRQ},
};
+/* CAN device registeration */
+static struct resource can0_resources[] = {
+ {
+ .start = SPEAR320_CAN0_BASE,
+ .end = SPEAR320_CAN0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .start = VIRQ_CANU,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device can0_device = {
+ .name = "c_can_platform",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(can0_resources),
+ .resource = can0_resources,
+};
+
+static struct resource can1_resources[] = {
+ {
+ .start = SPEAR320_CAN1_BASE,
+ .end = SPEAR320_CAN1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .start = VIRQ_CANL,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device can1_device = {
+ .name = "c_can_platform",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(can1_resources),
+ .resource = can1_resources,
+};
+
/* i2c1 device registeration */
static struct resource i2c1_resources[] = {
{
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 9dc8dc1..cf81208 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -65,6 +65,8 @@ static struct platform_device *plat_devs[] __initdata = {
&rtc_device,
/* spear320 specific devices */
+ &can0_device,
+ &can1_device,
&i2c1_device,
&plgpio_device,
&pwm_device,
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 34/62] ST SPEAr: Adding support for DDR in clock framework
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (31 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 33/62] SPEAr320: Adding support for CAN Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 35/62] ST SPEAr : EMI (Extrenal Memory Interface) controller driver Viresh Kumar
` (28 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Changing rate of clk, which is ancestor of DDR requires to put DDR in refresh
mode before changing parents rate. For this DDR support is added in clock
framework. Now at boot time all ancestors of DDR is marked specially and
changing their rate must be first acked by ddr (i.e. ddr will run on that
clock). This patch adds support for this.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
---
arch/arm/mach-spear13xx/clock.c | 69 ++++++++---
arch/arm/mach-spear13xx/include/mach/generic.h | 2 +-
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 4 +
arch/arm/mach-spear13xx/spear13xx.c | 2 +-
arch/arm/mach-spear3xx/clock.c | 105 ++++++++++++++----
arch/arm/mach-spear3xx/include/mach/generic.h | 2 +-
arch/arm/mach-spear3xx/include/mach/misc_regs.h | 7 +
arch/arm/mach-spear3xx/spear3xx.c | 2 +-
arch/arm/mach-spear6xx/clock.c | 105 ++++++++++++++----
arch/arm/mach-spear6xx/include/mach/generic.h | 2 +-
arch/arm/mach-spear6xx/include/mach/misc_regs.h | 7 +
arch/arm/mach-spear6xx/spear6xx.c | 2 +-
arch/arm/plat-spear/clock.c | 133 ++++++++++++++++++---
arch/arm/plat-spear/include/plat/clock.h | 42 +++++--
14 files changed, 385 insertions(+), 99 deletions(-)
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
index c39389e..709adb2 100644
--- a/arch/arm/mach-spear13xx/clock.c
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -23,19 +23,19 @@
/* root clks */
/* 24 MHz oscillator clock */
static struct clk osc1_24m_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.rate = 24000000,
};
/* 32 KHz oscillator clock */
static struct clk osc2_32k_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.rate = 32000,
};
/* 25 MHz MIPHY oscillator clock */
static struct clk osc3_25m_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.rate = 25000000,
};
@@ -99,7 +99,7 @@ struct pll_rate_tbl pll_rtbl[] = {
/* pll1 clock */
static struct clk pll1_clk = {
- .flags = ENABLED_ON_INIT,
+ .flags = ENABLED_ON_INIT | SYSTEM_CLK,
.pclk_sel = &pll_pclk_sel,
.pclk_sel_shift = PLL1_CLK_SHIFT,
.en_reg = PLL1_CTR,
@@ -113,7 +113,7 @@ static struct clk pll1_clk = {
/* pll1div2 clock */
static struct clk pll1div2_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.div_factor = 2,
.recalc = &follow_parent,
@@ -121,7 +121,7 @@ static struct clk pll1div2_clk = {
/* pll1div4 clock */
static struct clk pll1div4_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.div_factor = 4,
.recalc = &follow_parent,
@@ -136,6 +136,7 @@ static struct pll_clk_config pll2_config = {
/* pll2 clock */
static struct clk pll2_clk = {
+ .flags = SYSTEM_CLK,
.pclk_sel = &pll_pclk_sel,
.pclk_sel_shift = PLL2_CLK_SHIFT,
.en_reg = PLL2_CTR,
@@ -156,6 +157,7 @@ static struct pll_clk_config pll3_config = {
/* pll3 clock */
static struct clk pll3_clk = {
+ .flags = SYSTEM_CLK,
.pclk_sel = &pll_pclk_sel,
.pclk_sel_shift = PLL3_CLK_SHIFT,
.en_reg = PLL3_CTR,
@@ -184,7 +186,7 @@ struct pll_rate_tbl pll4_rtbl[] = {
/* pll4 (DDR) clock */
static struct clk pll4_clk = {
- .flags = ENABLED_ON_INIT,
+ .flags = ENABLED_ON_INIT | SYSTEM_CLK,
.pclk = &osc1_24m_clk,
.en_reg = PLL4_CTR,
.en_reg_bit = PLL_ENABLE,
@@ -197,22 +199,54 @@ static struct clk pll4_clk = {
/* pll5 USB 48 MHz clock */
static struct clk pll5_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &osc1_24m_clk,
.rate = 48000000,
};
/* pll6 (MIPHY) clock */
static struct clk pll6_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &osc3_25m_clk,
.rate = 25000000,
};
/* clocks derived from pll1 clk */
+/* ddr clock */
+struct ddr_rate_tbl ddr_rate_tbl = {
+ .minrate = 332000000,
+ .maxrate = 500000000,
+};
+
+static struct pclk_info ddr_pclk_info[] = {
+ {
+ .pclk = &pll1_clk,
+ .pclk_val = MCTR_CLK_PLL1_VAL,
+ }, {
+ .pclk = &pll4_clk,
+ .pclk_val = MCTR_CLK_PLL4_VAL,
+ },
+};
+
+/* ddr parent select structure */
+static struct pclk_sel ddr_pclk_sel = {
+ .pclk_info = ddr_pclk_info,
+ .pclk_count = ARRAY_SIZE(ddr_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = MCTR_CLK_MASK,
+};
+
+static struct clk ddr_clk = {
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
+ .recalc = &follow_parent,
+ .pclk_sel = &ddr_pclk_sel,
+ .pclk_sel_shift = MCTR_CLK_SHIFT,
+ .private_data = &ddr_rate_tbl,
+};
+
/* cpu clock */
static struct clk cpu_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.div_factor = 2,
.recalc = &follow_parent,
@@ -220,7 +254,7 @@ static struct clk cpu_clk = {
/* ahb clock */
static struct clk ahb_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.div_factor = 6,
.recalc = &follow_parent,
@@ -228,7 +262,7 @@ static struct clk ahb_clk = {
/* apb clock */
static struct clk apb_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.div_factor = 12,
.recalc = &follow_parent,
@@ -845,6 +879,7 @@ static struct clk_lookup spear_clk_lookups[] = {
{.con_id = "pll6_clk", .clk = &pll6_clk},
/* clock derived from pll1 clk */
+ {.con_id = "ddr_clk", .clk = &ddr_clk},
{.con_id = "cpu_clk", .clk = &cpu_clk},
{.con_id = "ahb_clk", .clk = &ahb_clk},
{.con_id = "apb_clk", .clk = &apb_clk},
@@ -911,12 +946,8 @@ static struct clk_lookup spear_clk_lookups[] = {
#endif
};
-void __init clk_init(void)
+/* machine clk init */
+void __init spear13xx_clk_init(void)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
- clk_register(&spear_clk_lookups[i]);
-
- recalc_root_clocks();
+ clk_init(spear_clk_lookups, ARRAY_SIZE(spear_clk_lookups), &ddr_clk);
}
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 9f25a85..6b249b5 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -44,7 +44,7 @@ extern struct platform_device spear13xx_sdhci_device;
extern struct sys_timer spear13xx_timer;
/* Add spear13xx family function declarations here */
-void __init clk_init(void);
+void __init spear13xx_clk_init(void);
void __init i2c_register_default_devices(void);
void __init spear_setup_timer(void);
void __init spear13xx_map_io(void);
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
index a7ba6cb..3cfd4fc 100644
--- a/arch/arm/mach-spear13xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -98,6 +98,10 @@
#define CLCD_CLK_SHIFT 2
#define C3_CLK_MASK 1
#define C3_CLK_SHIFT 1
+ #define MCTR_CLK_SHIFT 10
+ #define MCTR_CLK_MASK 0x1
+ #define MCTR_CLK_PLL1_VAL 0x0
+ #define MCTR_CLK_PLL4_VAL 0x1
#define GMAC_CLK_CFG ((unsigned int *)(MISC_BASE + 0x248))
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index f7ff7d7..6dc3f68 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -434,7 +434,7 @@ void __init spear13xx_map_io(void)
iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
/* This will initialize clock framework */
- clk_init();
+ spear13xx_clk_init();
}
static void __init spear13xx_timer_init(void)
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 8ae4ad0..58f0259 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -19,13 +19,13 @@
/* root clks */
/* 32 KHz oscillator clock */
static struct clk osc_32k_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.rate = 32000,
};
/* 24 MHz oscillator clock */
static struct clk osc_24m_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.rate = 24000000,
};
@@ -40,7 +40,7 @@ static struct clk rtc_clk = {
/* clock derived from 24 MHz osc clk */
/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
+static struct pll_clk_masks pll_masks = {
.mode_mask = PLL_MODE_MASK,
.mode_shift = PLL_MODE_SHIFT,
.norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
@@ -53,22 +53,22 @@ static struct pll_clk_masks pll1_masks = {
.div_n_shift = PLL_DIV_N_SHIFT,
};
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
- .mode_reg = PLL1_CTR,
- .cfg_reg = PLL1_FRQ,
- .masks = &pll1_masks,
-};
-
/* pll rate configuration table, in ascending order of rates */
struct pll_rate_tbl pll_rtbl[] = {
{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
};
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+ .mode_reg = PLL1_CTR,
+ .cfg_reg = PLL1_FRQ,
+ .masks = &pll_masks,
+};
+
/* PLL1 clock */
static struct clk pll1_clk = {
- .flags = ENABLED_ON_INIT,
+ .flags = ENABLED_ON_INIT | SYSTEM_CLK,
.pclk = &osc_24m_clk,
.en_reg = PLL1_CTR,
.en_reg_bit = PLL_ENABLE,
@@ -79,9 +79,29 @@ static struct clk pll1_clk = {
.private_data = &pll1_config,
};
+/* pll2 configuration structure */
+static struct pll_clk_config pll2_config = {
+ .mode_reg = PLL2_CTR,
+ .cfg_reg = PLL2_FRQ,
+ .masks = &pll_masks,
+};
+
+/* PLL2 clock */
+static struct clk pll2_clk = {
+ .flags = ENABLED_ON_INIT | SYSTEM_CLK,
+ .pclk = &osc_24m_clk,
+ .en_reg = PLL2_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
+ .private_data = &pll2_config,
+};
+
/* PLL3 48 MHz clock */
static struct clk pll3_48m_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &osc_24m_clk,
.rate = 48000000,
};
@@ -96,7 +116,7 @@ static struct clk wdt_clk = {
/* clock derived from pll1 clk */
/* cpu clock */
static struct clk cpu_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.recalc = &follow_parent,
};
@@ -123,7 +143,7 @@ struct bus_rate_tbl bus_rtbl[] = {
/* ahb clock */
static struct clk ahb_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.calc_rate = &bus_calc_rate,
.recalc = &bus_clk_recalc,
@@ -410,6 +430,48 @@ static struct clk usbd_clk = {
};
/* clock derived from ahb clk */
+/* ahb multiplied by 2 clock */
+static struct clk ahbmult2_clk = {
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
+ .pclk = &ahb_clk,
+ .recalc = &ahbmult2_clk_recalc,
+};
+
+/* ddr clock */
+struct ddr_rate_tbl ddr_rate_tbl = {
+ .minrate = 166000000,
+ .maxrate = 332000000,
+};
+
+static struct pclk_info ddr_pclk_info[] = {
+ {
+ .pclk = &ahb_clk,
+ .pclk_val = MCTR_CLK_HCLK_VAL,
+ }, {
+ .pclk = &ahbmult2_clk,
+ .pclk_val = MCTR_CLK_2HCLK_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = MCTR_CLK_PLL2_VAL,
+ },
+};
+
+/* ddr parent select structure */
+static struct pclk_sel ddr_pclk_sel = {
+ .pclk_info = ddr_pclk_info,
+ .pclk_count = ARRAY_SIZE(ddr_pclk_info),
+ .pclk_sel_reg = PLL_CLK_CFG,
+ .pclk_sel_mask = MCTR_CLK_MASK,
+};
+
+static struct clk ddr_clk = {
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
+ .recalc = &follow_parent,
+ .pclk_sel = &ddr_pclk_sel,
+ .pclk_sel_shift = MCTR_CLK_SHIFT,
+ .private_data = &ddr_rate_tbl,
+};
+
/* apb masks structure */
static struct bus_clk_masks apb_masks = {
.mask = HCLK_PCLK_RATIO_MASK,
@@ -424,7 +486,7 @@ static struct bus_clk_config apb_config = {
/* apb clock */
static struct clk apb_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &ahb_clk,
.calc_rate = &bus_calc_rate,
.recalc = &bus_clk_recalc,
@@ -658,6 +720,7 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "rtc-spear", .clk = &rtc_clk},
/* clock derived from 24 MHz osc clk */
{ .con_id = "pll1_clk", .clk = &pll1_clk},
+ { .con_id = "pll2_clk", .clk = &pll2_clk},
{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
{ .dev_id = "wdt", .clk = &wdt_clk},
/* clock derived from pll1 clk */
@@ -677,6 +740,8 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .con_id = "usbh_clk", .clk = &usbh_clk},
{ .dev_id = "usbd", .clk = &usbd_clk},
/* clock derived from ahb clk */
+ { .con_id = "ahbmult2_clk", .clk = &ahbmult2_clk},
+ { .con_id = "ddr_clk", .clk = &ddr_clk},
{ .con_id = "apb_clk", .clk = &apb_clk},
{ .dev_id = "i2c_designware.0", .clk = &i2c_clk},
{ .dev_id = "dma", .clk = &dma_clk},
@@ -732,12 +797,8 @@ static struct clk_lookup spear_clk_lookups[] = {
#endif
};
-void __init clk_init(void)
+/* machine clk init */
+void __init spear3xx_clk_init(void)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
- clk_register(&spear_clk_lookups[i]);
-
- recalc_root_clocks();
+ clk_init(spear_clk_lookups, ARRAY_SIZE(spear_clk_lookups), &ddr_clk);
}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index c373f6d..f8613f4 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -43,7 +43,7 @@ extern struct platform_device rtc_device;
extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
-void __init clk_init(void);
+void __init spear3xx_clk_init(void);
void __init i2c_register_default_devices(void);
void __init spear_setup_timer(void);
void __init spear3xx_map_io(void);
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 6cb4f3c..6316900 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -46,6 +46,13 @@
#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C))
#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020))
+/* PLL_CLK_CFG register masks */
+#define MCTR_CLK_SHIFT 28
+#define MCTR_CLK_MASK 0x7
+#define MCTR_CLK_HCLK_VAL 0x0
+#define MCTR_CLK_2HCLK_VAL 0x1
+#define MCTR_CLK_PLL2_VAL 0x3
+
#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024))
/* CORE CLK CFG register masks */
#define PLL_HCLK_RATIO_SHIFT 10
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index e98cdca..2806cbc 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -261,7 +261,7 @@ void __init spear3xx_map_io(void)
iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
/* This will initialize clock framework */
- clk_init();
+ spear3xx_clk_init();
}
/* pad multiplexing support */
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 9171952..99cc21d 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -19,13 +19,13 @@
/* root clks */
/* 32 KHz oscillator clock */
static struct clk osc_32k_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.rate = 32000,
};
/* 30 MHz oscillator clock */
static struct clk osc_30m_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.rate = 30000000,
};
@@ -40,7 +40,7 @@ static struct clk rtc_clk = {
/* clock derived from 30 MHz osc clk */
/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
+static struct pll_clk_masks pll_masks = {
.mode_mask = PLL_MODE_MASK,
.mode_shift = PLL_MODE_SHIFT,
.norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
@@ -53,22 +53,22 @@ static struct pll_clk_masks pll1_masks = {
.div_n_shift = PLL_DIV_N_SHIFT,
};
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
- .mode_reg = PLL1_CTR,
- .cfg_reg = PLL1_FRQ,
- .masks = &pll1_masks,
-};
-
/* pll rate configuration table, in ascending order of rates */
struct pll_rate_tbl pll_rtbl[] = {
{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
};
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+ .mode_reg = PLL1_CTR,
+ .cfg_reg = PLL1_FRQ,
+ .masks = &pll_masks,
+};
+
/* PLL1 clock */
static struct clk pll1_clk = {
- .flags = ENABLED_ON_INIT,
+ .flags = ENABLED_ON_INIT | SYSTEM_CLK,
.pclk = &osc_30m_clk,
.en_reg = PLL1_CTR,
.en_reg_bit = PLL_ENABLE,
@@ -79,9 +79,29 @@ static struct clk pll1_clk = {
.private_data = &pll1_config,
};
+/* pll2 configuration structure */
+static struct pll_clk_config pll2_config = {
+ .mode_reg = PLL2_CTR,
+ .cfg_reg = PLL2_FRQ,
+ .masks = &pll_masks,
+};
+
+/* PLL2 clock */
+static struct clk pll2_clk = {
+ .flags = ENABLED_ON_INIT | SYSTEM_CLK,
+ .pclk = &osc_30m_clk,
+ .en_reg = PLL2_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
+ .private_data = &pll2_config,
+};
+
/* PLL3 48 MHz clock */
static struct clk pll3_48m_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &osc_30m_clk,
.rate = 48000000,
};
@@ -96,7 +116,7 @@ static struct clk wdt_clk = {
/* clock derived from pll1 clk */
/* cpu clock */
static struct clk cpu_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.recalc = &follow_parent,
};
@@ -123,7 +143,7 @@ struct bus_rate_tbl bus_rtbl[] = {
/* ahb clock */
static struct clk ahb_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &pll1_clk,
.calc_rate = &bus_calc_rate,
.recalc = &bus_clk_recalc,
@@ -491,6 +511,48 @@ static struct clk usbd_clk = {
};
/* clock derived from ahb clk */
+/* ahb multiplied by 2 clock */
+static struct clk ahbmult2_clk = {
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
+ .pclk = &ahb_clk,
+ .recalc = &ahbmult2_clk_recalc,
+};
+
+/* ddr clock */
+struct ddr_rate_tbl ddr_rate_tbl = {
+ .minrate = 166000000,
+ .maxrate = 332000000,
+};
+
+static struct pclk_info ddr_pclk_info[] = {
+ {
+ .pclk = &ahb_clk,
+ .pclk_val = MCTR_CLK_HCLK_VAL,
+ }, {
+ .pclk = &ahbmult2_clk,
+ .pclk_val = MCTR_CLK_2HCLK_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = MCTR_CLK_PLL2_VAL,
+ },
+};
+
+/* ddr parent select structure */
+static struct pclk_sel ddr_pclk_sel = {
+ .pclk_info = ddr_pclk_info,
+ .pclk_count = ARRAY_SIZE(ddr_pclk_info),
+ .pclk_sel_reg = PLL_CLK_CFG,
+ .pclk_sel_mask = MCTR_CLK_MASK,
+};
+
+static struct clk ddr_clk = {
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
+ .recalc = &follow_parent,
+ .pclk_sel = &ddr_pclk_sel,
+ .pclk_sel_shift = MCTR_CLK_SHIFT,
+ .private_data = &ddr_rate_tbl,
+};
+
/* apb masks structure */
static struct bus_clk_masks apb_masks = {
.mask = HCLK_PCLK_RATIO_MASK,
@@ -505,7 +567,7 @@ static struct bus_clk_config apb_config = {
/* apb clock */
static struct clk apb_clk = {
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | SYSTEM_CLK,
.pclk = &ahb_clk,
.calc_rate = &bus_calc_rate,
.recalc = &bus_clk_recalc,
@@ -630,6 +692,7 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "rtc-spear", .clk = &rtc_clk},
/* clock derived from 30 MHz os clk */
{ .con_id = "pll1_clk", .clk = &pll1_clk},
+ { .con_id = "pll2_clk", .clk = &pll2_clk},
{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
{ .dev_id = "wdt", .clk = &wdt_clk},
/* clock derived from pll1 clk */
@@ -654,6 +717,8 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .con_id = "usbh.1_clk", .clk = &usbh1_clk},
{ .dev_id = "usbd", .clk = &usbd_clk},
/* clock derived from ahb clk */
+ { .con_id = "ahbmult2_clk", .clk = &ahbmult2_clk},
+ { .con_id = "ddr_clk", .clk = &ddr_clk},
{ .con_id = "apb_clk", .clk = &apb_clk},
{ .dev_id = "i2c_designware.0", .clk = &i2c_clk},
{ .dev_id = "dma", .clk = &dma_clk},
@@ -671,12 +736,8 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "gpio2", .clk = &gpio2_clk},
};
-void __init clk_init(void)
+/* machine clk init */
+void __init spear6xx_clk_init(void)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
- clk_register(&spear_clk_lookups[i]);
-
- recalc_root_clocks();
+ clk_init(spear_clk_lookups, ARRAY_SIZE(spear_clk_lookups), &ddr_clk);
}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 1394e45..1d288a5 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -50,7 +50,7 @@ void __init spear6xx_map_io(void);
void __init spear6xx_init_irq(void);
void __init spear6xx_init(void);
void __init spear600_init(void);
-void __init clk_init(void);
+void __init spear6xx_clk_init(void);
/* Add spear600 machine device structure declarations here */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index bd71e72..0f4562b 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -47,6 +47,13 @@
#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C))
#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020))
#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024))
+/* PLL_CLK_CFG register masks */
+#define MCTR_CLK_SHIFT 28
+#define MCTR_CLK_MASK 0x7
+#define MCTR_CLK_HCLK_VAL 0x0
+#define MCTR_CLK_2HCLK_VAL 0x1
+#define MCTR_CLK_PLL2_VAL 0x3
+
/* CORE CLK CFG register masks */
#define PLL_HCLK_RATIO_SHIFT 10
#define PLL_HCLK_RATIO_MASK 0x3
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 69287bf..eff6da1 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -420,7 +420,7 @@ void __init spear6xx_map_io(void)
iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
/* This will initialize clock framework */
- clk_init();
+ spear6xx_clk_init();
}
static void __init spear6xx_timer_init(void)
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index 7d3338f..fb1c87b 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -21,6 +21,8 @@
#include <linux/spinlock.h>
#include <plat/clock.h>
+/* pointer to ddr clock structure */
+static struct clk *ddr_clk;
static DEFINE_SPINLOCK(clocks_lock);
static LIST_HEAD(root_clks);
#ifdef CONFIG_DEBUG_FS
@@ -160,7 +162,7 @@ static int do_clk_enable(struct clk *clk)
* time please reclac
*/
if (clk->recalc) {
- ret = clk->recalc(clk);
+ ret = clk->recalc(clk, &clk->rate, clk->pclk->rate);
if (ret)
goto err;
}
@@ -298,7 +300,16 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
propagate_rate(clk, 0);
spin_unlock_irqrestore(&clocks_lock, flags);
} else if (clk->pclk) {
- u32 mult = clk->div_factor ? clk->div_factor : 1;
+ u32 mult;
+ /*
+ * if pclk is SYSTEM_CLK and clk is not SYSTEM_CLK then return
+ * error
+ */
+ if (clk->pclk->flags & SYSTEM_CLK)
+ if (!(clk->flags & SYSTEM_CLK))
+ return -EPERM;
+
+ mult = clk->div_factor ? clk->div_factor : 1;
ret = clk_set_rate(clk->pclk, mult * rate);
}
@@ -371,7 +382,7 @@ void propagate_rate(struct clk *pclk, int on_init)
list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
if (clk->recalc) {
- ret = clk->recalc(clk);
+ ret = clk->recalc(clk, &clk->rate, clk->pclk->rate);
/*
* recalc will return error if clk out is not programmed
* In this case configure default rate.
@@ -390,6 +401,47 @@ void propagate_rate(struct clk *pclk, int on_init)
}
}
+/* updates "rate" pointer with current_clk's output for input "rate" */
+static void rate_calc(struct clk *current_clk, struct clk *ancestor_clk,
+ unsigned long *rate)
+{
+ if (current_clk->pclk != ancestor_clk)
+ rate_calc(current_clk->pclk, ancestor_clk, rate);
+
+ if (current_clk->recalc)
+ current_clk->recalc(current_clk, rate, *rate);
+}
+
+/*
+ * Check if ancestor clk rate is acceptable to ddr or not.
+ * This will call recursive rate_calc function, starting from ddr upto ancestor
+ * clk mentioned. This will calculate divisions / multiplications by all
+ * intermediate ancestor clocks and return the final rate of ddr if ancestor clk
+ * sets its rate to "rate", value passed in function.
+ */
+static int ddr_rate_acceptable(struct clk *aclk, unsigned long rate)
+{
+ struct ddr_rate_tbl *tbl = ddr_clk->private_data;
+
+ rate_calc(ddr_clk, aclk, &rate);
+ if ((rate >= tbl->minrate) && (rate <= tbl->maxrate))
+ return true;
+
+ return false;
+}
+
+/* mark all ddr ancestors with DDR_ANCESTOR flag */
+static void mark_ddr_ancestors(struct clk *dclk)
+{
+ struct clk *clk = dclk->pclk;
+
+ /* mark all ancestors of DDR */
+ while (clk != NULL) {
+ clk->flags |= DDR_ANCESTOR;
+ clk = clk->pclk;
+ }
+}
+
/**
* round_rate - Returns index of closest programmable rate in rate_config tbl
* @clk: ptr to clock structure
@@ -475,7 +527,7 @@ unsigned long pll_calc_rate(struct clk *clk, int index)
* In Dithered mode
* rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
*/
-int pll_clk_recalc(struct clk *clk)
+int pll_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate)
{
struct pll_clk_config *config = clk->private_data;
unsigned int num = 2, den = 0, val, mode = 0;
@@ -504,7 +556,7 @@ int pll_clk_recalc(struct clk *clk)
if (!den)
return -EINVAL;
- clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
+ *rate = (((prate/10000) * num) / den) * 10000;
return 0;
}
@@ -522,6 +574,25 @@ int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
if (i < 0)
return i;
+ /* if clk is ddrs ancestor, check if rate is acceptable to ddr */
+ if (ddr_clk && (clk->flags & DDR_ANCESTOR)) {
+ int ret;
+
+ ret = ddr_rate_acceptable(clk, rate);
+ if (ret == false)
+ return -EPERM;
+ else {
+ /*
+ * call routine to put ddr in refresh mode, and
+ * configure pll.
+ */
+ /* TBD */
+ clk->rate = rate;
+ }
+
+ return ret;
+ }
+
val = readl(config->mode_reg) &
~(config->masks->mode_mask << config->masks->mode_shift);
val |= (tbls[i].mode & config->masks->mode_mask) <<
@@ -563,7 +634,7 @@ unsigned long bus_calc_rate(struct clk *clk, int index)
}
/* calculates current programmed rate of ahb or apb bus */
-int bus_clk_recalc(struct clk *clk)
+int bus_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate)
{
struct bus_clk_config *config = clk->private_data;
unsigned int div;
@@ -574,7 +645,7 @@ int bus_clk_recalc(struct clk *clk)
if (!div)
return -EINVAL;
- clk->rate = (unsigned long)clk->pclk->rate / div;
+ *rate = prate / div;
return 0;
}
@@ -600,6 +671,14 @@ int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
return 0;
}
+/* calculates current programmed rate of ahbmult2 */
+int
+ahbmult2_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate)
+{
+ *rate = prate * 2;
+ return 0;
+}
+
/*
* gives rate for different values of eq, x and y
*
@@ -627,7 +706,7 @@ unsigned long aux_calc_rate(struct clk *clk, int index)
*
* Selection of eqn 1 or 2 is programmed in register
*/
-int aux_clk_recalc(struct clk *clk)
+int aux_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate)
{
struct aux_clk_config *config = clk->private_data;
unsigned int num = 1, den = 1, val, eqn;
@@ -650,7 +729,7 @@ int aux_clk_recalc(struct clk *clk)
if (!den)
return -EINVAL;
- clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
+ *rate = (((prate / 10000) * num) / den) * 10000;
return 0;
}
@@ -704,7 +783,7 @@ unsigned long gpt_calc_rate(struct clk *clk, int index)
* Fout from synthesizer can be given from below equations:
* Fout= Fin/((2 ^ (N+1)) * (M+1))
*/
-int gpt_clk_recalc(struct clk *clk)
+int gpt_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate)
{
struct gpt_clk_config *config = clk->private_data;
unsigned int div = 1, val;
@@ -718,7 +797,7 @@ int gpt_clk_recalc(struct clk *clk)
if (!div)
return -EINVAL;
- clk->rate = (unsigned long)clk->pclk->rate / div;
+ *rate = prate / div;
return 0;
}
@@ -786,11 +865,10 @@ unsigned long clcd_calc_rate(struct clk *clk, int index)
* complete div (including fractional part) and then right shift the
* result by 14 places.
*/
-int clcd_clk_recalc(struct clk *clk)
+int clcd_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate)
{
struct clcd_clk_config *config = clk->private_data;
unsigned int div = 1;
- unsigned long prate;
unsigned int val;
val = readl(config->synth_reg);
@@ -800,10 +878,10 @@ int clcd_clk_recalc(struct clk *clk)
if (!div)
return -EINVAL;
- prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
+ prate = prate / 1000; /* first level division, make it KHz */
- clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
- clk->rate *= 1000;
+ *rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
+ *rate *= 1000;
return 0;
}
@@ -834,11 +912,11 @@ int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
* Used for clocks that always have value as the parent clock divided by a
* fixed divisor
*/
-int follow_parent(struct clk *clk)
+int follow_parent(struct clk *clk, unsigned long *rate, unsigned long prate)
{
unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
- clk->rate = clk->pclk->rate/div_factor;
+ *rate = prate / div_factor;
return 0;
}
@@ -857,7 +935,7 @@ void recalc_root_clocks(void)
spin_lock_irqsave(&clocks_lock, flags);
list_for_each_entry(pclk, &root_clks, sibling) {
if (pclk->recalc) {
- ret = pclk->recalc(pclk);
+ ret = pclk->recalc(pclk, &pclk->rate, pclk->pclk->rate);
/*
* recalc will return error if clk out is not programmed
* In this case configure default clock.
@@ -873,6 +951,23 @@ void recalc_root_clocks(void)
spin_unlock_irqrestore(&clocks_lock, flags);
}
+void __init
+clk_init(struct clk_lookup *clk_lookups, u32 count, struct clk *dclk)
+{
+ int i;
+
+ for (i = 0; i < count; i++)
+ clk_register(&clk_lookups[i]);
+
+ recalc_root_clocks();
+
+ /* Mark all ancestors of DDR with special flag */
+ if (dclk) {
+ ddr_clk = dclk;
+ mark_ddr_ancestors(dclk);
+ }
+}
+
#ifdef CONFIG_DEBUG_FS
/*
* debugfs support to trace clock tree hierarchy and attributes
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index 16aa0c9..e519900 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -19,9 +19,12 @@
#include <linux/types.h>
/* clk structure flags */
-#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
-#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
-#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */
+#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
+#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
+#define ENABLED_ON_INIT (1 << 2) /* clocks enabled@init */
+/* Only System clocks can call other sytem clocks set rate function */
+#define SYSTEM_CLK (1 << 3)
+#define DDR_ANCESTOR (1 << 4) /* ancestor clks of DDR */
/**
* struct clkops - clock operations
@@ -99,8 +102,9 @@ struct clk {
unsigned int *en_reg;
u8 en_reg_bit;
const struct clkops *ops;
- int (*recalc) (struct clk *);
- int (*set_rate) (struct clk *, unsigned long rate);
+ int (*recalc) (struct clk *clk, unsigned long *rate,
+ unsigned long prate);
+ int (*set_rate) (struct clk *clk, unsigned long rate);
unsigned long (*calc_rate)(struct clk *, int index);
struct rate_config rate_config;
unsigned int div_factor;
@@ -223,26 +227,42 @@ struct clcd_rate_tbl {
u16 div;
};
+/* ddr min, max clk rate table */
+struct ddr_rate_tbl {
+ unsigned long minrate;
+ unsigned long maxrate;
+};
+
/* platform specific clock functions */
+/*
+ * must be called from machine clock.c file, dclk is pointer to ddr_clk
+ * strucutre. Which is required by clock framework.
+ *
+ * Actually before changing rate of DDRs ancestor, we must put ddr in refresh
+ * state and then change parent.
+ */
+void clk_init(struct clk_lookup *clk_lookups, u32 count, struct clk *dclk);
void clk_register(struct clk_lookup *cl);
void recalc_root_clocks(void);
/* clock recalc & set rate functions */
-int follow_parent(struct clk *clk);
+int follow_parent(struct clk *clk, unsigned long *rate, unsigned long prate);
unsigned long pll_calc_rate(struct clk *clk, int index);
-int pll_clk_recalc(struct clk *clk);
+int pll_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate);
int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long bus_calc_rate(struct clk *clk, int index);
-int bus_clk_recalc(struct clk *clk);
+int bus_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate);
int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+int ahbmult2_clk_recalc(struct clk *clk, unsigned long *rate,
+ unsigned long prate);
unsigned long gpt_calc_rate(struct clk *clk, int index);
-int gpt_clk_recalc(struct clk *clk);
+int gpt_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate);
int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long aux_calc_rate(struct clk *clk, int index);
-int aux_clk_recalc(struct clk *clk);
+int aux_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate);
int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long clcd_calc_rate(struct clk *clk, int index);
-int clcd_clk_recalc(struct clk *clk);
+int clcd_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate);
int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
#endif /* __PLAT_CLOCK_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 35/62] ST SPEAr : EMI (Extrenal Memory Interface) controller driver
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (32 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 34/62] ST SPEAr: Adding support for DDR in clock framework Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 36/62] SPEAr Clock Framework: Adding support for PLL frequency change Viresh Kumar
` (27 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipin Kumar <vipin.kumar@st.com>
2 SPEAr platform SoCs(spear310 and spear320) support an External Memory
Interface controller. This controller is used to interface with
Parallel NOR Flash devices.
This patch adds just the platform code needed for EMI (mainly EMI
initialization). The driver being used is driver/mtd/maps/physmap.c
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/Makefile | 4 +
arch/arm/mach-spear3xx/emi.c | 101 ++++++++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/emi.h | 64 +++++++++++++++
arch/arm/mach-spear3xx/include/mach/generic.h | 2 +
arch/arm/mach-spear3xx/include/mach/spear310.h | 9 ++
arch/arm/mach-spear3xx/include/mach/spear320.h | 6 ++
arch/arm/mach-spear3xx/spear310.c | 9 ++
arch/arm/mach-spear3xx/spear310_evb.c | 28 +++++++
arch/arm/mach-spear3xx/spear320.c | 9 ++
arch/arm/mach-spear3xx/spear320_evb.c | 27 ++++++
10 files changed, 259 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear3xx/emi.c
create mode 100644 arch/arm/mach-spear3xx/include/mach/emi.h
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b248624..d38ae47 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -24,3 +24,7 @@ obj-$(CONFIG_MACH_SPEAR320) += spear320.o
# spear320 boards files
obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
+
+# specific files
+obj-$(CONFIG_MACH_SPEAR310) += emi.o
+obj-$(CONFIG_MACH_SPEAR320) += emi.o
diff --git a/arch/arm/mach-spear3xx/emi.c b/arch/arm/mach-spear3xx/emi.c
new file mode 100644
index 0000000..7b62ff0
--- /dev/null
+++ b/arch/arm/mach-spear3xx/emi.c
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mach-spear3xx/emi.c
+ *
+ * EMI (External Memory Interface) file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Vipin Kumar<vipin.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <mach/emi.h>
+
+int __init emi_init(struct platform_device *pdev, unsigned long base,
+ u32 bank, u32 width)
+{
+ void __iomem *emi_reg_base;
+ struct clk *clk;
+ int ret;
+
+ if (bank > (EMI_MAX_BANKS - 1))
+ return -EINVAL;
+
+ emi_reg_base = ioremap(base, EMI_REG_SIZE);
+ if (!emi_reg_base)
+ return -ENOMEM;
+
+ clk = clk_get(NULL, "emi");
+ if (IS_ERR(clk)) {
+ iounmap(emi_reg_base);
+ return PTR_ERR(clk);
+ }
+
+ ret = clk_enable(clk);
+ if (ret) {
+ iounmap(emi_reg_base);
+ return ret;
+ }
+
+ /*
+ * Note: These are relaxed NOR device timings. Nor devices on spear
+ * eval machines are working fine with these timings. Specific board
+ * files can optimize these timings based on devices found on board.
+ */
+ writel(0x10, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TAP_REG);
+ writel(0x05, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TSDP_REG);
+ writel(0x0a, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TDPW_REG);
+ writel(0x0a, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TDPR_REG);
+ writel(0x05, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TDCS_REG);
+
+ switch (width) {
+ case EMI_FLASH_WIDTH8:
+ width = EMI_CNTL_WIDTH8;
+ break;
+
+ case EMI_FLASH_WIDTH16:
+ width = EMI_CNTL_WIDTH16;
+ break;
+
+ case EMI_FLASH_WIDTH32:
+ width = EMI_CNTL_WIDTH32;
+ break;
+ default:
+ width = EMI_CNTL_WIDTH8;
+ break;
+ }
+ /* set the data width */
+ writel(width | EMI_CNTL_ENBBYTERW,
+ emi_reg_base + (EMI_BANK_REG_SIZE * bank) + CTRL_REG);
+
+ /* disable all the acks */
+ writel(0x3f, emi_reg_base + ack_reg);
+
+ iounmap(emi_reg_base);
+
+ return 0;
+}
+
+void __init
+emi_init_board_info(struct platform_device *pdev, struct resource *resources,
+ int res_num, struct mtd_partition *partitions,
+ unsigned int nr_partitions, unsigned int width)
+{
+ struct physmap_flash_data *emi_plat_data = dev_get_platdata(&pdev->dev);
+
+ pdev->resource = resources;
+ pdev->num_resources = res_num;
+
+ if (partitions) {
+ emi_plat_data->parts = partitions;
+ emi_plat_data->nr_parts = nr_partitions;
+ }
+
+ emi_plat_data->width = width;
+}
diff --git a/arch/arm/mach-spear3xx/include/mach/emi.h b/arch/arm/mach-spear3xx/include/mach/emi.h
new file mode 100644
index 0000000..b620bf5
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/emi.h
@@ -0,0 +1,64 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/emi.h
+ *
+ * EMI macros for SPEAr platform
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Vipin Kumar <vipin.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_EMI_H
+#define __MACH_EMI_H
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+
+#define EMI_FLASH_WIDTH8 1
+#define EMI_FLASH_WIDTH16 2
+#define EMI_FLASH_WIDTH32 4
+
+#define EMI_REG_SIZE 0x100
+#define EMI_BANK_REG_SIZE 0x18
+
+#define TAP_REG (0x0)
+#define TSDP_REG (0x4)
+#define TDPW_REG (0x8)
+#define TDPR_REG (0xC)
+#define TDCS_REG (0x10)
+#define CTRL_REG (0x14)
+
+#if defined(CONFIG_MACH_SPEAR310)
+#define TIMEOUT_REG (0x90)
+#define ACK_REG (0x94)
+#define IRQ_REG (0x98)
+
+#define EMI_MAX_BANKS 6
+
+#elif defined(CONFIG_MACH_SPEAR320)
+#define TIMEOUT_REG (0x60)
+#define ACK_REG (0x64)
+#define IRQ_REG (0x68)
+
+#define EMI_MAX_BANKS 4
+
+#endif
+
+/* Control register definitions */
+#define EMI_CNTL_WIDTH8 (0 << 0)
+#define EMI_CNTL_WIDTH16 (1 << 0)
+#define EMI_CNTL_WIDTH32 (2 << 0)
+#define EMI_CNTL_ENBBYTEW (1 << 2)
+#define EMI_CNTL_ENBBYTER (1 << 3)
+#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
+
+extern int __init emi_init(struct platform_device *pdev, unsigned long base,
+ u32 bank, u32 width);
+extern void __init emi_init_board_info(struct platform_device *pdev,
+ struct resource *resources, int res_num, struct mtd_partition
+ *partitions, unsigned int nr_partitions, unsigned int width);
+#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index f8613f4..da0eaa3 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -165,6 +165,7 @@ extern struct amba_device uart2_device;
extern struct amba_device uart3_device;
extern struct amba_device uart4_device;
extern struct amba_device uart5_device;
+extern struct platform_device emi_nor_device;
extern struct platform_device plgpio_device;
extern struct platform_device nand_device;
@@ -190,6 +191,7 @@ extern struct amba_device uart1_device;
extern struct amba_device uart2_device;
extern struct platform_device can0_device;
extern struct platform_device can1_device;
+extern struct platform_device emi_nor_device;
extern struct platform_device i2c1_device;
extern struct platform_device nand_device;
extern struct platform_device plgpio_device;
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1e85347..37556b6 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -18,6 +18,15 @@
#define SPEAR310_NAND_BASE UL(0x40000000)
#define SPEAR310_FSMC_BASE UL(0x44000000)
+#define SPEAR310_EMI_REG_BASE UL(0x4F000000)
+#define SPEAR310_EMI_MEM_0_BASE UL(0x50000000)
+#define SPEAR310_EMI_MEM_1_BASE UL(0x60000000)
+#define SPEAR310_EMI_MEM_2_BASE UL(0x70000000)
+#define SPEAR310_EMI_MEM_3_BASE UL(0x80000000)
+#define SPEAR310_EMI_MEM_4_BASE UL(0x90000000)
+#define SPEAR310_EMI_MEM_5_BASE UL(0xA0000000)
+#define SPEAR310_EMI_MEM_SIZE UL(0x10000000)
+
#define SPEAR310_UART1_BASE UL(0xB2000000)
#define SPEAR310_UART2_BASE UL(0xB2080000)
#define SPEAR310_UART3_BASE UL(0xB2100000)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 940f0d8..4f60073 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -17,6 +17,12 @@
#define __MACH_SPEAR320_H
#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
+#define SPEAR320_EMI_MEM_0_BASE UL(0x44000000)
+#define SPEAR320_EMI_MEM_1_BASE UL(0x45000000)
+#define SPEAR320_EMI_MEM_2_BASE UL(0x46000000)
+#define SPEAR320_EMI_MEM_3_BASE UL(0x47000000)
+#define SPEAR320_EMI_MEM_SIZE UL(0x01000000)
+
#define SPEAR320_FSMC_BASE UL(0x4C000000)
#define SPEAR320_NAND_BASE UL(0x50000000)
#define SPEAR320_I2S_BASE UL(0x60000000)
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 673874a..5f72d3a 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/mtd/physmap.h>
#include <linux/ptrace.h>
#include <linux/mtd/fsmc.h>
#include <asm/irq.h>
@@ -268,6 +269,14 @@ int spear300_o2p(int offset)
return offset + 2;
}
+/* emi nor flash device registeration */
+static struct physmap_flash_data emi_norflash_data;
+struct platform_device emi_nor_device = {
+ .name = "physmap-flash",
+ .id = -1,
+ .dev.platform_data = &emi_norflash_data,
+};
+
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
.irq_base = SPEAR_PLGPIO_INT_BASE,
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 6daacbb..a3cd4a1 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -17,12 +17,31 @@
#include <asm/mach-types.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
+#include <mach/emi.h>
#include <mach/generic.h>
#include <mach/gpio.h>
#include <mach/spear.h>
#include <plat/fsmc.h>
#include <plat/spi.h>
+#define PARTITION(n, off, sz) {.name = n, .offset = off, .size = sz}
+
+static struct mtd_partition partition_info[] = {
+ PARTITION("X-loader", 0, 1 * 0x20000),
+ PARTITION("U-Boot", 0x20000, 3 * 0x20000),
+ PARTITION("Kernel", 0x80000, 24 * 0x20000),
+ PARTITION("Root File System", 0x380000, 84 * 0x20000),
+};
+
+/* emi nor flash resources registeration */
+static struct resource emi_nor_resources[] = {
+ {
+ .start = SPEAR310_EMI_MEM_0_BASE,
+ .end = SPEAR310_EMI_MEM_0_BASE + SPEAR310_EMI_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
@@ -67,6 +86,7 @@ static struct platform_device *plat_devs[] __initdata = {
&rtc_device,
/* spear310 specific devices */
+ &emi_nor_device,
&plgpio_device,
};
@@ -119,6 +139,14 @@ static void __init spear310_evb_init(void)
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
+ /* initialize emi related data in emi plat data */
+ emi_init_board_info(&emi_nor_device, emi_nor_resources,
+ ARRAY_SIZE(emi_nor_resources), partition_info,
+ ARRAY_SIZE(partition_info), EMI_FLASH_WIDTH32);
+
+ /* Initialize emi regiters */
+ emi_init(&emi_nor_device, SPEAR310_EMI_REG_BASE, 0, EMI_FLASH_WIDTH32);
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 3c90d47..e7ca5db 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -12,6 +12,7 @@
*/
#include <linux/amba/pl022.h>
+#include <linux/mtd/physmap.h>
#include <linux/ptrace.h>
#include <linux/types.h>
#include <linux/mmc/sdhci-spear.h>
@@ -510,6 +511,14 @@ struct platform_device can1_device = {
.resource = can1_resources,
};
+/* emi nor flash device registeration */
+static struct physmap_flash_data emi_norflash_data;
+struct platform_device emi_nor_device = {
+ .name = "physmap-flash",
+ .id = -1,
+ .dev.platform_data = &emi_norflash_data,
+};
+
/* i2c1 device registeration */
static struct resource i2c1_resources[] = {
{
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index cf81208..e1a0b3c 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -18,12 +18,31 @@
#include <linux/spi/flash.h>
#include <linux/mmc/sdhci-spear.h>
#include <linux/spi/spi.h>
+#include <mach/emi.h>
#include <mach/generic.h>
#include <mach/gpio.h>
#include <mach/spear.h>
#include <plat/fsmc.h>
#include <plat/spi.h>
+#define PARTITION(n, off, sz) {.name = n, .offset = off, .size = sz}
+
+static struct mtd_partition partition_info[] = {
+ PARTITION("X-loader", 0, 1 * 0x20000),
+ PARTITION("U-Boot", 0x20000, 3 * 0x20000),
+ PARTITION("Kernel", 0x80000, 24 * 0x20000),
+ PARTITION("Root File System", 0x380000, 84 * 0x20000),
+};
+
+/* emi nor flash resources registeration */
+static struct resource emi_nor_resources[] = {
+ {
+ .start = SPEAR310_EMI_MEM_0_BASE,
+ .end = SPEAR310_EMI_MEM_0_BASE + SPEAR310_EMI_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
@@ -106,6 +125,14 @@ static void __init spear320_evb_init(void)
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
+ /* initialize emi related data in emi plat data */
+ emi_init_board_info(&emi_nor_device, emi_nor_resources,
+ ARRAY_SIZE(emi_nor_resources), partition_info,
+ ARRAY_SIZE(partition_info), EMI_FLASH_WIDTH16);
+
+ /* Initialize emi regiters */
+ emi_init(&emi_nor_device, SPEAR320_EMI_CTRL_BASE, 0, EMI_FLASH_WIDTH16);
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 36/62] SPEAr Clock Framework: Adding support for PLL frequency change
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (33 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 35/62] ST SPEAr : EMI (Extrenal Memory Interface) controller driver Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 37/62] SPEAr Power Management: Added the support for Standby mode Viresh Kumar
` (26 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/spear3xx.c | 5 +
arch/arm/mach-spear6xx/spear6xx.c | 5 +
arch/arm/plat-spear/Makefile | 2 +-
arch/arm/plat-spear/clock.c | 6 +-
arch/arm/plat-spear/include/plat/clock.h | 1 +
arch/arm/plat-spear/pll_clk.S | 187 ++++++++++++++++++++++++++++++
6 files changed, 201 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/plat-spear/pll_clk.S
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 2806cbc..dceb632 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -252,6 +252,11 @@ struct map_desc spear3xx_io_desc[] __initdata = {
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
.length = SZ_4K,
.type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR3XX_ICM3_SDRAM_CTRL_BASE),
+ .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SDRAM_CTRL_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
},
};
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index eff6da1..96a3245 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -411,6 +411,11 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
.length = SZ_4K,
.type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR6XX_ICM3_SDRAM_CTRL_BASE),
+ .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SDRAM_CTRL_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
},
};
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 37a61cc..6ff3eb7 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,7 +3,7 @@
#
# Common support
-obj-y := clcd.o clock.o time.o
+obj-y := clcd.o clock.o pll_clk.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index fb1c87b..ee8f82b 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -586,11 +586,10 @@ int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
* call routine to put ddr in refresh mode, and
* configure pll.
*/
- /* TBD */
+ pll_set_rate(tbls[i].m, tbls[i].p, tbls[i].n);
clk->rate = rate;
}
-
- return ret;
+ return 0;
}
val = readl(config->mode_reg) &
@@ -616,7 +615,6 @@ int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
config->masks->norm_fdbk_m_shift;
writel(val, config->cfg_reg);
-
clk->rate = rate;
return 0;
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index e519900..4c4bf87 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -264,5 +264,6 @@ int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long clcd_calc_rate(struct clk *clk, int index);
int clcd_clk_recalc(struct clk *clk, unsigned long *rate, unsigned long prate);
int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
+void pll_set_rate(u16 pdiv, u8 nmul, u8 hclkdiv);
#endif /* __PLAT_CLOCK_H */
diff --git a/arch/arm/plat-spear/pll_clk.S b/arch/arm/plat-spear/pll_clk.S
new file mode 100644
index 0000000..d0687b4
--- /dev/null
+++ b/arch/arm/plat-spear/pll_clk.S
@@ -0,0 +1,187 @@
+/*
+ * arch/arm/plat-spear/pll_clk.S
+ *
+ * SPEAR3xx and SPEAR6xx specific functions that will run in
+ * cache. These funstions intend to configure the PLL.
+ *
+ * Copyright (ST) 2010 Deepak Sikri <deepak.sikri@.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <mach/suspend.h>
+
+#if defined(CONFIG_ARCH_SPEAR3XX) || defined(CONFIG_ARCH_SPEAR6XX)
+.text
+ENTRY(pll_set_rate)
+ stmfd sp!, {r0-r12, lr}
+
+ /* Lock down the TLB entry to the current victim */
+ mrc p15, 0, r3, c10, c0, 0 /* read the lockdown register */
+ orr r3, r3, #1 /* set the preserved bit */
+ mcr p15, 0, r3, c10, c0, 0 /* write to the lockdown register */
+
+ /*
+ * set r4 to the value of the address to be locked down.
+ * Invalidate the TLB single entry in TLB to ensure that
+ * the locked address is not already in TLB.
+ * MPMC, System Controller & Miscellaneous register address
+ * are locked down below.
+ */
+
+ ldr r4, MPMC_BASE_VA
+ /* Invalidate the MPMC virtual address in TLB. */
+ mcr p15, 0, r4, c8, c7, 1
+ /* TLB will miss and entry will be reloaded */
+ ldr r4, [r4]
+ /* read the lockdown register (victim will have rloaded) */
+ mrc p15, 0, r3, c10, c0, 0
+
+ ldr r4, SYS_CTRL_BASE_VA
+ /* Invalidate the System controller virtual address in TLB */
+ mcr p15, 0, r4, c8, c7, 1
+ /* TLB will miss and entry will be reloaded */
+ ldr r4, [r4]
+ /* read the lockdown register (victim will have rloaded) */
+ mrc p15, 0, r3, c10, c0, 0
+
+ ldr r4, MISC_BASE_VA
+ /* Invalidate the Miscellaneous registers virtual address in TLB */
+ mcr p15, 0, r4, c8, c7, 1
+ /* TLB will miss and entry will be reloaded */
+ ldr r4, [r4]
+ /* read the lockdown register (victim will have rloaded) */
+ mrc p15, 0, r3, c10, c0, 0
+
+ /* clear preserve bit */
+ bic r3, r3, #1
+ /* write to the lockdown register */
+ mcr p15, 0, r3, c10, c0, 0
+
+ ldr r7, MPMC_BASE_VA
+ ldr r8, SYS_CTRL_BASE_VA
+ ldr r6, MISC_BASE_VA
+ /* Prefetch certain instructions in the cache. */
+ adr r4, cache_prefetch_start1
+ adr r5, cache_prefetch_end1
+ mvn r3, #0x1F
+ ands r4, r3, r4
+ /* Lock Instructions in i-cache */
+fetch_loop:
+ /*
+ * copy a cache-line-sized block of main memory to a cache
+ * line in the I-cache.
+ */
+ mcr p15, 0, r4, c7, c13, 1
+ cmp r4, r5
+ addls r4, r4, #0x20
+ bls fetch_loop
+cache_prefetch_start1:
+ /* Put SDRAM in self-refresh mode */
+ ldr r3, [r7, #0x1c]
+ /* Clear START bit(24) of MEMCTL_GP_03 register in MPMC */
+ ldr r4, =0x1000000
+ bic r3, r3, r4
+ str r3, [r7, #0x1c]
+
+ ldr r3, [r7, #0xe4]
+ ldr r4, =0xffff0000
+ /* Latch the current self refresh time */
+ mov r9, r3
+ /* Increase the self refresh exit time */
+ bic r3, r3, r4
+ ldr r4, =0xffff
+ /* Program the SDRAM self refresh exit time on read command */
+ orr r3, r3, r4, LSL #16
+ str r3, [r7, #0xe4]
+
+ ldr r3, [r7, #0x1c]
+ /* Set the SREFRESH bit(16) */
+ ldr r4, =0x10000
+ orr r3, r3, r4
+ str r3, [r7, #0x1c]
+
+ /* Put the system in slow mode, use system controller */
+ ldr r3, [r8]
+ bic r3, r3, #0x7
+ /* Set the apt mode bits(2:0) in SCCTRL register */
+ orr r3, r3, #0x2
+ str r3, [r8]
+
+wait_till_slow_mode:
+ ldr r3, [r8]
+ and r3, r3, #0x78 /* Wait for the mode to be updated */
+ cmp r3, #0x10 /* Poll the SCCTRL register status bits (6:3) */
+ bne wait_till_slow_mode
+
+ /*
+ * reprogram the m(r0), p(r2), n(r1) values in the PLL
+ * control registers (PLL_FRQ register in misc space).
+ */
+ ldr r3, [r6, #0x0c]
+ bic r3, r3, #0x00ff
+ /* Program the PLL post divisor: p */
+ orr r3, r3, r2
+ str r3, [r6, #0x0c]
+
+ ldr r3, [r6, #0x0c]
+ ldr r4, =0xffff0000
+ bic r3, r3, r4
+ bic r3, r3, #0x0700
+ /* Program the PLL pre divisor: n */
+ orr r3, r3, r1, LSL #8
+ /* Program the PLL feedback divisor: m */
+ orr r3, r3, r0, LSL #24
+ str r3, [r6, #0x0c]
+
+ /* Move the system in Normal mode, use system controller */
+ ldr r3, [r8, #0x0]
+ ldr r4, =0xfffffff8
+ /* Set the apt mode bits(2:0) in SCCTRL register */
+ and r3, r3, r4
+ orr r3, r3, #0x4
+ str r3, [r8, #0x0]
+
+wait_till_normal_mode:
+ ldr r3, [r8, #0x0]
+ and r3, r3, #0x78
+ cmp r3, #0x20 /* Poll the SCCTRL register status bits (6:3) */
+ bne wait_till_normal_mode
+
+ /* Exit DDR-SDRAM from self-refresh mode */
+ ldr r10, MPMC_BASE_VA
+ /* Clear the SREFRESH bit(16) */
+ ldr r3, [r10, #0x1c]
+ ldr r4, =0x10000
+ bic r3, r3, r4
+ str r3, [r10, #0x1c]
+ /* Restore the SDRAM self refresh exit time on read command */
+ mov r3, r9
+ str r3, [r7, #0xe4]
+ /* Begin the command processing in controller */
+ ldr r4, =0x1000000
+ orr r3, r3, r4
+ /* Set START bit(24) of MEMCTL_GP_03 register in MPMC*/
+ str r3, [r10, #0x1c]
+
+ ldmfd sp!, {r0-r12, pc}
+
+/* This is the end of the code to be copied */
+
+SYS_CTRL_BASE_VA :
+ .word IO_ADDRESS(SYS_CTRL_BASE_PA)
+MPMC_BASE_VA :
+ .word IO_ADDRESS(MPMC_BASE_PA)
+MISC_BASE_VA :
+ .word IO_ADDRESS(MISC_BASE_PA)
+cache_prefetch_end1 :
+
+#elif defined(CONFIG_ARCH_SPEAR13XX)
+.text
+ENTRY(pll_set_rate)
+#endif
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 37/62] SPEAr Power Management: Added the support for Standby mode.
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (34 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 36/62] SPEAr Clock Framework: Adding support for PLL frequency change Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework Viresh Kumar
` (25 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Deepak Sikri <deepak.sikri@st.com>
Open Points:
-> Suspend to RAM support needs to be added.
-> SPEAr13xx: The power domains need to be added.
-> For SPEAr13xx: PLL-4 has not been switch off while moving
into sleep. There is some problem in getting the pll back to on.
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/Makefile | 1 +
arch/arm/mach-spear13xx/include/mach/suspend.h | 47 +++
arch/arm/mach-spear13xx/pm.c | 107 ++++++
arch/arm/mach-spear13xx/sleep.S | 435 ++++++++++++++++++++++++
arch/arm/mach-spear13xx/spear13xx.c | 5 +
arch/arm/mach-spear3xx/include/mach/suspend.h | 44 +++
arch/arm/mach-spear3xx/spear3xx.c | 5 +-
arch/arm/mach-spear6xx/include/mach/suspend.h | 44 +++
arch/arm/mach-spear6xx/spear6xx.c | 9 +-
arch/arm/plat-spear/Makefile | 6 +
arch/arm/plat-spear/pm.c | 104 ++++++
arch/arm/plat-spear/sleep.S | 288 ++++++++++++++++
12 files changed, 1093 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/suspend.h
create mode 100644 arch/arm/mach-spear13xx/pm.c
create mode 100644 arch/arm/mach-spear13xx/sleep.S
create mode 100644 arch/arm/mach-spear3xx/include/mach/suspend.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/suspend.h
create mode 100644 arch/arm/plat-spear/pm.c
create mode 100644 arch/arm/plat-spear/sleep.S
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index 838405a..0611278 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -7,6 +7,7 @@ obj-y += spear13xx.o clock.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
obj-$(CONFIG_PCIEPORTBUS) += pcie.o
+obj-$(CONFIG_PM) += pm.o sleep.o
# spear1300 specific files
obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
diff --git a/arch/arm/mach-spear13xx/include/mach/suspend.h b/arch/arm/mach-spear13xx/include/mach/suspend.h
new file mode 100644
index 0000000..c8d13e6
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/suspend.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/suspend.h
+ *
+ * Sleep mode defines for SPEAr13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * AUTHOR : Deepak Sikri <deepak.sikri@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SUSPEND_H
+#define __MACH_SUSPEND_H
+
+#include <mach/spear.h>
+
+#ifndef __ASSEMBLER__
+extern void spear_sleep_mode(suspend_state_t state);
+extern unsigned int spear_sleep_mode_sz;
+extern void spear_wakeup(void);
+extern unsigned int spear_wakeup_sz;
+#endif
+
+/* SRAM related defines*/
+#define SRAM_STACK_STRT_OFF 0x500
+#define SRAM_STACK_SCR_OFFS 0xF00
+#define SPEAR_START_SRAM SPEAR13XX_SYSRAM1_BASE
+#define SPEAR_LIMIT_SRAM (SPEAR_START_SRAM + SZ_4K - 1)
+#define SPEAR_SRAM_STACK_PA (SPEAR_START_SRAM + SRAM_STACK_STRT_OFF)
+#define SPEAR_SRAM_SCR_REG (SPEAR_START_SRAM + SRAM_STACK_SCR_OFFS)
+/* SPEAr subsystem physical addresses */
+#define MPMC_BASE_PA SPEAR13XX_MPMC_BASE
+#define MISC_BASE_PA SPEAR13XX_MISC_BASE
+
+/* ARM Modes of Operation */
+#define MODE_USR_32 0x10
+#define MODE_FIQ_32 0x11
+#define MODE_IRQ_32 0x12
+#define MODE_SVC_32 0x13
+#define MODE_ABT_32 0x17
+#define MODE_UND_32 0x1B
+#define MODE_SYS_32 0x1F
+#define MODE_BITS 0x1F
+
+#endif /* __MACH_SUSPEND_H */
diff --git a/arch/arm/mach-spear13xx/pm.c b/arch/arm/mach-spear13xx/pm.c
new file mode 100644
index 0000000..6152043
--- /dev/null
+++ b/arch/arm/mach-spear13xx/pm.c
@@ -0,0 +1,107 @@
+/*
+ * arch/arm/mach-spear13xx/pm.c
+ *
+ * SPEAr13xx Power Management source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Deepak Sikri <deepak.sikri@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/suspend.h>
+#include <linux/sysfs.h>
+#include <linux/module.h>
+#include <asm/cacheflush.h>
+#include <mach/irqs.h>
+#include <mach/suspend.h>
+#include <mach/hardware.h>
+
+static int spear_pm_sleep(suspend_state_t state)
+{
+ void (*spear_sram_sleep)(suspend_state_t state) = NULL;
+ void (*spear_sram_wake)(void) = NULL;
+ void *sram_dest = (void *)IO_ADDRESS(SPEAR_START_SRAM);
+
+ if (state == PM_SUSPEND_MEM) {
+ spear_sram_wake = memcpy(sram_dest, (void *)spear_wakeup,
+ spear_wakeup_sz);
+ /* Increment destination pointer by the size copied*/
+ sram_dest += roundup(spear_wakeup_sz, 4);
+ }
+
+ /* Copy the Sleep code on to the SRAM*/
+ spear_sram_sleep = memcpy(sram_dest, (void *)spear_sleep_mode,
+ spear_sleep_mode_sz);
+ flush_cache_all();
+ /* Jump to the suspend routines in sram */
+ spear_sram_sleep(state);
+ return 0;
+}
+
+/*
+ * spear_pm_prepare - Do preliminary suspend work.
+ *
+ */
+static int spear_pm_prepare(void)
+{
+ /* We cannot sleep in idle until we have resumed */
+ disable_hlt();
+ return 0;
+}
+
+/*
+ * spear_pm_enter - Actually enter a sleep state.
+ * @state: State we're entering.
+ *
+ */
+static int spear_pm_enter(suspend_state_t state)
+{
+ int ret;
+
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ case PM_SUSPEND_MEM:
+ ret = spear_pm_sleep(state);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+/*
+ * spear_pm_finish - Finish up suspend sequence.
+ *
+ * This is called after we wake back up (or if entering the sleep state
+ * failed).
+ */
+static void spear_pm_finish(void)
+{
+ enable_hlt();
+}
+
+static struct platform_suspend_ops spear_pm_ops = {
+ .prepare = spear_pm_prepare,
+ .enter = spear_pm_enter,
+ .finish = spear_pm_finish,
+ .valid = suspend_valid_only_mem,
+};
+
+static int __init spear_pm_init(void)
+{
+ void * sram_limit_va = (void *)IO_ADDRESS(SPEAR_LIMIT_SRAM);
+ void * sram_st_va = (void *)IO_ADDRESS(SPEAR_START_SRAM);
+
+ /* In case the suspend code size is more than sram size return */
+ if (spear_sleep_mode_sz > (sram_limit_va - sram_st_va))
+ return -ENOMEM;
+
+ suspend_set_ops(&spear_pm_ops);
+
+ return 0;
+}
+arch_initcall(spear_pm_init);
diff --git a/arch/arm/mach-spear13xx/sleep.S b/arch/arm/mach-spear13xx/sleep.S
new file mode 100644
index 0000000..9c7f12b
--- /dev/null
+++ b/arch/arm/mach-spear13xx/sleep.S
@@ -0,0 +1,435 @@
+/*
+ * linux/arch/arm/mach-spear13xx/sleep.S
+ *
+ * SPEAR13xx specific functions that will run in internal SRAM.
+ * The functions are used in power management.
+ *
+ * Copyright (C) 2010 ST MicroElectronics
+ * Deepak Sikri <deepak.sikri@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <mach/suspend.h>
+
+/* #define DDR_PLL_SREFRESH */
+/* #define TEST_PWRDOMAINS */
+.text
+ENTRY(spear_wakeup)
+
+spear_wakeup:
+ b spear_wakeup
+ adr r0, spear_sleep_restore
+ bx r0
+
+ENTRY(spear_wakeup_sz)
+ .word . - spear_wakeup
+/*
+ * spear_sleep_mode()
+ * Forces SPEAr into sleep
+ */
+ENTRY(spear_sleep_mode)
+ stmfd sp!, {r0-r12, lr} @ save registers on stack
+ /* Store Stack address in r8 */
+ ldr r8, SRAM_STACK_VA
+
+ /* Store sp and spsr to SDRAM */
+ mov r4, sp
+ mrs r5, spsr
+ mov r6, lr
+ stmia r8!, {r4-r6}
+
+ /* Save all ARM registers */
+ /* Coprocessor access control register */
+ mrc p15, 0, r6, c1, c0, 2
+ stmia r8!, {r6}
+ /* TTBR0, TTBR1 and Translation table base control */
+ mrc p15, 0, r4, c2, c0, 0
+ mrc p15, 0, r5, c2, c0, 1
+ mrc p15, 0, r6, c2, c0, 2
+ stmia r8!, {r4-r6}
+ /*
+ * Domain access control register, data fault status register,
+ * and instruction fault status register
+ */
+ mrc p15, 0, r4, c3, c0, 0
+ mrc p15, 0, r5, c5, c0, 0
+ mrc p15, 0, r6, c5, c0, 1
+ stmia r8!, {r4-r6}
+ /*
+ * Data aux fault status register, instruction aux fault status,
+ * data fault address register and instruction fault address register
+ */
+ mrc p15, 0, r4, c5, c1, 0
+ mrc p15, 0, r5, c5, c1, 1
+ mrc p15, 0, r6, c6, c0, 0
+ mrc p15, 0, r7, c6, c0, 2
+ stmia r8!, {r4-r7}
+ /*
+ * user r/w thread and process ID, user r/o thread and process ID,
+ * priv only thread and process ID, cache size selection
+ */
+ mrc p15, 0, r4, c13, c0, 2
+ mrc p15, 0, r5, c13, c0, 3
+ mrc p15, 0, r6, c13, c0, 4
+ mrc p15, 2, r7, c0, c0, 0
+ stmia r8!, {r4-r7}
+ /* Data TLB lockdown, instruction TLB lockdown registers */
+ mrc p15, 0, r5, c10, c0, 0
+ mrc p15, 0, r6, c10, c0, 1
+ stmia r8!, {r5-r6}
+ /* Secure or non secure vector base address, FCSE PID, Context PID*/
+ mrc p15, 0, r4, c12, c0, 0
+ mrc p15, 0, r5, c13, c0, 0
+ mrc p15, 0, r6, c13, c0, 1
+ stmia r8!, {r4-r6}
+ /* Primary remap, normal remap registers */
+ mrc p15, 0, r4, c10, c2, 0
+ mrc p15, 0, r5, c10, c2, 1
+ stmia r8!, {r4-r5}
+ /* Store current cpsr*/
+ mrs r2, cpsr
+ stmia r8!, {r2}
+ mrc p15, 0, r4, c1, c0, 0
+ /* save control register */
+ stmia r8!, {r4}
+ /* Data memory barrier and Data sync barrier */
+ mov r1, #0
+ mcr p15, 0, r1, c7, c10, 4
+ mcr p15, 0, r1, c7, c10, 5
+ dsb
+ isb
+ /* Extract the physical address to jump to */
+ adr r0, mmu_off
+ mov r1, #0xcfffffff
+ and r0, r0, r1
+ ldr r1, =0x20000000
+ orr r0, r0, r1
+ mov r2, r0
+
+ /* Disable MMU */
+ mrc p15, 0, r0, c1, c0, 0
+ ldr r1, DISABLE_I_C_M_V
+ bic r0, r0, r1
+ mcr p15, 0, r0, c1, c0, 0
+ /* Move the Physical address into PC */
+ bx r2
+ nop
+mmu_off:
+ /* Put the DDR in self refresh mode */
+ ldr r6, MISC_BASE_P
+ /* Program MPMC Control Status register in Misc Space */
+ ldr r0, [r6, #0x334]
+ /* Set srefresh_enter bit(2) */
+ orr r0, r0, #0x4
+ str r0, [r6, #0x334]
+wait_till_srefresh_on:
+ ldr r0, [r6, #0x334]
+ /* check for cke_status bit(13) */
+ tst r0, #0x2000
+ beq wait_till_srefresh_on
+
+ /* Put the system in slow mode */
+ ldr r0, [r6, #0x200]
+ bic r0, r0, #0x4
+ /* Set the apt mode bits(2:0) in SCCTRL register */
+ orr r0, r0, #0x2
+ str r0, [r6, #0x200] /* System is now in slow mode */
+wait_till_slow_mode:
+ ldr r0, [r6, #0x200]
+ /* Wait for the mode to be updated */
+ and r0, r0, #0xF0000
+ /* Poll the SCCTRL register status bits (6:3) */
+ cmp r0, #0xA0000
+ bne wait_till_slow_mode
+
+ /*
+ * Put the all the system pll's to off state
+ * The loop of count 3 is provided below to
+ * switch off the pll-1/2/3.
+ * r1 contains the offset for the pll control
+ * registers in the misc space.
+ * DDR pll-4 requires different processing.
+ */
+ ldr r1, MISC_PLL_OFFS
+ ldr r2, =0x0 /* PLL Counter 1, 2, 3, 4 */
+swoff_pll:
+ ldr r0, [r6, r1]
+ /* Clear pll_enable bit(1) of PLL1_CTR register in Misc registers */
+ bic r0, r0, #0x02
+ str r0, [r6, r1]
+ add r1, #0xc
+ add r2, #0x1
+ cmp r2, #0x3 /* Switch off pll-1/2/3 */
+ bne swoff_pll
+
+#ifdef DDR_PLL_SREFRESH
+ /* Switch off pll-4 */
+ ldr r0, [r6, r1]
+ /* Clear pll_enable bit(2) of PLL1_CTR register in Misc registers */
+ bic r0, r0, #0x04
+ str r0, [r6, r1]
+#endif
+
+#ifdef TEST_PWRDOMAINS
+ /* Switch off the undesired PLL's */
+ nop
+ ldr r6, MISC_BASE_P
+ ldr r0, [r6, #0x200]
+ bic r0, r0, #0x7
+ orr r0, r0, #0x2
+ str r0, [r6, #0x200 ]
+wait_ack0:
+ ldr r0, [r6, #0x200]
+ and r0, r0, #0xF0000
+ cmp r0, #0xA0000
+ bne wait_ack0
+ ldr r6, MISC_BASE_P
+ ldr r0, [r6, #0x100]
+
+ /*
+ * Switch off the power domains.
+ * Clear the ack bit
+ */
+ bic r0, r0, #0xc000
+ str r0, [r6, #0x100]
+
+ bic r0, r0, #0x1000
+ str r0, [r6, #0x100]
+
+wait_ack1:
+ ldr r0, [r6, #0x100]
+ tst r0, #0x4000
+ beq wait_ack1
+
+ /* Clear the ack bit */
+ bic r0, r0, #0xc000
+ str r0, [r6, #0x100]
+
+ bic r0, r0, #0x0800
+ str r0, [r6, #0x100]
+wait_ack2:
+ ldr r0, [r6, #0x100]
+ tst r0, #0x4000
+ beq wait_ack2
+
+ /* Clear the ack bit */
+ bic r0, r0, #0xc000
+ str r0, [r6, #0x100]
+
+ bic r0, r0, #0x2400
+ str r0, [r6, #0x100]
+wait_ack3:
+ ldr r0, [r6, #0x100]
+ tst r0, #0x4000
+ beq wait_ack3
+#endif
+ wfi @ wait for interrupt
+ nop
+spear_sleep_restore:
+ /*
+ * Reenable the switched off pll's. The Pll's are
+ * enabled using loop count of 4 to activalte all the
+ * pll-1/2/3/4.
+ * The strobing is done for pll-4 only.
+ */
+
+ ldr r6, MISC_BASE_P
+ ldr r1, MISC_PLL_OFFS
+ ldr r2, =0x0 /* PLL Counter 1, 2, 3, 4 */
+swon_pll_1_3:
+ /* Switch on Pll-1/2/3 */
+ ldr r0, [r6, r1]
+ orr r0, r0, #0x2
+ str r0, [r6, r1]
+pll_lock_1_3:
+ /* Set the pll_lock bit(0) in PLLX_CTR register in misc space*/
+ ldr r5, [r6, r1]
+ and r5, r5, #0x1
+ /* Wait for pll lock status */
+ cmp r5, #0x1
+ bne pll_lock_1_3
+
+ /* Loop for all the pll's */
+ add r1, #0xc
+ add r2, #0x1
+ cmp r2, #0x3 /* Switch on till pll-3 */
+ bne swon_pll_1_3
+
+#ifdef DDR_PLL_SREFRESH
+ /* Switch on PLL-4, strobe the pll also */
+ ldr r0, [r6, r1]
+ ldr r0, PLL_VAL1
+ str r0, [r6, r1]
+ ldr r0, PLL_VAL2
+ str r0, [r6, r1]
+ ldr r0, PLL_VAL3
+ str r0, [r6, r1]
+ ldr r0, PLL_VAL2
+ str r0, [r6, r1]
+pll_lock_4:
+ /* Set the pll_lock bit(0) in PLLX_CTR register in misc space*/
+ ldr r5, [r6, r1]
+ and r5, r5, #0x1
+ /* Wait for pll lock status */
+ cmp r5, #0x1
+ bne pll_lock_4
+#endif
+
+ /* Put the system in normal mode */
+ ldr r0, [r6, #0x200]
+ bic r0, r0, #0x7
+ /* Set the apt mode bits(2:0) in SCCTRL register */
+ orr r0, r0, #0x4
+ str r0, [r6, #0x200] /* System is now in slow mode */
+wait_till_normal_mode:
+ ldr r0, [r6, #0x200]
+ /* Wait for the mode to be updated */
+ and r0, r0, #0xF0000
+ /* Poll the SCCTRL register status bits (6:3) */
+ cmp r0, #0xf0000
+ bne wait_till_normal_mode
+
+ /*
+ * Invalidate all instruction caches to PoU
+ * and flush branch target cache
+ */
+ mov r1, #0
+ mcr p15, 0, r1, c7, c5, 0
+
+ ldr r3, SRAM_STACK_PA
+ ldmia r3!, {r4-r6}
+ mov sp, r4
+ msr spsr_cxsf, r5
+ mov lr, r6
+
+ ldmia r3!, {r4-r9}
+ /* Coprocessor access Control Register */
+ mcr p15, 0, r4, c1, c0, 2
+
+ /* TTBR0 */
+ mcr p15, 0, r5, c2, c0, 0
+ /* TTBR1 */
+ mcr p15, 0, r6, c2, c0, 1
+ /* Translation table base control register */
+ mcr p15, 0, r7, c2, c0, 2
+ /*domain access Control Register */
+ mcr p15, 0, r8, c3, c0, 0
+ /* data fault status Register */
+ mcr p15, 0, r9, c5, c0, 0
+
+ ldmia r3!, {r4-r8}
+ /* instruction fault status Register */
+ mcr p15, 0, r4, c5, c0, 1
+ /*Data Auxiliary Fault Status Register */
+ mcr p15, 0, r5, c5, c1, 0
+ /*Instruction Auxiliary Fault Status Register*/
+ mcr p15, 0, r6, c5, c1, 1
+ /*Data Fault Address Register */
+ mcr p15, 0, r7, c6, c0, 0
+ /*Instruction Fault Address Register*/
+ mcr p15, 0, r8, c6, c0, 2
+ ldmia r3!, {r4-r7}
+
+ /* user r/w thread and process ID */
+ mcr p15, 0, r4, c13, c0, 2
+ /* user ro thread and process ID */
+ mcr p15, 0, r5, c13, c0, 3
+ /*Privileged only thread and process ID */
+ mcr p15, 0, r6, c13, c0, 4
+ /* cache size selection */
+ mcr p15, 2, r7, c0, c0, 0
+ ldmia r3!, {r4-r8}
+ /* Data TLB lockdown registers */
+ mcr p15, 0, r4, c10, c0, 0
+ /* Instruction TLB lockdown registers */
+ mcr p15, 0, r5, c10, c0, 1
+ /* Secure or Nonsecure Vector Base Address */
+ mcr p15, 0, r6, c12, c0, 0
+ /* FCSE PID */
+ mcr p15, 0, r7, c13, c0, 0
+ /* Context PID */
+ mcr p15, 0, r8, c13, c0, 1
+
+ ldmia r3!, {r4-r5}
+ /* primary memory remap register */
+ mcr p15, 0, r4, c10, c2, 0
+ /*normal memory remap register */
+ mcr p15, 0, r5, c10, c2, 1
+
+ /* Restore cpsr */
+ ldmfd r3!, {r4} /*load CPSR from SDRAM*/
+ msr cpsr, r4 /*store cpsr */
+ dsb
+ isb
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
+ mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
+ mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
+ mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
+
+ adr r5, mmu_on
+ mov r1, #0xcfffffff
+ and r5, r5, r1
+ ldr r1, =0x30000000
+ orr r5, r5, r1
+ mov r4, r5
+
+ /* Move the DDR out of self refresh mode */
+ ldr r6, MISC_BASE_P
+ ldr r7, MPMC_BASE_P
+ /* Program MPMC Control Status register in Misc Space */
+ ldr r0, [r6, #0x334]
+ /* Clear srefresh_enter bit(2) */
+ bic r0, r0, #0x4
+ str r0, [r6, #0x334]
+ /* Additional clearance is required in the mpmc space */
+ ldr r0, [r7, #0x2c]
+ /*
+ * Clear bit srefresh bit (2) of MPMC_11 register
+ * The misc wrapper does not works fine by itself till
+ * this bit is also cleared.
+ */
+ bic r0, r0, #0x10000
+ str r0, [r7, #0x2c]
+wait_for_refresh_exit:
+ ldr r0, [r6, #0x334]
+ tst r0, #0x2000
+ bne wait_for_refresh_exit
+
+ ldmfd r3!, {r2}
+ /* restore the MMU control register from stack to enable mmu */
+ mcr p15, 0, r2, c1, c0, 0
+ bx r4
+
+mmu_on:
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
+ nop
+
+MPMC_BASE_P :
+ .word MPMC_BASE_PA
+MISC_BASE_P :
+ .word MISC_BASE_PA
+SRAM_STACK_VA :
+ .word IO_ADDRESS(SPEAR_SRAM_STACK_PA)
+SRAM_STACK_PA :
+ .word SPEAR_SRAM_STACK_PA
+DISABLE_I_C_M_V:
+ .word 0x1805
+MISC_PLL_OFFS:
+ .word 0x214
+#ifdef DDR_PLL_SREFRESH
+PLL_VAL1:
+ .word 0x060a
+PLL_VAL2:
+ .word 0x060e
+PLL_VAL3:
+ .word 0x0606
+#endif
+ENTRY(spear_sleep_mode_sz)
+ .word . - spear_sleep_mode
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 6dc3f68..8cdb37e 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -425,6 +425,11 @@ struct map_desc spear13xx_io_desc[] __initdata = {
.pfn = __phys_to_pfn(SPEAR13XX_SYSRAM0_BASE),
.length = SZ_32K,
.type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_SYSRAM1_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_SYSRAM1_BASE),
+ .length = SZ_1M,
+ .type = MT_MEMORY_NONCACHED
},
};
diff --git a/arch/arm/mach-spear3xx/include/mach/suspend.h b/arch/arm/mach-spear3xx/include/mach/suspend.h
new file mode 100644
index 0000000..a525173
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/suspend.h
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/suspend.h
+ *
+ * Sleep mode defines for SPEAr3xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * AUTHOR : Deepak Sikri <deepak.sikri@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SUSPEND_H
+#define __MACH_SUSPEND_H
+
+#include <mach/spear.h>
+
+#ifndef __ASSEMBLER__
+extern void spear_sleep_mode(suspend_state_t state);
+extern unsigned int spear_sleep_mode_sz;
+#endif
+
+/* SRAM related defines*/
+#define SRAM_STACK_SCR_OFFS 0xF00
+#define SPEAR_START_SRAM SPEAR3XX_ICM1_SRAM_BASE
+#define SPEAR_SRAM_SIZE SZ_4K
+#define SPEAR_SRAM_SCR_REG (SPEAR_START_SRAM + SRAM_STACK_SCR_OFFS)
+/* SPEAr subsystem physical addresses */
+#define SYS_CTRL_BASE_PA SPEAR3XX_ICM3_SYS_CTRL_BASE
+#define MPMC_BASE_PA SPEAR3XX_ICM3_SDRAM_CTRL_BASE
+#define MISC_BASE_PA SPEAR3XX_ICM3_MISC_REG_BASE
+
+/* ARM Modes of Operation */
+#define MODE_USR_32 0x10
+#define MODE_FIQ_32 0x11
+#define MODE_IRQ_32 0x12
+#define MODE_SVC_32 0x13
+#define MODE_ABT_32 0x17
+#define MODE_UND_32 0x1B
+#define MODE_SYS_32 0x1F
+#define MODE_BITS 0x1F
+
+#endif /* __MACH_SUSPEND_H */
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index dceb632..12285ee 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -22,6 +22,8 @@
#include <mach/generic.h>
#include <mach/spear.h>
+#define SPEAR3XX_WKUP_SRCS (1 << IRQ_MAC_1 | 1 << IRQ_USB_DEV | \
+ 1 << IRQ_BASIC_RTC | 1 << IRQ_BASIC_GPIO)
/* Add spear3xx machines common devices here */
/* gpio device registration */
static struct pl061_platform_data gpio_plat_data = {
@@ -227,7 +229,8 @@ void __init spear3xx_init(void)
/* This will initialize vic */
void __init spear3xx_init_irq(void)
{
- vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
+ vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0,
+ SPEAR3XX_WKUP_SRCS);
}
/* Following will create static virtual/physical mappings */
diff --git a/arch/arm/mach-spear6xx/include/mach/suspend.h b/arch/arm/mach-spear6xx/include/mach/suspend.h
new file mode 100644
index 0000000..e98e831
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/suspend.h
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/suspend.h
+ *
+ * Sleep mode defines for SPEAr6xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * AUTHOR : Deepak Sikri <deepak.sikri@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SUSPEND_H
+#define __MACH_SUSPEND_H
+
+#include <mach/spear.h>
+
+#ifndef __ASSEMBLER__
+extern void spear_sleep_mode(suspend_state_t state);
+extern unsigned int spear_sleep_mode_sz;
+#endif
+
+/* SRAM related defines*/
+#define SRAM_STACK_SCR_OFFS 0xF00
+#define SPEAR_START_SRAM SPEAR6XX_ICM1_SRAM_BASE
+#define SPEAR_SRAM_SIZE SZ_4K
+#define SPEAR_SRAM_SCR_REG (SPEAR_START_SRAM + SRAM_STACK_SCR_OFFS)
+/* SPEAr subsystem physical addresses */
+#define SYS_CTRL_BASE_PA SPEAR6XX_ICM3_SYS_CTRL_BASE
+#define MPMC_BASE_PA SPEAR6XX_ICM3_SDRAM_CTRL_BASE
+#define MISC_BASE_PA SPEAR6XX_ICM3_MISC_REG_BASE
+
+/* ARM Modes of Operation */
+#define MODE_USR_32 0x10
+#define MODE_FIQ_32 0x11
+#define MODE_IRQ_32 0x12
+#define MODE_SVC_32 0x13
+#define MODE_ABT_32 0x17
+#define MODE_UND_32 0x1B
+#define MODE_SYS_32 0x1F
+#define MODE_BITS 0x1F
+
+#endif /* __MACH_SUSPEND_H */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 96a3245..af588d8 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -24,6 +24,12 @@
#include <mach/generic.h>
#include <mach/spear.h>
+/* The wake sources are routed through vic-2 */
+#define SPEAR6XX_WKUP_SRCS_VIC2 (1 << (IRQ_GMAC_1 - 32) | \
+ 1 << (IRQ_USB_DEV - 32) | \
+ 1 << (IRQ_BASIC_RTC - 32) |\
+ 1 << (IRQ_BASIC_GPIO - 32))
+
/* Add spear6xx machines common devices here */
/* CLCD device registration */
@@ -381,7 +387,8 @@ void __init spear6xx_init(void)
void __init spear6xx_init_irq(void)
{
vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0);
- vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0);
+ vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0,
+ SPEAR6XX_WKUP_SRCS_VIC2);
}
/* Following will create static virtual/physical mappings */
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 6ff3eb7..4c28f01 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -6,6 +6,7 @@
obj-y := clcd.o clock.o pll_clk.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
+
obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
obj-$(CONFIG_MACH_SPEAR320) += plgpio.o
obj-$(CONFIG_SPEAR_PWM) += pwm.o
@@ -16,3 +17,8 @@ obj-$(CONFIG_BOARD_SPEAR300_EVB) += i2c_eval_board.o
obj-$(CONFIG_BOARD_SPEAR310_EVB) += i2c_eval_board.o
obj-$(CONFIG_BOARD_SPEAR320_EVB) += i2c_eval_board.o
obj-$(CONFIG_BOARD_SPEAR600_EVB) += i2c_eval_board.o
+
+ifeq ($(CONFIG_PM),y)
+obj-$(CONFIG_ARCH_SPEAR3XX) += pm.o sleep.o
+obj-$(CONFIG_ARCH_SPEAR6XX) += pm.o sleep.o
+endif
diff --git a/arch/arm/plat-spear/pm.c b/arch/arm/plat-spear/pm.c
new file mode 100644
index 0000000..0cb2d0c
--- /dev/null
+++ b/arch/arm/plat-spear/pm.c
@@ -0,0 +1,104 @@
+/*
+ * arch/arm/plat-spear/pm.c
+ *
+ * SPEAr3xx & SPEAr6xx Power Management source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Deepak Sikri <deepak.sikri@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/suspend.h>
+#include <linux/sysfs.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#include <mach/irqs.h>
+#include <mach/suspend.h>
+
+static void (*saved_idle)(void);
+static void __iomem *spear_sram_base;
+
+static int spear_pm_sleep(suspend_state_t state)
+{
+ void (*spear_sram_sleep)(suspend_state_t state) = NULL;
+
+ /* Copy the Sleep code on to the SRAM*/
+ spear_sram_sleep = memcpy((void *)spear_sram_base,
+ (void *)spear_sleep_mode, spear_sleep_mode_sz);
+ flush_cache_all();
+ /* Jump to the suspend routines in sram */
+ spear_sram_sleep(state);
+ return 0;
+}
+
+/*
+ * spear_pm_prepare - Do preliminary suspend work.
+ *
+ */
+static int spear_pm_prepare(void)
+{
+ /* We cannot sleep in idle until we have resumed */
+ saved_idle = pm_idle;
+ pm_idle = NULL;
+ return 0;
+}
+
+/*
+ * spear_pm_enter - Actually enter a sleep state.
+ * @state: State we're entering.
+ *
+ */
+static int spear_pm_enter(suspend_state_t state)
+{
+ int ret;
+
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ case PM_SUSPEND_MEM:
+ ret = spear_pm_sleep(state);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+/*
+ * spear_pm_finish - Finish up suspend sequence.
+ *
+ * This is called after we wake back up (or if entering the sleep state
+ * failed).
+ */
+static void spear_pm_finish(void)
+{
+ pm_idle = saved_idle;
+}
+
+static struct platform_suspend_ops spear_pm_ops = {
+ .prepare = spear_pm_prepare,
+ .enter = spear_pm_enter,
+ .finish = spear_pm_finish,
+ .valid = suspend_valid_only_mem,
+};
+
+static int __init spear_pm_init(void)
+{
+
+ spear_sram_base = ioremap(SPEAR_START_SRAM, SPEAR_SRAM_SIZE);
+
+ if (!spear_sram_base)
+ return -ENOMEM;
+
+ /* In case the suspend code size is more than sram size return */
+ if (spear_sleep_mode_sz > (SPEAR_SRAM_SIZE))
+ return -ENOMEM;
+
+ suspend_set_ops(&spear_pm_ops);
+ return 0;
+}
+arch_initcall(spear_pm_init);
diff --git a/arch/arm/plat-spear/sleep.S b/arch/arm/plat-spear/sleep.S
new file mode 100644
index 0000000..5347789
--- /dev/null
+++ b/arch/arm/plat-spear/sleep.S
@@ -0,0 +1,288 @@
+/*
+ * arch/arm/plat-spear/sleep.S
+ *
+ * SPEAR3xx and SPEAR6xx specific functions that will run in
+ * internal SRAM. The functions are used in power management.
+ *
+ * Copyright (ST) 2010 Deepak Sikri <deepak.sikri@.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <mach/suspend.h>
+
+.text
+ENTRY(spear_sleep_mode)
+ stmfd sp!, {r0-r12, lr}
+
+ /* Latch some of MMU registers on to stack */
+ mrc p15, 0, r0, c5, c0, 0 /* FSR--Domain Fault */
+ mrc p15, 0, r1, c5, c0, 1 /* FSR--Instruction Fault */
+ mrc p15, 0, r2, c6, c0, 0 /* FAR */
+ mrc p15, 0, r3, c9, c0, 0 /* Read Dcache Lockdown */
+ mrc p15, 0, r4, c9, c0, 1 /* Read ICache Lockdown */
+ mrc p15, 0, r5, c9, c1, 0 /* Read Data TLB */
+ mrc p15, 0, r6, c9, c1, 1 /* Read Instr TCM region register */
+
+ mrc p15, 0, r7, c10, c0, 0 /* Data TLBLock Down operation */
+ mrc p15, 0, r8, c13, c0, 0 /* FCSE--PID */
+ mrc p15, 0, r9, c13, c0, 1 /* Context-ID */
+
+ /* Save all these registers onto the stack */
+ stmfd sp!, {r0-r9}
+ /* Save the stack pointer */
+ mov r3, sp
+ /* Store the two mode registers */
+ stmfd r3!, {sp, lr}
+ /* Save the current mode with irq disabled */
+ mrs r0, cpsr
+ stmfd r3!, {r0}
+ /*
+ * Save the MMU registers on the SRAM Stack
+ * Domain Register on Back-up RAM structure
+ */
+ mrc p15, 0, r2, c3, c0, 0
+ /* TTB Register */
+ mrc p15, 0, r1, c2, c0, 0
+ /* MMU Enable Register */
+ mrc p15, 0, r0, c1, c0, 0
+ stmfd r3!, {r0, r1, r2}
+ /*
+ * Capture the Physical Address.
+ * This will be used once MMU is Off
+ */
+ adr r0, mmu_off
+ adr r1, spear_sleep_mode
+ /* Store the virtual address on to DDR */
+ stmfd r3!, {r1}
+ sub r1, r0, r1
+ ldr r0, SRAM_START_P
+ add r2, r1, r0
+
+ /* Disable MMU */
+ mrc p15, 0, r0, c1, c0, 0
+ ldr r1, DISABLE_I_C_M_V
+ bic r0, r0, r1
+ mcr p15, 0, r0, c1, c0, 0
+ /* Move the Physical address into PC */
+ bx r2
+
+ /*
+ * This portion of code is executed from SRAM
+ * post MMU has been turned off
+ */
+mmu_off:
+ /* Store the DDR stack address onto scratch pad location */
+ ldr r0, SCRATCH_PAD
+ str r3, [r0]
+
+ ldr r6, MISC_BASE_P
+ ldr r7, MPMC_BASE_P
+ ldr r8, SYS_CTRL_BASE_P
+
+ /*
+ * Put SDRAM in self-refresh mode
+ * Clear START bit(24) of MEMCTL_GP_03 register in MPMC
+ */
+ ldr r0, [r7, #0x1c]
+ ldr r4, =0x1000000
+ /* Begin the command processing in controller */
+ bic r0, r0, r4
+ str r0, [r7, #0x1c]
+ ldr r0, [r7, #0x1c]
+ /* set the SREFRESH bit(16) */
+ ldr r4, =0x10000
+ orr r0, r0, r4
+ str r0, [r7, #0x1c]
+
+ /* Put the DDR into low power mode */
+ ldr r0, [r6, #0xf0]
+ ldr r4, =0x00000001
+ /* Clear DDR_LOW_POWER_DDR2_MODE bit(1) of DDR_PAD register */
+ bic r0, r0, r4
+ str r0, [r6, #0xf0]
+
+ /* Put the system in slow mode, use system controller */
+ ldr r0, [r8]
+ bic r0, r0, #0x4
+ /* Set the apt mode bits(2:0) in SCCTRL register */
+ orr r0, r0, #0x2
+ str r0, [r8] /* System is now in slow mode */
+
+wait_till_slow_mode:
+ ldr r0, [r8]
+ and r0, r0, #0x78 /* Wait for the mode to be updated */
+ cmp r0, #0x10 /* Poll the SCCTRL register status bits (6:3) */
+ bne wait_till_slow_mode
+
+ /* Put the Pll-1 to off. */
+ ldr r0, [r6, #0x08]
+ /* Clear pll_enable bit(2) of PLL1_CTR register in Misc registers */
+ bic r0, r0, #0x04
+ str r0, [r6, #0x08]
+
+ /* Put the Pll-2 to off */
+ ldr r0, [r6, #0x14]
+ /* Clear pll_enable bit(2) of PLL2_CTR register in Misc registers */
+ bic r0, r0, #0x04
+ str r0, [r6, #0x14]
+ mov r2, #0
+ /* Put the system in sleep */
+ ldr r0, [r8]
+ /* Set the apt mode bits(2:0) in SCCTRL register */
+ bic r0, r0, #0x7
+#ifdef TEST_SLOW
+ orr r0, r0, #0x2 /* Slow Mode */
+#endif
+ str r0, [r8]
+ /* Put system in WFI */
+ mcr p15, 0, r2, c7, c0, 4
+wakeup_addr:
+ ldr r6, MISC_BASE_P
+ ldr r7, MPMC_BASE_P
+ ldr r8, SYS_CTRL_BASE_P
+ /* Reenable pll1 and pll2 */
+ ldr r0, PLL_VAL1
+ str r0, [r6, #0x08]
+ str r0, [r6, #0x14]
+ ldr r0, PLL_VAL2
+ str r0, [r6, #0x08]
+ str r0, [r6, #0x14]
+ /* Strobe */
+ ldr r2, PLL_VAL3
+ str r2, [r6, #0x08]
+ str r2, [r6, #0x14]
+ ldr r2, PLL_VAL2
+ str r2, [r6, #0x08]
+ str r2, [r6, #0x14]
+pll1_lock_1:
+ /* Set the pll_lock bit(0) in PLL1_CTR register in misc space*/
+ ldr r2, [r6, #0x08]
+ and r2, r2, #0x1
+ /* Wait for pll-1 lock status */
+ cmp r2, #0x1
+ bne pll1_lock_1
+
+pll2_lock_2:
+ /* Set the pll_lock bit(0) in PLL2_CTR register in misc space*/
+ ldr r2, [r6, #0x14]
+ and r2, r2, #0x1
+ /* Wait for pll-2 lock status */
+ cmp r2, #0x1
+ bne pll2_lock_2
+
+ /* Move the system in Normal mode, use system controller */
+ ldr r3, [r8]
+ /* Set the apt mode bits(2:0) in SCCTRL register */
+ bic r3, r3, #0x7
+ orr r3, r3, #0x4
+ str r3, [r8]
+
+wait_till_norm_mode:
+ ldr r3, [r8]
+ and r3, r3, #0x78
+ cmp r3, #0x20 /* Poll the SCCTRL register status bits (6:3) */
+ bne wait_till_norm_mode
+
+ /* Resume the DDR from Low power mode. */
+ ldr r0, [r6, #0xf0]
+ /* Set DDR_LOW_POWER_DDR2_MODE bit(1) of DDR_PAD register */
+ orr r0, r0, #0x01
+ str r0, [r6, #0xf0]
+
+ /* Exit DDR-SDRAM from self-refresh mode */
+ ldr r1, [r7, #0x1c]
+ /* clear the SREFRESH bit(16) */
+ ldr r4, =0x10000
+ bic r1, r1, r4
+ str r1, [r7, #0x1c]
+
+ /* Begin the command processing in controller */
+ ldr r4, =0x1000000
+ /* Set START bit(24) of MEMCTL_GP_03 register in MPMC*/
+ orr r1, r1, r4
+ str r1, [r7, #0x1c]
+
+ mov r0, r0
+ /* Start the Restore Processing */
+ ldr r0, SCRATCH_PAD
+ ldr r6, [r0]
+
+ /* Restore the Virtual Address to be used */
+ /* Once MMU is made on */
+ ldr r0, SRAM_START_P
+ adr r1, mmu_on
+ sub r0, r1, r0
+ /* Get the physical Address */
+ mov r3, #0xc0000000
+ sub r6, r6, r3
+ /* Fetch the sram virtual address */
+ ldmfd r6!, {r1}
+ add r4, r1, r0
+
+ /* Fetch the MMU Related information latched on SDRAM */
+ ldmfd r6!, {r0, r1, r2}
+ /* Enable the MMU */
+ mcr p15, 0, r2, c3, c0, 0
+ mcr p15, 0, r1, c2, c0, 0
+ mcr p15, 0, r0, c1, c0, 0
+ bx r4
+mmu_on:
+ add r6, r6, r3
+ /* Store the value of cpsr in R0 */
+ mrs r0, cpsr
+ bic r0, r0, #MODE_BITS
+
+ /* Here we will restore our cpsr IRQ/FIQ Disabled */
+ ldr r0, [r6]
+ msr cpsr_cxsf, r0
+ add r6, r6, #4
+
+ /* Now only two user-mode registers are left */
+ ldmfd r6!, {sp, lr}
+ mov r0, r0
+
+ /* Restore stack pointer for the current mode */
+ mov sp, r6
+
+ ldmfd sp!, {r0-r9}
+ mcr p15, 0, r0, c5, c0, 0 /* FSR--Domain Fault */
+ mcr p15, 0, r1, c5, c0, 1 /* FSR--Instruction Fault */
+ mcr p15, 0, r2, c6, c0, 0 /* FAR */
+ mcr p15, 0, r3, c9, c0, 0 /* Read Dcache Lockdown */
+ mcr p15, 0, r4, c9, c0, 1 /* Read ICache Lockdown */
+ mcr p15, 0, r5, c9, c1, 0 /* Read Data TLB */
+ mcr p15, 0, r6, c9, c1, 1 /* Read Instruction Lockdown */
+
+ mcr p15, 0, r7, c10, c0, 0 /* Data TLB LockDown operation */
+ mcr p15, 0, r8, c13, c0, 0 /* FCSE--PID */
+ mcr p15, 0, r9, c13, c0, 1 /* Context-ID */
+
+ mov r0, #0
+ ldmfd sp!, {r0-r12, pc}
+
+SYS_CTRL_BASE_P :
+ .word SYS_CTRL_BASE_PA
+MPMC_BASE_P :
+ .word MPMC_BASE_PA
+MISC_BASE_P :
+ .word MISC_BASE_PA
+SRAM_START_P:
+ .word SPEAR_START_SRAM
+SCRATCH_PAD:
+ .word SPEAR_SRAM_SCR_REG
+DISABLE_I_C_M_V:
+ .word 0x1005
+PLL_VAL1:
+ .word 0x1c0a
+PLL_VAL2:
+ .word 0x1c0e
+PLL_VAL3:
+ .word 0x1c06
+ENTRY(spear_sleep_mode_sz)
+ .word . - spear_sleep_mode
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (35 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 37/62] SPEAr Power Management: Added the support for Standby mode Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-19 0:20 ` Jamie Iles
2011-01-18 7:12 ` [PATCH V4 39/62] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms Viresh Kumar
` (24 subsequent siblings)
61 siblings, 1 reply; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-spear13xx/clock.c | 7 +-
arch/arm/mach-spear3xx/clock.c | 5 +-
arch/arm/mach-spear6xx/clock.c | 5 +-
arch/arm/plat-spear/Makefile | 2 +-
arch/arm/plat-spear/cpufreq.c | 159 +++++++++++++++++++++++++++++++++++++++
6 files changed, 171 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/plat-spear/cpufreq.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 957d320..11501de 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -872,6 +872,7 @@ config PLAT_SPEAR
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select HAVE_CLK
+ select ARCH_HAS_CPUFREQ
help
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
index 709adb2..a7e75ca 100644
--- a/arch/arm/mach-spear13xx/clock.c
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -91,6 +91,7 @@ static struct pll_clk_config pll1_config = {
/* pll rate configuration table, in ascending order of rates */
struct pll_rate_tbl pll_rtbl[] = {
/* PCLK 24MHz */
+ {.mode = 0, .m = 0x64, .n = 0x03, .p = 0x2}, /* 400 MHz */
{.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
{.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
{.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
@@ -107,7 +108,7 @@ static struct clk pll1_clk = {
.calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
.set_rate = &pll_clk_set_rate,
- .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 4},
.private_data = &pll1_config,
};
@@ -144,7 +145,7 @@ static struct clk pll2_clk = {
.calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
.set_rate = &pll_clk_set_rate,
- .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 4},
.private_data = &pll2_config,
};
@@ -165,7 +166,7 @@ static struct clk pll3_clk = {
.calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
.set_rate = &pll_clk_set_rate,
- .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 4},
.private_data = &pll3_config,
};
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 58f0259..37faef1 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -55,6 +55,7 @@ static struct pll_clk_masks pll_masks = {
/* pll rate configuration table, in ascending order of rates */
struct pll_rate_tbl pll_rtbl[] = {
+ {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* 166 MHz */
{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
};
@@ -75,7 +76,7 @@ static struct clk pll1_clk = {
.calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
.set_rate = &pll_clk_set_rate,
- .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 2},
.private_data = &pll1_config,
};
@@ -95,7 +96,7 @@ static struct clk pll2_clk = {
.calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
.set_rate = &pll_clk_set_rate,
- .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 2},
.private_data = &pll2_config,
};
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 99cc21d..0a38e16 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -55,6 +55,7 @@ static struct pll_clk_masks pll_masks = {
/* pll rate configuration table, in ascending order of rates */
struct pll_rate_tbl pll_rtbl[] = {
+ {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* 166 MHz */
{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
};
@@ -75,7 +76,7 @@ static struct clk pll1_clk = {
.calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
.set_rate = &pll_clk_set_rate,
- .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 2},
.private_data = &pll1_config,
};
@@ -95,7 +96,7 @@ static struct clk pll2_clk = {
.calc_rate = &pll_calc_rate,
.recalc = &pll_clk_recalc,
.set_rate = &pll_clk_set_rate,
- .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 2},
.private_data = &pll2_config,
};
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 4c28f01..ec85b82 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -6,7 +6,7 @@
obj-y := clcd.o clock.o pll_clk.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
-
+obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
obj-$(CONFIG_MACH_SPEAR320) += plgpio.o
obj-$(CONFIG_SPEAR_PWM) += pwm.o
diff --git a/arch/arm/plat-spear/cpufreq.c b/arch/arm/plat-spear/cpufreq.c
new file mode 100644
index 0000000..9384d65
--- /dev/null
+++ b/arch/arm/plat-spear/cpufreq.c
@@ -0,0 +1,159 @@
+/*
+ * arch/arm/plat-spear/cpufreq.c
+ *
+ * CPU Frequency Scaling for SPEAr platform
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Deepak Sikri<deepak.sikri@st.com>
+ *
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <asm/system.h>
+#include <mach/hardware.h>
+
+#define CPU_CLK "cpu_clk"
+
+#ifdef CONFIG_ARCH_SPEAR13XX
+#define MIN_CPU_FREQ 200000
+#define MAX_CPU_FREQ 500000
+
+static u32 spear_cpu_freq[] = {
+ 200000, /* 200 MHZ */
+ 250000, /* 250 MHZ */
+ 332000, /* 332 MHZ */
+ 400000, /* 400 MHZ */
+ 500000, /* 500 MHZ */
+};
+#elif defined(CONFIG_ARCH_SPEAR6XX) || defined(CONFIG_ARCH_SPEAR3XX)
+#define MIN_CPU_FREQ 166000
+#define MAX_CPU_FREQ 332000
+
+static u32 spear_cpu_freq[] = {
+ 166000, /* 166 MHZ */
+ 266000, /* 266 MHZ */
+ 332000, /* 333 MHZ */
+};
+#endif
+
+static struct
+ cpufreq_frequency_table spear_freq_tbl[ARRAY_SIZE(spear_cpu_freq) + 1];
+static struct clk *cpu_clk;
+
+int spear_cpufreq_verify(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, spear_freq_tbl);
+}
+
+unsigned int spear_cpufreq_get(unsigned int cpu)
+{
+ unsigned long rate;
+
+ if (cpu)
+ return 0;
+
+ rate = clk_get_rate(cpu_clk) / 1000;
+ return rate;
+}
+
+static int spear_cpufreq_target(struct cpufreq_policy *policy,
+ unsigned int target_freq, unsigned int relation)
+{
+ struct cpufreq_freqs freqs;
+ int ret = 0;
+ int index;
+
+ if (policy->cpu != 0)
+ return -EINVAL;
+
+ if (cpufreq_frequency_table_target(policy, spear_freq_tbl,
+ target_freq, relation, &index))
+ return -EINVAL;
+
+ freqs.old = spear_cpufreq_get(0);
+ freqs.new = spear_cpu_freq[index];
+ freqs.cpu = policy->cpu;
+
+ if (freqs.old == target_freq)
+ return 0;
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+ ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+ return ret;
+}
+
+static int spear_cpufreq_init(struct cpufreq_policy *policy)
+{
+ int result;
+ int i = 0;
+
+ if (policy->cpu != 0)
+ return -EINVAL;
+
+ cpu_clk = clk_get(NULL, CPU_CLK);
+ if (IS_ERR(cpu_clk))
+ return PTR_ERR(cpu_clk);
+
+ policy->cpuinfo.min_freq = MIN_CPU_FREQ;
+ policy->cpuinfo.max_freq = MAX_CPU_FREQ;
+ policy->cur = policy->min = policy->max = spear_cpufreq_get(0);
+
+ for (i = 0; i < ARRAY_SIZE(spear_cpu_freq); i++) {
+ spear_freq_tbl[i].index = i;
+ spear_freq_tbl[i].frequency = spear_cpu_freq[i];
+ }
+
+ spear_freq_tbl[i].index = i;
+ spear_freq_tbl[i].frequency = CPUFREQ_TABLE_END;
+ result = cpufreq_frequency_table_cpuinfo(policy, spear_freq_tbl);
+ if (!result)
+ cpufreq_frequency_table_get_attr(spear_freq_tbl,
+ policy->cpu);
+
+ policy->cpuinfo.transition_latency = 300*1000; /*250 uS*/
+
+ return 0;
+}
+
+static int spear_cpufreq_exit(struct cpufreq_policy *policy)
+{
+ clk_put(cpu_clk);
+ return 0;
+}
+
+static struct freq_attr *spear_cpufreq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+static struct cpufreq_driver spear_driver = {
+ .flags = CPUFREQ_STICKY,
+ .verify = spear_cpufreq_verify,
+ .target = spear_cpufreq_target,
+ .get = spear_cpufreq_get,
+ .init = spear_cpufreq_init,
+ .exit = spear_cpufreq_exit,
+ .name = "spear_cpufreq",
+ .attr = spear_cpufreq_attr,
+};
+
+static int __init spear_cpufreq_register(void)
+{
+ return cpufreq_register_driver(&spear_driver);
+}
+
+arch_initcall(spear_cpufreq_register);
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 39/62] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (36 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 40/62] ST SPEAr: replace readl, writel with readl_relaxed, writel_relaxed in uncompress.h Viresh Kumar
` (23 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/Makefile | 1 +
arch/arm/mach-spear13xx/hotplug.c | 121 +++++++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/hotplug.c
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index 0611278..42d378e 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -5,6 +5,7 @@
# common files
obj-y += spear13xx.o clock.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
obj-$(CONFIG_PCIEPORTBUS) += pcie.o
obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
new file mode 100644
index 0000000..ee6b06d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -0,0 +1,121 @@
+/*
+ * linux/arch/arm/mach-spear13xx/hotplug.c
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Deepak Sikri <deepak.sikri@st.com>
+ *
+ * based upon linux/arch/arm/mach-realview/hotplug.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/system.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+ unsigned int v;
+
+ flush_cache_all();
+ asm volatile(
+ " mcr p15, 0, %1, c7, c5, 0\n"
+ " dsb\n"
+ /*
+ * Turn off coherency
+ */
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, #0x20\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v)
+ : "r" (0), "Ir" (CR_C)
+ : "cc", "memory");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+ unsigned int v;
+
+ asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, %1\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, #0x20\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v)
+ : "Ir" (CR_C)
+ : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+ for (;;) {
+ wfi();
+
+ if (pen_release == cpu) {
+ /*
+ * OK, proper wakeup, we're done
+ */
+ break;
+ }
+
+ /*
+ * Getting here, means that we have come out of WFI without
+ * having been woken up - this shouldn't happen
+ *
+ * Just note it happening - when we're woken, we can report
+ * its occurrence.
+ */
+ (*spurious)++;
+ }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+ return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __cpuinit platform_cpu_die(unsigned int cpu)
+{
+ int spurious = 0;
+
+ /*
+ * we're ready for shutdown now, so do it
+ */
+ cpu_enter_lowpower();
+ platform_do_lowpower(cpu, &spurious);
+
+ /*
+ * bring this CPU back into the world of cache
+ * coherency, and then restore interrupts
+ */
+ cpu_leave_lowpower();
+
+ if (spurious)
+ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+ /*
+ * we don't allow CPU 0 to be shutdown (it is still too special
+ * e.g. clock tick interrupts)
+ */
+ return cpu == 0 ? -EPERM : 0;
+}
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 40/62] ST SPEAr: replace readl, writel with readl_relaxed, writel_relaxed in uncompress.h
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (37 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 39/62] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 41/62] ST SPEAr13xx: add L2 cache support Viresh Kumar
` (22 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
readl also calls outer cache maintainance operations which are not available
during Linux uncompression. This patch replaces readl, writel with readl_relaxed
and writel_relaxed.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/plat-spear/include/plat/uncompress.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 99ba678..6dd455b 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -24,10 +24,10 @@ static inline void putc(int c)
{
void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE;
- while (readl(base + UART01x_FR) & UART01x_FR_TXFF)
+ while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF)
barrier();
- writel(c, base + UART01x_DR);
+ writel_relaxed(c, base + UART01x_DR);
}
static inline void flush(void)
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 41/62] ST SPEAr13xx: add L2 cache support
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (38 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 40/62] ST SPEAr: replace readl, writel with readl_relaxed, writel_relaxed in uncompress.h Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 42/62] ST SPEAr13xx: Modified static mappings Viresh Kumar
` (21 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/spear13xx.c | 19 +++++++++++++++++++
arch/arm/mm/Kconfig | 2 +-
2 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 8cdb37e..b6936c5 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -21,6 +21,7 @@
#include <asm/irq.h>
#include <asm/localtimer.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_twd.h>
#include <mach/irqs.h>
#include <mach/generic.h>
@@ -393,6 +394,17 @@ struct platform_device spear13xx_sdhci_device = {
/* Do spear13xx familiy common initialization part here */
void __init spear13xx_init(void)
{
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * 512KB (64KB/way), 8-way associativity, parity supported
+ *
+ * TODO: 0x249, picked from nomadik, to be analyzed
+ * Comment from nomadik:
+ * At full speed latency must be >=2, so 0x249 in low bits
+ */
+ l2x0_init(__io_address(SPEAR13XX_L2CC_BASE), 0x00260249, 0xfe00ffff);
+#endif
+
sdhci_enable();
}
@@ -415,6 +427,13 @@ struct map_desc spear13xx_io_desc[] __initdata = {
.pfn = __phys_to_pfn(SPEAR13XX_A9SM_PERIP_BASE),
.length = SZ_8K,
.type = MT_DEVICE
+#ifdef CONFIG_CACHE_L2X0
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_L2CC_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_L2CC_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+#endif
}, {
.virtual = IO_ADDRESS(SPEAR13XX_MISC_BASE),
.pfn = __phys_to_pfn(SPEAR13XX_MISC_BASE),
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9d30c6f..d4d967b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -813,7 +813,7 @@ config CACHE_L2X0
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+ ARCH_SPEAR13XX || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
default y
select OUTER_CACHE
select OUTER_CACHE_SYNC
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 42/62] ST SPEAr13xx: Modified static mappings
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (39 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 41/62] ST SPEAr13xx: add L2 cache support Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 43/62] SPEAr1310: Adding Static Mapping for RAS Area Viresh Kumar
` (20 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
The new static io mappings map regions in 0xE...,.... space to
0xF...,.... and those in space 0x6...,.... to 0xE...,.... range.
This is done to accomodate regions of RAS configuration registers to be
used by clock frameowrk and possibly others.
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/hardware.h | 7 ++++++-
arch/arm/mach-spear13xx/include/mach/vmalloc.h | 2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
index 4abc2c0..44cd0c2 100644
--- a/arch/arm/mach-spear13xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -17,7 +17,12 @@
#include <mach/spear.h>
/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x) (x | 0xF0000000)
+/*
+ * if phy_addr is 0x8...,.... and above then map it to 0xF...,....
+ * else map it to 0xE...,....
+ */
+
+#define IO_ADDRESS(x) ((x) | ((((x) >> 31) << 28) | 0xE0000000))
/* typesafe io address */
#define __io_address(n) __io(IO_ADDRESS(n))
diff --git a/arch/arm/mach-spear13xx/include/mach/vmalloc.h b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
index 85ad57e..0f243af 100644
--- a/arch/arm/mach-spear13xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
@@ -13,6 +13,6 @@
#ifndef __MACH_VMALLOC_H
#define __MACH_VMALLOC_H
-#include <plat/vmalloc.h>
+#define VMALLOC_END 0xEC800000UL
#endif /* __MACH_VMALLOC_H */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 43/62] SPEAr1310: Adding Static Mapping for RAS Area
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (40 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 42/62] ST SPEAr13xx: Modified static mappings Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 44/62] SPEAr: Adding and Updating Clock definitions Viresh Kumar
` (19 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds static mapping for RAS area in SPEAr1310.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 1 +
arch/arm/mach-spear13xx/spear1310.c | 17 +++++++++++++++++
arch/arm/mach-spear13xx/spear1310_evb.c | 2 +-
3 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 6b249b5..20a7fb4 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -68,6 +68,7 @@ extern struct platform_device spear1310_can1_device;
/* Add spear1310 machine function declarations here */
void __init spear1310_init(void);
+void __init spear1310_map_io(void);
#endif /* CONFIG_MACH_SPEAR1310 */
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 561f68b..9e2036d 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -55,6 +55,23 @@ struct platform_device spear1310_can1_device = {
.resource = can1_resources,
};
+/* Following will create 1310 specific static virtual/physical mappings */
+struct map_desc spear1310_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(SPEAR1310_RAS_BASE),
+ .pfn = __phys_to_pfn(SPEAR1310_RAS_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear1310_map_io(void)
+{
+ spear13xx_map_io();
+ iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
+}
+
void __init spear1310_init(void)
{
/* call spear13xx family common init function */
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
index 1270b4d..010eab4 100644
--- a/arch/arm/mach-spear13xx/spear1310_evb.c
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -126,7 +126,7 @@ static void __init spear1310_evb_init(void)
MACHINE_START(SPEAR1310, "ST-SPEAR1310-EVB")
.boot_params = 0x00000100,
- .map_io = spear13xx_map_io,
+ .map_io = spear1310_map_io,
.init_irq = spear13xx_init_irq,
.timer = &spear13xx_timer,
.init_machine = spear1310_evb_init,
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 44/62] SPEAr: Adding and Updating Clock definitions
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (41 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 43/62] SPEAr1310: Adding Static Mapping for RAS Area Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 45/62] SPEAr : Pad multiplexing handling modified Viresh Kumar
` (18 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/clock.c | 210 ++++++++++++++++++++-
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 19 ++
arch/arm/mach-spear3xx/clock.c | 6 +-
arch/arm/mach-spear6xx/clock.c | 4 +-
4 files changed, 224 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
index a7e75ca..43e1bf1 100644
--- a/arch/arm/mach-spear13xx/clock.c
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -355,6 +355,7 @@ static struct aux_clk_config uart_synth_config = {
/* aux rate configuration table, in ascending order of rates */
struct aux_rate_tbl aux_rtbl[] = {
/* For PLL1div2 = 500 MHz */
+ {.xscale = 2, .yscale = 21, .eq = 1}, /* 48 MHz */
{.xscale = 1, .yscale = 6, .eq = 1}, /* 83 MHz */
{.xscale = 1, .yscale = 4, .eq = 1}, /* 125 MHz */
{.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
@@ -369,7 +370,7 @@ static struct clk uart_synth_clk = {
.calc_rate = &aux_calc_rate,
.recalc = &aux_clk_recalc,
.set_rate = &aux_clk_set_rate,
- .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
.private_data = &uart_synth_config,
};
@@ -415,7 +416,7 @@ static struct clk sdhci_synth_clk = {
.calc_rate = &aux_calc_rate,
.recalc = &aux_clk_recalc,
.set_rate = &aux_clk_set_rate,
- .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
.private_data = &sdhci_synth_config,
};
@@ -441,7 +442,7 @@ static struct clk cfxd_synth_clk = {
.calc_rate = &aux_calc_rate,
.recalc = &aux_clk_recalc,
.set_rate = &aux_clk_set_rate,
- .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
.private_data = &cfxd_synth_config,
};
@@ -467,7 +468,7 @@ static struct clk c3_synth_clk = {
.calc_rate = &aux_calc_rate,
.recalc = &aux_clk_recalc,
.set_rate = &aux_clk_set_rate,
- .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
.private_data = &c3_synth_config,
};
@@ -579,7 +580,7 @@ static struct pclk_sel gmac_phy_pclk_sel = {
};
/* gmac phy clock */
-static struct clk gmac_phy_clk = {
+static struct clk gmac_phy0_clk = {
.flags = ALWAYS_ENABLED,
.pclk_sel = &gmac_phy_pclk_sel,
.pclk_sel_shift = GMAC_PHY_CLK_SHIFT,
@@ -697,8 +698,8 @@ static struct clk jpeg_clk = {
.recalc = &follow_parent,
};
-/* gmac clock */
-static struct clk gmac_clk = {
+/* gmac clock :Fixed Part*/
+static struct clk gmac0_clk = {
.pclk = &ahb_clk,
.en_reg = PERIP1_CLK_ENB,
.en_reg_bit = GMAC_CLK_ENB,
@@ -839,6 +840,92 @@ static struct clk kbd_clk = {
.recalc = &follow_parent,
};
+/* RAS CLOCKS */
+/* pll3 generated clock */
+static struct clk ras_pll3_clk = {
+ .pclk = &pll3_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PLL3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* pll2 generated clock */
+static struct clk ras_pll2_clk = {
+ .pclk = &pll2_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PLL2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* 125MHz clock generated on Tx pad */
+static struct clk ras_tx125_clk = {
+ .pclk = &gmii_txclk125_pad,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C125_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* 30 MHz clock generated by USB PHy Pll */
+static struct clk ras_30Mhz_clk = {
+ .rate = 30000000,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C30_CLK_ENB,
+};
+
+/* 48 MHz clock generated by USB PHy Pll */
+static struct clk ras_48Mhz_clk = {
+ .pclk = &pll5_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C48_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc3 generated clock */
+static struct clk ras_osc3_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc2 generated clock */
+static struct clk ras_osc2_clk = {
+ .pclk = &osc2_32k_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc1 generated clock */
+static struct clk ras_osc1_clk = {
+ .pclk = &osc1_24m_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* apb generated clock */
+static struct clk ras_pclk_clk = {
+ .pclk = &apb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PCLK_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ahb generated clock */
+static struct clk ras_aclk_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = ACLK_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* External pad 50 MHz clock for phy operation */
+static struct clk ras_tx50_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 50000000,
+};
+
/* spear1300 machine specific clock structures */
#ifdef CONFIG_MACH_SPEAR1300
@@ -859,10 +946,92 @@ static struct clk can1_clk = {
.pclk = &apb_clk,
.recalc = &follow_parent,
};
+
+/* gmac clocks :RAS part*/
+static struct clk gmac_ras1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* phy clock parent select */
+static struct pclk_info phy_pclk_info[] = {
+ {
+ .pclk = &ras_pll2_clk,
+ .pclk_val = 0x8,
+ }, {
+ .pclk = &ras_tx125_clk,
+ .pclk_val = 0x4,
+ }, {
+ .pclk = &ras_tx50_clk,
+ .pclk_val = 0x0,
+ },
+};
+
+static struct pclk_sel phy_pclk_sel = {
+ .pclk_info = phy_pclk_info,
+ .pclk_count = ARRAY_SIZE(phy_pclk_info),
+ .pclk_sel_reg = (unsigned int *)(IO_ADDRESS(SPEAR1310_RAS_CTRL_REG1)),
+ .pclk_sel_mask = SPEAR1310_PHY_CLK_MASK,
+};
+
+/* Phy 1 Clock */
+struct clk gmac_phy1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 2 Clock */
+static struct clk gmac_phy2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 3 Clock */
+static struct clk gmac_phy3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 4 Clock */
+static struct clk gmac_phy4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
#endif
+static struct clk dummy_apb_pclk;
+
/* array of all spear 13xx clock lookups */
static struct clk_lookup spear_clk_lookups[] = {
+ { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
/* root clks */
{.con_id = "osc1_24m_clk", .clk = &osc1_24m_clk},
{.con_id = "osc2_32k_clk", .clk = &osc2_32k_clk},
@@ -896,7 +1065,20 @@ static struct clk_lookup spear_clk_lookups[] = {
{.con_id = "cfxd_synth_clk", .clk = &cfxd_synth_clk},
{.con_id = "gmac_phy_input_clk", .clk = &gmac_phy_input_clk},
{.con_id = "gmac_phy_synth_clk", .clk = &gmac_phy_synth_clk},
- {.con_id = "gmac_phy_clk", .clk = &gmac_phy_clk},
+ {.dev_id = "stmmacphy.0", .clk = &gmac_phy0_clk},
+
+ /* RAS clocks */
+ {.con_id = "ras_pll3_clk", .clk = &ras_pll3_clk},
+ {.con_id = "ras_pll2_clk", .clk = &ras_pll2_clk},
+ {.con_id = "ras_tx125_clk", .clk = &ras_tx125_clk},
+ {.con_id = "ras_30Mhz_clk", .clk = &ras_30Mhz_clk},
+ {.con_id = "ras_48Mhz_clk", .clk = &ras_48Mhz_clk},
+ {.con_id = "ras_osc3_clk", .clk = &ras_osc3_clk},
+ {.con_id = "ras_osc2_clk", .clk = &ras_osc2_clk},
+ {.con_id = "ras_osc1_clk", .clk = &ras_osc1_clk},
+ {.con_id = "ras_pclk_clk", .clk = &ras_pclk_clk},
+ {.con_id = "ras_aclk_clk", .clk = &ras_aclk_clk},
+ {.con_id = "ras_tx50_clk", .clk = &ras_tx50_clk},
/* clocks having multiple parent source from above clocks */
{.dev_id = "clcd", .clk = &clcd_clk},
@@ -910,12 +1092,12 @@ static struct clk_lookup spear_clk_lookups[] = {
{.dev_id = "smi", .clk = &smi_clk},
{.con_id = "usbh.0_clk", .clk = &uhci0_clk},
{.con_id = "usbh.1_clk", .clk = &uhci1_clk},
- {.dev_id = "usbd", .clk = &usbd_clk},
+ {.dev_id = "designware_udc", .clk = &usbd_clk},
{.dev_id = "i2c_designware.0", .clk = &i2c_clk},
{.dev_id = "dma0", .clk = &dma0_clk},
{.dev_id = "dma1", .clk = &dma1_clk},
{.dev_id = "jpeg", .clk = &jpeg_clk},
- {.dev_id = "gmac", .clk = &gmac_clk},
+ {.dev_id = "stmmaceth.0", .clk = &gmac0_clk},
{.dev_id = "c3", .clk = &c3_clk},
{.dev_id = "pcie0", .clk = &pcie0_clk},
{.dev_id = "pcie1", .clk = &pcie1_clk},
@@ -944,6 +1126,14 @@ static struct clk_lookup spear_clk_lookups[] = {
#ifdef CONFIG_MACH_SPEAR1310
{.dev_id = "c_can_platform.0", .clk = &can0_clk},
{.dev_id = "c_can_platform.1", .clk = &can1_clk},
+ {.dev_id = "stmmaceth.1", .clk = &gmac_ras1_clk},
+ {.dev_id = "stmmaceth.2", .clk = &gmac_ras2_clk},
+ {.dev_id = "stmmaceth.3", .clk = &gmac_ras3_clk},
+ {.dev_id = "stmmaceth.4", .clk = &gmac_ras4_clk},
+ {.dev_id = "stmmacphy.1", .clk = &gmac_phy1_clk},
+ {.dev_id = "stmmacphy.2", .clk = &gmac_phy2_clk},
+ {.dev_id = "stmmacphy.3", .clk = &gmac_phy3_clk},
+ {.dev_id = "stmmacphy.4", .clk = &gmac_phy4_clk},
#endif
};
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
index 3cfd4fc..ea6096f 100644
--- a/arch/arm/mach-spear13xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -191,6 +191,25 @@
#define JPEG_SOF_RST 28
#define PERIP2_SW_RST ((unsigned int *)(MISC_BASE + 0x280))
#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x284))
+ /* RAS_CLK_ENB register masks */
+ #define ACLK_CLK_ENB 0
+ #define PCLK_CLK_ENB 1
+ #define OSC1_CLK_ENB 2
+ #define OSC2_CLK_ENB 3
+ #define OSC3_CLK_ENB 4
+ #define C48_CLK_ENB 5
+ #define C30_CLK_ENB 6
+ #define C125_CLK_ENB 7
+ #define PLL2_CLK_ENB 8
+ #define PLL3_CLK_ENB 9
+ #define PCLK0_CLK_ENB 10
+ #define PCLK1_CLK_ENB 11
+ #define PCLK2_CLK_ENB 12
+ #define PCLK3_CLK_ENB 13
+ #define SYN0_CLK_ENB 14
+ #define SYN1_CLK_ENB 15
+ #define SYN2_CLK_ENB 16
+ #define SYN3_CLK_ENB 17
#define RAS_SW_RST ((unsigned int *)(MISC_BASE + 0x288))
#define PLL1_SYNT ((unsigned int *)(MISC_BASE + 0x28c))
#define I2S_CLK_CFG ((unsigned int *)(MISC_BASE + 0x290))
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 37faef1..12d8c46 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -713,7 +713,7 @@ static struct clk pwm_clk = {
/* array of all spear 3xx clock lookups */
static struct clk_lookup spear_clk_lookups[] = {
- { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
+ { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
/* root clks */
{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
{ .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
@@ -738,8 +738,8 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "gpt1", .clk = &gpt1_clk},
{ .dev_id = "gpt2", .clk = &gpt2_clk},
/* clock derived from pll3 clk */
+ { .dev_id = "designware_udc", .clk = &usbd_clk},
{ .con_id = "usbh_clk", .clk = &usbh_clk},
- { .dev_id = "usbd", .clk = &usbd_clk},
/* clock derived from ahb clk */
{ .con_id = "ahbmult2_clk", .clk = &ahbmult2_clk},
{ .con_id = "ddr_clk", .clk = &ddr_clk},
@@ -755,7 +755,7 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
{ .dev_id = "gpio", .clk = &gpio_clk},
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
- { .dev_id = "physmap-flash", .clk = &emi_clk},
+ { .con_id = "emi", .clk = &emi_clk},
#endif
#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
defined(CONFIG_MACH_SPEAR320)
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 0a38e16..f304102 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -685,7 +685,7 @@ static struct clk dummy_apb_pclk;
/* array of all spear 6xx clock lookups */
static struct clk_lookup spear_clk_lookups[] = {
- { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
+ { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
/* root clks */
{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
{ .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
@@ -714,9 +714,9 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "gpt2", .clk = &gpt2_clk},
{ .dev_id = "gpt3", .clk = &gpt3_clk},
/* clock derived from pll3 clk */
+ { .dev_id = "designware_udc", .clk = &usbd_clk},
{ .con_id = "usbh.0_clk", .clk = &usbh0_clk},
{ .con_id = "usbh.1_clk", .clk = &usbh1_clk},
- { .dev_id = "usbd", .clk = &usbd_clk},
/* clock derived from ahb clk */
{ .con_id = "ahbmult2_clk", .clk = &ahbmult2_clk},
{ .con_id = "ddr_clk", .clk = &ddr_clk},
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 45/62] SPEAr : Pad multiplexing handling modified
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (42 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 44/62] SPEAr: Adding and Updating Clock definitions Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 46/62] SPEAr13xx : Fixed part devices in SPEAr13xx addded to the generic implementation Viresh Kumar
` (17 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipin Kumar <vipin.kumar@st.com>
Until now, the platform code assumed 1 32 bit register to be used for pad
multiplexing. This assumption is not true for SPEAr13xx devices, so the generic
implementation of pad multiplexing adopts a new concepts of multiple
multiplexing registers.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 3 +
arch/arm/mach-spear3xx/spear300.c | 314 ++++++++++++++----
arch/arm/mach-spear3xx/spear310.c | 118 +++++--
arch/arm/mach-spear3xx/spear320.c | 387 +++++++++++++++++-----
arch/arm/mach-spear3xx/spear3xx.c | 451 ++++++++++++++++++++-----
arch/arm/plat-spear/include/plat/padmux.h | 28 ++-
arch/arm/plat-spear/padmux.c | 28 +-
7 files changed, 1040 insertions(+), 289 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index da0eaa3..990e5b7 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -147,6 +147,7 @@ extern struct pmx_dev pmx_telecom_boot_pins;
extern struct pmx_dev pmx_telecom_sdhci_4bit;
extern struct pmx_dev pmx_telecom_sdhci_8bit;
extern struct pmx_dev pmx_gpio1;
+#define PAD_MUX_CONFIG_REG 0x00
/* Add spear300 machine function declarations here */
void __init spear300_init(void);
@@ -178,6 +179,7 @@ extern struct pmx_dev pmx_uart3_4_5;
extern struct pmx_dev pmx_fsmc;
extern struct pmx_dev pmx_rs485_0_1;
extern struct pmx_dev pmx_tdm0;
+#define PAD_MUX_CONFIG_REG 0x08
/* Add spear310 machine function declarations here */
void __init spear310_init(void);
@@ -227,6 +229,7 @@ extern struct pmx_dev pmx_mii1;
extern struct pmx_dev pmx_smii0;
extern struct pmx_dev pmx_smii1;
extern struct pmx_dev pmx_i2c1;
+#define PAD_MUX_CONFIG_REG 0x0C
/* Add spear320 machine function declarations here */
void __init spear320_init(void);
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 30e893f..91e25d7 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -21,8 +21,6 @@
#include <plat/shirq.h>
/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG 0x00
#define MODE_CONFIG_REG 0x04
/* modes */
@@ -44,87 +42,97 @@
struct pmx_mode nand_mode = {
.id = NAND_MODE,
.name = "nand mode",
- .mask = 0x00,
+ .value = 0x00,
};
struct pmx_mode nor_mode = {
.id = NOR_MODE,
.name = "nor mode",
- .mask = 0x01,
+ .value = 0x01,
};
struct pmx_mode photo_frame_mode = {
.id = PHOTO_FRAME_MODE,
.name = "photo frame mode",
- .mask = 0x02,
+ .value = 0x02,
};
struct pmx_mode lend_ip_phone_mode = {
.id = LEND_IP_PHONE_MODE,
.name = "lend ip phone mode",
- .mask = 0x03,
+ .value = 0x03,
};
struct pmx_mode hend_ip_phone_mode = {
.id = HEND_IP_PHONE_MODE,
.name = "hend ip phone mode",
- .mask = 0x04,
+ .value = 0x04,
};
struct pmx_mode lend_wifi_phone_mode = {
.id = LEND_WIFI_PHONE_MODE,
.name = "lend wifi phone mode",
- .mask = 0x05,
+ .value = 0x05,
};
struct pmx_mode hend_wifi_phone_mode = {
.id = HEND_WIFI_PHONE_MODE,
.name = "hend wifi phone mode",
- .mask = 0x06,
+ .value = 0x06,
};
struct pmx_mode ata_pabx_wi2s_mode = {
.id = ATA_PABX_WI2S_MODE,
.name = "ata pabx wi2s mode",
- .mask = 0x07,
+ .value = 0x07,
};
struct pmx_mode ata_pabx_i2s_mode = {
.id = ATA_PABX_I2S_MODE,
.name = "ata pabx i2s mode",
- .mask = 0x08,
+ .value = 0x08,
};
struct pmx_mode caml_lcdw_mode = {
.id = CAML_LCDW_MODE,
.name = "caml lcdw mode",
- .mask = 0x0C,
+ .value = 0x0C,
};
struct pmx_mode camu_lcd_mode = {
.id = CAMU_LCD_MODE,
.name = "camu lcd mode",
- .mask = 0x0D,
+ .value = 0x0D,
};
struct pmx_mode camu_wlcd_mode = {
.id = CAMU_WLCD_MODE,
.name = "camu wlcd mode",
- .mask = 0x0E,
+ .value = 0x0E,
};
struct pmx_mode caml_lcd_mode = {
.id = CAML_LCD_MODE,
.name = "caml lcd mode",
- .mask = 0x0F,
+ .value = 0x0F,
};
/* devices */
-struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
+/* Pad multiplexing for FSMC 2 NAND devices */
+static struct pmx_mux_reg pmx_fsmc_2_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_FIRDA_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
{
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
- .mask = PMX_FIRDA_MASK,
+ .mux_regs = pmx_fsmc_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_fsmc_2_mux),
},
};
@@ -132,14 +140,23 @@ struct pmx_dev pmx_fsmc_2_chips = {
.name = "fsmc_2_chips",
.modes = pmx_fsmc_2_chips_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
+/* Pad multiplexing for FSMC 4 NAND devices */
+static struct pmx_mux_reg pmx_fsmc_4_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
{
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
- .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
+ .mux_regs = pmx_fsmc_4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_fsmc_4_mux),
},
};
@@ -147,16 +164,25 @@ struct pmx_dev pmx_fsmc_4_chips = {
.name = "fsmc_4_chips",
.modes = pmx_fsmc_4_chips_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_keyboard_modes[] = {
+/* Pad multiplexing for Keyboard device */
+static struct pmx_mux_reg pmx_kbd_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = 0x0,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_keyboard_modes[] = {
{
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
CAML_LCD_MODE,
- .mask = 0x0,
+ .mux_regs = pmx_kbd_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_kbd_mux),
},
};
@@ -164,17 +190,35 @@ struct pmx_dev pmx_keyboard = {
.name = "keyboard",
.modes = pmx_keyboard_modes,
.mode_count = ARRAY_SIZE(pmx_keyboard_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_clcd_modes[] = {
+/* Pad multiplexing for CLCD device */
+static struct pmx_mux_reg pmx_clcd_pfmode_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_clcd_lcdmode_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_clcd_modes[] = {
{
.ids = PHOTO_FRAME_MODE,
- .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
+ .mux_regs = pmx_clcd_pfmode_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd_pfmode_mux),
}, {
.ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
CAMU_LCD_MODE | CAML_LCD_MODE,
- .mask = PMX_TIMER_3_4_MASK,
+ .mux_regs = pmx_clcd_lcdmode_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd_lcdmode_mux),
},
};
@@ -182,26 +226,71 @@ struct pmx_dev pmx_clcd = {
.name = "clcd",
.modes = pmx_clcd_modes,
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
+/* Pad multiplexing for Telecom GPIO device */
+static struct pmx_mux_reg pmx_gpio_lcdmode_mux[] = {
{
- .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_gpio_fonemode_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_gpio_atai2smode_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_gpio_lendfonemode_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_gpio_atawi2smode_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
+ | PMX_UART0_MODEM_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
+ {
+ .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
+ .mux_regs = pmx_gpio_lcdmode_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_lcdmode_mux),
}, {
.ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
- .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ .mux_regs = pmx_gpio_fonemode_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_fonemode_mux),
}, {
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
- .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
+ .mux_regs = pmx_gpio_atai2smode_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_atai2smode_mux),
}, {
.ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
- .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
+ .mux_regs = pmx_gpio_lendfonemode_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_lendfonemode_mux),
}, {
.ids = ATA_PABX_WI2S_MODE,
- .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
- | PMX_UART0_MODEM_MASK,
+ .mux_regs = pmx_gpio_atawi2smode_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_atawi2smode_mux),
},
};
@@ -209,17 +298,26 @@ struct pmx_dev pmx_telecom_gpio = {
.name = "telecom_gpio",
.modes = pmx_telecom_gpio_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
+/* Pad multiplexing for TDM device */
+static struct pmx_mux_reg pmx_tdm_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
{
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
| HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
| ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
| CAMU_WLCD_MODE | CAML_LCD_MODE,
- .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+ .mux_regs = pmx_tdm_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_tdm_mux),
},
};
@@ -227,16 +325,25 @@ struct pmx_dev pmx_telecom_tdm = {
.name = "telecom_tdm",
.modes = pmx_telecom_tdm_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
+/* Pad multiplexing for spi cs i2c device */
+static struct pmx_mux_reg pmx_spi_cs_i2c_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
{
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
| ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
CAML_LCDW_MODE | CAML_LCD_MODE,
- .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ .mux_regs = pmx_spi_cs_i2c_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_spi_cs_i2c_mux),
},
};
@@ -244,16 +351,33 @@ struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
.name = "telecom_spi_cs_i2c_clk",
.modes = pmx_telecom_spi_cs_i2c_clk_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_camera_modes[] = {
+static struct pmx_mux_reg pmx_caml_mux[] = {
{
- .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_camu_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
+ {
+ .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
+ .mux_regs = pmx_caml_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_caml_mux),
}, {
.ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
- .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
+ .mux_regs = pmx_camu_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_camu_mux),
},
};
@@ -261,14 +385,23 @@ struct pmx_dev pmx_telecom_camera = {
.name = "telecom_camera",
.modes = pmx_telecom_camera_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_dac_modes[] = {
+/* Pad multiplexing for dac device */
+static struct pmx_mux_reg pmx_dac_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_TIMER_1_2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
{
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
| CAMU_WLCD_MODE | CAML_LCD_MODE,
- .mask = PMX_TIMER_1_2_MASK,
+ .mux_regs = pmx_dac_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_dac_mux),
},
};
@@ -276,16 +409,25 @@ struct pmx_dev pmx_telecom_dac = {
.name = "telecom_dac",
.modes = pmx_telecom_dac_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
+/* Pad multiplexing for spi cs i2c device */
+static struct pmx_mux_reg pmx_i2s_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_UART0_MODEM_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
{
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
| CAMU_WLCD_MODE | CAML_LCD_MODE,
- .mask = PMX_UART0_MODEM_MASK,
+ .mux_regs = pmx_i2s_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2s_mux),
},
};
@@ -293,14 +435,23 @@ struct pmx_dev pmx_telecom_i2s = {
.name = "telecom_i2s",
.modes = pmx_telecom_i2s_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
+/* Pad multiplexing for bootpins device */
+static struct pmx_mux_reg pmx_bootpins_mux[] = {
{
- .ids = NAND_MODE | NOR_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
+ {
+ .ids = NAND_MODE | NOR_MODE,
+ .mux_regs = pmx_bootpins_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_bootpins_mux),
},
};
@@ -308,19 +459,28 @@ struct pmx_dev pmx_telecom_boot_pins = {
.name = "telecom_boot_pins",
.modes = pmx_telecom_boot_pins_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
+/* Pad multiplexing for sdhci 4bit device */
+static struct pmx_mux_reg pmx_sdhci_4bit_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+ PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+ PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
{
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
ATA_PABX_I2S_MODE,
- .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
- PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
- PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+ .mux_regs = pmx_sdhci_4bit_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_sdhci_4bit_mux),
},
};
@@ -328,18 +488,27 @@ struct pmx_dev pmx_telecom_sdhci_4bit = {
.name = "telecom_sdhci_4bit",
.modes = pmx_telecom_sdhci_4bit_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
+/* Pad multiplexing for spi cs i2c device */
+static struct pmx_mux_reg pmx_sdhci_8bit_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+ PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+ PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
{
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
CAMU_WLCD_MODE | CAML_LCD_MODE,
- .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
- PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
- PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
+ .mux_regs = pmx_sdhci_8bit_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_sdhci_8bit_mux),
},
};
@@ -347,14 +516,23 @@ struct pmx_dev pmx_telecom_sdhci_8bit = {
.name = "telecom_sdhci_8bit",
.modes = pmx_telecom_sdhci_8bit_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_gpio1_modes[] = {
+/* Pad multiplexing for spi cs i2c device */
+static struct pmx_mux_reg pmx_gpio1_mux[] = {
{
- .ids = PHOTO_FRAME_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpio1_modes[] = {
+ {
+ .ids = PHOTO_FRAME_MODE,
+ .mux_regs = pmx_gpio1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio1_mux),
},
};
@@ -362,13 +540,11 @@ struct pmx_dev pmx_gpio1 = {
.name = "arm gpio1",
.modes = pmx_gpio1_modes,
.mode_count = ARRAY_SIZE(pmx_gpio1_modes),
- .enb_on_reset = 1,
};
/* pmx driver structure */
struct pmx_driver pmx_driver = {
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
- .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
};
/* Add spear300 specific devices here */
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 5f72d3a..3a2ed0d 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -21,14 +21,21 @@
#include <plat/shirq.h>
/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG 0x08
/* devices */
-struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
+/* Pad multiplexing for emi_cs_0_1_4_5 devices */
+static struct pmx_mux_reg pmx_emi_cs_0_1_4_5_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
+ {
+ .mux_regs = pmx_emi_cs_0_1_4_5_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_mux),
},
};
@@ -36,13 +43,21 @@ struct pmx_dev pmx_emi_cs_0_1_4_5 = {
.name = "emi_cs_0_1_4_5",
.modes = pmx_emi_cs_0_1_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
+/* Pad multiplexing for emi_cs_2_3 devices */
+static struct pmx_mux_reg pmx_emi_cs_2_3_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
+ {
+ .mux_regs = pmx_emi_cs_2_3_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_emi_cs_2_3_mux),
},
};
@@ -50,13 +65,21 @@ struct pmx_dev pmx_emi_cs_2_3 = {
.name = "emi_cs_2_3",
.modes = pmx_emi_cs_2_3_modes,
.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart1_modes[] = {
+/* Pad multiplexing for uart1 device */
+static struct pmx_mux_reg pmx_uart1_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart1_modes[] = {
+ {
+ .mux_regs = pmx_uart1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart1_mux),
},
};
@@ -64,13 +87,21 @@ struct pmx_dev pmx_uart1 = {
.name = "uart1",
.modes = pmx_uart1_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart2_modes[] = {
+/* Pad multiplexing for uart2 device */
+static struct pmx_mux_reg pmx_uart2_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart2_modes[] = {
+ {
+ .mux_regs = pmx_uart2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart2_mux),
},
};
@@ -78,13 +109,21 @@ struct pmx_dev pmx_uart2 = {
.name = "uart2",
.modes = pmx_uart2_modes,
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
+/* Pad multiplexing for uart3_4_5 devices */
+static struct pmx_mux_reg pmx_uart3_4_5_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
+ {
+ .mux_regs = pmx_uart3_4_5_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart3_4_5_mux),
},
};
@@ -92,13 +131,21 @@ struct pmx_dev pmx_uart3_4_5 = {
.name = "uart3_4_5",
.modes = pmx_uart3_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_fsmc_modes[] = {
+/* Pad multiplexing for fsmc device */
+static struct pmx_mux_reg pmx_fsmc_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_fsmc_modes[] = {
+ {
+ .mux_regs = pmx_fsmc_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_fsmc_mux),
},
};
@@ -106,13 +153,21 @@ struct pmx_dev pmx_fsmc = {
.name = "fsmc",
.modes = pmx_fsmc_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
+/* Pad multiplexing for rs485_0_1 devices */
+static struct pmx_mux_reg pmx_rs485_0_1_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
+ {
+ .mux_regs = pmx_rs485_0_1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_rs485_0_1_mux),
},
};
@@ -120,13 +175,21 @@ struct pmx_dev pmx_rs485_0_1 = {
.name = "rs485_0_1",
.modes = pmx_rs485_0_1_modes,
.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_tdm0_modes[] = {
+/* Pad multiplexing for tdm0 device */
+static struct pmx_mux_reg pmx_tdm0_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_tdm0_modes[] = {
+ {
+ .mux_regs = pmx_tdm0_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_tdm0_mux),
},
};
@@ -134,13 +197,10 @@ struct pmx_dev pmx_tdm0 = {
.name = "tdm0",
.modes = pmx_tdm0_modes,
.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
- .enb_on_reset = 1,
};
/* pmx driver structure */
-struct pmx_driver pmx_driver = {
- .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
+struct pmx_driver pmx_driver;
/* Add spear310 specific devices here */
/* uart1 device registeration */
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index e7ca5db..2bdd798 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -24,8 +24,6 @@
#include <plat/shirq.h>
/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG 0x0C
#define MODE_CONFIG_REG 0x10
/* modes */
@@ -38,32 +36,42 @@
struct pmx_mode auto_net_smii_mode = {
.id = AUTO_NET_SMII_MODE,
.name = "Automation Networking SMII Mode",
- .mask = 0x00,
+ .value = 0x00,
};
struct pmx_mode auto_net_mii_mode = {
.id = AUTO_NET_MII_MODE,
.name = "Automation Networking MII Mode",
- .mask = 0x01,
+ .value = 0x01,
};
struct pmx_mode auto_exp_mode = {
.id = AUTO_EXP_MODE,
.name = "Automation Expanded Mode",
- .mask = 0x02,
+ .value = 0x02,
};
struct pmx_mode small_printers_mode = {
.id = SMALL_PRINTERS_MODE,
.name = "Small Printers Mode",
- .mask = 0x03,
+ .value = 0x03,
};
/* devices */
-struct pmx_dev_mode pmx_clcd_modes[] = {
+/* Pad multiplexing for CLCD device */
+static struct pmx_mux_reg pmx_clcd_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = 0x0,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_clcd_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE,
+ .mux_regs = pmx_clcd_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd_mux),
},
};
@@ -71,13 +79,22 @@ struct pmx_dev pmx_clcd = {
.name = "clcd",
.modes = pmx_clcd_modes,
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_emi_modes[] = {
+/* Pad multiplexing for EMI (Parallel NOR flash) device */
+static struct pmx_mux_reg pmx_emi_mux[] = {
{
- .ids = AUTO_EXP_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_emi_modes[] = {
+ {
+ .ids = AUTO_EXP_MODE,
+ .mux_regs = pmx_emi_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_emi_mux),
},
};
@@ -85,13 +102,22 @@ struct pmx_dev pmx_emi = {
.name = "emi",
.modes = pmx_emi_modes,
.mode_count = ARRAY_SIZE(pmx_emi_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_fsmc_modes[] = {
+/* Pad multiplexing for FSMC (NAND flash) device */
+static struct pmx_mux_reg pmx_fsmc_mux[] = {
{
- .ids = ALL_MODES,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = 0x0,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_fsmc_modes[] = {
+ {
+ .ids = ALL_MODES,
+ .mux_regs = pmx_fsmc_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_fsmc_mux),
},
};
@@ -99,13 +125,22 @@ struct pmx_dev pmx_fsmc = {
.name = "fsmc",
.modes = pmx_fsmc_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_spp_modes[] = {
+/* Pad multiplexing for SPP device */
+static struct pmx_mux_reg pmx_spp_mux[] = {
{
- .ids = SMALL_PRINTERS_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = 0x0,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_spp_modes[] = {
+ {
+ .ids = SMALL_PRINTERS_MODE,
+ .mux_regs = pmx_spp_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_spp_mux),
},
};
@@ -113,14 +148,23 @@ struct pmx_dev pmx_spp = {
.name = "spp",
.modes = pmx_spp_modes,
.mode_count = ARRAY_SIZE(pmx_spp_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_sdhci_modes[] = {
+/* Pad multiplexing for SDHCI device */
+static struct pmx_mux_reg pmx_sdhci_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_sdhci_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
SMALL_PRINTERS_MODE,
- .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ .mux_regs = pmx_sdhci_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_sdhci_mux),
},
};
@@ -128,13 +172,22 @@ struct pmx_dev pmx_sdhci = {
.name = "sdhci",
.modes = pmx_sdhci_modes,
.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_i2s_modes[] = {
+/* Pad multiplexing for I2S device */
+static struct pmx_mux_reg pmx_i2s_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2s_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mux_regs = pmx_i2s_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2s_mux),
},
};
@@ -142,13 +195,22 @@ struct pmx_dev pmx_i2s = {
.name = "i2s",
.modes = pmx_i2s_modes,
.mode_count = ARRAY_SIZE(pmx_i2s_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart1_modes[] = {
+/* Pad multiplexing for UART1 device */
+static struct pmx_mux_reg pmx_uart1_mux[] = {
{
- .ids = ALL_MODES,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart1_modes[] = {
+ {
+ .ids = ALL_MODES,
+ .mux_regs = pmx_uart1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart1_mux),
},
};
@@ -156,18 +218,36 @@ struct pmx_dev pmx_uart1 = {
.name = "uart1",
.modes = pmx_uart1_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart1_modem_modes[] = {
+/* Pad multiplexing for UART1 Modem device */
+static struct pmx_mux_reg pmx_uart1_modem_autoexp_mux[] = {
{
- .ids = AUTO_EXP_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
PMX_SSP_CS_MASK,
- }, {
- .ids = SMALL_PRINTERS_MODE,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_uart1_modem_smallpri_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
+ {
+ .ids = AUTO_EXP_MODE,
+ .mux_regs = pmx_uart1_modem_autoexp_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart1_modem_autoexp_mux),
+ }, {
+ .ids = SMALL_PRINTERS_MODE,
+ .mux_regs = pmx_uart1_modem_smallpri_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart1_modem_smallpri_mux),
},
};
@@ -175,13 +255,22 @@ struct pmx_dev pmx_uart1_modem = {
.name = "uart1_modem",
.modes = pmx_uart1_modem_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart2_modes[] = {
+/* Pad multiplexing for UART2 device */
+static struct pmx_mux_reg pmx_uart2_mux[] = {
{
- .ids = ALL_MODES,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart2_modes[] = {
+ {
+ .ids = ALL_MODES,
+ .mux_regs = pmx_uart2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart2_mux),
},
};
@@ -189,13 +278,22 @@ struct pmx_dev pmx_uart2 = {
.name = "uart2",
.modes = pmx_uart2_modes,
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_touchscreen_modes[] = {
+/* Pad multiplexing for Touchscreen device */
+static struct pmx_mux_reg pmx_touchscreen_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_touchscreen_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE,
+ .mux_regs = pmx_touchscreen_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_touchscreen_mux),
},
};
@@ -203,14 +301,23 @@ struct pmx_dev pmx_touchscreen = {
.name = "touchscreen",
.modes = pmx_touchscreen_modes,
.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_can_modes[] = {
+/* Pad multiplexing for CAN device */
+static struct pmx_mux_reg pmx_can_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_can_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
+ .mux_regs = pmx_can_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_can_mux),
},
};
@@ -218,13 +325,22 @@ struct pmx_dev pmx_can = {
.name = "can",
.modes = pmx_can_modes,
.mode_count = ARRAY_SIZE(pmx_can_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_sdhci_led_modes[] = {
+/* Pad multiplexing for SDHCI LED device */
+static struct pmx_mux_reg pmx_sdhci_led_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mux_regs = pmx_sdhci_led_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_sdhci_led_mux),
},
};
@@ -232,16 +348,34 @@ struct pmx_dev pmx_sdhci_led = {
.name = "sdhci_led",
.modes = pmx_sdhci_led_modes,
.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_pwm0_modes[] = {
+/* Pad multiplexing for PWM0 device */
+static struct pmx_mux_reg pmx_pwm0_net_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_pwm0_autoexpsmallpri_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_pwm0_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mux_regs = pmx_pwm0_net_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pwm0_net_mux),
}, {
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
- .mask = PMX_MII_MASK,
+ .mux_regs = pmx_pwm0_autoexpsmallpri_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pwm0_autoexpsmallpri_mux),
},
};
@@ -249,16 +383,34 @@ struct pmx_dev pmx_pwm0 = {
.name = "pwm0",
.modes = pmx_pwm0_modes,
.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_pwm1_modes[] = {
+/* Pad multiplexing for PWM1 device */
+static struct pmx_mux_reg pmx_pwm1_net_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_pwm1_autoexpsmallpri_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_pwm1_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mux_regs = pmx_pwm1_net_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pwm1_net_mux),
}, {
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
- .mask = PMX_MII_MASK,
+ .mux_regs = pmx_pwm1_autoexpsmallpri_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pwm1_autoexpsmallpri_mux),
},
};
@@ -266,16 +418,34 @@ struct pmx_dev pmx_pwm1 = {
.name = "pwm1",
.modes = pmx_pwm1_modes,
.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_pwm2_modes[] = {
+/* Pad multiplexing for PWM2 device */
+static struct pmx_mux_reg pmx_pwm2_net_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_mux_reg pmx_pwm2_autoexpsmallpri_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG,
+ .mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_pwm2_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mux_regs = pmx_pwm2_net_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pwm2_net_mux),
}, {
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
- .mask = PMX_MII_MASK,
+ .mux_regs = pmx_pwm2_autoexpsmallpri_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pwm2_autoexpsmallpri_mux),
},
};
@@ -283,13 +453,22 @@ struct pmx_dev pmx_pwm2 = {
.name = "pwm2",
.modes = pmx_pwm2_modes,
.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_pwm3_modes[] = {
+/* Pad multiplexing for PWM3 device */
+static struct pmx_mux_reg pmx_pwm3_mux[] = {
{
- .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_pwm3_modes[] = {
+ {
+ .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
+ .mux_regs = pmx_pwm3_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pwm3_mux),
},
};
@@ -297,13 +476,22 @@ struct pmx_dev pmx_pwm3 = {
.name = "pwm3",
.modes = pmx_pwm3_modes,
.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_ssp1_modes[] = {
+/* Pad multiplexing for SSP1 device */
+static struct pmx_mux_reg pmx_ssp1_mux[] = {
{
- .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_ssp1_modes[] = {
+ {
+ .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
+ .mux_regs = pmx_ssp1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_ssp1_mux),
},
};
@@ -311,13 +499,22 @@ struct pmx_dev pmx_ssp1 = {
.name = "ssp1",
.modes = pmx_ssp1_modes,
.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_ssp2_modes[] = {
+/* Pad multiplexing for SSP2 device */
+static struct pmx_mux_reg pmx_ssp2_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_ssp2_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE,
+ .mux_regs = pmx_ssp2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_ssp2_mux),
},
};
@@ -325,13 +522,22 @@ struct pmx_dev pmx_ssp2 = {
.name = "ssp2",
.modes = pmx_ssp2_modes,
.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_mii1_modes[] = {
+/* Pad multiplexing for mii1 device */
+static struct pmx_mux_reg pmx_mii1_mux[] = {
{
- .ids = AUTO_NET_MII_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = 0x0,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_mii1_modes[] = {
+ {
+ .ids = AUTO_NET_MII_MODE,
+ .mux_regs = pmx_mii1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_mii1_mux),
},
};
@@ -339,13 +545,22 @@ struct pmx_dev pmx_mii1 = {
.name = "mii1",
.modes = pmx_mii1_modes,
.mode_count = ARRAY_SIZE(pmx_mii1_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_smii0_modes[] = {
+/* Pad multiplexing for smii0 device */
+static struct pmx_mux_reg pmx_smii0_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_smii0_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
+ .mux_regs = pmx_smii0_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_smii0_mux),
},
};
@@ -353,13 +568,22 @@ struct pmx_dev pmx_smii0 = {
.name = "smii0",
.modes = pmx_smii0_modes,
.mode_count = ARRAY_SIZE(pmx_smii0_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_smii1_modes[] = {
+/* Pad multiplexing for smii1 device */
+static struct pmx_mux_reg pmx_smii1_mux[] = {
{
- .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_smii1_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
+ .mux_regs = pmx_smii1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_smii1_mux),
},
};
@@ -367,13 +591,22 @@ struct pmx_dev pmx_smii1 = {
.name = "smii1",
.modes = pmx_smii1_modes,
.mode_count = ARRAY_SIZE(pmx_smii1_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_i2c1_modes[] = {
+/* Pad multiplexing for i2c1 device */
+static struct pmx_mux_reg pmx_i2c1_mux[] = {
{
- .ids = AUTO_EXP_MODE,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = 0x0,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2c1_modes[] = {
+ {
+ .ids = AUTO_EXP_MODE,
+ .mux_regs = pmx_i2c1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2c1_mux),
},
};
@@ -381,13 +614,11 @@ struct pmx_dev pmx_i2c1 = {
.name = "i2c1",
.modes = pmx_i2c1_modes,
.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
- .enb_on_reset = 1,
};
/* pmx driver structure */
struct pmx_driver pmx_driver = {
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
- .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
};
/* Add spear320 specific devices here */
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 12285ee..7ea3a25 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -274,10 +274,21 @@ void __init spear3xx_map_io(void)
/* pad multiplexing support */
/* devices */
-struct pmx_dev_mode pmx_firda_modes[] = {
+
+/* Pad multiplexing for firda device */
+static struct pmx_mux_reg pmx_firda_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
+ .value = PMX_FIRDA_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_firda_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_firda_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_firda_mux),
},
};
@@ -285,13 +296,22 @@ struct pmx_dev pmx_firda = {
.name = "firda",
.modes = pmx_firda_modes,
.mode_count = ARRAY_SIZE(pmx_firda_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_i2c_modes[] = {
+/* Pad multiplexing for i2c device */
+static struct pmx_mux_reg pmx_i2c_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_I2C_MASK,
+ .value = PMX_I2C_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2c_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_i2c_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2c_mux),
},
};
@@ -299,13 +319,22 @@ struct pmx_dev pmx_i2c = {
.name = "i2c",
.modes = pmx_i2c_modes,
.mode_count = ARRAY_SIZE(pmx_i2c_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_ssp_cs_modes[] = {
+/* Pad multiplexing for firda device */
+static struct pmx_mux_reg pmx_ssp_cs_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
+ .value = PMX_SSP_CS_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_ssp_cs_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_ssp_cs_mux),
},
};
@@ -313,13 +342,22 @@ struct pmx_dev pmx_ssp_cs = {
.name = "ssp_chip_selects",
.modes = pmx_ssp_cs_modes,
.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_ssp_modes[] = {
+/* Pad multiplexing for ssp device */
+static struct pmx_mux_reg pmx_ssp_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_MASK,
+ .value = PMX_SSP_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_ssp_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_ssp_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_ssp_mux),
},
};
@@ -327,13 +365,22 @@ struct pmx_dev pmx_ssp = {
.name = "ssp",
.modes = pmx_ssp_modes,
.mode_count = ARRAY_SIZE(pmx_ssp_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_mii_modes[] = {
+/* Pad multiplexing for mii device */
+static struct pmx_mux_reg pmx_mii_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = PMX_MII_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_mii_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_mii_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_mii_mux),
},
};
@@ -341,13 +388,22 @@ struct pmx_dev pmx_mii = {
.name = "mii",
.modes = pmx_mii_modes,
.mode_count = ARRAY_SIZE(pmx_mii_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
+/* Pad multiplexing for gpio pin0 device */
+static struct pmx_mux_reg pmx_gpio_pin0_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK,
+ .value = PMX_GPIO_PIN0_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_gpio_pin0_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_pin0_mux),
},
};
@@ -355,13 +411,22 @@ struct pmx_dev pmx_gpio_pin0 = {
.name = "gpio_pin0",
.modes = pmx_gpio_pin0_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
+/* Pad multiplexing for gpio pin1 device */
+static struct pmx_mux_reg pmx_gpio_pin1_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN1_MASK,
+ .value = PMX_GPIO_PIN1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_gpio_pin1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_pin1_mux),
},
};
@@ -369,13 +434,22 @@ struct pmx_dev pmx_gpio_pin1 = {
.name = "gpio_pin1",
.modes = pmx_gpio_pin1_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
+/* Pad multiplexing for gpio pin2 device */
+static struct pmx_mux_reg pmx_gpio_pin2_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK,
+ .value = PMX_GPIO_PIN2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_gpio_pin2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_pin2_mux),
},
};
@@ -383,13 +457,22 @@ struct pmx_dev pmx_gpio_pin2 = {
.name = "gpio_pin2",
.modes = pmx_gpio_pin2_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
+/* Pad multiplexing for gpio pin3 device */
+static struct pmx_mux_reg pmx_gpio_pin3_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK,
+ .value = PMX_GPIO_PIN3_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_gpio_pin3_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_pin3_mux),
},
};
@@ -397,13 +480,22 @@ struct pmx_dev pmx_gpio_pin3 = {
.name = "gpio_pin3",
.modes = pmx_gpio_pin3_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
+/* Pad multiplexing for gpio pin4 device */
+static struct pmx_mux_reg pmx_gpio_pin4_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN4_MASK,
+ .value = PMX_GPIO_PIN4_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_gpio_pin4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_pin4_mux),
},
};
@@ -411,13 +503,22 @@ struct pmx_dev pmx_gpio_pin4 = {
.name = "gpio_pin4",
.modes = pmx_gpio_pin4_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
+/* Pad multiplexing for gpio pin5 device */
+static struct pmx_mux_reg pmx_gpio_pin5_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN5_MASK,
+ .value = PMX_GPIO_PIN5_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_gpio_pin5_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpio_pin5_mux),
},
};
@@ -425,13 +526,22 @@ struct pmx_dev pmx_gpio_pin5 = {
.name = "gpio_pin5",
.modes = pmx_gpio_pin5_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_uart0_modem_modes[] = {
+/* Pad multiplexing for uart0 modem device */
+static struct pmx_mux_reg pmx_uart0_modem_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
+ .value = PMX_UART0_MODEM_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_uart0_modem_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart0_modem_mux),
},
};
@@ -439,13 +549,22 @@ struct pmx_dev pmx_uart0_modem = {
.name = "uart0_modem",
.modes = pmx_uart0_modem_modes,
.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_uart0_modes[] = {
+/* Pad multiplexing for uart0 device */
+static struct pmx_mux_reg pmx_uart0_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MASK,
+ .value = PMX_UART0_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart0_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_uart0_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart0_mux),
},
};
@@ -453,13 +572,22 @@ struct pmx_dev pmx_uart0 = {
.name = "uart0",
.modes = pmx_uart0_modes,
.mode_count = ARRAY_SIZE(pmx_uart0_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_timer_3_4_modes[] = {
+/* Pad multiplexing for timer 3, 4 device */
+static struct pmx_mux_reg pmx_timer_3_4_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
+ .value = PMX_TIMER_3_4_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_timer_3_4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_timer_3_4_mux),
},
};
@@ -467,13 +595,22 @@ struct pmx_dev pmx_timer_3_4 = {
.name = "timer_3_4",
.modes = pmx_timer_3_4_modes,
.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
- .enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_timer_1_2_modes[] = {
+/* Pad multiplexing for gpio pin0 device */
+static struct pmx_mux_reg pmx_timer_1_2_mux[] = {
{
- .ids = 0xffffffff,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
+ .value = PMX_TIMER_1_2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_timer_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_timer_1_2_mux),
},
};
@@ -481,15 +618,24 @@ struct pmx_dev pmx_timer_1_2 = {
.name = "timer_1_2",
.modes = pmx_timer_1_2_modes,
.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
- .enb_on_reset = 0,
};
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
/* plgpios devices */
-struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
+/* Pad multiplexing for plgpio_0_1 devices */
+static struct pmx_mux_reg pmx_plgpio_0_1_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_0_1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_0_1_mux),
},
};
@@ -497,13 +643,22 @@ struct pmx_dev pmx_plgpio_0_1 = {
.name = "plgpio 0 and 1",
.modes = pmx_plgpio_0_1_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
+/* Pad multiplexing for plgpio_2_3 devices */
+static struct pmx_mux_reg pmx_plgpio_2_3_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_2_3_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_2_3_mux),
},
};
@@ -511,13 +666,22 @@ struct pmx_dev pmx_plgpio_2_3 = {
.name = "plgpio 2 and 3",
.modes = pmx_plgpio_2_3_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
+/* Pad multiplexing for plgpio_4_5 devices */
+static struct pmx_mux_reg pmx_plgpio_4_5_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_I2C_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_4_5_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_4_5_mux),
},
};
@@ -525,13 +689,22 @@ struct pmx_dev pmx_plgpio_4_5 = {
.name = "plgpio 4 and 5",
.modes = pmx_plgpio_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
+/* Pad multiplexing for plgpio_6_9 devices */
+static struct pmx_mux_reg pmx_plgpio_6_9_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_6_9_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_6_9_mux),
},
};
@@ -539,13 +712,22 @@ struct pmx_dev pmx_plgpio_6_9 = {
.name = "plgpio 6 to 9",
.modes = pmx_plgpio_6_9_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
+/* Pad multiplexing for plgpio_10_27 devices */
+static struct pmx_mux_reg pmx_plgpio_10_27_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_10_27_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_10_27_mux),
},
};
@@ -553,13 +735,22 @@ struct pmx_dev pmx_plgpio_10_27 = {
.name = "plgpio 10 to 27",
.modes = pmx_plgpio_10_27_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_28_modes[] = {
+/* Pad multiplexing for plgpio_28 devices */
+static struct pmx_mux_reg pmx_plgpio_28_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_28_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_28_mux),
},
};
@@ -567,13 +758,22 @@ struct pmx_dev pmx_plgpio_28 = {
.name = "plgpio 28",
.modes = pmx_plgpio_28_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_29_modes[] = {
+/* Pad multiplexing for plgpio_29 devices */
+static struct pmx_mux_reg pmx_plgpio_29_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_29_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_29_mux),
},
};
@@ -581,13 +781,22 @@ struct pmx_dev pmx_plgpio_29 = {
.name = "plgpio 29",
.modes = pmx_plgpio_29_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_30_modes[] = {
+/* Pad multiplexing for plgpio_30 device */
+static struct pmx_mux_reg pmx_plgpio_30_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_30_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_30_mux),
},
};
@@ -595,13 +804,22 @@ struct pmx_dev pmx_plgpio_30 = {
.name = "plgpio 30",
.modes = pmx_plgpio_30_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_31_modes[] = {
+/* Pad multiplexing for plgpio_31 device */
+static struct pmx_mux_reg pmx_plgpio_31_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_31_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_31_mux),
},
};
@@ -609,13 +827,22 @@ struct pmx_dev pmx_plgpio_31 = {
.name = "plgpio 31",
.modes = pmx_plgpio_31_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_32_modes[] = {
+/* Pad multiplexing for plgpio_32 device */
+static struct pmx_mux_reg pmx_plgpio_32_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_32_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_32_mux),
},
};
@@ -623,13 +850,22 @@ struct pmx_dev pmx_plgpio_32 = {
.name = "plgpio 32",
.modes = pmx_plgpio_32_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_33_modes[] = {
+/* Pad multiplexing for plgpio_33 device */
+static struct pmx_mux_reg pmx_plgpio_33_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN5_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_33_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_33_mux),
},
};
@@ -637,13 +873,22 @@ struct pmx_dev pmx_plgpio_33 = {
.name = "plgpio 33",
.modes = pmx_plgpio_33_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
+/* Pad multiplexing for plgpio_34_36 device */
+static struct pmx_mux_reg pmx_plgpio_34_36_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_34_36_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_34_36_mux),
},
};
@@ -651,13 +896,22 @@ struct pmx_dev pmx_plgpio_34_36 = {
.name = "plgpio 34 to 36",
.modes = pmx_plgpio_34_36_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
+/* Pad multiplexing for plgpio_37_42 device */
+static struct pmx_mux_reg pmx_plgpio_37_42_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_37_42_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_37_42_mux),
},
};
@@ -665,13 +919,22 @@ struct pmx_dev pmx_plgpio_37_42 = {
.name = "plgpio 37 to 42",
.modes = pmx_plgpio_37_42_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
+/* Pad multiplexing for plgpio_43_44_47_48 device */
+static struct pmx_mux_reg pmx_plgpio_43_44_47_48_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_43_44_47_48_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_43_44_47_48_mux),
},
};
@@ -679,13 +942,22 @@ struct pmx_dev pmx_plgpio_43_44_47_48 = {
.name = "plgpio 43, 44, 47 and 48",
.modes = pmx_plgpio_43_44_47_48_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
- .enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
+/* Pad multiplexing for plgpio_45_46_49_50 device */
+static struct pmx_mux_reg pmx_plgpio_45_46_49_50_mux[] = {
{
- .ids = 0x00,
+ .offset = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mux_regs = pmx_plgpio_45_46_49_50_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_plgpio_45_46_49_50_mux),
},
};
@@ -693,7 +965,6 @@ struct pmx_dev pmx_plgpio_45_46_49_50 = {
.name = "plgpio 45, 46, 49 and 50",
.modes = pmx_plgpio_45_46_49_50_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
- .enb_on_reset = 1,
};
#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
index 877f3ad..1b69ca5 100644
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ b/arch/arm/plat-spear/include/plat/padmux.h
@@ -28,26 +28,42 @@ struct pmx_reg {
};
/*
+ * struct pmx_mux_reg: configuration structure every group of modes of a device
+ *
+ * offset: multiplexing register offset
+ * mask: mask for supported mode
+ * value: value to be written
+ */
+struct pmx_mux_reg {
+ u32 offset;
+ u32 mask;
+ u32 value;
+};
+
+/*
* struct pmx_dev_mode: configuration structure every group of modes of a device
*
* ids: all modes for this configuration
- * mask: mask for supported mode
+ * mux_regs: array of mux registers, masks and values to enable the device in
+ * this group of modes
+ * mux_reg_cnt: count of mux_regs elements
*/
struct pmx_dev_mode {
u32 ids;
- u32 mask;
+ struct pmx_mux_reg *mux_regs;
+ u8 mux_reg_cnt;
};
/*
* struct pmx_mode: mode definition structure
*
* name: mode name
- * mask: mode mask
+ * value: mode value
*/
struct pmx_mode {
char *name;
u32 id;
- u32 mask;
+ u32 value;
};
/*
@@ -57,14 +73,12 @@ struct pmx_mode {
* modes: device configuration array for different modes supported
* mode_count: size of modes array
* is_active: is peripheral active/enabled
- * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
*/
struct pmx_dev {
char *name;
struct pmx_dev_mode *modes;
u8 mode_count;
bool is_active;
- bool enb_on_reset;
};
/*
@@ -75,7 +89,6 @@ struct pmx_dev {
* devs_count: ARRAY_SIZE of devs
* base: base address of soc config registers
* mode_reg: structure of mode config register
- * mux_reg: structure of device mux config register
*/
struct pmx_driver {
struct pmx_mode *mode;
@@ -83,7 +96,6 @@ struct pmx_driver {
u8 devs_count;
u32 *base;
struct pmx_reg mode_reg;
- struct pmx_reg mux_reg;
};
/* pmx functions */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
index 555eec6..f30f94b 100644
--- a/arch/arm/plat-spear/padmux.c
+++ b/arch/arm/plat-spear/padmux.c
@@ -21,13 +21,11 @@
*
* base: base address of configuration registers
* mode_reg: mode configurations
- * mux_reg: muxing configurations
* active_mode: pointer to current active mode
*/
struct pmx {
u32 base;
struct pmx_reg mode_reg;
- struct pmx_reg mux_reg;
struct pmx_mode *active_mode;
};
@@ -51,7 +49,7 @@ static int pmx_mode_set(struct pmx_mode *mode)
val = readl(pmx->base + pmx->mode_reg.offset);
val &= ~pmx->mode_reg.mask;
- val |= mode->mask & pmx->mode_reg.mask;
+ val |= mode->value & pmx->mode_reg.mask;
writel(val, pmx->base + pmx->mode_reg.offset);
return 0;
@@ -66,19 +64,18 @@ static int pmx_mode_set(struct pmx_mode *mode)
* If peripheral is not supported by current mode then request is rejected.
* Conflicts between peripherals are not handled and peripherals will be
* enabled in the order they are present in pmx_dev array.
- * In case of conflicts last peripheral enabled will be present.
+ * In case of conflicts last peripheral enabled will remain present.
* Returns -ve on Err otherwise 0
*/
static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
{
- u32 val, i, mask;
+ u32 val, i;
if (!count)
return -EINVAL;
- val = readl(pmx->base + pmx->mux_reg.offset);
for (i = 0; i < count; i++) {
- u8 j = 0;
+ u8 k, j = 0;
if (!devs[i]->name || !devs[i]->modes) {
printk(KERN_ERR "padmux: dev name or modes is null\n");
@@ -103,15 +100,18 @@ static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
}
/* enable peripheral */
- mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
- if (devs[i]->enb_on_reset)
- val &= ~mask;
- else
- val |= mask;
+ for (k = 0; k < devs[i]->modes[j].mux_reg_cnt; k++) {
+ struct pmx_mux_reg *mux_reg =
+ &devs[i]->modes[j].mux_regs[k];
+
+ val = readl(pmx->base + mux_reg->offset);
+ val &= ~mux_reg->mask;
+ val |= mux_reg->value & mux_reg->mask;
+ writel(val, pmx->base + mux_reg->offset);
+ }
devs[i]->is_active = true;
}
- writel(val, pmx->base + pmx->mux_reg.offset);
kfree(pmx);
/* this will ensure that multiplexing can't be changed now */
@@ -144,8 +144,6 @@ int pmx_register(struct pmx_driver *driver)
pmx->base = (u32)driver->base;
pmx->mode_reg.offset = driver->mode_reg.offset;
pmx->mode_reg.mask = driver->mode_reg.mask;
- pmx->mux_reg.offset = driver->mux_reg.offset;
- pmx->mux_reg.mask = driver->mux_reg.mask;
/* choose mode to enable */
if (driver->mode) {
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 46/62] SPEAr13xx : Fixed part devices in SPEAr13xx addded to the generic implementation
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (43 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 45/62] SPEAr : Pad multiplexing handling modified Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 47/62] SPEAr : Updating pad multiplexing support Viresh Kumar
` (16 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 164 ++++++++
arch/arm/mach-spear13xx/include/mach/spear.h | 3 +
arch/arm/mach-spear13xx/spear1300.c | 15 +
arch/arm/mach-spear13xx/spear1300_evb.c | 25 ++
arch/arm/mach-spear13xx/spear1310.c | 15 +
arch/arm/mach-spear13xx/spear1310_evb.c | 25 ++
arch/arm/mach-spear13xx/spear13xx.c | 528 ++++++++++++++++++++++++
arch/arm/plat-spear/Makefile | 1 +
8 files changed, 776 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 20a7fb4..795d48e 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -19,6 +19,168 @@
#include <linux/amba/bus.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
+#include <plat/padmux.h>
+
+/*
+ * Function enable (Pad multiplexing register) offsets
+ */
+#define PAD_MUX_CONFIG_REG_0 0x0
+#define PAD_MUX_CONFIG_REG_1 0x4
+#define PAD_MUX_CONFIG_REG_2 0x8
+#define PAD_MUX_CONFIG_REG_3 0xC
+
+/* pad mux declarations */
+#define PMX_I2S1_MASK (1 << 3)
+#define PMX_I2S2_MASK (1 << 16) /* Offset 4 */
+#define PMX_CLCD1_MASK (1 << 5)
+#define PMX_CLCD2_MASK (1 << 3) /* Offset 4 */
+#define PMX_EGPIO00_MASK (1 << 6)
+#define PMX_EGPIO01_MASK (1 << 7)
+#define PMX_EGPIO02_MASK (1 << 8)
+#define PMX_EGPIO03_MASK (1 << 9)
+#define PMX_EGPIO04_MASK (1 << 10)
+#define PMX_EGPIO05_MASK (1 << 11)
+#define PMX_EGPIO06_MASK (1 << 12)
+#define PMX_EGPIO07_MASK (1 << 13)
+#define PMX_EGPIO08_MASK (1 << 14)
+#define PMX_EGPIO09_MASK (1 << 15)
+#define PMX_EGPIO10_MASK (1 << 5) /* Offset 4 */
+#define PMX_EGPIO11_MASK (1 << 6) /* Offset 4 */
+#define PMX_EGPIO12_MASK (1 << 7) /* Offset 4 */
+#define PMX_EGPIO13_MASK (1 << 8) /* Offset 4 */
+#define PMX_EGPIO14_MASK (1 << 9) /* Offset 4 */
+#define PMX_EGPIO15_MASK (1 << 10) /* Offset 4 */
+#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
+ PMX_EGPIO02_MASK | PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
+ PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | PMX_EGPIO07_MASK | \
+ PMX_EGPIO08_MASK | PMX_EGPIO09_MASK)
+#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
+ PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | PMX_EGPIO14_MASK | \
+ PMX_EGPIO15_MASK)
+
+#define PMX_SMI_MASK (1 << 16)
+#define PMX_SMINCS2_MASK (1 << 1) /* Offset 4 */
+#define PMX_SMINCS3_MASK (1 << 2) /* Offset 4 */
+
+#define PMX_GMIICLK_MASK (1 << 18)
+#define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
+#define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
+#define PMX_GMIID47_MASK (1 << 21)
+#define PMX_MDC_MDIO_MASK (1 << 22)
+
+#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
+ PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
+ PMX_RXCLK_RDV_TXEN_D03_MASK | PMX_GMIID47_MASK | \
+ PMX_MDC_MDIO_MASK)
+
+#define PMX_NAND8_MASK (1 << 17)
+#define PMX_NFAD023_MASK (1 << 24)
+#define PMX_NFAD24_MASK (1 << 25)
+#define PMX_NFAD25_MASK (1 << 26)
+#define PMX_NFWPRT1_MASK (1 << 24) /* Offset 4 */
+#define PMX_NFWPRT2_MASK (1 << 26) /* Offset 4 */
+#define PMX_NFWPRT3_MASK (1 << 28)
+#define PMX_NFRSTPWDWN0_MASK (1 << 29)
+#define PMX_NFRSTPWDWN1_MASK (1 << 30)
+#define PMX_NFRSTPWDWN2_MASK (1 << 31)
+#define PMX_NFRSTPWDWN3_MASK (1 << 0) /* Offset 4 */
+#define PMX_NFCE1_MASK (1 << 20) /* Offset 4 */
+#define PMX_NFCE2_MASK (1 << 22) /* Offset 4 */
+#define PMX_NFCE3_MASK (1 << 27)
+#define PMX_NFIO815_MASK (1 << 18) /* Offset 4 */
+
+#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD023_MASK | \
+ PMX_NFAD24_MASK | PMX_NFAD25_MASK | PMX_NFWPRT3_MASK | \
+ PMX_NFRSTPWDWN0_MASK | PMX_NFRSTPWDWN1_MASK | \
+ PMX_NFRSTPWDWN2_MASK | PMX_NFCE3_MASK)
+#define PMX_NAND8BIT_1_MASK (PMX_NFRSTPWDWN3_MASK)
+
+#define PMX_NAND8BIT4DEV_0_MASK (PMX_NAND8BIT_0_MASK)
+#define PMX_NAND8BIT4DEV_1_MASK (PMX_NAND8BIT_1_MASK | PMX_NFCE1_MASK | \
+ PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK)
+
+#define PMX_NAND16BIT_0_MASK (PMX_NAND8BIT_0_MASK)
+#define PMX_NAND16BIT_1_MASK (PMX_NAND8BIT_1_MASK | PMX_NFIO815_MASK)
+#define PMX_NAND16BIT4DEV_0_MASK (PMX_NAND8BIT4DEV_0_MASK)
+#define PMX_NAND16BIT4DEV_1_MASK (PMX_NAND8BIT4DEV_1_MASK | \
+ PMX_NFIO815_MASK)
+
+#define PMX_KBD_ROW0_MASK (1 << 25) /* Offset 4 */
+#define PMX_KBD_ROW1_MASK (1 << 23) /* Offset 4 */
+#define PMX_KBD_ROWCOL25_MASK (1 << 17) /* Offset 4 */
+#define PMX_KBD_ROWCOL68_MASK (1 << 4) /* Offset 4 */
+#define PMX_KBD_COL0_MASK (1 << 21) /* Offset 4 */
+#define PMX_KBD_COL1_MASK (1 << 19) /* Offset 4 */
+#define PMX_KEYBOARD_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
+ PMX_KBD_ROWCOL25_MASK | PMX_KBD_ROWCOL68_MASK | \
+ PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
+
+#define PMX_UART0_MASK (1 << 1)
+#define PMX_I2C_MASK (1 << 2)
+#define PMX_SSP_MASK (1 << 4)
+#define PMX_UART0_MODEM_MASK (1 << 11) /* Offset 4 */
+#define PMX_GPT0_TMR1_MASK (1 << 12) /* Offset 4 */
+#define PMX_GPT0_TMR2_MASK (1 << 13) /* Offset 4 */
+#define PMX_GPT1_TMR1_MASK (1 << 14) /* Offset 4 */
+#define PMX_GPT1_TMR2_MASK (1 << 15) /* Offset 4 */
+
+#define PMX_MCIDATA0_MASK (1 << 27) /* Offset 4 */
+#define PMX_MCIDATA1_MASK (1 << 28) /* Offset 4 */
+#define PMX_MCIDATA2_MASK (1 << 29) /* Offset 4 */
+#define PMX_MCIDATA3_MASK (1 << 30) /* Offset 4 */
+#define PMX_MCIDATA4_MASK (1 << 31) /* Offset 4 */
+#define PMX_MCIDATA5_MASK (1 << 0) /* Offset 8 */
+#define PMX_MCIDATA6_MASK (1 << 1) /* Offset 8 */
+#define PMX_MCIDATA7_MASK (1 << 2) /* Offset 8 */
+#define PMX_MCIDATA1SD_MASK (1 << 3) /* Offset 8 */
+#define PMX_MCIDATA2SD_MASK (1 << 4) /* Offset 8 */
+#define PMX_MCIDATA3SD_MASK (1 << 5) /* Offset 8 */
+#define PMX_MCIADDR0ALE_MASK (1 << 6) /* Offset 8 */
+#define PMX_MCIADDR1CLECLK_MASK (1 << 7) /* Offset 8 */
+#define PMX_MCIADDR2_MASK (1 << 8) /* Offset 8 */
+#define PMX_MCICECF_MASK (1 << 9) /* Offset 8 */
+#define PMX_MCICEXD_MASK (1 << 10) /* Offset 8 */
+#define PMX_MCICESDMMC_MASK (1 << 11) /* Offset 8 */
+#define PMX_MCICDCF1_MASK (1 << 12) /* Offset 8 */
+#define PMX_MCICDCF2_MASK (1 << 13) /* Offset 8 */
+#define PMX_MCICDXD_MASK (1 << 14) /* Offset 8 */
+#define PMX_MCICDSDMMC_MASK (1 << 15) /* Offset 8 */
+#define PMX_MCIDATADIR_MASK (1 << 16) /* Offset 8 */
+#define PMX_MCIDMARQWP_MASK (1 << 17) /* Offset 8 */
+#define PMX_MCIIORDRE_MASK (1 << 18) /* Offset 8 */
+#define PMX_MCIIOWRWE_MASK (1 << 19) /* Offset 8 */
+#define PMX_MCIRESETCF_MASK (1 << 20) /* Offset 8 */
+#define PMX_MCICS0CE_MASK (1 << 21) /* Offset 8 */
+#define PMX_MCICFINTR_MASK (1 << 22) /* Offset 8 */
+#define PMX_MCIIORDY_MASK (1 << 23) /* Offset 8 */
+#define PMX_MCICS1_MASK (1 << 24) /* Offset 8 */
+#define PMX_MCIDMAACK_MASK (1 << 25) /* Offset 8 */
+#define PMX_MCISDCMD_MASK (1 << 26) /* Offset 8 */
+#define PMX_MCILEDS_MASK (1 << 27) /* Offset 8 */
+
+#define PMX_MCIFALL_1_MASK (0xF8000000)
+#define PMX_MCIFALL_2_MASK (0x0FFFFFFF)
+
+/* pad mux devices */
+extern struct pmx_dev pmx_i2c;
+extern struct pmx_dev pmx_ssp;
+extern struct pmx_dev pmx_i2s2;
+extern struct pmx_dev pmx_clcd1;
+extern struct pmx_dev pmx_clcd2;
+extern struct pmx_dev pmx_egpio_grp;
+extern struct pmx_dev pmx_smi_2_chips;
+extern struct pmx_dev pmx_smi_4_chips;
+extern struct pmx_dev pmx_gmii;
+extern struct pmx_dev pmx_nand_8bit;
+extern struct pmx_dev pmx_nand_16bit;
+extern struct pmx_dev pmx_keyboard;
+extern struct pmx_dev pmx_uart0;
+extern struct pmx_dev pmx_uart0_modem;
+extern struct pmx_dev pmx_gpt_0_1;
+extern struct pmx_dev pmx_gpt_0_2;
+extern struct pmx_dev pmx_gpt_1_1;
+extern struct pmx_dev pmx_gpt_1_2;
+extern struct pmx_dev pmx_mcif;
/*
* Each GPT has 2 timer channels
@@ -28,6 +190,8 @@
#define SPEAR_GPT0_CHAN0_IRQ IRQ_GPT0_TMR0
#define SPEAR_GPT0_CHAN1_IRQ IRQ_GPT0_TMR1
+extern struct pmx_driver pmx_driver;
+
/* Add spear13xx family device structure declarations here */
extern struct amba_device spear13xx_gpio_device[];
extern struct amba_device spear13xx_ssp_device;
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index cf25eb5..ca96ce9 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -88,6 +88,9 @@
#define SPEAR13XX_MCIF_CF_BASE UL(0xB2800000)
#define SPEAR13XX_MCIF_SDHCI_BASE UL(0xB3000000)
+/* Pad multiplexing base */
+#define SPEAR13XX_FUNC_ENB_BASE UL(0xE0700650)
+
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR13XX_UART_BASE
#define VA_SPEAR_DBG_UART_BASE VA_SPEAR13XX_UART_BASE
diff --git a/arch/arm/mach-spear13xx/spear1300.c b/arch/arm/mach-spear13xx/spear1300.c
index c1b82f1..4569cb5 100644
--- a/arch/arm/mach-spear13xx/spear1300.c
+++ b/arch/arm/mach-spear13xx/spear1300.c
@@ -14,10 +14,25 @@
#include <mach/generic.h>
#include <mach/spear.h>
+/* pmx driver structure */
+struct pmx_driver pmx_driver;
+
/* Add spear1300 specific devices here */
void __init spear1300_init(void)
{
+ int ret;
+
/* call spear13xx family common init function */
spear13xx_init();
+
+ /* pmx initialization */
+ pmx_driver.base = ioremap(SPEAR13XX_FUNC_ENB_BASE, SZ_4K);
+ if (pmx_driver.base) {
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registeration failed. err no: %d\n",
+ ret);
+ iounmap(pmx_driver.base);
+ }
}
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index ef30ffd..5bfdefa 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -26,6 +26,26 @@
#include <plat/fsmc.h>
#include <plat/spi.h>
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+ /* spear13xx specific devices */
+ &pmx_i2c,
+ &pmx_i2s1,
+ &pmx_i2s2,
+ &pmx_clcd1,
+ &pmx_clcd2,
+ &pmx_egpio_grp,
+ &pmx_gmii,
+ &pmx_keyboard,
+ &pmx_mcif,
+ &pmx_nand_8bit,
+ &pmx_smi_4_chips,
+ &pmx_ssp,
+ &pmx_uart0,
+
+ /* spear1300 specific devices */
+};
+
static struct amba_device *amba_devs[] __initdata = {
&spear13xx_gpio_device[0],
&spear13xx_gpio_device[1],
@@ -88,6 +108,11 @@ static void __init spear1300_evb_init(void)
{
unsigned int i;
+ /* padmux initialization, must be done before spear1300_init */
+ pmx_driver.mode = NULL;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
+
/* set keyboard plat data */
kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 9e2036d..07c4c94 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -16,6 +16,9 @@
#include <mach/generic.h>
#include <mach/hardware.h>
+/* pmx driver structure */
+struct pmx_driver pmx_driver;
+
/* Add spear1310 specific devices here */
/* CAN device registeration */
@@ -74,6 +77,18 @@ void __init spear1310_map_io(void)
void __init spear1310_init(void)
{
+ int ret;
+
/* call spear13xx family common init function */
spear13xx_init();
+
+ /* pmx initialization */
+ pmx_driver.base = ioremap(SPEAR13XX_FUNC_ENB_BASE, SZ_4K);
+ if (pmx_driver.base) {
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registeration failed. err no: %d\n",
+ ret);
+ iounmap(pmx_driver.base);
+ }
}
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
index 010eab4..de5a2dc 100644
--- a/arch/arm/mach-spear13xx/spear1310_evb.c
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -26,6 +26,26 @@
#include <mach/spear.h>
#include <mach/pcie.h>
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+ /* spear13xx specific devices */
+ &pmx_i2c,
+ &pmx_i2s1,
+ &pmx_i2s2,
+ &pmx_clcd1,
+ &pmx_clcd2,
+ &pmx_egpio_grp,
+ &pmx_gmii,
+ &pmx_keyboard,
+ &pmx_mcif,
+ &pmx_nand_8bit,
+ &pmx_smi_4_chips,
+ &pmx_ssp,
+ &pmx_uart0,
+
+ /* spear1310 specific devices */
+};
+
static struct amba_device *amba_devs[] __initdata = {
/* spear13xx specific devices */
&spear13xx_gpio_device[0],
@@ -94,6 +114,11 @@ static void __init spear1310_evb_init(void)
{
unsigned int i;
+ /* padmux initialization, must be done before spear1300_init */
+ pmx_driver.mode = NULL;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
+
/* set keyboard plat data */
kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index b6936c5..bbcfdf4 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -496,3 +496,531 @@ static void __init spear13xx_timer_init(void)
struct sys_timer spear13xx_timer = {
.init = spear13xx_timer_init,
};
+
+/* pad multiplexing support */
+/* devices */
+
+/* Pad multiplexing for i2c device */
+static struct pmx_mux_reg pmx_i2c_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_I2C_MASK,
+ .value = PMX_I2C_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2c_modes[] = {
+ {
+ .mux_regs = pmx_i2c_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2c_mux),
+ },
+};
+
+struct pmx_dev pmx_i2c = {
+ .name = "i2c",
+ .modes = pmx_i2c_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2c_modes),
+};
+
+/* Pad multiplexing for ssp device */
+static struct pmx_mux_reg pmx_ssp_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SSP_MASK,
+ .value = PMX_SSP_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_ssp_modes[] = {
+ {
+ .mux_regs = pmx_ssp_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_ssp_mux),
+ },
+};
+
+struct pmx_dev pmx_ssp = {
+ .name = "ssp",
+ .modes = pmx_ssp_modes,
+ .mode_count = ARRAY_SIZE(pmx_ssp_modes),
+};
+
+/* Pad multiplexing for i2s1 device */
+static struct pmx_mux_reg pmx_i2s1_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_I2S1_MASK,
+ .value = PMX_I2S1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2s1_modes[] = {
+ {
+ .mux_regs = pmx_i2s1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2s1_mux),
+ },
+};
+
+struct pmx_dev pmx_i2s1 = {
+ .name = "i2s1",
+ .modes = pmx_i2s1_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2s1_modes),
+};
+
+/* Pad multiplexing for i2s2 device */
+static struct pmx_mux_reg pmx_i2s2_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_I2S2_MASK,
+ .value = PMX_I2S2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2s2_modes[] = {
+ {
+ .mux_regs = pmx_i2s2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2s2_mux),
+ },
+};
+
+struct pmx_dev pmx_i2s2 = {
+ .name = "i2s2",
+ .modes = pmx_i2s2_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2s2_modes),
+};
+
+/* Pad multiplexing for clcd1 device */
+static struct pmx_mux_reg pmx_clcd1_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = PMX_CLCD1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_clcd1_modes[] = {
+ {
+ .mux_regs = pmx_clcd1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd1_mux),
+ },
+};
+
+struct pmx_dev pmx_clcd1 = {
+ .name = "clcd1",
+ .modes = pmx_clcd1_modes,
+ .mode_count = ARRAY_SIZE(pmx_clcd1_modes),
+};
+
+/* Pad multiplexing for clcd2 device */
+static struct pmx_mux_reg pmx_clcd2_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_CLCD2_MASK,
+ .value = PMX_CLCD2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_clcd2_modes[] = {
+ {
+ .mux_regs = pmx_clcd2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd2_mux),
+ },
+};
+
+struct pmx_dev pmx_clcd2 = {
+ .name = "clcd2",
+ .modes = pmx_clcd2_modes,
+ .mode_count = ARRAY_SIZE(pmx_clcd2_modes),
+};
+
+/*
+ * By default, all EGPIOs are enabled.
+ * TBD : Board specific enabling of specific GPIOs only
+ */
+static struct pmx_mux_reg pmx_egpio_grp_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_EGPIO_0_GRP_MASK,
+ .value = PMX_EGPIO_0_GRP_MASK,
+ }, {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_EGPIO_1_GRP_MASK,
+ .value = PMX_EGPIO_1_GRP_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_egpio_grp_modes[] = {
+ {
+ .mux_regs = pmx_egpio_grp_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_egpio_grp_mux),
+ },
+};
+
+struct pmx_dev pmx_egpio_grp = {
+ .name = "egpios",
+ .modes = pmx_egpio_grp_modes,
+ .mode_count = ARRAY_SIZE(pmx_egpio_grp_modes),
+};
+
+/* Pad multiplexing for smi 2 chips device */
+static struct pmx_mux_reg pmx_smi_2_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SMI_MASK,
+ .value = PMX_SMI_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_smi_2_modes[] = {
+ {
+ .mux_regs = pmx_smi_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_smi_2_mux),
+ },
+};
+
+struct pmx_dev pmx_smi_2_chips = {
+ .name = "smi_2_chips",
+ .modes = pmx_smi_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_smi_2_modes),
+};
+
+/* Pad multiplexing for smi 4 chips device */
+static struct pmx_mux_reg pmx_smi_4_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SMI_MASK,
+ .value = PMX_SMI_MASK,
+ }, {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+ .value = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_smi_4_modes[] = {
+ {
+ .mux_regs = pmx_smi_4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_smi_4_mux),
+ },
+};
+
+struct pmx_dev pmx_smi_4_chips = {
+ .name = "smi_4_chips",
+ .modes = pmx_smi_4_modes,
+ .mode_count = ARRAY_SIZE(pmx_smi_4_modes),
+};
+
+/* Pad multiplexing for gmii device */
+static struct pmx_mux_reg pmx_gmii_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_GMII_MASK,
+ .value = PMX_GMII_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gmii_modes[] = {
+ {
+ .mux_regs = pmx_gmii_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gmii_mux),
+ },
+};
+
+struct pmx_dev pmx_gmii = {
+ .name = "gmii",
+ .modes = pmx_gmii_modes,
+ .mode_count = ARRAY_SIZE(pmx_gmii_modes),
+};
+
+/* Pad multiplexing for nand 8bit (4 chips) */
+static struct pmx_mux_reg pmx_nand8_4_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND8BIT4DEV_0_MASK,
+ .value = PMX_NAND8BIT4DEV_0_MASK,
+ }, {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND8BIT4DEV_1_MASK,
+ .value = PMX_NAND8BIT4DEV_1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_nand8_4_modes[] = {
+ {
+ .mux_regs = pmx_nand8_4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_nand8_4_mux),
+ },
+};
+
+struct pmx_dev pmx_nand_8bit_4_chips = {
+ .name = "nand-8bit_4_chips",
+ .modes = pmx_nand8_4_modes,
+ .mode_count = ARRAY_SIZE(pmx_nand8_4_modes),
+};
+
+/* Pad multiplexing for nand 8bit device */
+static struct pmx_mux_reg pmx_nand8_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND8BIT_0_MASK,
+ .value = PMX_NAND8BIT_0_MASK,
+ }, {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND8BIT_1_MASK,
+ .value = PMX_NAND8BIT_1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_nand8_modes[] = {
+ {
+ .mux_regs = pmx_nand8_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_nand8_mux),
+ },
+};
+
+struct pmx_dev pmx_nand_8bit = {
+ .name = "nand-8bit",
+ .modes = pmx_nand8_modes,
+ .mode_count = ARRAY_SIZE(pmx_nand8_modes),
+};
+
+/*
+ * Pad multiplexing for nand 16bit device
+ * Note : Enabling pmx_nand_16bit means that all the required pads for
+ * 16bit nand device operations are enabled. These also include pads
+ * for 8bit devices
+ */
+static struct pmx_mux_reg pmx_nand16_4_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND16BIT4DEV_0_MASK,
+ .value = PMX_NAND16BIT4DEV_0_MASK,
+ }, {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND16BIT4DEV_1_MASK,
+ .value = PMX_NAND16BIT4DEV_1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_nand16_4_modes[] = {
+ {
+ .mux_regs = pmx_nand16_4_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_nand16_4_mux),
+ },
+};
+
+struct pmx_dev pmx_nand_16bit_4_chips = {
+ .name = "nand-16bit_4_chips",
+ .modes = pmx_nand16_4_modes,
+ .mode_count = ARRAY_SIZE(pmx_nand16_4_modes),
+};
+
+/* Pad multiplexing for nand 16bit device */
+static struct pmx_mux_reg pmx_nand16_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND16BIT_0_MASK,
+ .value = PMX_NAND16BIT_0_MASK,
+ }, {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND16BIT_1_MASK,
+ .value = PMX_NAND16BIT_1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_nand16_modes[] = {
+ {
+ .mux_regs = pmx_nand16_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_nand16_mux),
+ },
+};
+
+struct pmx_dev pmx_nand_16bit = {
+ .name = "nand-16bit",
+ .modes = pmx_nand16_modes,
+ .mode_count = ARRAY_SIZE(pmx_nand16_modes),
+};
+
+/* Pad multiplexing for keyboard device */
+static struct pmx_mux_reg pmx_keyboard_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_MASK,
+ .value = PMX_KEYBOARD_MASK,
+ }, {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NFIO815_MASK | PMX_NFCE1_MASK | \
+ PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_keyboard_modes[] = {
+ {
+ .mux_regs = pmx_keyboard_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_keyboard_mux),
+ },
+};
+
+struct pmx_dev pmx_keyboard = {
+ .name = "keyboard",
+ .modes = pmx_keyboard_modes,
+ .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
+};
+
+/* Pad multiplexing for uart0 device */
+static struct pmx_mux_reg pmx_uart0_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_UART0_MASK,
+ .value = PMX_UART0_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart0_modes[] = {
+ {
+ .mux_regs = pmx_uart0_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart0_mux),
+ },
+};
+
+struct pmx_dev pmx_uart0 = {
+ .name = "uart0",
+ .modes = pmx_uart0_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart0_modes),
+};
+
+/* Pad multiplexing for uart0_modem device */
+static struct pmx_mux_reg pmx_uart0_modem_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_UART0_MODEM_MASK,
+ .value = PMX_UART0_MODEM_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
+ {
+ .mux_regs = pmx_uart0_modem_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart0_modem_mux),
+ },
+};
+
+struct pmx_dev pmx_uart0_modem = {
+ .name = "uart0_modem",
+ .modes = pmx_uart0_modem_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
+};
+
+/* Pad multiplexing for gpt_0_1 device */
+static struct pmx_mux_reg pmx_gpt_0_1_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_GPT0_TMR1_MASK,
+ .value = PMX_GPT0_TMR1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpt_0_1_modes[] = {
+ {
+ .mux_regs = pmx_gpt_0_1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpt_0_1_mux),
+ },
+};
+
+struct pmx_dev pmx_gpt_0_1 = {
+ .name = "gpt_0_1",
+ .modes = pmx_gpt_0_1_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpt_0_1_modes),
+};
+
+/* Pad multiplexing for gpt_0_2 device */
+static struct pmx_mux_reg pmx_gpt_0_2_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_GPT0_TMR2_MASK,
+ .value = PMX_GPT0_TMR2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpt_0_2_modes[] = {
+ {
+ .mux_regs = pmx_gpt_0_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpt_0_2_mux),
+ },
+};
+
+struct pmx_dev pmx_gpt_0_2 = {
+ .name = "gpt_0_2",
+ .modes = pmx_gpt_0_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpt_0_2_modes),
+};
+
+/* Pad multiplexing for gpt_1_1 device */
+static struct pmx_mux_reg pmx_gpt_1_1_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_GPT1_TMR1_MASK,
+ .value = PMX_GPT1_TMR1_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpt_1_1_modes[] = {
+ {
+ .mux_regs = pmx_gpt_1_1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpt_1_1_mux),
+ },
+};
+
+struct pmx_dev pmx_gpt_1_1 = {
+ .name = "gpt_1_1",
+ .modes = pmx_gpt_1_1_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpt_1_1_modes),
+};
+
+/* Pad multiplexing for gpt_1_2 device */
+static struct pmx_mux_reg pmx_gpt_1_2_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_GPT1_TMR2_MASK,
+ .value = PMX_GPT1_TMR2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_gpt_1_2_modes[] = {
+ {
+ .mux_regs = pmx_gpt_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gpt_1_2_mux),
+ },
+};
+
+struct pmx_dev pmx_gpt_1_2 = {
+ .name = "gpt_1_2",
+ .modes = pmx_gpt_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpt_1_2_modes),
+};
+
+/* Pad multiplexing for mcif device */
+static struct pmx_mux_reg pmx_mcif_mux[] = {
+ {
+ .offset = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_MCIFALL_1_MASK,
+ .value = PMX_MCIFALL_1_MASK,
+ }, {
+ .offset = PAD_MUX_CONFIG_REG_2,
+ .mask = PMX_MCIFALL_2_MASK,
+ .value = PMX_MCIFALL_2_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_mcif_modes[] = {
+ {
+ .mux_regs = pmx_mcif_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_mcif_mux),
+ },
+};
+
+struct pmx_dev pmx_mcif = {
+ .name = "mcif",
+ .modes = pmx_mcif_modes,
+ .mode_count = ARRAY_SIZE(pmx_mcif_modes),
+};
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index ec85b82..eafa29d 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -5,6 +5,7 @@
# Common support
obj-y := clcd.o clock.o pll_clk.o time.o
+obj-$(CONFIG_ARCH_SPEAR13XX) += padmux.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 47/62] SPEAr : Updating pad multiplexing support
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (44 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 46/62] SPEAr13xx : Fixed part devices in SPEAr13xx addded to the generic implementation Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 48/62] ST SPEAr3xx: Passing pmx devices address from machine *.c files Viresh Kumar
` (15 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Vipin Kumar <vipin.kumar@st.com>
This patch makes the following changes
-> Addition of SPEAr1310 pad multiplexing devices.
-> A few bugfixes eg. clcd1 and clcd2 removed and clcd/clcd_hires added
-> Support for modifying multiple regiters in different address ranges
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 50 +++-
arch/arm/mach-spear13xx/include/mach/spear.h | 3 -
arch/arm/mach-spear13xx/spear1300.c | 11 +-
arch/arm/mach-spear13xx/spear1300_evb.c | 5 +-
arch/arm/mach-spear13xx/spear1310.c | 346 +++++++++++++++++++++++-
arch/arm/mach-spear13xx/spear1310_evb.c | 17 +-
arch/arm/mach-spear13xx/spear13xx.c | 169 +++++++-----
arch/arm/mach-spear3xx/include/mach/generic.h | 12 +-
arch/arm/mach-spear3xx/include/mach/spear300.h | 1 -
arch/arm/mach-spear3xx/spear300.c | 67 ++---
arch/arm/mach-spear3xx/spear310.c | 20 +-
arch/arm/mach-spear3xx/spear320.c | 61 ++---
arch/arm/mach-spear3xx/spear3xx.c | 60 ++--
arch/arm/plat-spear/include/plat/padmux.h | 10 +-
arch/arm/plat-spear/padmux.c | 36 ++-
15 files changed, 626 insertions(+), 242 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 795d48e..0551850 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -24,10 +24,21 @@
/*
* Function enable (Pad multiplexing register) offsets
*/
-#define PAD_MUX_CONFIG_REG_0 0x0
-#define PAD_MUX_CONFIG_REG_1 0x4
-#define PAD_MUX_CONFIG_REG_2 0x8
-#define PAD_MUX_CONFIG_REG_3 0xC
+/* Pad multiplexing base */
+#define SPEAR13XX_FUNC_ENB_BASE UL(0xE0700650)
+#define SPEAR13XX_PCM_CFG_BASE UL(0xE0700100)
+
+#define PAD_MUX_CONFIG_REG_0 UL(0xE0700650)
+#define PAD_MUX_CONFIG_REG_1 UL(0xE0700654)
+#define PAD_MUX_CONFIG_REG_2 UL(0xE0700658)
+#define PAD_MUX_CONFIG_REG_3 UL(0xE070065C)
+
+#if defined(CONFIG_MACH_SPEAR1310)
+#define SPEAR1310_FUNC_CNTL_0 UL(0x6C800000)
+
+#define PMX_SMII_MASK (1 << 24) /* Func cntl reg0 */
+#define PMX_EGPIO7_MASK (1 << 2) /* Pcm cfg reg */
+#endif
/* pad mux declarations */
#define PMX_I2S1_MASK (1 << 3)
@@ -111,9 +122,8 @@
#define PMX_KBD_ROWCOL68_MASK (1 << 4) /* Offset 4 */
#define PMX_KBD_COL0_MASK (1 << 21) /* Offset 4 */
#define PMX_KBD_COL1_MASK (1 << 19) /* Offset 4 */
-#define PMX_KEYBOARD_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
- PMX_KBD_ROWCOL25_MASK | PMX_KBD_ROWCOL68_MASK | \
- PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
+#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
+ PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
#define PMX_UART0_MASK (1 << 1)
#define PMX_I2C_MASK (1 << 2)
@@ -164,16 +174,18 @@
/* pad mux devices */
extern struct pmx_dev pmx_i2c;
extern struct pmx_dev pmx_ssp;
+extern struct pmx_dev pmx_i2s1;
extern struct pmx_dev pmx_i2s2;
-extern struct pmx_dev pmx_clcd1;
-extern struct pmx_dev pmx_clcd2;
+extern struct pmx_dev pmx_clcd;
+extern struct pmx_dev pmx_clcd_hires;
extern struct pmx_dev pmx_egpio_grp;
extern struct pmx_dev pmx_smi_2_chips;
extern struct pmx_dev pmx_smi_4_chips;
extern struct pmx_dev pmx_gmii;
extern struct pmx_dev pmx_nand_8bit;
extern struct pmx_dev pmx_nand_16bit;
-extern struct pmx_dev pmx_keyboard;
+extern struct pmx_dev pmx_keyboard_6x6;
+extern struct pmx_dev pmx_keyboard_9x9;
extern struct pmx_dev pmx_uart0;
extern struct pmx_dev pmx_uart0_modem;
extern struct pmx_dev pmx_gpt_0_1;
@@ -182,6 +194,24 @@ extern struct pmx_dev pmx_gpt_1_1;
extern struct pmx_dev pmx_gpt_1_2;
extern struct pmx_dev pmx_mcif;
+#if defined(CONFIG_MACH_SPEAR1310)
+extern struct pmx_dev pmx_uart1_modem;
+extern struct pmx_dev pmx_uart_1;
+extern struct pmx_dev pmx_uart_2;
+extern struct pmx_dev pmx_uart_3_4_5;
+extern struct pmx_dev pmx_rs485_hdlc_1_2;
+extern struct pmx_dev pmx_tdm_hdlc_1_2;
+extern struct pmx_dev pmx_nand32bit;
+extern struct pmx_dev pmx_fsmc16bit_4_chips;
+extern struct pmx_dev pmx_fsmc32bit_4_chips;
+extern struct pmx_dev pmx_gmii1;
+extern struct pmx_dev pmx_rgmii;
+extern struct pmx_dev pmx_i2c1;
+extern struct pmx_dev pmx_smii_0_1_2;
+extern struct pmx_dev pmx_can;
+extern struct pmx_dev pmx_uart1_modem;
+#endif
+
/*
* Each GPT has 2 timer channels
* Following GPT channels will be used as clock source and clockevent
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index ca96ce9..cf25eb5 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -88,9 +88,6 @@
#define SPEAR13XX_MCIF_CF_BASE UL(0xB2800000)
#define SPEAR13XX_MCIF_SDHCI_BASE UL(0xB3000000)
-/* Pad multiplexing base */
-#define SPEAR13XX_FUNC_ENB_BASE UL(0xE0700650)
-
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR13XX_UART_BASE
#define VA_SPEAR_DBG_UART_BASE VA_SPEAR13XX_UART_BASE
diff --git a/arch/arm/mach-spear13xx/spear1300.c b/arch/arm/mach-spear13xx/spear1300.c
index 4569cb5..28822a3 100644
--- a/arch/arm/mach-spear13xx/spear1300.c
+++ b/arch/arm/mach-spear13xx/spear1300.c
@@ -27,12 +27,7 @@ void __init spear1300_init(void)
spear13xx_init();
/* pmx initialization */
- pmx_driver.base = ioremap(SPEAR13XX_FUNC_ENB_BASE, SZ_4K);
- if (pmx_driver.base) {
- ret = pmx_register(&pmx_driver);
- if (ret)
- pr_err("padmux: registeration failed. err no: %d\n",
- ret);
- iounmap(pmx_driver.base);
- }
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registeration failed. err no: %d\n", ret);
}
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 5bfdefa..09babdd 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -32,11 +32,10 @@ static struct pmx_dev *pmx_devs[] = {
&pmx_i2c,
&pmx_i2s1,
&pmx_i2s2,
- &pmx_clcd1,
- &pmx_clcd2,
+ &pmx_clcd,
&pmx_egpio_grp,
&pmx_gmii,
- &pmx_keyboard,
+ &pmx_keyboard_6x6,
&pmx_mcif,
&pmx_nand_8bit,
&pmx_smi_4_chips,
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 07c4c94..db9bbdb 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -19,6 +19,341 @@
/* pmx driver structure */
struct pmx_driver pmx_driver;
+/* Pad multiplexing for uart1_modem device */
+static struct pmx_mux_reg pmx_uart1_modem_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_I2S1_MASK | PMX_SSP_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
+ {
+ .mux_regs = pmx_uart1_modem_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart1_modem_mux),
+ },
+};
+
+struct pmx_dev pmx_uart1_modem = {
+ .name = "uart1_modem",
+ .modes = pmx_uart1_modem_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
+};
+
+/* Pad multiplexing for uart1 device */
+static struct pmx_mux_reg pmx_uart1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SSP_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart1_modes[] = {
+ {
+ .mux_regs = pmx_uart1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart1_mux),
+ },
+};
+
+struct pmx_dev pmx_uart_1 = {
+ .name = "uart1",
+ .modes = pmx_uart1_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart1_modes),
+};
+
+/* Pad multiplexing for uart2 device */
+static struct pmx_mux_reg pmx_uart2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_SSP_MASK | PMX_CLCD1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart2_modes[] = {
+ {
+ .mux_regs = pmx_uart2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart2_mux),
+ },
+};
+
+struct pmx_dev pmx_uart_2 = {
+ .name = "uart2",
+ .modes = pmx_uart2_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart2_modes),
+};
+
+/* Pad multiplexing for uart_3_4_5 device */
+static struct pmx_mux_reg pmx_uart_3_4_5_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_uart_3_4_5_modes[] = {
+ {
+ .mux_regs = pmx_uart_3_4_5_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_uart_3_4_5_mux),
+ },
+};
+
+struct pmx_dev pmx_uart_3_4_5 = {
+ .name = "uart_3_4_5",
+ .modes = pmx_uart_3_4_5_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart_3_4_5_modes),
+};
+
+/* Pad multiplexing for rs485_hdlc_1_2 device */
+static struct pmx_mux_reg pmx_rs485_hdlc_1_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_rs485_hdlc_1_2_modes[] = {
+ {
+ .mux_regs = pmx_rs485_hdlc_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_rs485_hdlc_1_2_mux),
+ },
+};
+
+struct pmx_dev pmx_rs485_hdlc_1_2 = {
+ .name = "rs485_hdlc_1_2",
+ .modes = pmx_rs485_hdlc_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_rs485_hdlc_1_2_modes),
+};
+
+/* Pad multiplexing for tdm_hdlc_1_2 device */
+static struct pmx_mux_reg pmx_tdm_hdlc_1_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_tdm_hdlc_1_2_modes[] = {
+ {
+ .mux_regs = pmx_tdm_hdlc_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_tdm_hdlc_1_2_mux),
+ },
+};
+
+struct pmx_dev pmx_tdm_hdlc_1_2 = {
+ .name = "tdm_hdlc_1_2",
+ .modes = pmx_tdm_hdlc_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_tdm_hdlc_1_2_modes),
+};
+
+/* Pad multiplexing for fsmc32bit device */
+static struct pmx_mux_reg pmx_fsmc32bit_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_EGPIO_0_GRP_MASK | PMX_SMI_MASK | \
+ PMX_NAND16BIT4DEV_0_MASK | PMX_CLCD1_MASK,
+ .value = 0,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_6X6_MASK | PMX_NAND16BIT4DEV_1_MASK,
+ .value = 0,
+ }, {
+ .address = SPEAR13XX_PCM_CFG_BASE,
+ .mask = PMX_EGPIO7_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_fsmc32bit_modes[] = {
+ {
+ .mux_regs = pmx_fsmc32bit_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_fsmc32bit_mux),
+ },
+};
+
+struct pmx_dev pmx_fsmc32bit_4_chips = {
+ .name = "fsmc32bit",
+ .modes = pmx_fsmc32bit_modes,
+ .mode_count = ARRAY_SIZE(pmx_fsmc32bit_modes),
+};
+
+/* Pad multiplexing for fsmc16bit device */
+static struct pmx_mux_reg pmx_fsmc16bit_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_NAND16BIT4DEV_0_MASK,
+ .value = 0,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_6X6_MASK | PMX_NAND16BIT4DEV_1_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_fsmc16bit_modes[] = {
+ {
+ .mux_regs = pmx_fsmc16bit_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_fsmc16bit_mux),
+ },
+};
+
+struct pmx_dev pmx_fsmc16bit_4_chips = {
+ .name = "fsmc16bit",
+ .modes = pmx_fsmc16bit_modes,
+ .mode_count = ARRAY_SIZE(pmx_fsmc16bit_modes),
+};
+
+/* Pad multiplexing for gmii1 device */
+static struct pmx_mux_reg pmx_gmii1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_GMII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_gmii1_modes[] = {
+ {
+ .mux_regs = pmx_gmii1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_gmii1_mux),
+ },
+};
+
+struct pmx_dev pmx_gmii1 = {
+ .name = "gmii1",
+ .modes = pmx_gmii1_modes,
+ .mode_count = ARRAY_SIZE(pmx_gmii1_modes),
+};
+
+/* Pad multiplexing for rgmii device */
+static struct pmx_mux_reg pmx_rgmii_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_GMII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_rgmii_modes[] = {
+ {
+ .mux_regs = pmx_rgmii_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_rgmii_mux),
+ },
+};
+
+struct pmx_dev pmx_rgmii = {
+ .name = "rgmii",
+ .modes = pmx_rgmii_modes,
+ .mode_count = ARRAY_SIZE(pmx_rgmii_modes),
+};
+
+/* Pad multiplexing for i2c1 device */
+static struct pmx_mux_reg pmx_i2c1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_i2c1_modes[] = {
+ {
+ .mux_regs = pmx_i2c1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_i2c1_mux),
+ },
+};
+
+struct pmx_dev pmx_i2c1 = {
+ .name = "i2c1",
+ .modes = pmx_i2c1_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
+};
+
+/* Pad multiplexing for smii_0_1_2 device */
+static struct pmx_mux_reg pmx_smii_0_1_2_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
+ PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR1_MASK | \
+ PMX_GPT0_TMR2_MASK | PMX_GPT1_TMR1_MASK | \
+ PMX_GPT1_TMR2_MASK,
+ .value = 0,
+ }, {
+ .address = SPEAR1310_FUNC_CNTL_0,
+ .mask = PMX_SMII_MASK,
+ .value = PMX_SMII_MASK,
+ },
+};
+
+static struct pmx_dev_mode pmx_smii_0_1_2_modes[] = {
+ {
+ .mux_regs = pmx_smii_0_1_2_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_smii_0_1_2_mux),
+ },
+};
+
+struct pmx_dev pmx_smii_0_1_2 = {
+ .name = "smii_0_1_2",
+ .modes = pmx_smii_0_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_smii_0_1_2_modes),
+};
+
+/* Pad multiplexing for pci1 device */
+static struct pmx_mux_reg pmx_pci1_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
+ PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR1_MASK | \
+ PMX_GPT0_TMR2_MASK | PMX_GPT1_TMR1_MASK | \
+ PMX_GPT1_TMR2_MASK,
+ .value = 0,
+ }, {
+ .address = SPEAR1310_FUNC_CNTL_0,
+ .mask = PMX_SMII_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_pci1_modes[] = {
+ {
+ .mux_regs = pmx_pci1_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_pci1_mux),
+ },
+};
+
+struct pmx_dev pmx_pci1 = {
+ .name = "pci1",
+ .modes = pmx_pci1_modes,
+ .mode_count = ARRAY_SIZE(pmx_pci1_modes),
+};
+
+/* Pad multiplexing for can device */
+static struct pmx_mux_reg pmx_can_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_I2S2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_can_modes[] = {
+ {
+ .mux_regs = pmx_can_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_can_mux),
+ },
+};
+
+struct pmx_dev pmx_can = {
+ .name = "can",
+ .modes = pmx_can_modes,
+ .mode_count = ARRAY_SIZE(pmx_can_modes),
+};
+
/* Add spear1310 specific devices here */
/* CAN device registeration */
@@ -83,12 +418,7 @@ void __init spear1310_init(void)
spear13xx_init();
/* pmx initialization */
- pmx_driver.base = ioremap(SPEAR13XX_FUNC_ENB_BASE, SZ_4K);
- if (pmx_driver.base) {
- ret = pmx_register(&pmx_driver);
- if (ret)
- pr_err("padmux: registeration failed. err no: %d\n",
- ret);
- iounmap(pmx_driver.base);
- }
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registeration failed. err no: %d\n", ret);
}
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
index de5a2dc..3a275c1 100644
--- a/arch/arm/mach-spear13xx/spear1310_evb.c
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -31,19 +31,24 @@ static struct pmx_dev *pmx_devs[] = {
/* spear13xx specific devices */
&pmx_i2c,
&pmx_i2s1,
- &pmx_i2s2,
- &pmx_clcd1,
- &pmx_clcd2,
&pmx_egpio_grp,
&pmx_gmii,
- &pmx_keyboard,
+ &pmx_keyboard_6x6,
&pmx_mcif,
&pmx_nand_8bit,
- &pmx_smi_4_chips,
- &pmx_ssp,
+ &pmx_smi_2_chips,
&pmx_uart0,
/* spear1310 specific devices */
+ &pmx_can,
+ &pmx_i2c1,
+ &pmx_smii_0_1_2,
+ &pmx_fsmc16bit_4_chips,
+ &pmx_rs485_hdlc_1_2,
+ &pmx_tdm_hdlc_1_2,
+ &pmx_uart_1,
+ &pmx_uart_2,
+ &pmx_uart_3_4_5,
};
static struct amba_device *amba_devs[] __initdata = {
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index bbcfdf4..19a3eab 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -503,7 +503,7 @@ struct sys_timer spear13xx_timer = {
/* Pad multiplexing for i2c device */
static struct pmx_mux_reg pmx_i2c_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_I2C_MASK,
.value = PMX_I2C_MASK,
},
@@ -525,7 +525,7 @@ struct pmx_dev pmx_i2c = {
/* Pad multiplexing for ssp device */
static struct pmx_mux_reg pmx_ssp_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_SSP_MASK,
.value = PMX_SSP_MASK,
},
@@ -547,7 +547,7 @@ struct pmx_dev pmx_ssp = {
/* Pad multiplexing for i2s1 device */
static struct pmx_mux_reg pmx_i2s1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_I2S1_MASK,
.value = PMX_I2S1_MASK,
},
@@ -569,7 +569,7 @@ struct pmx_dev pmx_i2s1 = {
/* Pad multiplexing for i2s2 device */
static struct pmx_mux_reg pmx_i2s2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_I2S2_MASK,
.value = PMX_I2S2_MASK,
},
@@ -588,48 +588,52 @@ struct pmx_dev pmx_i2s2 = {
.mode_count = ARRAY_SIZE(pmx_i2s2_modes),
};
-/* Pad multiplexing for clcd1 device */
-static struct pmx_mux_reg pmx_clcd1_mux[] = {
+/* Pad multiplexing for clcd device */
+static struct pmx_mux_reg pmx_clcd_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_CLCD1_MASK,
.value = PMX_CLCD1_MASK,
},
};
-static struct pmx_dev_mode pmx_clcd1_modes[] = {
+static struct pmx_dev_mode pmx_clcd_modes[] = {
{
- .mux_regs = pmx_clcd1_mux,
- .mux_reg_cnt = ARRAY_SIZE(pmx_clcd1_mux),
+ .mux_regs = pmx_clcd_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd_mux),
},
};
-struct pmx_dev pmx_clcd1 = {
- .name = "clcd1",
- .modes = pmx_clcd1_modes,
- .mode_count = ARRAY_SIZE(pmx_clcd1_modes),
+struct pmx_dev pmx_clcd = {
+ .name = "clcd",
+ .modes = pmx_clcd_modes,
+ .mode_count = ARRAY_SIZE(pmx_clcd_modes),
};
-/* Pad multiplexing for clcd2 device */
-static struct pmx_mux_reg pmx_clcd2_mux[] = {
+/* Pad multiplexing for clcd_hires device */
+static struct pmx_mux_reg pmx_clcd_hires_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_0,
+ .mask = PMX_CLCD1_MASK,
+ .value = PMX_CLCD1_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_CLCD2_MASK,
.value = PMX_CLCD2_MASK,
},
};
-static struct pmx_dev_mode pmx_clcd2_modes[] = {
+static struct pmx_dev_mode pmx_clcd_hires_modes[] = {
{
- .mux_regs = pmx_clcd2_mux,
- .mux_reg_cnt = ARRAY_SIZE(pmx_clcd2_mux),
+ .mux_regs = pmx_clcd_hires_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_clcd_hires_mux),
},
};
-struct pmx_dev pmx_clcd2 = {
- .name = "clcd2",
- .modes = pmx_clcd2_modes,
- .mode_count = ARRAY_SIZE(pmx_clcd2_modes),
+struct pmx_dev pmx_clcd_hires = {
+ .name = "clcd_high_res",
+ .modes = pmx_clcd_hires_modes,
+ .mode_count = ARRAY_SIZE(pmx_clcd_hires_modes),
};
/*
@@ -638,11 +642,11 @@ struct pmx_dev pmx_clcd2 = {
*/
static struct pmx_mux_reg pmx_egpio_grp_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_EGPIO_0_GRP_MASK,
.value = PMX_EGPIO_0_GRP_MASK,
}, {
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_EGPIO_1_GRP_MASK,
.value = PMX_EGPIO_1_GRP_MASK,
},
@@ -664,7 +668,7 @@ struct pmx_dev pmx_egpio_grp = {
/* Pad multiplexing for smi 2 chips device */
static struct pmx_mux_reg pmx_smi_2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_SMI_MASK,
.value = PMX_SMI_MASK,
},
@@ -686,11 +690,11 @@ struct pmx_dev pmx_smi_2_chips = {
/* Pad multiplexing for smi 4 chips device */
static struct pmx_mux_reg pmx_smi_4_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_SMI_MASK,
.value = PMX_SMI_MASK,
}, {
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
.value = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
},
@@ -712,7 +716,7 @@ struct pmx_dev pmx_smi_4_chips = {
/* Pad multiplexing for gmii device */
static struct pmx_mux_reg pmx_gmii_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_GMII_MASK,
.value = PMX_GMII_MASK,
},
@@ -734,13 +738,13 @@ struct pmx_dev pmx_gmii = {
/* Pad multiplexing for nand 8bit (4 chips) */
static struct pmx_mux_reg pmx_nand8_4_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_NAND8BIT4DEV_0_MASK,
.value = PMX_NAND8BIT4DEV_0_MASK,
}, {
- .offset = PAD_MUX_CONFIG_REG_1,
- .mask = PMX_NAND8BIT4DEV_1_MASK,
- .value = PMX_NAND8BIT4DEV_1_MASK,
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND8BIT4DEV_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_NAND8BIT4DEV_1_MASK | PMX_KEYBOARD_6X6_MASK,
},
};
@@ -757,16 +761,16 @@ struct pmx_dev pmx_nand_8bit_4_chips = {
.mode_count = ARRAY_SIZE(pmx_nand8_4_modes),
};
-/* Pad multiplexing for nand 8bit device */
+/* Pad multiplexing for nand 8bit device (cs0 only) */
static struct pmx_mux_reg pmx_nand8_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_NAND8BIT_0_MASK,
.value = PMX_NAND8BIT_0_MASK,
}, {
- .offset = PAD_MUX_CONFIG_REG_1,
- .mask = PMX_NAND8BIT_1_MASK,
- .value = PMX_NAND8BIT_1_MASK,
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND8BIT_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_NAND8BIT_1_MASK | PMX_KEYBOARD_6X6_MASK,
},
};
@@ -791,13 +795,13 @@ struct pmx_dev pmx_nand_8bit = {
*/
static struct pmx_mux_reg pmx_nand16_4_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_NAND16BIT4DEV_0_MASK,
.value = PMX_NAND16BIT4DEV_0_MASK,
}, {
- .offset = PAD_MUX_CONFIG_REG_1,
- .mask = PMX_NAND16BIT4DEV_1_MASK,
- .value = PMX_NAND16BIT4DEV_1_MASK,
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND16BIT4DEV_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_NAND16BIT4DEV_1_MASK | PMX_KEYBOARD_6X6_MASK,
},
};
@@ -814,16 +818,16 @@ struct pmx_dev pmx_nand_16bit_4_chips = {
.mode_count = ARRAY_SIZE(pmx_nand16_4_modes),
};
-/* Pad multiplexing for nand 16bit device */
+/* Pad multiplexing for nand 16bit device (cs0 only) */
static struct pmx_mux_reg pmx_nand16_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_NAND16BIT_0_MASK,
.value = PMX_NAND16BIT_0_MASK,
}, {
- .offset = PAD_MUX_CONFIG_REG_1,
- .mask = PMX_NAND16BIT_1_MASK,
- .value = PMX_NAND16BIT_1_MASK,
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NAND16BIT_1_MASK | PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_NAND16BIT_1_MASK | PMX_KEYBOARD_6X6_MASK,
},
};
@@ -840,37 +844,64 @@ struct pmx_dev pmx_nand_16bit = {
.mode_count = ARRAY_SIZE(pmx_nand16_modes),
};
-/* Pad multiplexing for keyboard device */
-static struct pmx_mux_reg pmx_keyboard_mux[] = {
+/* Pad multiplexing for keyboard_6x6 device */
+static struct pmx_mux_reg pmx_keyboard_6x6_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
- .mask = PMX_KEYBOARD_MASK,
- .value = PMX_KEYBOARD_MASK,
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_6X6_MASK,
+ .value = PMX_KEYBOARD_6X6_MASK,
}, {
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_NFIO815_MASK | PMX_NFCE1_MASK | \
PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK,
.value = 0,
},
};
-static struct pmx_dev_mode pmx_keyboard_modes[] = {
+static struct pmx_dev_mode pmx_keyboard_6x6_modes[] = {
{
- .mux_regs = pmx_keyboard_mux,
- .mux_reg_cnt = ARRAY_SIZE(pmx_keyboard_mux),
+ .mux_regs = pmx_keyboard_6x6_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_keyboard_6x6_mux),
},
};
-struct pmx_dev pmx_keyboard = {
- .name = "keyboard",
- .modes = pmx_keyboard_modes,
- .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
+struct pmx_dev pmx_keyboard_6x6 = {
+ .name = "keyboard_6x6",
+ .modes = pmx_keyboard_6x6_modes,
+ .mode_count = ARRAY_SIZE(pmx_keyboard_6x6_modes),
+};
+
+/* Pad multiplexing for keyboard_9x9 device */
+static struct pmx_mux_reg pmx_keyboard_9x9_mux[] = {
+ {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_KEYBOARD_6X6_MASK | PMX_KBD_ROWCOL68_MASK,
+ .value = PMX_KEYBOARD_6X6_MASK | PMX_KBD_ROWCOL68_MASK,
+ }, {
+ .address = PAD_MUX_CONFIG_REG_1,
+ .mask = PMX_NFIO815_MASK | PMX_NFCE1_MASK | \
+ PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK,
+ .value = 0,
+ },
+};
+
+static struct pmx_dev_mode pmx_keyboard_9x9_modes[] = {
+ {
+ .mux_regs = pmx_keyboard_9x9_mux,
+ .mux_reg_cnt = ARRAY_SIZE(pmx_keyboard_9x9_mux),
+ },
+};
+
+struct pmx_dev pmx_keyboard_9x9 = {
+ .name = "keyboard_9x9",
+ .modes = pmx_keyboard_9x9_modes,
+ .mode_count = ARRAY_SIZE(pmx_keyboard_9x9_modes),
};
/* Pad multiplexing for uart0 device */
static struct pmx_mux_reg pmx_uart0_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_0,
+ .address = PAD_MUX_CONFIG_REG_0,
.mask = PMX_UART0_MASK,
.value = PMX_UART0_MASK,
},
@@ -892,7 +923,7 @@ struct pmx_dev pmx_uart0 = {
/* Pad multiplexing for uart0_modem device */
static struct pmx_mux_reg pmx_uart0_modem_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_UART0_MODEM_MASK,
.value = PMX_UART0_MODEM_MASK,
},
@@ -914,7 +945,7 @@ struct pmx_dev pmx_uart0_modem = {
/* Pad multiplexing for gpt_0_1 device */
static struct pmx_mux_reg pmx_gpt_0_1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_GPT0_TMR1_MASK,
.value = PMX_GPT0_TMR1_MASK,
},
@@ -936,7 +967,7 @@ struct pmx_dev pmx_gpt_0_1 = {
/* Pad multiplexing for gpt_0_2 device */
static struct pmx_mux_reg pmx_gpt_0_2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_GPT0_TMR2_MASK,
.value = PMX_GPT0_TMR2_MASK,
},
@@ -958,7 +989,7 @@ struct pmx_dev pmx_gpt_0_2 = {
/* Pad multiplexing for gpt_1_1 device */
static struct pmx_mux_reg pmx_gpt_1_1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_GPT1_TMR1_MASK,
.value = PMX_GPT1_TMR1_MASK,
},
@@ -980,7 +1011,7 @@ struct pmx_dev pmx_gpt_1_1 = {
/* Pad multiplexing for gpt_1_2 device */
static struct pmx_mux_reg pmx_gpt_1_2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_GPT1_TMR2_MASK,
.value = PMX_GPT1_TMR2_MASK,
},
@@ -1002,11 +1033,11 @@ struct pmx_dev pmx_gpt_1_2 = {
/* Pad multiplexing for mcif device */
static struct pmx_mux_reg pmx_mcif_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG_1,
+ .address = PAD_MUX_CONFIG_REG_1,
.mask = PMX_MCIFALL_1_MASK,
.value = PMX_MCIFALL_1_MASK,
}, {
- .offset = PAD_MUX_CONFIG_REG_2,
+ .address = PAD_MUX_CONFIG_REG_2,
.mask = PMX_MCIFALL_2_MASK,
.value = PMX_MCIFALL_2_MASK,
},
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 990e5b7..6b46a91 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -147,7 +147,10 @@ extern struct pmx_dev pmx_telecom_boot_pins;
extern struct pmx_dev pmx_telecom_sdhci_4bit;
extern struct pmx_dev pmx_telecom_sdhci_8bit;
extern struct pmx_dev pmx_gpio1;
-#define PAD_MUX_CONFIG_REG 0x00
+
+/* pad multiplexing support */
+#define PAD_MUX_CONFIG_REG 0x99000000
+#define MODE_CONFIG_REG 0x99000004
/* Add spear300 machine function declarations here */
void __init spear300_init(void);
@@ -179,7 +182,7 @@ extern struct pmx_dev pmx_uart3_4_5;
extern struct pmx_dev pmx_fsmc;
extern struct pmx_dev pmx_rs485_0_1;
extern struct pmx_dev pmx_tdm0;
-#define PAD_MUX_CONFIG_REG 0x08
+#define PAD_MUX_CONFIG_REG 0xB4000008
/* Add spear310 machine function declarations here */
void __init spear310_init(void);
@@ -229,7 +232,10 @@ extern struct pmx_dev pmx_mii1;
extern struct pmx_dev pmx_smii0;
extern struct pmx_dev pmx_smii1;
extern struct pmx_dev pmx_i2c1;
-#define PAD_MUX_CONFIG_REG 0x0C
+
+/* pad multiplexing support */
+#define PAD_MUX_CONFIG_REG 0xB300000C
+#define MODE_CONFIG_REG 0xB3000010
/* Add spear320 machine function declarations here */
void __init spear320_init(void);
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index c723515..4fd2d22 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -45,7 +45,6 @@
#define SPEAR300_NOR_2_BASE UL(0x92000000)
#define SPEAR300_NOR_3_BASE UL(0x93000000)
#define SPEAR300_FSMC_BASE UL(0x94000000)
-#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
#define SPEAR300_GPIO_BASE UL(0xA9000000)
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 91e25d7..78925db 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -20,9 +20,6 @@
#include <mach/spear.h>
#include <plat/shirq.h>
-/* pad multiplexing support */
-#define MODE_CONFIG_REG 0x04
-
/* modes */
#define NAND_MODE (1 << 0)
#define NOR_MODE (1 << 1)
@@ -121,7 +118,7 @@ struct pmx_mode caml_lcd_mode = {
/* Pad multiplexing for FSMC 2 NAND devices */
static struct pmx_mux_reg pmx_fsmc_2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = 0,
},
@@ -145,7 +142,7 @@ struct pmx_dev pmx_fsmc_2_chips = {
/* Pad multiplexing for FSMC 4 NAND devices */
static struct pmx_mux_reg pmx_fsmc_4_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
.value = 0,
},
@@ -169,7 +166,7 @@ struct pmx_dev pmx_fsmc_4_chips = {
/* Pad multiplexing for Keyboard device */
static struct pmx_mux_reg pmx_kbd_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -195,7 +192,7 @@ struct pmx_dev pmx_keyboard = {
/* Pad multiplexing for CLCD device */
static struct pmx_mux_reg pmx_clcd_pfmode_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -203,7 +200,7 @@ static struct pmx_mux_reg pmx_clcd_pfmode_mux[] = {
static struct pmx_mux_reg pmx_clcd_lcdmode_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -231,7 +228,7 @@ struct pmx_dev pmx_clcd = {
/* Pad multiplexing for Telecom GPIO device */
static struct pmx_mux_reg pmx_gpio_lcdmode_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -239,7 +236,7 @@ static struct pmx_mux_reg pmx_gpio_lcdmode_mux[] = {
static struct pmx_mux_reg pmx_gpio_fonemode_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -247,7 +244,7 @@ static struct pmx_mux_reg pmx_gpio_fonemode_mux[] = {
static struct pmx_mux_reg pmx_gpio_atai2smode_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -255,7 +252,7 @@ static struct pmx_mux_reg pmx_gpio_atai2smode_mux[] = {
static struct pmx_mux_reg pmx_gpio_lendfonemode_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -263,7 +260,7 @@ static struct pmx_mux_reg pmx_gpio_lendfonemode_mux[] = {
static struct pmx_mux_reg pmx_gpio_atawi2smode_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
| PMX_UART0_MODEM_MASK,
.value = 0,
@@ -303,7 +300,7 @@ struct pmx_dev pmx_telecom_gpio = {
/* Pad multiplexing for TDM device */
static struct pmx_mux_reg pmx_tdm_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
.value = 0,
},
@@ -330,7 +327,7 @@ struct pmx_dev pmx_telecom_tdm = {
/* Pad multiplexing for spi cs i2c device */
static struct pmx_mux_reg pmx_spi_cs_i2c_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -355,7 +352,7 @@ struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
static struct pmx_mux_reg pmx_caml_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -363,7 +360,7 @@ static struct pmx_mux_reg pmx_caml_mux[] = {
static struct pmx_mux_reg pmx_camu_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
.value = 0,
},
@@ -390,7 +387,7 @@ struct pmx_dev pmx_telecom_camera = {
/* Pad multiplexing for dac device */
static struct pmx_mux_reg pmx_dac_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -414,7 +411,7 @@ struct pmx_dev pmx_telecom_dac = {
/* Pad multiplexing for spi cs i2c device */
static struct pmx_mux_reg pmx_i2s_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -440,7 +437,7 @@ struct pmx_dev pmx_telecom_i2s = {
/* Pad multiplexing for bootpins device */
static struct pmx_mux_reg pmx_bootpins_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
PMX_TIMER_3_4_MASK,
.value = 0,
@@ -464,7 +461,7 @@ struct pmx_dev pmx_telecom_boot_pins = {
/* Pad multiplexing for sdhci 4bit device */
static struct pmx_mux_reg pmx_sdhci_4bit_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
@@ -493,7 +490,7 @@ struct pmx_dev pmx_telecom_sdhci_4bit = {
/* Pad multiplexing for spi cs i2c device */
static struct pmx_mux_reg pmx_sdhci_8bit_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
@@ -521,7 +518,7 @@ struct pmx_dev pmx_telecom_sdhci_8bit = {
/* Pad multiplexing for spi cs i2c device */
static struct pmx_mux_reg pmx_gpio1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
PMX_TIMER_3_4_MASK,
.value = 0,
@@ -544,7 +541,7 @@ struct pmx_dev pmx_gpio1 = {
/* pmx driver structure */
struct pmx_driver pmx_driver = {
- .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
+ .mode_reg = {.address = MODE_CONFIG_REG, .mask = 0x0000000f},
};
/* Add spear300 specific devices here */
@@ -780,18 +777,20 @@ struct spear_shirq shirq_ras1 = {
void sdhci_i2s_mem_enable(u8 mask)
{
u32 val;
- void __iomem *base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
- if (!base) {
+ void __iomem *config = ioremap(MODE_CONFIG_REG, SZ_16);
+ if (!config) {
pr_debug("sdhci_i2s_enb: ioremap fail\n");
return;
}
- val = readl(base + MODE_CONFIG_REG);
+ val = readl(config);
if (mask == SDHCI_MEM_ENB)
val |= SDHCI_MEM_SELECT;
else
val &= ~SDHCI_MEM_SELECT;
- writel(val, base + MODE_CONFIG_REG);
+ writel(val, config);
+
+ iounmap(config);
}
/* spear300 routines */
@@ -811,13 +810,7 @@ void __init spear300_init(void)
}
/* pmx initialization */
- pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
- if (pmx_driver.base) {
- ret = pmx_register(&pmx_driver);
- if (ret)
- printk(KERN_ERR "padmux: registeration failed. err no"
- ": %d\n", ret);
- /* Free Mapping, device selection already done */
- iounmap(pmx_driver.base);
- }
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registeration failed. err no: %d\n", ret);
}
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 3a2ed0d..1673b63 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -26,7 +26,7 @@
/* Pad multiplexing for emi_cs_0_1_4_5 devices */
static struct pmx_mux_reg pmx_emi_cs_0_1_4_5_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -48,7 +48,7 @@ struct pmx_dev pmx_emi_cs_0_1_4_5 = {
/* Pad multiplexing for emi_cs_2_3 devices */
static struct pmx_mux_reg pmx_emi_cs_2_3_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -70,7 +70,7 @@ struct pmx_dev pmx_emi_cs_2_3 = {
/* Pad multiplexing for uart1 device */
static struct pmx_mux_reg pmx_uart1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = 0,
},
@@ -92,7 +92,7 @@ struct pmx_dev pmx_uart1 = {
/* Pad multiplexing for uart2 device */
static struct pmx_mux_reg pmx_uart2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -114,7 +114,7 @@ struct pmx_dev pmx_uart2 = {
/* Pad multiplexing for uart3_4_5 devices */
static struct pmx_mux_reg pmx_uart3_4_5_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -136,7 +136,7 @@ struct pmx_dev pmx_uart3_4_5 = {
/* Pad multiplexing for fsmc device */
static struct pmx_mux_reg pmx_fsmc_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -158,7 +158,7 @@ struct pmx_dev pmx_fsmc = {
/* Pad multiplexing for rs485_0_1 devices */
static struct pmx_mux_reg pmx_rs485_0_1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -180,7 +180,7 @@ struct pmx_dev pmx_rs485_0_1 = {
/* Pad multiplexing for tdm0 device */
static struct pmx_mux_reg pmx_tdm0_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -524,9 +524,7 @@ void __init spear310_init(void)
}
/* pmx initialization */
- pmx_driver.base = base;
ret = pmx_register(&pmx_driver);
if (ret)
- printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
- ret);
+ pr_err("padmux: registeration failed. err no: %d\n", ret);
}
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 2bdd798..7f576dd 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -23,9 +23,6 @@
#include <plat/gpio.h>
#include <plat/shirq.h>
-/* pad multiplexing support */
-#define MODE_CONFIG_REG 0x10
-
/* modes */
#define AUTO_NET_SMII_MODE (1 << 0)
#define AUTO_NET_MII_MODE (1 << 1)
@@ -61,7 +58,7 @@ struct pmx_mode small_printers_mode = {
/* Pad multiplexing for CLCD device */
static struct pmx_mux_reg pmx_clcd_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -84,7 +81,7 @@ struct pmx_dev pmx_clcd = {
/* Pad multiplexing for EMI (Parallel NOR flash) device */
static struct pmx_mux_reg pmx_emi_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -107,7 +104,7 @@ struct pmx_dev pmx_emi = {
/* Pad multiplexing for FSMC (NAND flash) device */
static struct pmx_mux_reg pmx_fsmc_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -130,7 +127,7 @@ struct pmx_dev pmx_fsmc = {
/* Pad multiplexing for SPP device */
static struct pmx_mux_reg pmx_spp_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -153,7 +150,7 @@ struct pmx_dev pmx_spp = {
/* Pad multiplexing for SDHCI device */
static struct pmx_mux_reg pmx_sdhci_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -177,7 +174,7 @@ struct pmx_dev pmx_sdhci = {
/* Pad multiplexing for I2S device */
static struct pmx_mux_reg pmx_i2s_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -200,7 +197,7 @@ struct pmx_dev pmx_i2s = {
/* Pad multiplexing for UART1 device */
static struct pmx_mux_reg pmx_uart1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
.value = 0,
},
@@ -223,7 +220,7 @@ struct pmx_dev pmx_uart1 = {
/* Pad multiplexing for UART1 Modem device */
static struct pmx_mux_reg pmx_uart1_modem_autoexp_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
PMX_SSP_CS_MASK,
.value = 0,
@@ -232,7 +229,7 @@ static struct pmx_mux_reg pmx_uart1_modem_autoexp_mux[] = {
static struct pmx_mux_reg pmx_uart1_modem_smallpri_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
.value = 0,
@@ -260,7 +257,7 @@ struct pmx_dev pmx_uart1_modem = {
/* Pad multiplexing for UART2 device */
static struct pmx_mux_reg pmx_uart2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = 0,
},
@@ -283,7 +280,7 @@ struct pmx_dev pmx_uart2 = {
/* Pad multiplexing for Touchscreen device */
static struct pmx_mux_reg pmx_touchscreen_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -306,7 +303,7 @@ struct pmx_dev pmx_touchscreen = {
/* Pad multiplexing for CAN device */
static struct pmx_mux_reg pmx_can_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
.value = 0,
@@ -330,7 +327,7 @@ struct pmx_dev pmx_can = {
/* Pad multiplexing for SDHCI LED device */
static struct pmx_mux_reg pmx_sdhci_led_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -353,7 +350,7 @@ struct pmx_dev pmx_sdhci_led = {
/* Pad multiplexing for PWM0 device */
static struct pmx_mux_reg pmx_pwm0_net_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -361,7 +358,7 @@ static struct pmx_mux_reg pmx_pwm0_net_mux[] = {
static struct pmx_mux_reg pmx_pwm0_autoexpsmallpri_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -388,7 +385,7 @@ struct pmx_dev pmx_pwm0 = {
/* Pad multiplexing for PWM1 device */
static struct pmx_mux_reg pmx_pwm1_net_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -396,7 +393,7 @@ static struct pmx_mux_reg pmx_pwm1_net_mux[] = {
static struct pmx_mux_reg pmx_pwm1_autoexpsmallpri_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -423,7 +420,7 @@ struct pmx_dev pmx_pwm1 = {
/* Pad multiplexing for PWM2 device */
static struct pmx_mux_reg pmx_pwm2_net_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -431,7 +428,7 @@ static struct pmx_mux_reg pmx_pwm2_net_mux[] = {
static struct pmx_mux_reg pmx_pwm2_autoexpsmallpri_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -458,7 +455,7 @@ struct pmx_dev pmx_pwm2 = {
/* Pad multiplexing for PWM3 device */
static struct pmx_mux_reg pmx_pwm3_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -481,7 +478,7 @@ struct pmx_dev pmx_pwm3 = {
/* Pad multiplexing for SSP1 device */
static struct pmx_mux_reg pmx_ssp1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -504,7 +501,7 @@ struct pmx_dev pmx_ssp1 = {
/* Pad multiplexing for SSP2 device */
static struct pmx_mux_reg pmx_ssp2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -527,7 +524,7 @@ struct pmx_dev pmx_ssp2 = {
/* Pad multiplexing for mii1 device */
static struct pmx_mux_reg pmx_mii1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -550,7 +547,7 @@ struct pmx_dev pmx_mii1 = {
/* Pad multiplexing for smii0 device */
static struct pmx_mux_reg pmx_smii0_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -573,7 +570,7 @@ struct pmx_dev pmx_smii0 = {
/* Pad multiplexing for smii1 device */
static struct pmx_mux_reg pmx_smii1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -596,7 +593,7 @@ struct pmx_dev pmx_smii1 = {
/* Pad multiplexing for i2c1 device */
static struct pmx_mux_reg pmx_i2c1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -618,7 +615,7 @@ struct pmx_dev pmx_i2c1 = {
/* pmx driver structure */
struct pmx_driver pmx_driver = {
- .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
+ .mode_reg = {.address = MODE_CONFIG_REG, .mask = 0x00000007},
};
/* Add spear320 specific devices here */
@@ -1019,9 +1016,7 @@ void __init spear320_init(void)
}
/* pmx initialization */
- pmx_driver.base = base;
ret = pmx_register(&pmx_driver);
if (ret)
- printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
- ret);
+ pr_err("padmux: registeration failed. err no: %d\n", ret);
}
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 7ea3a25..c4e4b1b 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -278,7 +278,7 @@ void __init spear3xx_map_io(void)
/* Pad multiplexing for firda device */
static struct pmx_mux_reg pmx_firda_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = PMX_FIRDA_MASK,
},
@@ -301,7 +301,7 @@ struct pmx_dev pmx_firda = {
/* Pad multiplexing for i2c device */
static struct pmx_mux_reg pmx_i2c_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_I2C_MASK,
.value = PMX_I2C_MASK,
},
@@ -324,7 +324,7 @@ struct pmx_dev pmx_i2c = {
/* Pad multiplexing for firda device */
static struct pmx_mux_reg pmx_ssp_cs_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = PMX_SSP_CS_MASK,
},
@@ -347,7 +347,7 @@ struct pmx_dev pmx_ssp_cs = {
/* Pad multiplexing for ssp device */
static struct pmx_mux_reg pmx_ssp_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_MASK,
.value = PMX_SSP_MASK,
},
@@ -370,7 +370,7 @@ struct pmx_dev pmx_ssp = {
/* Pad multiplexing for mii device */
static struct pmx_mux_reg pmx_mii_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = PMX_MII_MASK,
},
@@ -393,7 +393,7 @@ struct pmx_dev pmx_mii = {
/* Pad multiplexing for gpio pin0 device */
static struct pmx_mux_reg pmx_gpio_pin0_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK,
.value = PMX_GPIO_PIN0_MASK,
},
@@ -416,7 +416,7 @@ struct pmx_dev pmx_gpio_pin0 = {
/* Pad multiplexing for gpio pin1 device */
static struct pmx_mux_reg pmx_gpio_pin1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN1_MASK,
.value = PMX_GPIO_PIN1_MASK,
},
@@ -439,7 +439,7 @@ struct pmx_dev pmx_gpio_pin1 = {
/* Pad multiplexing for gpio pin2 device */
static struct pmx_mux_reg pmx_gpio_pin2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK,
.value = PMX_GPIO_PIN2_MASK,
},
@@ -462,7 +462,7 @@ struct pmx_dev pmx_gpio_pin2 = {
/* Pad multiplexing for gpio pin3 device */
static struct pmx_mux_reg pmx_gpio_pin3_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK,
.value = PMX_GPIO_PIN3_MASK,
},
@@ -485,7 +485,7 @@ struct pmx_dev pmx_gpio_pin3 = {
/* Pad multiplexing for gpio pin4 device */
static struct pmx_mux_reg pmx_gpio_pin4_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN4_MASK,
.value = PMX_GPIO_PIN4_MASK,
},
@@ -508,7 +508,7 @@ struct pmx_dev pmx_gpio_pin4 = {
/* Pad multiplexing for gpio pin5 device */
static struct pmx_mux_reg pmx_gpio_pin5_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN5_MASK,
.value = PMX_GPIO_PIN5_MASK,
},
@@ -531,7 +531,7 @@ struct pmx_dev pmx_gpio_pin5 = {
/* Pad multiplexing for uart0 modem device */
static struct pmx_mux_reg pmx_uart0_modem_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = PMX_UART0_MODEM_MASK,
},
@@ -554,7 +554,7 @@ struct pmx_dev pmx_uart0_modem = {
/* Pad multiplexing for uart0 device */
static struct pmx_mux_reg pmx_uart0_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MASK,
.value = PMX_UART0_MASK,
},
@@ -577,7 +577,7 @@ struct pmx_dev pmx_uart0 = {
/* Pad multiplexing for timer 3, 4 device */
static struct pmx_mux_reg pmx_timer_3_4_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
.value = PMX_TIMER_3_4_MASK,
},
@@ -600,7 +600,7 @@ struct pmx_dev pmx_timer_3_4 = {
/* Pad multiplexing for gpio pin0 device */
static struct pmx_mux_reg pmx_timer_1_2_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = PMX_TIMER_1_2_MASK,
},
@@ -625,7 +625,7 @@ struct pmx_dev pmx_timer_1_2 = {
/* Pad multiplexing for plgpio_0_1 devices */
static struct pmx_mux_reg pmx_plgpio_0_1_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = 0,
},
@@ -648,7 +648,7 @@ struct pmx_dev pmx_plgpio_0_1 = {
/* Pad multiplexing for plgpio_2_3 devices */
static struct pmx_mux_reg pmx_plgpio_2_3_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MASK,
.value = 0,
},
@@ -671,7 +671,7 @@ struct pmx_dev pmx_plgpio_2_3 = {
/* Pad multiplexing for plgpio_4_5 devices */
static struct pmx_mux_reg pmx_plgpio_4_5_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_I2C_MASK,
.value = 0,
},
@@ -694,7 +694,7 @@ struct pmx_dev pmx_plgpio_4_5 = {
/* Pad multiplexing for plgpio_6_9 devices */
static struct pmx_mux_reg pmx_plgpio_6_9_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_MASK,
.value = 0,
},
@@ -717,7 +717,7 @@ struct pmx_dev pmx_plgpio_6_9 = {
/* Pad multiplexing for plgpio_10_27 devices */
static struct pmx_mux_reg pmx_plgpio_10_27_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -740,7 +740,7 @@ struct pmx_dev pmx_plgpio_10_27 = {
/* Pad multiplexing for plgpio_28 devices */
static struct pmx_mux_reg pmx_plgpio_28_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK,
.value = 0,
},
@@ -763,7 +763,7 @@ struct pmx_dev pmx_plgpio_28 = {
/* Pad multiplexing for plgpio_29 devices */
static struct pmx_mux_reg pmx_plgpio_29_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN1_MASK,
.value = 0,
},
@@ -786,7 +786,7 @@ struct pmx_dev pmx_plgpio_29 = {
/* Pad multiplexing for plgpio_30 device */
static struct pmx_mux_reg pmx_plgpio_30_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK,
.value = 0,
},
@@ -809,7 +809,7 @@ struct pmx_dev pmx_plgpio_30 = {
/* Pad multiplexing for plgpio_31 device */
static struct pmx_mux_reg pmx_plgpio_31_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK,
.value = 0,
},
@@ -832,7 +832,7 @@ struct pmx_dev pmx_plgpio_31 = {
/* Pad multiplexing for plgpio_32 device */
static struct pmx_mux_reg pmx_plgpio_32_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN4_MASK,
.value = 0,
},
@@ -855,7 +855,7 @@ struct pmx_dev pmx_plgpio_32 = {
/* Pad multiplexing for plgpio_33 device */
static struct pmx_mux_reg pmx_plgpio_33_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN5_MASK,
.value = 0,
},
@@ -878,7 +878,7 @@ struct pmx_dev pmx_plgpio_33 = {
/* Pad multiplexing for plgpio_34_36 device */
static struct pmx_mux_reg pmx_plgpio_34_36_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -901,7 +901,7 @@ struct pmx_dev pmx_plgpio_34_36 = {
/* Pad multiplexing for plgpio_37_42 device */
static struct pmx_mux_reg pmx_plgpio_37_42_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -924,7 +924,7 @@ struct pmx_dev pmx_plgpio_37_42 = {
/* Pad multiplexing for plgpio_43_44_47_48 device */
static struct pmx_mux_reg pmx_plgpio_43_44_47_48_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -947,7 +947,7 @@ struct pmx_dev pmx_plgpio_43_44_47_48 = {
/* Pad multiplexing for plgpio_45_46_49_50 device */
static struct pmx_mux_reg pmx_plgpio_45_46_49_50_mux[] = {
{
- .offset = PAD_MUX_CONFIG_REG,
+ .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
.value = 0,
},
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
index 1b69ca5..1959235 100644
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ b/arch/arm/plat-spear/include/plat/padmux.h
@@ -19,23 +19,23 @@
/*
* struct pmx_reg: configuration structure for mode reg and mux reg
*
- * offset: offset of mode reg
+ * address: physical address of mode reg
* mask: mask of mode reg
*/
struct pmx_reg {
- u32 offset;
+ u32 address;
u32 mask;
};
/*
* struct pmx_mux_reg: configuration structure every group of modes of a device
*
- * offset: multiplexing register offset
+ * address: physical address of multiplexing register
* mask: mask for supported mode
* value: value to be written
*/
struct pmx_mux_reg {
- u32 offset;
+ u32 address;
u32 mask;
u32 value;
};
@@ -87,14 +87,12 @@ struct pmx_dev {
* mode: mode to be set
* devs: array of pointer to pmx devices
* devs_count: ARRAY_SIZE of devs
- * base: base address of soc config registers
* mode_reg: structure of mode config register
*/
struct pmx_driver {
struct pmx_mode *mode;
struct pmx_dev **devs;
u8 devs_count;
- u32 *base;
struct pmx_reg mode_reg;
};
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
index f30f94b..97e4d96 100644
--- a/arch/arm/plat-spear/padmux.c
+++ b/arch/arm/plat-spear/padmux.c
@@ -19,12 +19,10 @@
/*
* struct pmx: pmx definition structure
*
- * base: base address of configuration registers
* mode_reg: mode configurations
* active_mode: pointer to current active mode
*/
struct pmx {
- u32 base;
struct pmx_reg mode_reg;
struct pmx_mode *active_mode;
};
@@ -40,17 +38,22 @@ static struct pmx *pmx;
*/
static int pmx_mode_set(struct pmx_mode *mode)
{
- u32 val;
+ u32 val, *address;
if (!mode->name)
return -EFAULT;
pmx->active_mode = mode;
- val = readl(pmx->base + pmx->mode_reg.offset);
- val &= ~pmx->mode_reg.mask;
- val |= mode->value & pmx->mode_reg.mask;
- writel(val, pmx->base + pmx->mode_reg.offset);
+ address = ioremap(pmx->mode_reg.address, SZ_16);
+ if (address) {
+ val = readl(address);
+ val &= ~pmx->mode_reg.mask;
+ val |= mode->value & pmx->mode_reg.mask;
+ writel(val, address);
+
+ iounmap(address);
+ }
return 0;
}
@@ -70,6 +73,7 @@ static int pmx_mode_set(struct pmx_mode *mode)
static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
{
u32 val, i;
+ u32 *address;
if (!count)
return -EINVAL;
@@ -104,10 +108,15 @@ static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
struct pmx_mux_reg *mux_reg =
&devs[i]->modes[j].mux_regs[k];
- val = readl(pmx->base + mux_reg->offset);
- val &= ~mux_reg->mask;
- val |= mux_reg->value & mux_reg->mask;
- writel(val, pmx->base + mux_reg->offset);
+ address = ioremap(mux_reg->address, SZ_16);
+ if (address) {
+ val = readl(address);
+ val &= ~mux_reg->mask;
+ val |= mux_reg->value & mux_reg->mask;
+ writel(val, address);
+
+ iounmap(address);
+ }
}
devs[i]->is_active = true;
@@ -134,15 +143,14 @@ int pmx_register(struct pmx_driver *driver)
if (pmx)
return -EPERM;
- if (!driver->base || !driver->devs)
+ if (!driver->devs)
return -EFAULT;
pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
if (!pmx)
return -ENOMEM;
- pmx->base = (u32)driver->base;
- pmx->mode_reg.offset = driver->mode_reg.offset;
+ pmx->mode_reg.address = driver->mode_reg.address;
pmx->mode_reg.mask = driver->mode_reg.mask;
/* choose mode to enable */
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 48/62] ST SPEAr3xx: Passing pmx devices address from machine *.c files
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (45 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 47/62] SPEAr : Updating pad multiplexing support Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 49/62] ST SPEAr Clock Framework: Updating for single image solution Viresh Kumar
` (14 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
All spear3xx machines have different pad mux register addresses.
In order to have single image for all spear3xx boards, we need to pass
this address from machine specific files to fix addresses of pmx devs found
in spear3xx.c
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 11 +++---
arch/arm/mach-spear3xx/spear300.c | 27 +++-----------
arch/arm/mach-spear3xx/spear310.c | 11 ++----
arch/arm/mach-spear3xx/spear320.c | 31 ++--------------
arch/arm/mach-spear3xx/spear3xx.c | 48 +++++++++---------------
5 files changed, 36 insertions(+), 92 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 6b46a91..eb4c85a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -49,6 +49,7 @@ void __init spear_setup_timer(void);
void __init spear3xx_map_io(void);
void __init spear3xx_init_irq(void);
void __init spear3xx_init(void);
+void spear3xx_pmx_init_addr(struct pmx_driver *driver, unsigned int addr);
/* pad mux declarations */
#define PMX_FIRDA_MASK (1 << 14)
@@ -149,8 +150,8 @@ extern struct pmx_dev pmx_telecom_sdhci_8bit;
extern struct pmx_dev pmx_gpio1;
/* pad multiplexing support */
-#define PAD_MUX_CONFIG_REG 0x99000000
-#define MODE_CONFIG_REG 0x99000004
+#define SPEAR300_PAD_MUX_CONFIG_REG 0x99000000
+#define SPEAR300_MODE_CONFIG_REG 0x99000004
/* Add spear300 machine function declarations here */
void __init spear300_init(void);
@@ -182,7 +183,7 @@ extern struct pmx_dev pmx_uart3_4_5;
extern struct pmx_dev pmx_fsmc;
extern struct pmx_dev pmx_rs485_0_1;
extern struct pmx_dev pmx_tdm0;
-#define PAD_MUX_CONFIG_REG 0xB4000008
+#define SPEAR310_PAD_MUX_CONFIG_REG 0xB4000008
/* Add spear310 machine function declarations here */
void __init spear310_init(void);
@@ -234,8 +235,8 @@ extern struct pmx_dev pmx_smii1;
extern struct pmx_dev pmx_i2c1;
/* pad multiplexing support */
-#define PAD_MUX_CONFIG_REG 0xB300000C
-#define MODE_CONFIG_REG 0xB3000010
+#define SPEAR320_PAD_MUX_CONFIG_REG 0xB300000C
+#define SPEAR320_MODE_CONFIG_REG 0xB3000010
/* Add spear320 machine function declarations here */
void __init spear320_init(void);
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 78925db..313938f 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -118,7 +118,6 @@ struct pmx_mode caml_lcd_mode = {
/* Pad multiplexing for FSMC 2 NAND devices */
static struct pmx_mux_reg pmx_fsmc_2_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = 0,
},
@@ -142,7 +141,6 @@ struct pmx_dev pmx_fsmc_2_chips = {
/* Pad multiplexing for FSMC 4 NAND devices */
static struct pmx_mux_reg pmx_fsmc_4_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
.value = 0,
},
@@ -166,7 +164,6 @@ struct pmx_dev pmx_fsmc_4_chips = {
/* Pad multiplexing for Keyboard device */
static struct pmx_mux_reg pmx_kbd_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -192,7 +189,6 @@ struct pmx_dev pmx_keyboard = {
/* Pad multiplexing for CLCD device */
static struct pmx_mux_reg pmx_clcd_pfmode_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -200,7 +196,6 @@ static struct pmx_mux_reg pmx_clcd_pfmode_mux[] = {
static struct pmx_mux_reg pmx_clcd_lcdmode_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -228,7 +223,6 @@ struct pmx_dev pmx_clcd = {
/* Pad multiplexing for Telecom GPIO device */
static struct pmx_mux_reg pmx_gpio_lcdmode_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -236,7 +230,6 @@ static struct pmx_mux_reg pmx_gpio_lcdmode_mux[] = {
static struct pmx_mux_reg pmx_gpio_fonemode_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -244,7 +237,6 @@ static struct pmx_mux_reg pmx_gpio_fonemode_mux[] = {
static struct pmx_mux_reg pmx_gpio_atai2smode_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -252,7 +244,6 @@ static struct pmx_mux_reg pmx_gpio_atai2smode_mux[] = {
static struct pmx_mux_reg pmx_gpio_lendfonemode_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -260,7 +251,6 @@ static struct pmx_mux_reg pmx_gpio_lendfonemode_mux[] = {
static struct pmx_mux_reg pmx_gpio_atawi2smode_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
| PMX_UART0_MODEM_MASK,
.value = 0,
@@ -300,7 +290,6 @@ struct pmx_dev pmx_telecom_gpio = {
/* Pad multiplexing for TDM device */
static struct pmx_mux_reg pmx_tdm_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
.value = 0,
},
@@ -327,7 +316,6 @@ struct pmx_dev pmx_telecom_tdm = {
/* Pad multiplexing for spi cs i2c device */
static struct pmx_mux_reg pmx_spi_cs_i2c_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -352,7 +340,6 @@ struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
static struct pmx_mux_reg pmx_caml_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -360,7 +347,6 @@ static struct pmx_mux_reg pmx_caml_mux[] = {
static struct pmx_mux_reg pmx_camu_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
.value = 0,
},
@@ -387,7 +373,6 @@ struct pmx_dev pmx_telecom_camera = {
/* Pad multiplexing for dac device */
static struct pmx_mux_reg pmx_dac_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -411,7 +396,6 @@ struct pmx_dev pmx_telecom_dac = {
/* Pad multiplexing for spi cs i2c device */
static struct pmx_mux_reg pmx_i2s_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -437,7 +421,6 @@ struct pmx_dev pmx_telecom_i2s = {
/* Pad multiplexing for bootpins device */
static struct pmx_mux_reg pmx_bootpins_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
PMX_TIMER_3_4_MASK,
.value = 0,
@@ -461,7 +444,6 @@ struct pmx_dev pmx_telecom_boot_pins = {
/* Pad multiplexing for sdhci 4bit device */
static struct pmx_mux_reg pmx_sdhci_4bit_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
@@ -490,7 +472,6 @@ struct pmx_dev pmx_telecom_sdhci_4bit = {
/* Pad multiplexing for spi cs i2c device */
static struct pmx_mux_reg pmx_sdhci_8bit_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
@@ -518,7 +499,6 @@ struct pmx_dev pmx_telecom_sdhci_8bit = {
/* Pad multiplexing for spi cs i2c device */
static struct pmx_mux_reg pmx_gpio1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
PMX_TIMER_3_4_MASK,
.value = 0,
@@ -541,7 +521,7 @@ struct pmx_dev pmx_gpio1 = {
/* pmx driver structure */
struct pmx_driver pmx_driver = {
- .mode_reg = {.address = MODE_CONFIG_REG, .mask = 0x0000000f},
+ .mode_reg = {.address = SPEAR300_MODE_CONFIG_REG, .mask = 0x0000000f},
};
/* Add spear300 specific devices here */
@@ -777,7 +757,7 @@ struct spear_shirq shirq_ras1 = {
void sdhci_i2s_mem_enable(u8 mask)
{
u32 val;
- void __iomem *config = ioremap(MODE_CONFIG_REG, SZ_16);
+ void __iomem *config = ioremap(SPEAR300_MODE_CONFIG_REG, SZ_16);
if (!config) {
pr_debug("sdhci_i2s_enb: ioremap fail\n");
return;
@@ -809,6 +789,9 @@ void __init spear300_init(void)
printk(KERN_ERR "Error registering Shared IRQ\n");
}
+ /* This fixes addresses of all pmx devices for spear300 */
+ spear3xx_pmx_init_addr(&pmx_driver, SPEAR300_PAD_MUX_CONFIG_REG);
+
/* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 1673b63..4192ed2 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -26,7 +26,6 @@
/* Pad multiplexing for emi_cs_0_1_4_5 devices */
static struct pmx_mux_reg pmx_emi_cs_0_1_4_5_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -48,7 +47,6 @@ struct pmx_dev pmx_emi_cs_0_1_4_5 = {
/* Pad multiplexing for emi_cs_2_3 devices */
static struct pmx_mux_reg pmx_emi_cs_2_3_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -70,7 +68,6 @@ struct pmx_dev pmx_emi_cs_2_3 = {
/* Pad multiplexing for uart1 device */
static struct pmx_mux_reg pmx_uart1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = 0,
},
@@ -92,7 +89,6 @@ struct pmx_dev pmx_uart1 = {
/* Pad multiplexing for uart2 device */
static struct pmx_mux_reg pmx_uart2_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -114,7 +110,6 @@ struct pmx_dev pmx_uart2 = {
/* Pad multiplexing for uart3_4_5 devices */
static struct pmx_mux_reg pmx_uart3_4_5_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -136,7 +131,6 @@ struct pmx_dev pmx_uart3_4_5 = {
/* Pad multiplexing for fsmc device */
static struct pmx_mux_reg pmx_fsmc_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -158,7 +152,6 @@ struct pmx_dev pmx_fsmc = {
/* Pad multiplexing for rs485_0_1 devices */
static struct pmx_mux_reg pmx_rs485_0_1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -180,7 +173,6 @@ struct pmx_dev pmx_rs485_0_1 = {
/* Pad multiplexing for tdm0 device */
static struct pmx_mux_reg pmx_tdm0_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -523,6 +515,9 @@ void __init spear310_init(void)
printk(KERN_ERR "Error registering Shared IRQ 4\n");
}
+ /* This fixes addresses of all pmx devices for spear310 */
+ spear3xx_pmx_init_addr(&pmx_driver, SPEAR310_PAD_MUX_CONFIG_REG);
+
/* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 7f576dd..419d968 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -58,7 +58,6 @@ struct pmx_mode small_printers_mode = {
/* Pad multiplexing for CLCD device */
static struct pmx_mux_reg pmx_clcd_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -81,7 +80,6 @@ struct pmx_dev pmx_clcd = {
/* Pad multiplexing for EMI (Parallel NOR flash) device */
static struct pmx_mux_reg pmx_emi_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -104,7 +102,6 @@ struct pmx_dev pmx_emi = {
/* Pad multiplexing for FSMC (NAND flash) device */
static struct pmx_mux_reg pmx_fsmc_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -127,7 +124,6 @@ struct pmx_dev pmx_fsmc = {
/* Pad multiplexing for SPP device */
static struct pmx_mux_reg pmx_spp_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -150,7 +146,6 @@ struct pmx_dev pmx_spp = {
/* Pad multiplexing for SDHCI device */
static struct pmx_mux_reg pmx_sdhci_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -174,7 +169,6 @@ struct pmx_dev pmx_sdhci = {
/* Pad multiplexing for I2S device */
static struct pmx_mux_reg pmx_i2s_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -197,7 +191,6 @@ struct pmx_dev pmx_i2s = {
/* Pad multiplexing for UART1 device */
static struct pmx_mux_reg pmx_uart1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
.value = 0,
},
@@ -220,7 +213,6 @@ struct pmx_dev pmx_uart1 = {
/* Pad multiplexing for UART1 Modem device */
static struct pmx_mux_reg pmx_uart1_modem_autoexp_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
PMX_SSP_CS_MASK,
.value = 0,
@@ -229,7 +221,6 @@ static struct pmx_mux_reg pmx_uart1_modem_autoexp_mux[] = {
static struct pmx_mux_reg pmx_uart1_modem_smallpri_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
.value = 0,
@@ -257,7 +248,6 @@ struct pmx_dev pmx_uart1_modem = {
/* Pad multiplexing for UART2 device */
static struct pmx_mux_reg pmx_uart2_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = 0,
},
@@ -280,7 +270,6 @@ struct pmx_dev pmx_uart2 = {
/* Pad multiplexing for Touchscreen device */
static struct pmx_mux_reg pmx_touchscreen_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -303,7 +292,6 @@ struct pmx_dev pmx_touchscreen = {
/* Pad multiplexing for CAN device */
static struct pmx_mux_reg pmx_can_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
.value = 0,
@@ -327,7 +315,6 @@ struct pmx_dev pmx_can = {
/* Pad multiplexing for SDHCI LED device */
static struct pmx_mux_reg pmx_sdhci_led_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -350,7 +337,6 @@ struct pmx_dev pmx_sdhci_led = {
/* Pad multiplexing for PWM0 device */
static struct pmx_mux_reg pmx_pwm0_net_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -358,7 +344,6 @@ static struct pmx_mux_reg pmx_pwm0_net_mux[] = {
static struct pmx_mux_reg pmx_pwm0_autoexpsmallpri_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -385,7 +370,6 @@ struct pmx_dev pmx_pwm0 = {
/* Pad multiplexing for PWM1 device */
static struct pmx_mux_reg pmx_pwm1_net_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -393,7 +377,6 @@ static struct pmx_mux_reg pmx_pwm1_net_mux[] = {
static struct pmx_mux_reg pmx_pwm1_autoexpsmallpri_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -420,7 +403,6 @@ struct pmx_dev pmx_pwm1 = {
/* Pad multiplexing for PWM2 device */
static struct pmx_mux_reg pmx_pwm2_net_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -428,7 +410,6 @@ static struct pmx_mux_reg pmx_pwm2_net_mux[] = {
static struct pmx_mux_reg pmx_pwm2_autoexpsmallpri_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -455,7 +436,6 @@ struct pmx_dev pmx_pwm2 = {
/* Pad multiplexing for PWM3 device */
static struct pmx_mux_reg pmx_pwm3_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -478,7 +458,6 @@ struct pmx_dev pmx_pwm3 = {
/* Pad multiplexing for SSP1 device */
static struct pmx_mux_reg pmx_ssp1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -501,7 +480,6 @@ struct pmx_dev pmx_ssp1 = {
/* Pad multiplexing for SSP2 device */
static struct pmx_mux_reg pmx_ssp2_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -524,7 +502,6 @@ struct pmx_dev pmx_ssp2 = {
/* Pad multiplexing for mii1 device */
static struct pmx_mux_reg pmx_mii1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -547,7 +524,6 @@ struct pmx_dev pmx_mii1 = {
/* Pad multiplexing for smii0 device */
static struct pmx_mux_reg pmx_smii0_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -570,7 +546,6 @@ struct pmx_dev pmx_smii0 = {
/* Pad multiplexing for smii1 device */
static struct pmx_mux_reg pmx_smii1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -593,7 +568,6 @@ struct pmx_dev pmx_smii1 = {
/* Pad multiplexing for i2c1 device */
static struct pmx_mux_reg pmx_i2c1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = 0x0,
.value = 0,
},
@@ -615,7 +589,7 @@ struct pmx_dev pmx_i2c1 = {
/* pmx driver structure */
struct pmx_driver pmx_driver = {
- .mode_reg = {.address = MODE_CONFIG_REG, .mask = 0x00000007},
+ .mode_reg = {.address = SPEAR320_MODE_CONFIG_REG, .mask = 0x00000007},
};
/* Add spear320 specific devices here */
@@ -1015,6 +989,9 @@ void __init spear320_init(void)
printk(KERN_ERR "Error registering Shared IRQ 4\n");
}
+ /* This fixes addresses of all pmx devices for spear320 */
+ spear3xx_pmx_init_addr(&pmx_driver, SPEAR320_PAD_MUX_CONFIG_REG);
+
/* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index c4e4b1b..7373bc9 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -278,7 +278,6 @@ void __init spear3xx_map_io(void)
/* Pad multiplexing for firda device */
static struct pmx_mux_reg pmx_firda_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = PMX_FIRDA_MASK,
},
@@ -301,7 +300,6 @@ struct pmx_dev pmx_firda = {
/* Pad multiplexing for i2c device */
static struct pmx_mux_reg pmx_i2c_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_I2C_MASK,
.value = PMX_I2C_MASK,
},
@@ -324,7 +322,6 @@ struct pmx_dev pmx_i2c = {
/* Pad multiplexing for firda device */
static struct pmx_mux_reg pmx_ssp_cs_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = PMX_SSP_CS_MASK,
},
@@ -347,7 +344,6 @@ struct pmx_dev pmx_ssp_cs = {
/* Pad multiplexing for ssp device */
static struct pmx_mux_reg pmx_ssp_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_MASK,
.value = PMX_SSP_MASK,
},
@@ -370,7 +366,6 @@ struct pmx_dev pmx_ssp = {
/* Pad multiplexing for mii device */
static struct pmx_mux_reg pmx_mii_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = PMX_MII_MASK,
},
@@ -393,7 +388,6 @@ struct pmx_dev pmx_mii = {
/* Pad multiplexing for gpio pin0 device */
static struct pmx_mux_reg pmx_gpio_pin0_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK,
.value = PMX_GPIO_PIN0_MASK,
},
@@ -416,7 +410,6 @@ struct pmx_dev pmx_gpio_pin0 = {
/* Pad multiplexing for gpio pin1 device */
static struct pmx_mux_reg pmx_gpio_pin1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN1_MASK,
.value = PMX_GPIO_PIN1_MASK,
},
@@ -439,7 +432,6 @@ struct pmx_dev pmx_gpio_pin1 = {
/* Pad multiplexing for gpio pin2 device */
static struct pmx_mux_reg pmx_gpio_pin2_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK,
.value = PMX_GPIO_PIN2_MASK,
},
@@ -462,7 +454,6 @@ struct pmx_dev pmx_gpio_pin2 = {
/* Pad multiplexing for gpio pin3 device */
static struct pmx_mux_reg pmx_gpio_pin3_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK,
.value = PMX_GPIO_PIN3_MASK,
},
@@ -485,7 +476,6 @@ struct pmx_dev pmx_gpio_pin3 = {
/* Pad multiplexing for gpio pin4 device */
static struct pmx_mux_reg pmx_gpio_pin4_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN4_MASK,
.value = PMX_GPIO_PIN4_MASK,
},
@@ -508,7 +498,6 @@ struct pmx_dev pmx_gpio_pin4 = {
/* Pad multiplexing for gpio pin5 device */
static struct pmx_mux_reg pmx_gpio_pin5_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN5_MASK,
.value = PMX_GPIO_PIN5_MASK,
},
@@ -531,7 +520,6 @@ struct pmx_dev pmx_gpio_pin5 = {
/* Pad multiplexing for uart0 modem device */
static struct pmx_mux_reg pmx_uart0_modem_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = PMX_UART0_MODEM_MASK,
},
@@ -554,7 +542,6 @@ struct pmx_dev pmx_uart0_modem = {
/* Pad multiplexing for uart0 device */
static struct pmx_mux_reg pmx_uart0_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MASK,
.value = PMX_UART0_MASK,
},
@@ -577,7 +564,6 @@ struct pmx_dev pmx_uart0 = {
/* Pad multiplexing for timer 3, 4 device */
static struct pmx_mux_reg pmx_timer_3_4_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
.value = PMX_TIMER_3_4_MASK,
},
@@ -600,7 +586,6 @@ struct pmx_dev pmx_timer_3_4 = {
/* Pad multiplexing for gpio pin0 device */
static struct pmx_mux_reg pmx_timer_1_2_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = PMX_TIMER_1_2_MASK,
},
@@ -625,7 +610,6 @@ struct pmx_dev pmx_timer_1_2 = {
/* Pad multiplexing for plgpio_0_1 devices */
static struct pmx_mux_reg pmx_plgpio_0_1_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.value = 0,
},
@@ -648,7 +632,6 @@ struct pmx_dev pmx_plgpio_0_1 = {
/* Pad multiplexing for plgpio_2_3 devices */
static struct pmx_mux_reg pmx_plgpio_2_3_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MASK,
.value = 0,
},
@@ -671,7 +654,6 @@ struct pmx_dev pmx_plgpio_2_3 = {
/* Pad multiplexing for plgpio_4_5 devices */
static struct pmx_mux_reg pmx_plgpio_4_5_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_I2C_MASK,
.value = 0,
},
@@ -694,7 +676,6 @@ struct pmx_dev pmx_plgpio_4_5 = {
/* Pad multiplexing for plgpio_6_9 devices */
static struct pmx_mux_reg pmx_plgpio_6_9_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_MASK,
.value = 0,
},
@@ -717,7 +698,6 @@ struct pmx_dev pmx_plgpio_6_9 = {
/* Pad multiplexing for plgpio_10_27 devices */
static struct pmx_mux_reg pmx_plgpio_10_27_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_MII_MASK,
.value = 0,
},
@@ -740,7 +720,6 @@ struct pmx_dev pmx_plgpio_10_27 = {
/* Pad multiplexing for plgpio_28 devices */
static struct pmx_mux_reg pmx_plgpio_28_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK,
.value = 0,
},
@@ -763,7 +742,6 @@ struct pmx_dev pmx_plgpio_28 = {
/* Pad multiplexing for plgpio_29 devices */
static struct pmx_mux_reg pmx_plgpio_29_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN1_MASK,
.value = 0,
},
@@ -786,7 +764,6 @@ struct pmx_dev pmx_plgpio_29 = {
/* Pad multiplexing for plgpio_30 device */
static struct pmx_mux_reg pmx_plgpio_30_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK,
.value = 0,
},
@@ -809,7 +786,6 @@ struct pmx_dev pmx_plgpio_30 = {
/* Pad multiplexing for plgpio_31 device */
static struct pmx_mux_reg pmx_plgpio_31_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK,
.value = 0,
},
@@ -832,7 +808,6 @@ struct pmx_dev pmx_plgpio_31 = {
/* Pad multiplexing for plgpio_32 device */
static struct pmx_mux_reg pmx_plgpio_32_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN4_MASK,
.value = 0,
},
@@ -855,7 +830,6 @@ struct pmx_dev pmx_plgpio_32 = {
/* Pad multiplexing for plgpio_33 device */
static struct pmx_mux_reg pmx_plgpio_33_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_GPIO_PIN5_MASK,
.value = 0,
},
@@ -878,7 +852,6 @@ struct pmx_dev pmx_plgpio_33 = {
/* Pad multiplexing for plgpio_34_36 device */
static struct pmx_mux_reg pmx_plgpio_34_36_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.value = 0,
},
@@ -901,7 +874,6 @@ struct pmx_dev pmx_plgpio_34_36 = {
/* Pad multiplexing for plgpio_37_42 device */
static struct pmx_mux_reg pmx_plgpio_37_42_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.value = 0,
},
@@ -924,7 +896,6 @@ struct pmx_dev pmx_plgpio_37_42 = {
/* Pad multiplexing for plgpio_43_44_47_48 device */
static struct pmx_mux_reg pmx_plgpio_43_44_47_48_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_1_2_MASK,
.value = 0,
},
@@ -947,7 +918,6 @@ struct pmx_dev pmx_plgpio_43_44_47_48 = {
/* Pad multiplexing for plgpio_45_46_49_50 device */
static struct pmx_mux_reg pmx_plgpio_45_46_49_50_mux[] = {
{
- .address = PAD_MUX_CONFIG_REG,
.mask = PMX_TIMER_3_4_MASK,
.value = 0,
},
@@ -998,3 +968,21 @@ static void __init spear3xx_timer_init(void)
struct sys_timer spear3xx_timer = {
.init = spear3xx_timer_init,
};
+
+/* This fixes addresses of all pmx devices for different machines */
+void spear3xx_pmx_init_addr(struct pmx_driver *driver, unsigned int addr)
+{
+ int i;
+ for (i = 0; i < driver->devs_count; i++) {
+ int j;
+ struct pmx_dev *pdev = driver->devs[i];
+
+ for (j = 0; j < pdev->mode_count; j++) {
+ int k;
+ struct pmx_dev_mode *mode = &pdev->modes[j];
+
+ for (k = 0; k < mode->mux_reg_cnt; k++)
+ mode->mux_regs[k].address = addr;
+ }
+ }
+}
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 49/62] ST SPEAr Clock Framework: Updating for single image solution
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (46 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 48/62] ST SPEAr3xx: Passing pmx devices address from machine *.c files Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 50/62] SPEAr3xx: Make local structures static Viresh Kumar
` (13 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
This patch creates different clk_lookup arrays for individual machines.
These lookup arrays will be registered only if that specific machine is
current machine.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/clock.c | 29 ++++++++++--
arch/arm/mach-spear3xx/clock.c | 75 +++++++++++++++++++-----------
arch/arm/mach-spear6xx/clock.c | 8 +++-
arch/arm/plat-spear/clock.c | 8 +---
arch/arm/plat-spear/include/plat/clock.h | 2 +-
5 files changed, 82 insertions(+), 40 deletions(-)
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
index 43e1bf1..b022ee9 100644
--- a/arch/arm/mach-spear13xx/clock.c
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -1117,13 +1117,17 @@ static struct clk_lookup spear_clk_lookups[] = {
{.dev_id = "gpio1", .clk = &gpio1_clk},
{.dev_id = "keyboard", .clk = &kbd_clk},
{.dev_id = "wdt", .clk = &wdt_clk},
+};
- /* spear1300 machine specific clock structures */
+/* array of all spear 1300 clock lookups */
#ifdef CONFIG_MACH_SPEAR1300
+static struct clk_lookup spear1300_clk_lookups[] = {
+};
#endif
- /* spear1310 machine specific clock structures */
+/* array of all spear 1310 clock lookups */
#ifdef CONFIG_MACH_SPEAR1310
+static struct clk_lookup spear1310_clk_lookups[] = {
{.dev_id = "c_can_platform.0", .clk = &can0_clk},
{.dev_id = "c_can_platform.1", .clk = &can1_clk},
{.dev_id = "stmmaceth.1", .clk = &gmac_ras1_clk},
@@ -1134,11 +1138,28 @@ static struct clk_lookup spear_clk_lookups[] = {
{.dev_id = "stmmacphy.2", .clk = &gmac_phy2_clk},
{.dev_id = "stmmacphy.3", .clk = &gmac_phy3_clk},
{.dev_id = "stmmacphy.4", .clk = &gmac_phy4_clk},
-#endif
};
+#endif
/* machine clk init */
void __init spear13xx_clk_init(void)
{
- clk_init(spear_clk_lookups, ARRAY_SIZE(spear_clk_lookups), &ddr_clk);
+ int i, cnt;
+ struct clk_lookup *lookups;
+
+ if (machine_is_spear1300()) {
+ cnt = ARRAY_SIZE(spear1300_clk_lookups);
+ lookups = spear1300_clk_lookups;
+ } else {
+ cnt = ARRAY_SIZE(spear1310_clk_lookups);
+ lookups = spear1310_clk_lookups;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ for (i = 0; i < cnt; i++)
+ clk_register(&lookups[i]);
+
+ clk_init(&ddr_clk);
}
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 12d8c46..19603f6 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
+#include <asm/mach-types.h>
#include <mach/misc_regs.h>
#include <plat/clock.h>
@@ -754,52 +755,72 @@ static struct clk_lookup spear_clk_lookups[] = {
{ .dev_id = "adc", .clk = &adc_clk},
{ .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
{ .dev_id = "gpio", .clk = &gpio_clk},
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
- { .con_id = "emi", .clk = &emi_clk},
-#endif
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
- defined(CONFIG_MACH_SPEAR320)
- { .con_id = "fsmc", .clk = &fsmc_clk},
-#endif
-
-/* common clocks to spear310 and spear320 */
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
- { .dev_id = "uart1", .clk = &uart1_clk},
- { .dev_id = "uart2", .clk = &uart2_clk},
-#endif
-
- /* common clock to spear300 and spear320 */
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
- { .dev_id = "clcd", .clk = &clcd_clk},
- { .dev_id = "sdhci", .clk = &sdhci_clk},
-#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
+};
- /* spear300 machine specific clock structures */
+/* array of all spear 300 clock lookups */
#ifdef CONFIG_MACH_SPEAR300
+static struct clk_lookup spear300_clk_lookups[] = {
+ { .dev_id = "clcd", .clk = &clcd_clk},
+ { .con_id = "fsmc", .clk = &fsmc_clk},
{ .dev_id = "gpio1", .clk = &gpio1_clk},
{ .dev_id = "keyboard", .clk = &kbd_clk},
+ { .dev_id = "sdhci", .clk = &sdhci_clk},
+};
#endif
- /* spear310 machine specific clock structures */
+/* array of all spear 310 clock lookups */
#ifdef CONFIG_MACH_SPEAR310
+static struct clk_lookup spear310_clk_lookups[] = {
+ { .con_id = "fsmc", .clk = &fsmc_clk},
+ { .con_id = "emi", .clk = &emi_clk},
+ { .dev_id = "uart1", .clk = &uart1_clk},
+ { .dev_id = "uart2", .clk = &uart2_clk},
{ .dev_id = "uart3", .clk = &uart3_clk},
{ .dev_id = "uart4", .clk = &uart4_clk},
{ .dev_id = "uart5", .clk = &uart5_clk},
-
+};
#endif
- /* spear320 machine specific clock structures */
+
+/* array of all spear 320 clock lookups */
#ifdef CONFIG_MACH_SPEAR320
+static struct clk_lookup spear320_clk_lookups[] = {
+ { .dev_id = "clcd", .clk = &clcd_clk},
+ { .con_id = "fsmc", .clk = &fsmc_clk},
+ { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
+ { .con_id = "emi", .clk = &emi_clk},
+ { .dev_id = "pwm", .clk = &pwm_clk},
+ { .dev_id = "sdhci", .clk = &sdhci_clk},
{ .dev_id = "c_can_platform.0", .clk = &can0_clk},
{ .dev_id = "c_can_platform.1", .clk = &can1_clk},
- { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
{ .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
{ .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
- { .dev_id = "pwm", .clk = &pwm_clk},
-#endif
+ { .dev_id = "uart1", .clk = &uart1_clk},
+ { .dev_id = "uart2", .clk = &uart2_clk},
};
+#endif
/* machine clk init */
void __init spear3xx_clk_init(void)
{
- clk_init(spear_clk_lookups, ARRAY_SIZE(spear_clk_lookups), &ddr_clk);
+ int i, cnt;
+ struct clk_lookup *lookups;
+
+ if (machine_is_spear300()) {
+ cnt = ARRAY_SIZE(spear300_clk_lookups);
+ lookups = spear300_clk_lookups;
+ } else if (machine_is_spear310()) {
+ cnt = ARRAY_SIZE(spear310_clk_lookups);
+ lookups = spear310_clk_lookups;
+ } else {
+ cnt = ARRAY_SIZE(spear320_clk_lookups);
+ lookups = spear320_clk_lookups;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ for (i = 0; i < cnt; i++)
+ clk_register(&lookups[i]);
+
+ clk_init(&ddr_clk);
}
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index f304102..4579e4a 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -14,6 +14,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <mach/misc_regs.h>
+#include <asm/mach-types.h>
#include <plat/clock.h>
/* root clks */
@@ -740,5 +741,10 @@ static struct clk_lookup spear_clk_lookups[] = {
/* machine clk init */
void __init spear6xx_clk_init(void)
{
- clk_init(spear_clk_lookups, ARRAY_SIZE(spear_clk_lookups), &ddr_clk);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ clk_init(&ddr_clk);
}
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index ee8f82b..2043c34 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -949,14 +949,8 @@ void recalc_root_clocks(void)
spin_unlock_irqrestore(&clocks_lock, flags);
}
-void __init
-clk_init(struct clk_lookup *clk_lookups, u32 count, struct clk *dclk)
+void __init clk_init(struct clk *dclk)
{
- int i;
-
- for (i = 0; i < count; i++)
- clk_register(&clk_lookups[i]);
-
recalc_root_clocks();
/* Mark all ancestors of DDR with special flag */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index 4c4bf87..5afd356 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -241,7 +241,7 @@ struct ddr_rate_tbl {
* Actually before changing rate of DDRs ancestor, we must put ddr in refresh
* state and then change parent.
*/
-void clk_init(struct clk_lookup *clk_lookups, u32 count, struct clk *dclk);
+void clk_init(struct clk *dclk);
void clk_register(struct clk_lookup *cl);
void recalc_root_clocks(void);
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 50/62] SPEAr3xx: Make local structures static
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (47 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 49/62] ST SPEAr Clock Framework: Updating for single image solution Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 51/62] SPEAR3xx: Rename register/irq defines to remove naming conflicts Viresh Kumar
` (12 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Ryan Mallon <ryan@bluewatersys.com>
Several structures in arch/arm/mach-spear3xx are not marked static
like they should be. Fix this.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/spear300.c | 6 +++---
arch/arm/mach-spear3xx/spear310.c | 16 ++++++++--------
arch/arm/mach-spear3xx/spear320.c | 12 ++++++------
arch/arm/mach-spear3xx/spear3xx.c | 2 --
4 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 313938f..230940f 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -114,7 +114,6 @@ struct pmx_mode caml_lcd_mode = {
.value = 0x0F,
};
-/* devices */
/* Pad multiplexing for FSMC 2 NAND devices */
static struct pmx_mux_reg pmx_fsmc_2_mux[] = {
{
@@ -700,7 +699,7 @@ struct platform_device sdhci_device = {
};
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
.virq = VIRQ_IT_PERS_S,
.enb_mask = IT_PERS_S_IRQ_MASK,
@@ -740,7 +739,8 @@ struct shirq_dev_config shirq_ras1_config[] = {
},
};
-struct spear_shirq shirq_ras1 = {
+
+static struct spear_shirq shirq_ras1 = {
.irq = IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 4192ed2..848bdde 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -363,7 +363,7 @@ struct platform_device plgpio_device = {
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
.virq = VIRQ_SMII0,
.status_mask = SMII0_IRQ_MASK,
@@ -391,7 +391,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
},
};
-struct spear_shirq shirq_ras1 = {
+static struct spear_shirq shirq_ras1 = {
.irq = IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
@@ -403,7 +403,7 @@ struct spear_shirq shirq_ras1 = {
},
};
-struct shirq_dev_config shirq_ras2_config[] = {
+static struct shirq_dev_config shirq_ras2_config[] = {
{
.virq = VIRQ_UART1,
.status_mask = UART1_IRQ_MASK,
@@ -422,7 +422,7 @@ struct shirq_dev_config shirq_ras2_config[] = {
},
};
-struct spear_shirq shirq_ras2 = {
+static struct spear_shirq shirq_ras2 = {
.irq = IRQ_GEN_RAS_2,
.dev_config = shirq_ras2_config,
.dev_count = ARRAY_SIZE(shirq_ras2_config),
@@ -434,14 +434,14 @@ struct spear_shirq shirq_ras2 = {
},
};
-struct shirq_dev_config shirq_ras3_config[] = {
+static struct shirq_dev_config shirq_ras3_config[] = {
{
.virq = VIRQ_EMI,
.status_mask = EMI_IRQ_MASK,
},
};
-struct spear_shirq shirq_ras3 = {
+static struct spear_shirq shirq_ras3 = {
.irq = IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
@@ -453,7 +453,7 @@ struct spear_shirq shirq_ras3 = {
},
};
-struct shirq_dev_config shirq_intrcomm_ras_config[] = {
+static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
.virq = VIRQ_TDM_HDLC,
.status_mask = TDM_HDLC_IRQ_MASK,
@@ -466,7 +466,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
},
};
-struct spear_shirq shirq_intrcomm_ras = {
+static struct spear_shirq shirq_intrcomm_ras = {
.irq = IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 419d968..2660d9a 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -835,7 +835,7 @@ struct platform_device sdhci_device = {
};
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
.virq = VIRQ_EMI,
.status_mask = EMI_IRQ_MASK,
@@ -851,7 +851,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
},
};
-struct spear_shirq shirq_ras1 = {
+static struct spear_shirq shirq_ras1 = {
.irq = IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
@@ -864,7 +864,7 @@ struct spear_shirq shirq_ras1 = {
},
};
-struct shirq_dev_config shirq_ras3_config[] = {
+static struct shirq_dev_config shirq_ras3_config[] = {
{
.virq = VIRQ_PLGPIO,
.enb_mask = GPIO_IRQ_MASK,
@@ -883,7 +883,7 @@ struct shirq_dev_config shirq_ras3_config[] = {
},
};
-struct spear_shirq shirq_ras3 = {
+static struct spear_shirq shirq_ras3 = {
.irq = IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
@@ -897,7 +897,7 @@ struct spear_shirq shirq_ras3 = {
},
};
-struct shirq_dev_config shirq_intrcomm_ras_config[] = {
+static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
.virq = VIRQ_CANU,
.status_mask = CAN_U_IRQ_MASK,
@@ -945,7 +945,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
},
};
-struct spear_shirq shirq_intrcomm_ras = {
+static struct spear_shirq shirq_intrcomm_ras = {
.irq = IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 7373bc9..e1efb5a 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -273,7 +273,6 @@ void __init spear3xx_map_io(void)
}
/* pad multiplexing support */
-/* devices */
/* Pad multiplexing for firda device */
static struct pmx_mux_reg pmx_firda_mux[] = {
@@ -606,7 +605,6 @@ struct pmx_dev pmx_timer_1_2 = {
};
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* plgpios devices */
/* Pad multiplexing for plgpio_0_1 devices */
static struct pmx_mux_reg pmx_plgpio_0_1_mux[] = {
{
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 51/62] SPEAR3xx: Rename register/irq defines to remove naming conflicts
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (48 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 50/62] SPEAr3xx: Make local structures static Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 52/62] SPEAr3xx: Rework pmx_dev code to remove conflicts Viresh Kumar
` (11 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Ryan Mallon <ryan@bluewatersys.com>
Prefix register and irq defintions to remove naming conflicts between
the three SPEAr3xx platforms.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 4 +-
arch/arm/mach-spear3xx/include/mach/gpio.h | 3 +-
arch/arm/mach-spear3xx/include/mach/irqs.h | 207 ++++++++++++------------
arch/arm/mach-spear3xx/include/mach/spear300.h | 26 ++--
arch/arm/mach-spear3xx/include/mach/spear310.h | 44 +++---
arch/arm/mach-spear3xx/include/mach/spear320.h | 48 +++---
arch/arm/mach-spear3xx/spear300.c | 73 ++++-----
arch/arm/mach-spear3xx/spear310.c | 108 ++++++------
arch/arm/mach-spear3xx/spear320.c | 154 +++++++++---------
arch/arm/mach-spear3xx/spear3xx.c | 23 ++--
10 files changed, 346 insertions(+), 344 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index eb4c85a..340e2f1 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -27,8 +27,8 @@
* Following GPT channels will be used as clock source and clockevent
*/
#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
+#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
+#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
/* Add spear3xx family device structure declarations here */
extern struct amba_device gpio_device;
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
index e531f6d..f15248c 100644
--- a/arch/arm/mach-spear3xx/include/mach/gpio.h
+++ b/arch/arm/mach-spear3xx/include/mach/gpio.h
@@ -51,8 +51,9 @@
#define RAS_GPIO_5 13
#define RAS_GPIO_6 14
#define RAS_GPIO_7 15
+#endif
-#elif defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
#define PLGPIO_0 8
#define PLGPIO_1 9
#define PLGPIO_2 10
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index df0c1f3..6e26544 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -15,139 +15,140 @@
#define __MACH_IRQS_H
/* SPEAr3xx IRQ definitions */
-#define IRQ_HW_ACCEL_MOD_0 0
-#define IRQ_INTRCOMM_RAS_ARM 1
-#define IRQ_CPU_GPT1_1 2
-#define IRQ_CPU_GPT1_2 3
-#define IRQ_BASIC_GPT1_1 4
-#define IRQ_BASIC_GPT1_2 5
-#define IRQ_BASIC_GPT2_1 6
-#define IRQ_BASIC_GPT2_2 7
-#define IRQ_BASIC_DMA 8
-#define IRQ_BASIC_SMI 9
-#define IRQ_BASIC_RTC 10
-#define IRQ_BASIC_GPIO 11
-#define IRQ_BASIC_WDT 12
-#define IRQ_DDR_CONTROLLER 13
-#define IRQ_SYS_ERROR 14
-#define IRQ_WAKEUP_RCV 15
-#define IRQ_JPEG 16
-#define IRQ_IRDA 17
-#define IRQ_ADC 18
-#define IRQ_UART 19
-#define IRQ_SSP 20
-#define IRQ_I2C 21
-#define IRQ_MAC_1 22
-#define IRQ_MAC_2 23
-#define IRQ_USB_DEV 24
-#define IRQ_USB_H_OHCI_0 25
-#define IRQ_USB_H_EHCI_0 26
-#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0
-#define IRQ_USB_H_OHCI_1 27
-#define IRQ_GEN_RAS_1 28
-#define IRQ_GEN_RAS_2 29
-#define IRQ_GEN_RAS_3 30
-#define IRQ_HW_ACCEL_MOD_1 31
-#define IRQ_VIC_END 32
-
-#define VIRQ_START IRQ_VIC_END
+#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
+#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
+#define SPEAR3XX_IRQ_CPU_GPT1_1 2
+#define SPEAR3XX_IRQ_CPU_GPT1_2 3
+#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
+#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
+#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
+#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
+#define SPEAR3XX_IRQ_BASIC_DMA 8
+#define SPEAR3XX_IRQ_BASIC_SMI 9
+#define SPEAR3XX_IRQ_BASIC_RTC 10
+#define SPEAR3XX_IRQ_BASIC_GPIO 11
+#define SPEAR3XX_IRQ_BASIC_WDT 12
+#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
+#define SPEAR3XX_IRQ_SYS_ERROR 14
+#define SPEAR3XX_IRQ_WAKEUP_RCV 15
+#define SPEAR3XX_IRQ_JPEG 16
+#define SPEAR3XX_IRQ_IRDA 17
+#define SPEAR3XX_IRQ_ADC 18
+#define SPEAR3XX_IRQ_UART 19
+#define SPEAR3XX_IRQ_SSP 20
+#define SPEAR3XX_IRQ_I2C 21
+#define SPEAR3XX_IRQ_MAC_1 22
+#define SPEAR3XX_IRQ_MAC_2 23
+#define SPEAR3XX_IRQ_USB_DEV 24
+#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
+#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
+#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
+#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
+#define SPEAR3XX_IRQ_GEN_RAS_1 28
+#define SPEAR3XX_IRQ_GEN_RAS_2 29
+#define SPEAR3XX_IRQ_GEN_RAS_3 30
+#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
+#define SPEAR3XX_IRQ_VIC_END 32
+
+#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
/* SPEAr300 Virtual irq definitions */
-#ifdef CONFIG_MACH_SPEAR300
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_IT_PERS_S (VIRQ_START + 0)
-#define VIRQ_IT_CHANGE_S (VIRQ_START + 1)
-#define VIRQ_I2S (VIRQ_START + 2)
-#define VIRQ_TDM (VIRQ_START + 3)
-#define VIRQ_CAMERA_L (VIRQ_START + 4)
-#define VIRQ_CAMERA_F (VIRQ_START + 5)
-#define VIRQ_CAMERA_V (VIRQ_START + 6)
-#define VIRQ_KEYBOARD (VIRQ_START + 7)
-#define VIRQ_GPIO1 (VIRQ_START + 8)
+#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define IRQ_CLCD IRQ_GEN_RAS_3
+#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9)
-#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
+#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
/* SPEAr310 Virtual irq definitions */
-#elif defined(CONFIG_MACH_SPEAR310)
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_SMII0 (VIRQ_START + 0)
-#define VIRQ_SMII1 (VIRQ_START + 1)
-#define VIRQ_SMII2 (VIRQ_START + 2)
-#define VIRQ_SMII3 (VIRQ_START + 3)
-#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4)
-#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5)
-#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6)
-#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7)
+#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
/* IRQs sharing IRQ_GEN_RAS_2 */
-#define VIRQ_UART1 (VIRQ_START + 8)
-#define VIRQ_UART2 (VIRQ_START + 9)
-#define VIRQ_UART3 (VIRQ_START + 10)
-#define VIRQ_UART4 (VIRQ_START + 11)
-#define VIRQ_UART5 (VIRQ_START + 12)
+#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define VIRQ_EMI (VIRQ_START + 13)
-#define VIRQ_PLGPIO (VIRQ_START + 14)
+#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define VIRQ_TDM_HDLC (VIRQ_START + 15)
-#define VIRQ_RS485_0 (VIRQ_START + 16)
-#define VIRQ_RS485_1 (VIRQ_START + 17)
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18)
+#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
/* SPEAr320 Virtual irq definitions */
-#else
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_EMI (VIRQ_START + 0)
-#define VIRQ_CLCD (VIRQ_START + 1)
-#define VIRQ_SPP (VIRQ_START + 2)
+#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
/* IRQs sharing IRQ_GEN_RAS_2 */
-#define IRQ_SDHCI IRQ_GEN_RAS_2
+#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define VIRQ_PLGPIO (VIRQ_START + 3)
-#define VIRQ_I2S_PLAY (VIRQ_START + 4)
-#define VIRQ_I2S_REC (VIRQ_START + 5)
+#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define VIRQ_CANU (VIRQ_START + 6)
-#define VIRQ_CANL (VIRQ_START + 7)
-#define VIRQ_UART1 (VIRQ_START + 8)
-#define VIRQ_UART2 (VIRQ_START + 9)
-#define VIRQ_SSP1 (VIRQ_START + 10)
-#define VIRQ_SSP2 (VIRQ_START + 11)
-#define VIRQ_SMII0 (VIRQ_START + 12)
-#define VIRQ_MII1_SMII1 (VIRQ_START + 13)
-#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14)
-#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15)
-#define VIRQ_I2C1 (VIRQ_START + 16)
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17)
+#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
+/*
+ * GPIO pins virtual irqs
+ * Use the lowest number for the GPIO virtual IRQs base on which subarchs
+ * we have compiled in
+ */
+#if defined(CONFIG_MACH_SPEAR310)
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
+#elif defined(CONFIG_MACH_SPEAR320)
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
+#else
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
#endif
-/* PLGPIO Virtual IRQs */
-#define SPEAR_PLGPIO_COUNT 102
+#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
+#define SPEAR3XX_PLGPIO_COUNT 102
+
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + SPEAR_PLGPIO_COUNT)
+#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
+#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
+ SPEAR3XX_PLGPIO_COUNT)
+#else
+#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
#endif
-#define VIRQ_END SPEAR_GPIO_INT_END
-#define NR_IRQS VIRQ_END
+#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
+#define NR_IRQS SPEAR3XX_VIRQ_END
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index 4fd2d22..7d5db76 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -20,19 +20,19 @@
#define SPEAR300_TELECOM_BASE UL(0x50000000)
/* Interrupt registers offsets and masks */
-#define INT_ENB_MASK_REG 0x54
-#define INT_STS_MASK_REG 0x58
-#define IT_PERS_S_IRQ_MASK (1 << 0)
-#define IT_CHANGE_S_IRQ_MASK (1 << 1)
-#define I2S_IRQ_MASK (1 << 2)
-#define TDM_IRQ_MASK (1 << 3)
-#define CAMERA_L_IRQ_MASK (1 << 4)
-#define CAMERA_F_IRQ_MASK (1 << 5)
-#define CAMERA_V_IRQ_MASK (1 << 6)
-#define KEYBOARD_IRQ_MASK (1 << 7)
-#define GPIO1_IRQ_MASK (1 << 8)
-
-#define SHIRQ_RAS1_MASK 0x1FF
+#define SPEAR300_INT_ENB_MASK_REG 0x54
+#define SPEAR300_INT_STS_MASK_REG 0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
#define SPEAR300_CLCD_BASE UL(0x60000000)
#define SPEAR300_SDHCI_BASE UL(0x70000000)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 37556b6..0780c47 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -38,29 +38,29 @@
#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
/* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG 0x04
-#define SMII0_IRQ_MASK (1 << 0)
-#define SMII1_IRQ_MASK (1 << 1)
-#define SMII2_IRQ_MASK (1 << 2)
-#define SMII3_IRQ_MASK (1 << 3)
-#define WAKEUP_SMII0_IRQ_MASK (1 << 4)
-#define WAKEUP_SMII1_IRQ_MASK (1 << 5)
-#define WAKEUP_SMII2_IRQ_MASK (1 << 6)
-#define WAKEUP_SMII3_IRQ_MASK (1 << 7)
-#define UART1_IRQ_MASK (1 << 8)
-#define UART2_IRQ_MASK (1 << 9)
-#define UART3_IRQ_MASK (1 << 10)
-#define UART4_IRQ_MASK (1 << 11)
-#define UART5_IRQ_MASK (1 << 12)
-#define EMI_IRQ_MASK (1 << 13)
-#define TDM_HDLC_IRQ_MASK (1 << 14)
-#define RS485_0_IRQ_MASK (1 << 15)
-#define RS485_1_IRQ_MASK (1 << 16)
+#define SPEAR310_INT_STS_MASK_REG 0x04
+#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
-#define SHIRQ_RAS1_MASK 0x000FF
-#define SHIRQ_RAS2_MASK 0x01F00
-#define SHIRQ_RAS3_MASK 0x02000
-#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000
+#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
#endif /* __MACH_SPEAR310_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 4f60073..30ea941 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -42,31 +42,31 @@
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
/* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG 0x04
-#define INT_CLR_MASK_REG 0x04
-#define INT_ENB_MASK_REG 0x08
-#define GPIO_IRQ_MASK (1 << 0)
-#define I2S_PLAY_IRQ_MASK (1 << 1)
-#define I2S_REC_IRQ_MASK (1 << 2)
-#define EMI_IRQ_MASK (1 << 7)
-#define CLCD_IRQ_MASK (1 << 8)
-#define SPP_IRQ_MASK (1 << 9)
-#define SDHCI_IRQ_MASK (1 << 10)
-#define CAN_U_IRQ_MASK (1 << 11)
-#define CAN_L_IRQ_MASK (1 << 12)
-#define UART1_IRQ_MASK (1 << 13)
-#define UART2_IRQ_MASK (1 << 14)
-#define SSP1_IRQ_MASK (1 << 15)
-#define SSP2_IRQ_MASK (1 << 16)
-#define SMII0_IRQ_MASK (1 << 17)
-#define MII1_SMII1_IRQ_MASK (1 << 18)
-#define WAKEUP_SMII0_IRQ_MASK (1 << 19)
-#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
-#define I2C1_IRQ_MASK (1 << 21)
+#define SPEAR320_INT_STS_MASK_REG 0x04
+#define SPEAR320_INT_CLR_MASK_REG 0x04
+#define SPEAR320_INT_ENB_MASK_REG 0x08
+#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
-#define SHIRQ_RAS1_MASK 0x000380
-#define SHIRQ_RAS3_MASK 0x000007
-#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
+#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
#endif /* __MACH_SPEAR320_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 230940f..5660fd0 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -538,13 +538,13 @@ struct amba_device clcd_device = {
.flags = IORESOURCE_MEM,
},
.dma_mask = ~0,
- .irq = {IRQ_CLCD, NO_IRQ},
+ .irq = {SPEAR300_IRQ_CLCD, NO_IRQ},
};
/* arm gpio1 device registration */
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
- .irq_base = SPEAR_GPIO1_INT_BASE,
+ .irq_base = SPEAR300_GPIO1_INT_BASE,
};
struct amba_device gpio1_device = {
@@ -557,7 +557,7 @@ struct amba_device gpio1_device = {
.end = SPEAR300_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_GPIO1, NO_IRQ},
+ .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
};
/* keyboard device registration */
@@ -567,7 +567,7 @@ static struct resource kbd_resources[] = {
.end = SPEAR300_KEYBOARD_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = VIRQ_KEYBOARD,
+ .start = SPEAR300_VIRQ_KEYBOARD,
.flags = IORESOURCE_IRQ,
},
};
@@ -683,7 +683,7 @@ static struct resource sdhci_resources[] = {
.end = SPEAR300_SDHCI_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IRQ_SDHCI,
+ .start = SPEAR300_IRQ_SDHCI,
.flags = IORESOURCE_IRQ,
}
};
@@ -701,53 +701,52 @@ struct platform_device sdhci_device = {
/* spear3xx shared irq */
static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_IT_PERS_S,
- .enb_mask = IT_PERS_S_IRQ_MASK,
- .status_mask = IT_PERS_S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_IT_PERS_S,
+ .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
+ .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
}, {
- .virq = VIRQ_IT_CHANGE_S,
- .enb_mask = IT_CHANGE_S_IRQ_MASK,
- .status_mask = IT_CHANGE_S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_IT_CHANGE_S,
+ .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
+ .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
}, {
- .virq = VIRQ_I2S,
- .enb_mask = I2S_IRQ_MASK,
- .status_mask = I2S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_I2S,
+ .enb_mask = SPEAR300_I2S_IRQ_MASK,
+ .status_mask = SPEAR300_I2S_IRQ_MASK,
}, {
- .virq = VIRQ_TDM,
- .enb_mask = TDM_IRQ_MASK,
- .status_mask = TDM_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_TDM,
+ .enb_mask = SPEAR300_TDM_IRQ_MASK,
+ .status_mask = SPEAR300_TDM_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_L,
- .enb_mask = CAMERA_L_IRQ_MASK,
- .status_mask = CAMERA_L_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_L,
+ .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_F,
- .enb_mask = CAMERA_F_IRQ_MASK,
- .status_mask = CAMERA_F_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_F,
+ .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_V,
- .enb_mask = CAMERA_V_IRQ_MASK,
- .status_mask = CAMERA_V_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_V,
+ .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
}, {
- .virq = VIRQ_KEYBOARD,
- .enb_mask = KEYBOARD_IRQ_MASK,
- .status_mask = KEYBOARD_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_KEYBOARD,
+ .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
+ .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
}, {
- .virq = VIRQ_GPIO1,
- .enb_mask = GPIO1_IRQ_MASK,
- .status_mask = GPIO1_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_GPIO1,
+ .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
+ .status_mask = SPEAR300_GPIO1_IRQ_MASK,
},
};
-
static struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
- .enb_reg = INT_ENB_MASK_REG,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
+ .enb_reg = SPEAR300_INT_ENB_MASK_REG,
+ .status_reg = SPEAR300_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
.clear_reg = -1,
},
};
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 848bdde..0995535 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -205,7 +205,7 @@ struct amba_device uart1_device = {
.end = SPEAR310_UART1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_UART1, NO_IRQ},
+ .irq = {SPEAR310_VIRQ_UART1, NO_IRQ},
};
/* uart2 device registeration */
@@ -218,7 +218,7 @@ struct amba_device uart2_device = {
.end = SPEAR310_UART2_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_UART2, NO_IRQ},
+ .irq = {SPEAR310_VIRQ_UART2, NO_IRQ},
};
/* uart3 device registeration */
@@ -231,7 +231,7 @@ struct amba_device uart3_device = {
.end = SPEAR310_UART3_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_UART3, NO_IRQ},
+ .irq = {SPEAR310_VIRQ_UART3, NO_IRQ},
};
/* uart4 device registeration */
@@ -244,7 +244,7 @@ struct amba_device uart4_device = {
.end = SPEAR310_UART4_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_UART4, NO_IRQ},
+ .irq = {SPEAR310_VIRQ_UART4, NO_IRQ},
};
/* uart5 device registeration */
@@ -257,7 +257,7 @@ struct amba_device uart5_device = {
.end = SPEAR310_UART5_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_UART5, NO_IRQ},
+ .irq = {SPEAR310_VIRQ_UART5, NO_IRQ},
};
/* nand device registeration */
@@ -331,8 +331,8 @@ struct platform_device emi_nor_device = {
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
- .irq_base = SPEAR_PLGPIO_INT_BASE,
- .gpio_count = SPEAR_PLGPIO_COUNT,
+ .irq_base = SPEAR3XX_PLGPIO_INT_BASE,
+ .gpio_count = SPEAR3XX_PLGPIO_COUNT,
.p2o = spear300_p2o,
.o2p = spear300_o2p,
/* list of registers with inconsistency */
@@ -346,7 +346,7 @@ static struct resource plgpio_resources[] = {
.end = SPEAR310_SOC_CONFIG_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = VIRQ_PLGPIO,
+ .start = SPEAR310_VIRQ_PLGPIO,
.flags = IORESOURCE_IRQ,
},
};
@@ -365,115 +365,115 @@ struct platform_device plgpio_device = {
/* spear3xx shared irq */
static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_SMII0,
- .status_mask = SMII0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII0,
+ .status_mask = SPEAR310_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_SMII1,
- .status_mask = SMII1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII1,
+ .status_mask = SPEAR310_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_SMII2,
- .status_mask = SMII2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII2,
+ .status_mask = SPEAR310_SMII2_IRQ_MASK,
}, {
- .virq = VIRQ_SMII3,
- .status_mask = SMII3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII3,
+ .status_mask = SPEAR310_SMII3_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII0,
- .status_mask = WAKEUP_SMII0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
+ .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII1,
- .status_mask = WAKEUP_SMII1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
+ .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII2,
- .status_mask = WAKEUP_SMII2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
+ .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII3,
- .status_mask = WAKEUP_SMII3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
+ .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
.clear_reg = -1,
},
};
static struct shirq_dev_config shirq_ras2_config[] = {
{
- .virq = VIRQ_UART1,
- .status_mask = UART1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART1,
+ .status_mask = SPEAR310_UART1_IRQ_MASK,
}, {
- .virq = VIRQ_UART2,
- .status_mask = UART2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART2,
+ .status_mask = SPEAR310_UART2_IRQ_MASK,
}, {
- .virq = VIRQ_UART3,
- .status_mask = UART3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART3,
+ .status_mask = SPEAR310_UART3_IRQ_MASK,
}, {
- .virq = VIRQ_UART4,
- .status_mask = UART4_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART4,
+ .status_mask = SPEAR310_UART4_IRQ_MASK,
}, {
- .virq = VIRQ_UART5,
- .status_mask = UART5_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART5,
+ .status_mask = SPEAR310_UART5_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras2 = {
- .irq = IRQ_GEN_RAS_2,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_2,
.dev_config = shirq_ras2_config,
.dev_count = ARRAY_SIZE(shirq_ras2_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS2_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
.clear_reg = -1,
},
};
static struct shirq_dev_config shirq_ras3_config[] = {
{
- .virq = VIRQ_EMI,
- .status_mask = EMI_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_EMI,
+ .status_mask = SPEAR310_EMI_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras3 = {
- .irq = IRQ_GEN_RAS_3,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS3_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
.clear_reg = -1,
},
};
static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
- .virq = VIRQ_TDM_HDLC,
- .status_mask = TDM_HDLC_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_TDM_HDLC,
+ .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
}, {
- .virq = VIRQ_RS485_0,
- .status_mask = RS485_0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_RS485_0,
+ .status_mask = SPEAR310_RS485_0_IRQ_MASK,
}, {
- .virq = VIRQ_RS485_1,
- .status_mask = RS485_1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_RS485_1,
+ .status_mask = SPEAR310_RS485_1_IRQ_MASK,
},
};
static struct spear_shirq shirq_intrcomm_ras = {
- .irq = IRQ_INTRCOMM_RAS_ARM,
+ .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
.clear_reg = -1,
},
};
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 2660d9a..00d206f 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -606,7 +606,7 @@ struct amba_device clcd_device = {
.flags = IORESOURCE_MEM,
},
.dma_mask = ~0,
- .irq = {VIRQ_CLCD, NO_IRQ},
+ .irq = {SPEAR320_VIRQ_CLCD, NO_IRQ},
};
/* ssp device registeration */
@@ -634,7 +634,7 @@ struct amba_device ssp_device[] = {
.end = SPEAR320_SSP0_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_SSP1, NO_IRQ},
+ .irq = {SPEAR320_VIRQ_SSP1, NO_IRQ},
}, {
.dev = {
.coherent_dma_mask = ~0,
@@ -646,7 +646,7 @@ struct amba_device ssp_device[] = {
.end = SPEAR320_SSP1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_SSP2, NO_IRQ},
+ .irq = {SPEAR320_VIRQ_SSP2, NO_IRQ},
}
};
@@ -660,7 +660,7 @@ struct amba_device uart1_device = {
.end = SPEAR320_UART1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_UART1, NO_IRQ},
+ .irq = {SPEAR320_VIRQ_UART1, NO_IRQ},
};
/* uart2 device registeration */
@@ -673,7 +673,7 @@ struct amba_device uart2_device = {
.end = SPEAR320_UART2_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_UART2, NO_IRQ},
+ .irq = {SPEAR320_VIRQ_UART2, NO_IRQ},
};
/* CAN device registeration */
@@ -683,7 +683,7 @@ static struct resource can0_resources[] = {
.end = SPEAR320_CAN0_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
}, {
- .start = VIRQ_CANU,
+ .start = SPEAR320_VIRQ_CANU,
.flags = IORESOURCE_IRQ,
},
};
@@ -701,7 +701,7 @@ static struct resource can1_resources[] = {
.end = SPEAR320_CAN1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
}, {
- .start = VIRQ_CANL,
+ .start = SPEAR320_VIRQ_CANL,
.flags = IORESOURCE_IRQ,
},
};
@@ -728,7 +728,7 @@ static struct resource i2c1_resources[] = {
.end = SPEAR320_I2C_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = VIRQ_I2C1 ,
+ .start = SPEAR320_VIRQ_I2C1 ,
.flags = IORESOURCE_IRQ,
},
};
@@ -781,7 +781,7 @@ static struct resource plgpio_resources[] = {
.end = SPEAR320_SOC_CONFIG_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = VIRQ_PLGPIO,
+ .start = SPEAR320_VIRQ_PLGPIO,
.flags = IORESOURCE_IRQ,
},
};
@@ -819,7 +819,7 @@ static struct resource sdhci_resources[] = {
.end = SPEAR320_SDHCI_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IRQ_SDHCI,
+ .start = SPEAR320_IRQ_SDHCI,
.flags = IORESOURCE_IRQ,
}
};
@@ -837,123 +837,123 @@ struct platform_device sdhci_device = {
/* spear3xx shared irq */
static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_EMI,
- .status_mask = EMI_IRQ_MASK,
- .clear_mask = EMI_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_EMI,
+ .status_mask = SPEAR320_EMI_IRQ_MASK,
+ .clear_mask = SPEAR320_EMI_IRQ_MASK,
}, {
- .virq = VIRQ_CLCD,
- .status_mask = CLCD_IRQ_MASK,
- .clear_mask = CLCD_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CLCD,
+ .status_mask = SPEAR320_CLCD_IRQ_MASK,
+ .clear_mask = SPEAR320_CLCD_IRQ_MASK,
}, {
- .virq = VIRQ_SPP,
- .status_mask = SPP_IRQ_MASK,
- .clear_mask = SPP_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SPP,
+ .status_mask = SPEAR320_SPP_IRQ_MASK,
+ .clear_mask = SPEAR320_SPP_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
static struct shirq_dev_config shirq_ras3_config[] = {
{
- .virq = VIRQ_PLGPIO,
- .enb_mask = GPIO_IRQ_MASK,
- .status_mask = GPIO_IRQ_MASK,
- .clear_mask = GPIO_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_PLGPIO,
+ .enb_mask = SPEAR320_GPIO_IRQ_MASK,
+ .status_mask = SPEAR320_GPIO_IRQ_MASK,
+ .clear_mask = SPEAR320_GPIO_IRQ_MASK,
}, {
- .virq = VIRQ_I2S_PLAY,
- .enb_mask = I2S_PLAY_IRQ_MASK,
- .status_mask = I2S_PLAY_IRQ_MASK,
- .clear_mask = I2S_PLAY_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2S_PLAY,
+ .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
+ .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
+ .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
}, {
- .virq = VIRQ_I2S_REC,
- .enb_mask = I2S_REC_IRQ_MASK,
- .status_mask = I2S_REC_IRQ_MASK,
- .clear_mask = I2S_REC_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2S_REC,
+ .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
+ .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
+ .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras3 = {
- .irq = IRQ_GEN_RAS_3,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
.regs = {
- .enb_reg = INT_ENB_MASK_REG,
+ .enb_reg = SPEAR320_INT_ENB_MASK_REG,
.reset_to_enb = 1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS3_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
- .virq = VIRQ_CANU,
- .status_mask = CAN_U_IRQ_MASK,
- .clear_mask = CAN_U_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CANU,
+ .status_mask = SPEAR320_CAN_U_IRQ_MASK,
+ .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
}, {
- .virq = VIRQ_CANL,
- .status_mask = CAN_L_IRQ_MASK,
- .clear_mask = CAN_L_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CANL,
+ .status_mask = SPEAR320_CAN_L_IRQ_MASK,
+ .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
}, {
- .virq = VIRQ_UART1,
- .status_mask = UART1_IRQ_MASK,
- .clear_mask = UART1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_UART1,
+ .status_mask = SPEAR320_UART1_IRQ_MASK,
+ .clear_mask = SPEAR320_UART1_IRQ_MASK,
}, {
- .virq = VIRQ_UART2,
- .status_mask = UART2_IRQ_MASK,
- .clear_mask = UART2_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_UART2,
+ .status_mask = SPEAR320_UART2_IRQ_MASK,
+ .clear_mask = SPEAR320_UART2_IRQ_MASK,
}, {
- .virq = VIRQ_SSP1,
- .status_mask = SSP1_IRQ_MASK,
- .clear_mask = SSP1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SSP1,
+ .status_mask = SPEAR320_SSP1_IRQ_MASK,
+ .clear_mask = SPEAR320_SSP1_IRQ_MASK,
}, {
- .virq = VIRQ_SSP2,
- .status_mask = SSP2_IRQ_MASK,
- .clear_mask = SSP2_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SSP2,
+ .status_mask = SPEAR320_SSP2_IRQ_MASK,
+ .clear_mask = SPEAR320_SSP2_IRQ_MASK,
}, {
- .virq = VIRQ_SMII0,
- .status_mask = SMII0_IRQ_MASK,
- .clear_mask = SMII0_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SMII0,
+ .status_mask = SPEAR320_SMII0_IRQ_MASK,
+ .clear_mask = SPEAR320_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_MII1_SMII1,
- .status_mask = MII1_SMII1_IRQ_MASK,
- .clear_mask = MII1_SMII1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_MII1_SMII1,
+ .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
+ .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII0,
- .status_mask = WAKEUP_SMII0_IRQ_MASK,
- .clear_mask = WAKEUP_SMII0_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
+ .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
+ .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_MII1_SMII1,
- .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
- .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
+ .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
+ .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_I2C1,
- .status_mask = I2C1_IRQ_MASK,
- .clear_mask = I2C1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2C1,
+ .status_mask = SPEAR320_I2C1_IRQ_MASK,
+ .clear_mask = SPEAR320_I2C1_IRQ_MASK,
},
};
static struct spear_shirq shirq_intrcomm_ras = {
- .irq = IRQ_INTRCOMM_RAS_ARM,
+ .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index e1efb5a..662ab1d 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -22,13 +22,14 @@
#include <mach/generic.h>
#include <mach/spear.h>
-#define SPEAR3XX_WKUP_SRCS (1 << IRQ_MAC_1 | 1 << IRQ_USB_DEV | \
- 1 << IRQ_BASIC_RTC | 1 << IRQ_BASIC_GPIO)
+#define SPEAR3XX_WKUP_SRCS (1 << SPEAR3XX_IRQ_MAC_1 | 1 << \
+ SPEAR3XX_IRQ_USB_DEV | 1 << SPEAR3XX_IRQ_BASIC_RTC | 1 << \
+ SPEAR3XX_IRQ_BASIC_GPIO)
/* Add spear3xx machines common devices here */
/* gpio device registration */
static struct pl061_platform_data gpio_plat_data = {
.gpio_base = 0,
- .irq_base = SPEAR_GPIO_INT_BASE,
+ .irq_base = SPEAR3XX_GPIO_INT_BASE,
};
struct amba_device gpio_device = {
@@ -41,7 +42,7 @@ struct amba_device gpio_device = {
.end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {IRQ_BASIC_GPIO, NO_IRQ},
+ .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
};
/* ssp device registration */
@@ -71,7 +72,7 @@ struct amba_device ssp0_device = {
.end = SPEAR3XX_ICM1_SSP_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {IRQ_SSP, NO_IRQ},
+ .irq = {SPEAR3XX_IRQ_SSP, NO_IRQ},
};
/* uart device registration */
@@ -84,7 +85,7 @@ struct amba_device uart_device = {
.end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {IRQ_UART, NO_IRQ},
+ .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
};
/* watchdog device registeration */
@@ -106,7 +107,7 @@ static struct resource i2c_resources[] = {
.end = SPEAR3XX_ICM1_I2C_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IRQ_I2C,
+ .start = SPEAR3XX_IRQ_I2C,
.flags = IORESOURCE_IRQ,
},
};
@@ -129,7 +130,7 @@ static struct resource ehci_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_USB_H_EHCI_0,
+ .start = SPEAR3XX_IRQ_USB_H_EHCI_0,
.flags = IORESOURCE_IRQ,
},
};
@@ -141,7 +142,7 @@ static struct resource ohci0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_USB_H_OHCI_0,
+ .start = SPEAR3XX_IRQ_USB_H_OHCI_0,
.flags = IORESOURCE_IRQ,
},
};
@@ -153,7 +154,7 @@ static struct resource ohci1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_USB_H_OHCI_1,
+ .start = SPEAR3XX_IRQ_USB_H_OHCI_1,
.flags = IORESOURCE_IRQ,
},
};
@@ -208,7 +209,7 @@ static struct resource rtc_resources[] = {
.end = SPEAR3XX_ICM3_RTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IRQ_BASIC_RTC,
+ .start = SPEAR3XX_IRQ_BASIC_RTC,
.flags = IORESOURCE_IRQ,
},
};
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 52/62] SPEAr3xx: Rework pmx_dev code to remove conflicts
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (49 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 51/62] SPEAR3xx: Rename register/irq defines to remove naming conflicts Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 53/62] SPEAr3xx: Rework KConfig to allow all boards to be compiled in Viresh Kumar
` (10 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Ryan Mallon <ryan@bluewatersys.com>
Prefix the pmx_devs to remove naming conflicts between the three
SPEAr3xx platforms. Also make pmx_driver static to each platform and
rework the init code to pass the devices rather than export the
pmx_driver structure.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 129 +++++++++++++------------
arch/arm/mach-spear3xx/spear300.c | 40 ++++----
arch/arm/mach-spear3xx/spear300_evb.c | 25 ++---
arch/arm/mach-spear3xx/spear310.c | 28 +++---
arch/arm/mach-spear3xx/spear310_evb.c | 41 ++++-----
arch/arm/mach-spear3xx/spear320.c | 56 ++++++-----
arch/arm/mach-spear3xx/spear320_evb.c | 35 +++----
arch/arm/mach-spear3xx/spear3xx.c | 60 ++++++------
8 files changed, 206 insertions(+), 208 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 340e2f1..d250c96 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -69,21 +69,21 @@ void spear3xx_pmx_init_addr(struct pmx_driver *driver, unsigned int addr);
#define PMX_TIMER_1_2_MASK (1 << 0)
/* pad mux devices */
-extern struct pmx_dev pmx_firda;
-extern struct pmx_dev pmx_i2c;
-extern struct pmx_dev pmx_ssp_cs;
-extern struct pmx_dev pmx_ssp;
-extern struct pmx_dev pmx_mii;
-extern struct pmx_dev pmx_gpio_pin0;
-extern struct pmx_dev pmx_gpio_pin1;
-extern struct pmx_dev pmx_gpio_pin2;
-extern struct pmx_dev pmx_gpio_pin3;
-extern struct pmx_dev pmx_gpio_pin4;
-extern struct pmx_dev pmx_gpio_pin5;
-extern struct pmx_dev pmx_uart0_modem;
-extern struct pmx_dev pmx_uart0;
-extern struct pmx_dev pmx_timer_3_4;
-extern struct pmx_dev pmx_timer_1_2;
+extern struct pmx_dev spear3xx_pmx_firda;
+extern struct pmx_dev spear3xx_pmx_i2c;
+extern struct pmx_dev spear3xx_pmx_ssp_cs;
+extern struct pmx_dev spear3xx_pmx_ssp;
+extern struct pmx_dev spear3xx_pmx_mii;
+extern struct pmx_dev spear3xx_pmx_gpio_pin0;
+extern struct pmx_dev spear3xx_pmx_gpio_pin1;
+extern struct pmx_dev spear3xx_pmx_gpio_pin2;
+extern struct pmx_dev spear3xx_pmx_gpio_pin3;
+extern struct pmx_dev spear3xx_pmx_gpio_pin4;
+extern struct pmx_dev spear3xx_pmx_gpio_pin5;
+extern struct pmx_dev spear3xx_pmx_uart0_modem;
+extern struct pmx_dev spear3xx_pmx_uart0;
+extern struct pmx_dev spear3xx_pmx_timer_3_4;
+extern struct pmx_dev spear3xx_pmx_timer_1_2;
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
/* padmux plgpio devices */
@@ -104,8 +104,6 @@ extern struct pmx_dev pmx_plgpio_43_44_47_48;
extern struct pmx_dev pmx_plgpio_45_46_49_50;
#endif
-extern struct pmx_driver pmx_driver;
-
/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
/* Add spear300 machine device structure declarations here */
@@ -134,27 +132,28 @@ extern struct pmx_mode camu_wlcd_mode;
extern struct pmx_mode caml_lcd_mode;
/* pad mux devices */
-extern struct pmx_dev pmx_fsmc_2_chips;
-extern struct pmx_dev pmx_fsmc_4_chips;
-extern struct pmx_dev pmx_keyboard;
-extern struct pmx_dev pmx_clcd;
-extern struct pmx_dev pmx_telecom_gpio;
-extern struct pmx_dev pmx_telecom_tdm;
-extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev pmx_telecom_camera;
-extern struct pmx_dev pmx_telecom_dac;
-extern struct pmx_dev pmx_telecom_i2s;
-extern struct pmx_dev pmx_telecom_boot_pins;
-extern struct pmx_dev pmx_telecom_sdhci_4bit;
-extern struct pmx_dev pmx_telecom_sdhci_8bit;
-extern struct pmx_dev pmx_gpio1;
+extern struct pmx_dev spear300_pmx_fsmc_2_chips;
+extern struct pmx_dev spear300_pmx_fsmc_4_chips;
+extern struct pmx_dev spear300_pmx_keyboard;
+extern struct pmx_dev spear300_pmx_clcd;
+extern struct pmx_dev spear300_pmx_telecom_gpio;
+extern struct pmx_dev spear300_pmx_telecom_tdm;
+extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
+extern struct pmx_dev spear300_pmx_telecom_camera;
+extern struct pmx_dev spear300_pmx_telecom_dac;
+extern struct pmx_dev spear300_pmx_telecom_i2s;
+extern struct pmx_dev spear300_pmx_telecom_boot_pins;
+extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
+extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
+extern struct pmx_dev spear300_pmx_gpio1;
/* pad multiplexing support */
#define SPEAR300_PAD_MUX_CONFIG_REG 0x99000000
#define SPEAR300_MODE_CONFIG_REG 0x99000004
/* Add spear300 machine function declarations here */
-void __init spear300_init(void);
+void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#define SDHCI_MEM_ENB 0x1
#define I2S_MEM_ENB 0x2
void sdhci_i2s_mem_enable(u8 mask);
@@ -175,18 +174,19 @@ extern struct platform_device plgpio_device;
extern struct platform_device nand_device;
/* pad mux devices */
-extern struct pmx_dev pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev pmx_emi_cs_2_3;
-extern struct pmx_dev pmx_uart1;
-extern struct pmx_dev pmx_uart2;
-extern struct pmx_dev pmx_uart3_4_5;
-extern struct pmx_dev pmx_fsmc;
-extern struct pmx_dev pmx_rs485_0_1;
-extern struct pmx_dev pmx_tdm0;
+extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
+extern struct pmx_dev spear310_pmx_emi_cs_2_3;
+extern struct pmx_dev spear310_pmx_uart1;
+extern struct pmx_dev spear310_pmx_uart2;
+extern struct pmx_dev spear310_pmx_uart3_4_5;
+extern struct pmx_dev spear310_pmx_fsmc;
+extern struct pmx_dev spear310_pmx_rs485_0_1;
+extern struct pmx_dev spear310_pmx_tdm0;
#define SPEAR310_PAD_MUX_CONFIG_REG 0xB4000008
/* Add spear310 machine function declarations here */
-void __init spear310_init(void);
+void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
/* spear320 declarations */
#elif defined(CONFIG_MACH_SPEAR320)
@@ -211,35 +211,36 @@ extern struct pmx_mode auto_exp_mode;
extern struct pmx_mode small_printers_mode;
/* pad mux devices */
-extern struct pmx_dev pmx_clcd;
-extern struct pmx_dev pmx_emi;
-extern struct pmx_dev pmx_fsmc;
-extern struct pmx_dev pmx_spp;
-extern struct pmx_dev pmx_sdhci;
-extern struct pmx_dev pmx_i2s;
-extern struct pmx_dev pmx_uart1;
-extern struct pmx_dev pmx_uart1_modem;
-extern struct pmx_dev pmx_uart2;
-extern struct pmx_dev pmx_touchscreen;
-extern struct pmx_dev pmx_can;
-extern struct pmx_dev pmx_sdhci_led;
-extern struct pmx_dev pmx_pwm0;
-extern struct pmx_dev pmx_pwm1;
-extern struct pmx_dev pmx_pwm2;
-extern struct pmx_dev pmx_pwm3;
-extern struct pmx_dev pmx_ssp1;
-extern struct pmx_dev pmx_ssp2;
-extern struct pmx_dev pmx_mii1;
-extern struct pmx_dev pmx_smii0;
-extern struct pmx_dev pmx_smii1;
-extern struct pmx_dev pmx_i2c1;
+extern struct pmx_dev spear320_pmx_clcd;
+extern struct pmx_dev spear320_pmx_emi;
+extern struct pmx_dev spear320_pmx_fsmc;
+extern struct pmx_dev spear320_pmx_spp;
+extern struct pmx_dev spear320_pmx_sdhci;
+extern struct pmx_dev spear320_pmx_i2s;
+extern struct pmx_dev spear320_pmx_uart1;
+extern struct pmx_dev spear320_pmx_uart1_modem;
+extern struct pmx_dev spear320_pmx_uart2;
+extern struct pmx_dev spear320_pmx_touchscreen;
+extern struct pmx_dev spear320_pmx_can;
+extern struct pmx_dev spear320_pmx_sdhci_led;
+extern struct pmx_dev spear320_pmx_pwm0;
+extern struct pmx_dev spear320_pmx_pwm1;
+extern struct pmx_dev spear320_pmx_pwm2;
+extern struct pmx_dev spear320_pmx_pwm3;
+extern struct pmx_dev spear320_pmx_ssp1;
+extern struct pmx_dev spear320_pmx_ssp2;
+extern struct pmx_dev spear320_pmx_mii1;
+extern struct pmx_dev spear320_pmx_smii0;
+extern struct pmx_dev spear320_pmx_smii1;
+extern struct pmx_dev spear320_pmx_i2c1;
/* pad multiplexing support */
#define SPEAR320_PAD_MUX_CONFIG_REG 0xB300000C
#define SPEAR320_MODE_CONFIG_REG 0xB3000010
/* Add spear320 machine function declarations here */
-void __init spear320_init(void);
+void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
/* Add misc structure declarations here */
extern struct clcd_board clcd_plat_data;
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 5660fd0..bd9d1ce 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -131,7 +131,7 @@ static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
},
};
-struct pmx_dev pmx_fsmc_2_chips = {
+struct pmx_dev spear300_pmx_fsmc_2_chips = {
.name = "fsmc_2_chips",
.modes = pmx_fsmc_2_chips_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
@@ -154,7 +154,7 @@ static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
},
};
-struct pmx_dev pmx_fsmc_4_chips = {
+struct pmx_dev spear300_pmx_fsmc_4_chips = {
.name = "fsmc_4_chips",
.modes = pmx_fsmc_4_chips_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
@@ -179,7 +179,7 @@ static struct pmx_dev_mode pmx_keyboard_modes[] = {
},
};
-struct pmx_dev pmx_keyboard = {
+struct pmx_dev spear300_pmx_keyboard = {
.name = "keyboard",
.modes = pmx_keyboard_modes,
.mode_count = ARRAY_SIZE(pmx_keyboard_modes),
@@ -213,7 +213,7 @@ static struct pmx_dev_mode pmx_clcd_modes[] = {
},
};
-struct pmx_dev pmx_clcd = {
+struct pmx_dev spear300_pmx_clcd = {
.name = "clcd",
.modes = pmx_clcd_modes,
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
@@ -280,7 +280,7 @@ static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
},
};
-struct pmx_dev pmx_telecom_gpio = {
+struct pmx_dev spear300_pmx_telecom_gpio = {
.name = "telecom_gpio",
.modes = pmx_telecom_gpio_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
@@ -306,7 +306,7 @@ static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
},
};
-struct pmx_dev pmx_telecom_tdm = {
+struct pmx_dev spear300_pmx_telecom_tdm = {
.name = "telecom_tdm",
.modes = pmx_telecom_tdm_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
@@ -331,7 +331,7 @@ static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
},
};
-struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
+struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
.name = "telecom_spi_cs_i2c_clk",
.modes = pmx_telecom_spi_cs_i2c_clk_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
@@ -363,7 +363,7 @@ static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
},
};
-struct pmx_dev pmx_telecom_camera = {
+struct pmx_dev spear300_pmx_telecom_camera = {
.name = "telecom_camera",
.modes = pmx_telecom_camera_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
@@ -386,7 +386,7 @@ static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
},
};
-struct pmx_dev pmx_telecom_dac = {
+struct pmx_dev spear300_pmx_telecom_dac = {
.name = "telecom_dac",
.modes = pmx_telecom_dac_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
@@ -411,7 +411,7 @@ static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
},
};
-struct pmx_dev pmx_telecom_i2s = {
+struct pmx_dev spear300_pmx_telecom_i2s = {
.name = "telecom_i2s",
.modes = pmx_telecom_i2s_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
@@ -434,7 +434,7 @@ static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
},
};
-struct pmx_dev pmx_telecom_boot_pins = {
+struct pmx_dev spear300_pmx_telecom_boot_pins = {
.name = "telecom_boot_pins",
.modes = pmx_telecom_boot_pins_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
@@ -462,7 +462,7 @@ static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
},
};
-struct pmx_dev pmx_telecom_sdhci_4bit = {
+struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
.name = "telecom_sdhci_4bit",
.modes = pmx_telecom_sdhci_4bit_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
@@ -489,7 +489,7 @@ static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
},
};
-struct pmx_dev pmx_telecom_sdhci_8bit = {
+struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
.name = "telecom_sdhci_8bit",
.modes = pmx_telecom_sdhci_8bit_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
@@ -512,14 +512,14 @@ static struct pmx_dev_mode pmx_gpio1_modes[] = {
},
};
-struct pmx_dev pmx_gpio1 = {
+struct pmx_dev spear300_pmx_gpio1 = {
.name = "arm gpio1",
.modes = pmx_gpio1_modes,
.mode_count = ARRAY_SIZE(pmx_gpio1_modes),
};
/* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
.mode_reg = {.address = SPEAR300_MODE_CONFIG_REG, .mask = 0x0000000f},
};
@@ -773,7 +773,8 @@ void sdhci_i2s_mem_enable(u8 mask)
}
/* spear300 routines */
-void __init spear300_init(void)
+void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
int ret = 0;
@@ -788,10 +789,13 @@ void __init spear300_init(void)
printk(KERN_ERR "Error registering Shared IRQ\n");
}
+ /* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
/* This fixes addresses of all pmx devices for spear300 */
spear3xx_pmx_init_addr(&pmx_driver, SPEAR300_PAD_MUX_CONFIG_REG);
-
- /* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
pr_err("padmux: registeration failed. err no: %d\n", ret);
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 8e6fff0..31c9e59 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -28,17 +28,17 @@
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp_cs,
- &pmx_ssp,
- &pmx_mii,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp_cs,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_mii,
+ &spear3xx_pmx_uart0,
/* spear300 specific devices */
- &pmx_fsmc_2_chips,
- &pmx_clcd,
- &pmx_telecom_sdhci_4bit,
- &pmx_gpio1,
+ &spear300_pmx_fsmc_2_chips,
+ &spear300_pmx_clcd,
+ &spear300_pmx_telecom_sdhci_4bit,
+ &spear300_pmx_gpio1,
};
static struct amba_device *amba_devs[] __initdata = {
@@ -109,11 +109,6 @@ static void __init spear300_evb_init(void)
{
unsigned int i;
- /* padmux initialization, must be done before spear300_init */
- pmx_driver.mode = &photo_frame_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* set keyboard plat data */
kbd_set_plat_data(&kbd_device, &kbd_data);
@@ -128,7 +123,7 @@ static void __init spear300_evb_init(void)
sdhci_i2s_mem_enable(SDHCI_MEM_ENB);
/* call spear300 machine init function */
- spear300_init();
+ spear300_init(&photo_frame_mode, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 0995535..9a45972 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -38,7 +38,7 @@ static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
},
};
-struct pmx_dev pmx_emi_cs_0_1_4_5 = {
+struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
.name = "emi_cs_0_1_4_5",
.modes = pmx_emi_cs_0_1_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
@@ -59,7 +59,7 @@ static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
},
};
-struct pmx_dev pmx_emi_cs_2_3 = {
+struct pmx_dev spear310_pmx_emi_cs_2_3 = {
.name = "emi_cs_2_3",
.modes = pmx_emi_cs_2_3_modes,
.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
@@ -80,7 +80,7 @@ static struct pmx_dev_mode pmx_uart1_modes[] = {
},
};
-struct pmx_dev pmx_uart1 = {
+struct pmx_dev spear310_pmx_uart1 = {
.name = "uart1",
.modes = pmx_uart1_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
@@ -101,7 +101,7 @@ static struct pmx_dev_mode pmx_uart2_modes[] = {
},
};
-struct pmx_dev pmx_uart2 = {
+struct pmx_dev spear310_pmx_uart2 = {
.name = "uart2",
.modes = pmx_uart2_modes,
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
@@ -122,7 +122,7 @@ static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
},
};
-struct pmx_dev pmx_uart3_4_5 = {
+struct pmx_dev spear310_pmx_uart3_4_5 = {
.name = "uart3_4_5",
.modes = pmx_uart3_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
@@ -143,7 +143,7 @@ static struct pmx_dev_mode pmx_fsmc_modes[] = {
},
};
-struct pmx_dev pmx_fsmc = {
+struct pmx_dev spear310_pmx_fsmc = {
.name = "fsmc",
.modes = pmx_fsmc_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
@@ -164,7 +164,7 @@ static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
},
};
-struct pmx_dev pmx_rs485_0_1 = {
+struct pmx_dev spear310_pmx_rs485_0_1 = {
.name = "rs485_0_1",
.modes = pmx_rs485_0_1_modes,
.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
@@ -185,14 +185,14 @@ static struct pmx_dev_mode pmx_tdm0_modes[] = {
},
};
-struct pmx_dev pmx_tdm0 = {
+struct pmx_dev spear310_pmx_tdm0 = {
.name = "tdm0",
.modes = pmx_tdm0_modes,
.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
};
/* pmx driver structure */
-struct pmx_driver pmx_driver;
+static struct pmx_driver pmx_driver;
/* Add spear310 specific devices here */
/* uart1 device registeration */
@@ -479,7 +479,8 @@ static struct spear_shirq shirq_intrcomm_ras = {
};
/* spear310 routines */
-void __init spear310_init(void)
+void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
void __iomem *base;
int ret = 0;
@@ -515,10 +516,13 @@ void __init spear310_init(void)
printk(KERN_ERR "Error registering Shared IRQ 4\n");
}
+ /* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
/* This fixes addresses of all pmx devices for spear310 */
spear3xx_pmx_init_addr(&pmx_driver, SPEAR310_PAD_MUX_CONFIG_REG);
-
- /* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
pr_err("padmux: registeration failed. err no: %d\n", ret);
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index a3cd4a1..f51540f 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -45,25 +45,25 @@ static struct resource emi_nor_resources[] = {
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp,
- &pmx_gpio_pin0,
- &pmx_gpio_pin1,
- &pmx_gpio_pin2,
- &pmx_gpio_pin3,
- &pmx_gpio_pin4,
- &pmx_gpio_pin5,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_gpio_pin0,
+ &spear3xx_pmx_gpio_pin1,
+ &spear3xx_pmx_gpio_pin2,
+ &spear3xx_pmx_gpio_pin3,
+ &spear3xx_pmx_gpio_pin4,
+ &spear3xx_pmx_gpio_pin5,
+ &spear3xx_pmx_uart0,
/* spear310 specific devices */
- &pmx_emi_cs_0_1_4_5,
- &pmx_emi_cs_2_3,
- &pmx_uart1,
- &pmx_uart2,
- &pmx_uart3_4_5,
- &pmx_fsmc,
- &pmx_rs485_0_1,
- &pmx_tdm0,
+ &spear310_pmx_emi_cs_0_1_4_5,
+ &spear310_pmx_emi_cs_2_3,
+ &spear310_pmx_uart1,
+ &spear310_pmx_uart2,
+ &spear310_pmx_uart3_4_5,
+ &spear310_pmx_fsmc,
+ &spear310_pmx_rs485_0_1,
+ &spear310_pmx_tdm0,
};
static struct amba_device *amba_devs[] __initdata = {
@@ -124,17 +124,12 @@ static void __init spear310_evb_init(void)
{
unsigned int i;
- /* padmux initialization, must be done before spear310_init */
- pmx_driver.mode = NULL;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* set nand device's plat data */
fsmc_nand_set_plat_data(&nand_device, NULL, 0, NAND_SKIP_BBTSCAN,
FSMC_NAND_BW8);
/* call spear310 machine init function */
- spear310_init();
+ spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 00d206f..82b8cbe 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -71,7 +71,7 @@ static struct pmx_dev_mode pmx_clcd_modes[] = {
},
};
-struct pmx_dev pmx_clcd = {
+struct pmx_dev spear320_pmx_clcd = {
.name = "clcd",
.modes = pmx_clcd_modes,
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
@@ -93,7 +93,7 @@ static struct pmx_dev_mode pmx_emi_modes[] = {
},
};
-struct pmx_dev pmx_emi = {
+struct pmx_dev spear320_pmx_emi = {
.name = "emi",
.modes = pmx_emi_modes,
.mode_count = ARRAY_SIZE(pmx_emi_modes),
@@ -115,7 +115,7 @@ static struct pmx_dev_mode pmx_fsmc_modes[] = {
},
};
-struct pmx_dev pmx_fsmc = {
+struct pmx_dev spear320_pmx_fsmc = {
.name = "fsmc",
.modes = pmx_fsmc_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
@@ -137,7 +137,7 @@ static struct pmx_dev_mode pmx_spp_modes[] = {
},
};
-struct pmx_dev pmx_spp = {
+struct pmx_dev spear320_pmx_spp = {
.name = "spp",
.modes = pmx_spp_modes,
.mode_count = ARRAY_SIZE(pmx_spp_modes),
@@ -160,7 +160,7 @@ static struct pmx_dev_mode pmx_sdhci_modes[] = {
},
};
-struct pmx_dev pmx_sdhci = {
+struct pmx_dev spear320_pmx_sdhci = {
.name = "sdhci",
.modes = pmx_sdhci_modes,
.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
@@ -182,7 +182,7 @@ static struct pmx_dev_mode pmx_i2s_modes[] = {
},
};
-struct pmx_dev pmx_i2s = {
+struct pmx_dev spear320_pmx_i2s = {
.name = "i2s",
.modes = pmx_i2s_modes,
.mode_count = ARRAY_SIZE(pmx_i2s_modes),
@@ -204,7 +204,7 @@ static struct pmx_dev_mode pmx_uart1_modes[] = {
},
};
-struct pmx_dev pmx_uart1 = {
+struct pmx_dev spear320_pmx_uart1 = {
.name = "uart1",
.modes = pmx_uart1_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
@@ -239,7 +239,7 @@ static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
},
};
-struct pmx_dev pmx_uart1_modem = {
+struct pmx_dev spear320_pmx_uart1_modem = {
.name = "uart1_modem",
.modes = pmx_uart1_modem_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
@@ -261,7 +261,7 @@ static struct pmx_dev_mode pmx_uart2_modes[] = {
},
};
-struct pmx_dev pmx_uart2 = {
+struct pmx_dev spear320_pmx_uart2 = {
.name = "uart2",
.modes = pmx_uart2_modes,
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
@@ -283,7 +283,7 @@ static struct pmx_dev_mode pmx_touchscreen_modes[] = {
},
};
-struct pmx_dev pmx_touchscreen = {
+struct pmx_dev spear320_pmx_touchscreen = {
.name = "touchscreen",
.modes = pmx_touchscreen_modes,
.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
@@ -306,7 +306,7 @@ static struct pmx_dev_mode pmx_can_modes[] = {
},
};
-struct pmx_dev pmx_can = {
+struct pmx_dev spear320_pmx_can = {
.name = "can",
.modes = pmx_can_modes,
.mode_count = ARRAY_SIZE(pmx_can_modes),
@@ -328,7 +328,7 @@ static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
},
};
-struct pmx_dev pmx_sdhci_led = {
+struct pmx_dev spear320_pmx_sdhci_led = {
.name = "sdhci_led",
.modes = pmx_sdhci_led_modes,
.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
@@ -361,7 +361,7 @@ static struct pmx_dev_mode pmx_pwm0_modes[] = {
},
};
-struct pmx_dev pmx_pwm0 = {
+struct pmx_dev spear320_pmx_pwm0 = {
.name = "pwm0",
.modes = pmx_pwm0_modes,
.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
@@ -394,7 +394,7 @@ static struct pmx_dev_mode pmx_pwm1_modes[] = {
},
};
-struct pmx_dev pmx_pwm1 = {
+struct pmx_dev spear320_pmx_pwm1 = {
.name = "pwm1",
.modes = pmx_pwm1_modes,
.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
@@ -427,7 +427,7 @@ static struct pmx_dev_mode pmx_pwm2_modes[] = {
},
};
-struct pmx_dev pmx_pwm2 = {
+struct pmx_dev spear320_pmx_pwm2 = {
.name = "pwm2",
.modes = pmx_pwm2_modes,
.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
@@ -449,7 +449,7 @@ static struct pmx_dev_mode pmx_pwm3_modes[] = {
},
};
-struct pmx_dev pmx_pwm3 = {
+struct pmx_dev spear320_pmx_pwm3 = {
.name = "pwm3",
.modes = pmx_pwm3_modes,
.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
@@ -471,7 +471,7 @@ static struct pmx_dev_mode pmx_ssp1_modes[] = {
},
};
-struct pmx_dev pmx_ssp1 = {
+struct pmx_dev spear320_pmx_ssp1 = {
.name = "ssp1",
.modes = pmx_ssp1_modes,
.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
@@ -493,7 +493,7 @@ static struct pmx_dev_mode pmx_ssp2_modes[] = {
},
};
-struct pmx_dev pmx_ssp2 = {
+struct pmx_dev spear320_pmx_ssp2 = {
.name = "ssp2",
.modes = pmx_ssp2_modes,
.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
@@ -515,7 +515,7 @@ static struct pmx_dev_mode pmx_mii1_modes[] = {
},
};
-struct pmx_dev pmx_mii1 = {
+struct pmx_dev spear320_pmx_mii1 = {
.name = "mii1",
.modes = pmx_mii1_modes,
.mode_count = ARRAY_SIZE(pmx_mii1_modes),
@@ -537,7 +537,7 @@ static struct pmx_dev_mode pmx_smii0_modes[] = {
},
};
-struct pmx_dev pmx_smii0 = {
+struct pmx_dev spear320_pmx_smii0 = {
.name = "smii0",
.modes = pmx_smii0_modes,
.mode_count = ARRAY_SIZE(pmx_smii0_modes),
@@ -559,7 +559,7 @@ static struct pmx_dev_mode pmx_smii1_modes[] = {
},
};
-struct pmx_dev pmx_smii1 = {
+struct pmx_dev spear320_pmx_smii1 = {
.name = "smii1",
.modes = pmx_smii1_modes,
.mode_count = ARRAY_SIZE(pmx_smii1_modes),
@@ -581,14 +581,14 @@ static struct pmx_dev_mode pmx_i2c1_modes[] = {
},
};
-struct pmx_dev pmx_i2c1 = {
+struct pmx_dev spear320_pmx_i2c1 = {
.name = "i2c1",
.modes = pmx_i2c1_modes,
.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
};
/* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
.mode_reg = {.address = SPEAR320_MODE_CONFIG_REG, .mask = 0x00000007},
};
@@ -959,7 +959,8 @@ static struct spear_shirq shirq_intrcomm_ras = {
};
/* spear320 routines */
-void __init spear320_init(void)
+void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
void __iomem *base;
int ret = 0;
@@ -989,10 +990,13 @@ void __init spear320_init(void)
printk(KERN_ERR "Error registering Shared IRQ 4\n");
}
+ /* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
/* This fixes addresses of all pmx devices for spear320 */
spear3xx_pmx_init_addr(&pmx_driver, SPEAR320_PAD_MUX_CONFIG_REG);
-
- /* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
pr_err("padmux: registeration failed. err no: %d\n", ret);
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index e1a0b3c..a87c6a9 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -46,22 +46,22 @@ static struct resource emi_nor_resources[] = {
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp,
- &pmx_mii,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_mii,
+ &spear3xx_pmx_uart0,
/* spear320 specific devices */
- &pmx_fsmc,
- &pmx_sdhci,
- &pmx_i2s,
- &pmx_uart1,
- &pmx_uart2,
- &pmx_can,
- &pmx_pwm0,
- &pmx_pwm1,
- &pmx_pwm2,
- &pmx_mii1,
+ &spear320_pmx_fsmc,
+ &spear320_pmx_sdhci,
+ &spear320_pmx_i2s,
+ &spear320_pmx_uart1,
+ &spear320_pmx_uart2,
+ &spear320_pmx_can,
+ &spear320_pmx_pwm0,
+ &spear320_pmx_pwm1,
+ &spear320_pmx_pwm2,
+ &spear320_pmx_mii1,
};
static struct amba_device *amba_devs[] __initdata = {
@@ -110,17 +110,12 @@ static void __init spear320_evb_init(void)
/* set sdhci device platform data */
sdhci_set_plat_data(&sdhci_device, &sdhci_plat_data);
- /* padmux initialization, must be done before spear320_init */
- pmx_driver.mode = &auto_net_mii_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* set nand device's plat data */
fsmc_nand_set_plat_data(&nand_device, NULL, 0, NAND_SKIP_BBTSCAN,
FSMC_NAND_BW8);
/* call spear320 machine init function */
- spear320_init();
+ spear320_init(&auto_net_mii_mode, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 662ab1d..4ec916a 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -291,7 +291,7 @@ static struct pmx_dev_mode pmx_firda_modes[] = {
},
};
-struct pmx_dev pmx_firda = {
+struct pmx_dev spear3xx_pmx_firda = {
.name = "firda",
.modes = pmx_firda_modes,
.mode_count = ARRAY_SIZE(pmx_firda_modes),
@@ -313,7 +313,7 @@ static struct pmx_dev_mode pmx_i2c_modes[] = {
},
};
-struct pmx_dev pmx_i2c = {
+struct pmx_dev spear3xx_pmx_i2c = {
.name = "i2c",
.modes = pmx_i2c_modes,
.mode_count = ARRAY_SIZE(pmx_i2c_modes),
@@ -335,7 +335,7 @@ static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
},
};
-struct pmx_dev pmx_ssp_cs = {
+struct pmx_dev spear3xx_pmx_ssp_cs = {
.name = "ssp_chip_selects",
.modes = pmx_ssp_cs_modes,
.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
@@ -357,7 +357,7 @@ static struct pmx_dev_mode pmx_ssp_modes[] = {
},
};
-struct pmx_dev pmx_ssp = {
+struct pmx_dev spear3xx_pmx_ssp = {
.name = "ssp",
.modes = pmx_ssp_modes,
.mode_count = ARRAY_SIZE(pmx_ssp_modes),
@@ -379,7 +379,7 @@ static struct pmx_dev_mode pmx_mii_modes[] = {
},
};
-struct pmx_dev pmx_mii = {
+struct pmx_dev spear3xx_pmx_mii = {
.name = "mii",
.modes = pmx_mii_modes,
.mode_count = ARRAY_SIZE(pmx_mii_modes),
@@ -401,7 +401,7 @@ static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin0 = {
+struct pmx_dev spear3xx_pmx_gpio_pin0 = {
.name = "gpio_pin0",
.modes = pmx_gpio_pin0_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
@@ -423,7 +423,7 @@ static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin1 = {
+struct pmx_dev spear3xx_pmx_gpio_pin1 = {
.name = "gpio_pin1",
.modes = pmx_gpio_pin1_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
@@ -445,7 +445,7 @@ static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin2 = {
+struct pmx_dev spear3xx_pmx_gpio_pin2 = {
.name = "gpio_pin2",
.modes = pmx_gpio_pin2_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
@@ -467,7 +467,7 @@ static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin3 = {
+struct pmx_dev spear3xx_pmx_gpio_pin3 = {
.name = "gpio_pin3",
.modes = pmx_gpio_pin3_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
@@ -489,7 +489,7 @@ static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin4 = {
+struct pmx_dev spear3xx_pmx_gpio_pin4 = {
.name = "gpio_pin4",
.modes = pmx_gpio_pin4_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
@@ -511,7 +511,7 @@ static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin5 = {
+struct pmx_dev spear3xx_pmx_gpio_pin5 = {
.name = "gpio_pin5",
.modes = pmx_gpio_pin5_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
@@ -533,7 +533,7 @@ static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
},
};
-struct pmx_dev pmx_uart0_modem = {
+struct pmx_dev spear3xx_pmx_uart0_modem = {
.name = "uart0_modem",
.modes = pmx_uart0_modem_modes,
.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
@@ -555,7 +555,7 @@ static struct pmx_dev_mode pmx_uart0_modes[] = {
},
};
-struct pmx_dev pmx_uart0 = {
+struct pmx_dev spear3xx_pmx_uart0 = {
.name = "uart0",
.modes = pmx_uart0_modes,
.mode_count = ARRAY_SIZE(pmx_uart0_modes),
@@ -577,7 +577,7 @@ static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
},
};
-struct pmx_dev pmx_timer_3_4 = {
+struct pmx_dev spear3xx_pmx_timer_3_4 = {
.name = "timer_3_4",
.modes = pmx_timer_3_4_modes,
.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
@@ -599,7 +599,7 @@ static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
},
};
-struct pmx_dev pmx_timer_1_2 = {
+struct pmx_dev spear3xx_pmx_timer_1_2 = {
.name = "timer_1_2",
.modes = pmx_timer_1_2_modes,
.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
@@ -622,7 +622,7 @@ static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_0_1 = {
+struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
.name = "plgpio 0 and 1",
.modes = pmx_plgpio_0_1_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
@@ -644,7 +644,7 @@ static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_2_3 = {
+struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
.name = "plgpio 2 and 3",
.modes = pmx_plgpio_2_3_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
@@ -666,7 +666,7 @@ static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_4_5 = {
+struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
.name = "plgpio 4 and 5",
.modes = pmx_plgpio_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
@@ -688,7 +688,7 @@ static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_6_9 = {
+struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
.name = "plgpio 6 to 9",
.modes = pmx_plgpio_6_9_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
@@ -710,7 +710,7 @@ static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_10_27 = {
+struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
.name = "plgpio 10 to 27",
.modes = pmx_plgpio_10_27_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
@@ -732,7 +732,7 @@ static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_28 = {
+struct pmx_dev spear3xx_pmx_plgpio_28 = {
.name = "plgpio 28",
.modes = pmx_plgpio_28_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
@@ -754,7 +754,7 @@ static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_29 = {
+struct pmx_dev spear3xx_pmx_plgpio_29 = {
.name = "plgpio 29",
.modes = pmx_plgpio_29_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
@@ -776,7 +776,7 @@ static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_30 = {
+struct pmx_dev spear3xx_pmx_plgpio_30 = {
.name = "plgpio 30",
.modes = pmx_plgpio_30_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
@@ -798,7 +798,7 @@ static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_31 = {
+struct pmx_dev spear3xx_pmx_plgpio_31 = {
.name = "plgpio 31",
.modes = pmx_plgpio_31_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
@@ -820,7 +820,7 @@ static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_32 = {
+struct pmx_dev spear3xx_pmx_plgpio_32 = {
.name = "plgpio 32",
.modes = pmx_plgpio_32_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
@@ -842,7 +842,7 @@ static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_33 = {
+struct pmx_dev spear3xx_pmx_plgpio_33 = {
.name = "plgpio 33",
.modes = pmx_plgpio_33_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
@@ -864,7 +864,7 @@ static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_34_36 = {
+struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
.name = "plgpio 34 to 36",
.modes = pmx_plgpio_34_36_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
@@ -886,7 +886,7 @@ static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_37_42 = {
+struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
.name = "plgpio 37 to 42",
.modes = pmx_plgpio_37_42_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
@@ -908,7 +908,7 @@ static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_43_44_47_48 = {
+struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
.name = "plgpio 43, 44, 47 and 48",
.modes = pmx_plgpio_43_44_47_48_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
@@ -930,7 +930,7 @@ static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_45_46_49_50 = {
+struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
.name = "plgpio 45, 46, 49 and 50",
.modes = pmx_plgpio_45_46_49_50_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 53/62] SPEAr3xx: Rework KConfig to allow all boards to be compiled in
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (50 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 52/62] SPEAr3xx: Rework pmx_dev code to remove conflicts Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 54/62] SPEAr3xx: Replace defconfigs with single unified defconfig Viresh Kumar
` (9 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Ryan Mallon <ryan@bluewatersys.com>
Now that all three SPEAr3xx platforms can be built into one kernel,
rework KConfig to allow this. Move everything into one KConfig file
while we are here.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/Kconfig | 30 ++++++++++++++++--------
arch/arm/mach-spear3xx/Kconfig300 | 17 --------------
arch/arm/mach-spear3xx/Kconfig310 | 17 --------------
arch/arm/mach-spear3xx/Kconfig320 | 17 --------------
arch/arm/mach-spear3xx/include/mach/generic.h | 6 +++-
5 files changed, 24 insertions(+), 63 deletions(-)
delete mode 100644 arch/arm/mach-spear3xx/Kconfig300
delete mode 100644 arch/arm/mach-spear3xx/Kconfig310
delete mode 100644 arch/arm/mach-spear3xx/Kconfig320
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 20d1317..2cee6b0 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -4,9 +4,26 @@
if ARCH_SPEAR3XX
-choice
- prompt "SPEAr3XX Family"
- default MACH_SPEAR300
+menu "SPEAr3xx Implementations"
+config BOARD_SPEAR300_EVB
+ bool "SPEAr300 Evaluation Board"
+ select MACH_SPEAR300
+ help
+ Supports ST SPEAr300 Evaluation Board
+
+config BOARD_SPEAR310_EVB
+ bool "SPEAr310 Evaluation Board"
+ select MACH_SPEAR310
+ help
+ Supports ST SPEAr310 Evaluation Board
+
+config BOARD_SPEAR320_EVB
+ bool "SPEAr320 Evaluation Board"
+ select MACH_SPEAR320
+ help
+ Supports ST SPEAr320 Evaluation Board
+
+endmenu
config MACH_SPEAR300
bool "SPEAr300"
@@ -23,11 +40,4 @@ config MACH_SPEAR320
help
Supports ST SPEAr320 Machine
-endchoice
-
-# Adding SPEAr3XX machine specific configuration files
-source "arch/arm/mach-spear3xx/Kconfig300"
-source "arch/arm/mach-spear3xx/Kconfig310"
-source "arch/arm/mach-spear3xx/Kconfig320"
-
endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300
deleted file mode 100644
index c519a05..0000000
--- a/arch/arm/mach-spear3xx/Kconfig300
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr300 machine configuration file
-#
-
-if MACH_SPEAR300
-
-choice
- prompt "SPEAr300 Boards"
- default BOARD_SPEAR300_EVB
-
-config BOARD_SPEAR300_EVB
- bool "SPEAr300 Evaluation Board"
- help
- Supports ST SPEAr300 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR300
diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310
deleted file mode 100644
index 60e7442..0000000
--- a/arch/arm/mach-spear3xx/Kconfig310
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr310 machine configuration file
-#
-
-if MACH_SPEAR310
-
-choice
- prompt "SPEAr310 Boards"
- default BOARD_SPEAR310_EVB
-
-config BOARD_SPEAR310_EVB
- bool "SPEAr310 Evaluation Board"
- help
- Supports ST SPEAr310 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR310
diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320
deleted file mode 100644
index 1c1d438..0000000
--- a/arch/arm/mach-spear3xx/Kconfig320
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr320 machine configuration file
-#
-
-if MACH_SPEAR320
-
-choice
- prompt "SPEAr320 Boards"
- default BOARD_SPEAR320_EVB
-
-config BOARD_SPEAR320_EVB
- bool "SPEAr320 Evaluation Board"
- help
- Supports ST SPEAr320 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR320
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index d250c96..3c2b189 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -160,9 +160,10 @@ void sdhci_i2s_mem_enable(u8 mask);
/* Add misc structure declarations here */
extern struct clcd_board clcd_plat_data;
+#endif
/* spear310 declarations */
-#elif defined(CONFIG_MACH_SPEAR310)
+#if defined(CONFIG_MACH_SPEAR310)
/* Add spear310 machine device structure declarations here */
extern struct amba_device uart1_device;
extern struct amba_device uart2_device;
@@ -187,9 +188,10 @@ extern struct pmx_dev spear310_pmx_tdm0;
/* Add spear310 machine function declarations here */
void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
u8 pmx_dev_count);
+#endif
/* spear320 declarations */
-#elif defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR320)
/* Add spear320 machine device structure declarations here */
extern struct amba_device clcd_device;
extern struct amba_device ssp_device[];
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 54/62] SPEAr3xx: Replace defconfigs with single unified defconfig
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (51 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 53/62] SPEAr3xx: Rework KConfig to allow all boards to be compiled in Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 55/62] ST SPEAr: Appending spear3** with global structures Viresh Kumar
` (8 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Ryan Mallon <ryan@bluewatersys.com>
We only need one defconfig for SPEAr3xx now since we can build all
three boards into one kernel.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/configs/spear310_defconfig | 52 --------------------
arch/arm/configs/spear320_defconfig | 52 --------------------
.../{spear300_defconfig => spear3xx_defconfig} | 4 +-
3 files changed, 3 insertions(+), 105 deletions(-)
delete mode 100644 arch/arm/configs/spear310_defconfig
delete mode 100644 arch/arm/configs/spear320_defconfig
rename arch/arm/configs/{spear300_defconfig => spear3xx_defconfig} (93%)
diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig
deleted file mode 100644
index 824e444..0000000
--- a/arch/arm/configs/spear310_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_MACH_SPEAR310=y
-CONFIG_BINFMT_MISC=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig
deleted file mode 100644
index 842f7f3..0000000
--- a/arch/arm/configs/spear320_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_MACH_SPEAR320=y
-CONFIG_BINFMT_MISC=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear3xx_defconfig
similarity index 93%
rename from arch/arm/configs/spear300_defconfig
rename to arch/arm/configs/spear3xx_defconfig
index cf29f3e..fea7e1f 100644
--- a/arch/arm/configs/spear300_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -7,6 +7,9 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PLAT_SPEAR=y
+CONFIG_BOARD_SPEAR300_EVB=y
+CONFIG_BOARD_SPEAR310_EVB=y
+CONFIG_BOARD_SPEAR320_EVB=y
CONFIG_BINFMT_MISC=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_RAM=y
@@ -24,7 +27,6 @@ CONFIG_MAX_RAW_DEVS=8192
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 55/62] ST SPEAr: Appending spear3** with global structures
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (52 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 54/62] SPEAr3xx: Replace defconfigs with single unified defconfig Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 56/62] ST SPEAr3xx: Updating plgpio and emi source to make it compliant with single image strategy Viresh Kumar
` (7 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 138 ++++++++++++------------
arch/arm/mach-spear3xx/spear300.c | 42 ++++----
arch/arm/mach-spear3xx/spear300_evb.c | 39 ++++----
arch/arm/mach-spear3xx/spear310.c | 16 ++--
arch/arm/mach-spear3xx/spear310_evb.c | 33 +++---
arch/arm/mach-spear3xx/spear320.c | 36 +++---
arch/arm/mach-spear3xx/spear320_evb.c | 46 +++++----
arch/arm/mach-spear3xx/spear3xx.c | 18 ++--
8 files changed, 186 insertions(+), 182 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 3c2b189..f08b5ef 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -31,15 +31,15 @@
#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
/* Add spear3xx family device structure declarations here */
-extern struct amba_device gpio_device;
-extern struct amba_device ssp0_device;
-extern struct amba_device uart_device;
-extern struct amba_device wdt_device;
-extern struct platform_device ehci_device;
-extern struct platform_device i2c_device;
-extern struct platform_device ohci0_device;
-extern struct platform_device ohci1_device;
-extern struct platform_device rtc_device;
+extern struct amba_device spear3xx_gpio_device;
+extern struct amba_device spear3xx_ssp0_device;
+extern struct amba_device spear3xx_uart_device;
+extern struct amba_device spear3xx_wdt_device;
+extern struct platform_device spear3xx_ehci_device;
+extern struct platform_device spear3xx_i2c_device;
+extern struct platform_device spear3xx_ohci0_device;
+extern struct platform_device spear3xx_ohci1_device;
+extern struct platform_device spear3xx_rtc_device;
extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
@@ -87,49 +87,49 @@ extern struct pmx_dev spear3xx_pmx_timer_1_2;
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
/* padmux plgpio devices */
-extern struct pmx_dev pmx_plgpio_0_1;
-extern struct pmx_dev pmx_plgpio_2_3;
-extern struct pmx_dev pmx_plgpio_4_5;
-extern struct pmx_dev pmx_plgpio_6_9;
-extern struct pmx_dev pmx_plgpio_10_27;
-extern struct pmx_dev pmx_plgpio_28;
-extern struct pmx_dev pmx_plgpio_29;
-extern struct pmx_dev pmx_plgpio_30;
-extern struct pmx_dev pmx_plgpio_31;
-extern struct pmx_dev pmx_plgpio_32;
-extern struct pmx_dev pmx_plgpio_33;
-extern struct pmx_dev pmx_plgpio_34_36;
-extern struct pmx_dev pmx_plgpio_37_42;
-extern struct pmx_dev pmx_plgpio_43_44_47_48;
-extern struct pmx_dev pmx_plgpio_45_46_49_50;
+extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
+extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
+extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
+extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
+extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
+extern struct pmx_dev spear3xx_pmx_plgpio_28;
+extern struct pmx_dev spear3xx_pmx_plgpio_29;
+extern struct pmx_dev spear3xx_pmx_plgpio_30;
+extern struct pmx_dev spear3xx_pmx_plgpio_31;
+extern struct pmx_dev spear3xx_pmx_plgpio_32;
+extern struct pmx_dev spear3xx_pmx_plgpio_33;
+extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
+extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
+extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
+extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
#endif
/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
/* Add spear300 machine device structure declarations here */
-extern struct amba_device clcd_device;
-extern struct amba_device gpio1_device;
-extern struct platform_device kbd_device;
-extern struct platform_device nand0_device;
-extern struct platform_device nand1_device;
-extern struct platform_device nand2_device;
-extern struct platform_device nand3_device;
-extern struct platform_device sdhci_device;
+extern struct amba_device spear300_clcd_device;
+extern struct amba_device spear300_gpio1_device;
+extern struct platform_device spear300_kbd_device;
+extern struct platform_device spear300_nand0_device;
+extern struct platform_device spear300_nand1_device;
+extern struct platform_device spear300_nand2_device;
+extern struct platform_device spear300_nand3_device;
+extern struct platform_device spear300_sdhci_device;
/* pad mux modes */
-extern struct pmx_mode nand_mode;
-extern struct pmx_mode nor_mode;
-extern struct pmx_mode photo_frame_mode;
-extern struct pmx_mode lend_ip_phone_mode;
-extern struct pmx_mode hend_ip_phone_mode;
-extern struct pmx_mode lend_wifi_phone_mode;
-extern struct pmx_mode hend_wifi_phone_mode;
-extern struct pmx_mode ata_pabx_wi2s_mode;
-extern struct pmx_mode ata_pabx_i2s_mode;
-extern struct pmx_mode caml_lcdw_mode;
-extern struct pmx_mode camu_lcd_mode;
-extern struct pmx_mode camu_wlcd_mode;
-extern struct pmx_mode caml_lcd_mode;
+extern struct pmx_mode spear300_nand_mode;
+extern struct pmx_mode spear300_nor_mode;
+extern struct pmx_mode spear300_photo_frame_mode;
+extern struct pmx_mode spear300_lend_ip_phone_mode;
+extern struct pmx_mode spear300_hend_ip_phone_mode;
+extern struct pmx_mode spear300_lend_wifi_phone_mode;
+extern struct pmx_mode spear300_hend_wifi_phone_mode;
+extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
+extern struct pmx_mode spear300_ata_pabx_i2s_mode;
+extern struct pmx_mode spear300_caml_lcdw_mode;
+extern struct pmx_mode spear300_camu_lcd_mode;
+extern struct pmx_mode spear300_camu_wlcd_mode;
+extern struct pmx_mode spear300_caml_lcd_mode;
/* pad mux devices */
extern struct pmx_dev spear300_pmx_fsmc_2_chips;
@@ -165,14 +165,14 @@ extern struct clcd_board clcd_plat_data;
/* spear310 declarations */
#if defined(CONFIG_MACH_SPEAR310)
/* Add spear310 machine device structure declarations here */
-extern struct amba_device uart1_device;
-extern struct amba_device uart2_device;
-extern struct amba_device uart3_device;
-extern struct amba_device uart4_device;
-extern struct amba_device uart5_device;
-extern struct platform_device emi_nor_device;
-extern struct platform_device plgpio_device;
-extern struct platform_device nand_device;
+extern struct amba_device spear310_uart1_device;
+extern struct amba_device spear310_uart2_device;
+extern struct amba_device spear310_uart3_device;
+extern struct amba_device spear310_uart4_device;
+extern struct amba_device spear310_uart5_device;
+extern struct platform_device spear310_emi_nor_device;
+extern struct platform_device spear310_plgpio_device;
+extern struct platform_device spear310_nand_device;
/* pad mux devices */
extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
@@ -193,24 +193,24 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
/* spear320 declarations */
#if defined(CONFIG_MACH_SPEAR320)
/* Add spear320 machine device structure declarations here */
-extern struct amba_device clcd_device;
-extern struct amba_device ssp_device[];
-extern struct amba_device uart1_device;
-extern struct amba_device uart2_device;
-extern struct platform_device can0_device;
-extern struct platform_device can1_device;
-extern struct platform_device emi_nor_device;
-extern struct platform_device i2c1_device;
-extern struct platform_device nand_device;
-extern struct platform_device plgpio_device;
-extern struct platform_device pwm_device;
-extern struct platform_device sdhci_device;
+extern struct amba_device spear320_clcd_device;
+extern struct amba_device spear320_ssp_device[];
+extern struct amba_device spear320_uart1_device;
+extern struct amba_device spear320_uart2_device;
+extern struct platform_device spear320_can0_device;
+extern struct platform_device spear320_can1_device;
+extern struct platform_device spear320_emi_nor_device;
+extern struct platform_device spear320_i2c1_device;
+extern struct platform_device spear320_nand_device;
+extern struct platform_device spear320_plgpio_device;
+extern struct platform_device spear320_pwm_device;
+extern struct platform_device spear320_sdhci_device;
/* pad mux modes */
-extern struct pmx_mode auto_net_smii_mode;
-extern struct pmx_mode auto_net_mii_mode;
-extern struct pmx_mode auto_exp_mode;
-extern struct pmx_mode small_printers_mode;
+extern struct pmx_mode spear320_auto_net_smii_mode;
+extern struct pmx_mode spear320_auto_net_mii_mode;
+extern struct pmx_mode spear320_auto_exp_mode;
+extern struct pmx_mode spear320_small_printers_mode;
/* pad mux devices */
extern struct pmx_dev spear320_pmx_clcd;
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index bd9d1ce..83171bd 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -36,79 +36,79 @@
#define CAML_LCD_MODE (1 << 12)
#define ALL_MODES 0x1FFF
-struct pmx_mode nand_mode = {
+struct pmx_mode spear300_nand_mode = {
.id = NAND_MODE,
.name = "nand mode",
.value = 0x00,
};
-struct pmx_mode nor_mode = {
+struct pmx_mode spear300_nor_mode = {
.id = NOR_MODE,
.name = "nor mode",
.value = 0x01,
};
-struct pmx_mode photo_frame_mode = {
+struct pmx_mode spear300_photo_frame_mode = {
.id = PHOTO_FRAME_MODE,
.name = "photo frame mode",
.value = 0x02,
};
-struct pmx_mode lend_ip_phone_mode = {
+struct pmx_mode spear300_lend_ip_phone_mode = {
.id = LEND_IP_PHONE_MODE,
.name = "lend ip phone mode",
.value = 0x03,
};
-struct pmx_mode hend_ip_phone_mode = {
+struct pmx_mode spear300_hend_ip_phone_mode = {
.id = HEND_IP_PHONE_MODE,
.name = "hend ip phone mode",
.value = 0x04,
};
-struct pmx_mode lend_wifi_phone_mode = {
+struct pmx_mode spear300_lend_wifi_phone_mode = {
.id = LEND_WIFI_PHONE_MODE,
.name = "lend wifi phone mode",
.value = 0x05,
};
-struct pmx_mode hend_wifi_phone_mode = {
+struct pmx_mode spear300_hend_wifi_phone_mode = {
.id = HEND_WIFI_PHONE_MODE,
.name = "hend wifi phone mode",
.value = 0x06,
};
-struct pmx_mode ata_pabx_wi2s_mode = {
+struct pmx_mode spear300_ata_pabx_wi2s_mode = {
.id = ATA_PABX_WI2S_MODE,
.name = "ata pabx wi2s mode",
.value = 0x07,
};
-struct pmx_mode ata_pabx_i2s_mode = {
+struct pmx_mode spear300_ata_pabx_i2s_mode = {
.id = ATA_PABX_I2S_MODE,
.name = "ata pabx i2s mode",
.value = 0x08,
};
-struct pmx_mode caml_lcdw_mode = {
+struct pmx_mode spear300_caml_lcdw_mode = {
.id = CAML_LCDW_MODE,
.name = "caml lcdw mode",
.value = 0x0C,
};
-struct pmx_mode camu_lcd_mode = {
+struct pmx_mode spear300_camu_lcd_mode = {
.id = CAMU_LCD_MODE,
.name = "camu lcd mode",
.value = 0x0D,
};
-struct pmx_mode camu_wlcd_mode = {
+struct pmx_mode spear300_camu_wlcd_mode = {
.id = CAMU_WLCD_MODE,
.name = "camu wlcd mode",
.value = 0x0E,
};
-struct pmx_mode caml_lcd_mode = {
+struct pmx_mode spear300_caml_lcd_mode = {
.id = CAML_LCD_MODE,
.name = "caml lcd mode",
.value = 0x0F,
@@ -526,7 +526,7 @@ static struct pmx_driver pmx_driver = {
/* Add spear300 specific devices here */
/* CLCD device registration */
-struct amba_device clcd_device = {
+struct amba_device spear300_clcd_device = {
.dev = {
.init_name = "clcd",
.coherent_dma_mask = ~0,
@@ -547,7 +547,7 @@ static struct pl061_platform_data gpio1_plat_data = {
.irq_base = SPEAR300_GPIO1_INT_BASE,
};
-struct amba_device gpio1_device = {
+struct amba_device spear300_gpio1_device = {
.dev = {
.init_name = "gpio1",
.platform_data = &gpio1_plat_data,
@@ -572,7 +572,7 @@ static struct resource kbd_resources[] = {
},
};
-struct platform_device kbd_device = {
+struct platform_device spear300_kbd_device = {
.name = "keyboard",
.id = -1,
.num_resources = ARRAY_SIZE(kbd_resources),
@@ -596,7 +596,7 @@ static struct resource nand0_resources[] = {
},
};
-struct platform_device nand0_device = {
+struct platform_device spear300_nand0_device = {
.name = "nand",
.id = 0,
.resource = nand0_resources,
@@ -620,7 +620,7 @@ static struct resource nand1_resources[] = {
},
};
-struct platform_device nand1_device = {
+struct platform_device spear300_nand1_device = {
.name = "nand",
.id = 1,
.resource = nand1_resources,
@@ -644,7 +644,7 @@ static struct resource nand2_resources[] = {
},
};
-struct platform_device nand2_device = {
+struct platform_device spear300_nand2_device = {
.name = "nand",
.id = 2,
.resource = nand2_resources,
@@ -668,7 +668,7 @@ static struct resource nand3_resources[] = {
},
};
-struct platform_device nand3_device = {
+struct platform_device spear300_nand3_device = {
.name = "nand",
.id = 3,
.resource = nand3_resources,
@@ -688,7 +688,7 @@ static struct resource sdhci_resources[] = {
}
};
-struct platform_device sdhci_device = {
+struct platform_device spear300_sdhci_device = {
.dev = {
.coherent_dma_mask = ~0,
},
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 31c9e59..05bb82c 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -43,28 +43,28 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &ssp0_device,
- &uart_device,
- &wdt_device,
+ &spear3xx_gpio_device,
+ &spear3xx_ssp0_device,
+ &spear3xx_uart_device,
+ &spear3xx_wdt_device,
/* spear300 specific devices */
- &clcd_device,
- &gpio1_device,
+ &spear300_clcd_device,
+ &spear300_gpio1_device,
};
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
- &ehci_device,
- &i2c_device,
- &nand0_device,
- &ohci0_device,
- &ohci1_device,
- &rtc_device,
+ &spear3xx_ehci_device,
+ &spear3xx_i2c_device,
+ &spear3xx_ohci0_device,
+ &spear3xx_ohci1_device,
+ &spear3xx_rtc_device,
/* spear300 specific devices */
- &kbd_device,
- &sdhci_device,
+ &spear300_kbd_device,
+ &spear300_nand0_device,
+ &spear300_sdhci_device,
};
/* sdhci board specific information */
@@ -110,20 +110,21 @@ static void __init spear300_evb_init(void)
unsigned int i;
/* set keyboard plat data */
- kbd_set_plat_data(&kbd_device, &kbd_data);
+ kbd_set_plat_data(&spear300_kbd_device, &kbd_data);
/* set nand0 device's plat data */
- fsmc_nand_set_plat_data(&nand0_device, NULL, 0, NAND_SKIP_BBTSCAN,
- FSMC_NAND_BW8);
+ fsmc_nand_set_plat_data(&spear300_nand0_device, NULL, 0,
+ NAND_SKIP_BBTSCAN, FSMC_NAND_BW8);
/* set sdhci device platform data */
- sdhci_set_plat_data(&sdhci_device, &sdhci_plat_data);
+ sdhci_set_plat_data(&spear300_sdhci_device, &sdhci_plat_data);
/* Enable sdhci memory */
sdhci_i2s_mem_enable(SDHCI_MEM_ENB);
/* call spear300 machine init function */
- spear300_init(&photo_frame_mode, pmx_devs, ARRAY_SIZE(pmx_devs));
+ spear300_init(&spear300_photo_frame_mode, pmx_devs,
+ ARRAY_SIZE(pmx_devs));
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 9a45972..01ea05b 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -196,7 +196,7 @@ static struct pmx_driver pmx_driver;
/* Add spear310 specific devices here */
/* uart1 device registeration */
-struct amba_device uart1_device = {
+struct amba_device spear310_uart1_device = {
.dev = {
.init_name = "uart1",
},
@@ -209,7 +209,7 @@ struct amba_device uart1_device = {
};
/* uart2 device registeration */
-struct amba_device uart2_device = {
+struct amba_device spear310_uart2_device = {
.dev = {
.init_name = "uart2",
},
@@ -222,7 +222,7 @@ struct amba_device uart2_device = {
};
/* uart3 device registeration */
-struct amba_device uart3_device = {
+struct amba_device spear310_uart3_device = {
.dev = {
.init_name = "uart3",
},
@@ -235,7 +235,7 @@ struct amba_device uart3_device = {
};
/* uart4 device registeration */
-struct amba_device uart4_device = {
+struct amba_device spear310_uart4_device = {
.dev = {
.init_name = "uart4",
},
@@ -248,7 +248,7 @@ struct amba_device uart4_device = {
};
/* uart5 device registeration */
-struct amba_device uart5_device = {
+struct amba_device spear310_uart5_device = {
.dev = {
.init_name = "uart5",
},
@@ -277,7 +277,7 @@ static struct resource nand_resources[] = {
},
};
-struct platform_device nand_device = {
+struct platform_device spear310_nand_device = {
.name = "nand",
.id = -1,
.resource = nand_resources,
@@ -323,7 +323,7 @@ int spear300_o2p(int offset)
/* emi nor flash device registeration */
static struct physmap_flash_data emi_norflash_data;
-struct platform_device emi_nor_device = {
+struct platform_device spear310_emi_nor_device = {
.name = "physmap-flash",
.id = -1,
.dev.platform_data = &emi_norflash_data,
@@ -351,7 +351,7 @@ static struct resource plgpio_resources[] = {
},
};
-struct platform_device plgpio_device = {
+struct platform_device spear310_plgpio_device = {
.name = "plgpio",
.id = -1,
.dev = {
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index f51540f..3f929e6 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -68,26 +68,26 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &ssp0_device,
- &uart_device,
- &wdt_device,
+ &spear3xx_gpio_device,
+ &spear3xx_ssp0_device,
+ &spear3xx_uart_device,
+ &spear3xx_wdt_device,
/* spear310 specific devices */
};
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
- &ehci_device,
- &i2c_device,
- &nand_device,
- &ohci0_device,
- &ohci1_device,
- &rtc_device,
+ &spear3xx_ehci_device,
+ &spear3xx_i2c_device,
+ &spear3xx_ohci0_device,
+ &spear3xx_ohci1_device,
+ &spear3xx_rtc_device,
/* spear310 specific devices */
- &emi_nor_device,
- &plgpio_device,
+ &spear310_emi_nor_device,
+ &spear310_nand_device,
+ &spear310_plgpio_device,
};
/* spi board information */
@@ -125,8 +125,8 @@ static void __init spear310_evb_init(void)
unsigned int i;
/* set nand device's plat data */
- fsmc_nand_set_plat_data(&nand_device, NULL, 0, NAND_SKIP_BBTSCAN,
- FSMC_NAND_BW8);
+ fsmc_nand_set_plat_data(&spear310_nand_device, NULL, 0,
+ NAND_SKIP_BBTSCAN, FSMC_NAND_BW8);
/* call spear310 machine init function */
spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
@@ -135,12 +135,13 @@ static void __init spear310_evb_init(void)
i2c_register_default_devices();
/* initialize emi related data in emi plat data */
- emi_init_board_info(&emi_nor_device, emi_nor_resources,
+ emi_init_board_info(&spear310_emi_nor_device, emi_nor_resources,
ARRAY_SIZE(emi_nor_resources), partition_info,
ARRAY_SIZE(partition_info), EMI_FLASH_WIDTH32);
/* Initialize emi regiters */
- emi_init(&emi_nor_device, SPEAR310_EMI_REG_BASE, 0, EMI_FLASH_WIDTH32);
+ emi_init(&spear310_emi_nor_device, SPEAR310_EMI_REG_BASE, 0,
+ EMI_FLASH_WIDTH32);
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 82b8cbe..7e33133 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -30,25 +30,25 @@
#define SMALL_PRINTERS_MODE (1 << 3)
#define ALL_MODES 0xF
-struct pmx_mode auto_net_smii_mode = {
+struct pmx_mode spear320_auto_net_smii_mode = {
.id = AUTO_NET_SMII_MODE,
.name = "Automation Networking SMII Mode",
.value = 0x00,
};
-struct pmx_mode auto_net_mii_mode = {
+struct pmx_mode spear320_auto_net_mii_mode = {
.id = AUTO_NET_MII_MODE,
.name = "Automation Networking MII Mode",
.value = 0x01,
};
-struct pmx_mode auto_exp_mode = {
+struct pmx_mode spear320_auto_exp_mode = {
.id = AUTO_EXP_MODE,
.name = "Automation Expanded Mode",
.value = 0x02,
};
-struct pmx_mode small_printers_mode = {
+struct pmx_mode spear320_small_printers_mode = {
.id = SMALL_PRINTERS_MODE,
.name = "Small Printers Mode",
.value = 0x03,
@@ -594,7 +594,7 @@ static struct pmx_driver pmx_driver = {
/* Add spear320 specific devices here */
/* CLCD device registration */
-struct amba_device clcd_device = {
+struct amba_device spear320_clcd_device = {
.dev = {
.init_name = "clcd",
.coherent_dma_mask = ~0,
@@ -622,7 +622,7 @@ static struct pl022_ssp_controller ssp_platform_data[] = {
}
};
-struct amba_device ssp_device[] = {
+struct amba_device spear320_ssp_device[] = {
{
.dev = {
.coherent_dma_mask = ~0,
@@ -651,7 +651,7 @@ struct amba_device ssp_device[] = {
};
/* uart1 device registeration */
-struct amba_device uart1_device = {
+struct amba_device spear320_uart1_device = {
.dev = {
.init_name = "uart1",
},
@@ -664,7 +664,7 @@ struct amba_device uart1_device = {
};
/* uart2 device registeration */
-struct amba_device uart2_device = {
+struct amba_device spear320_uart2_device = {
.dev = {
.init_name = "uart2",
},
@@ -688,7 +688,7 @@ static struct resource can0_resources[] = {
},
};
-struct platform_device can0_device = {
+struct platform_device spear320_can0_device = {
.name = "c_can_platform",
.id = 0,
.num_resources = ARRAY_SIZE(can0_resources),
@@ -706,7 +706,7 @@ static struct resource can1_resources[] = {
},
};
-struct platform_device can1_device = {
+struct platform_device spear320_can1_device = {
.name = "c_can_platform",
.id = 1,
.num_resources = ARRAY_SIZE(can1_resources),
@@ -715,7 +715,7 @@ struct platform_device can1_device = {
/* emi nor flash device registeration */
static struct physmap_flash_data emi_norflash_data;
-struct platform_device emi_nor_device = {
+struct platform_device spear320_emi_nor_device = {
.name = "physmap-flash",
.id = -1,
.dev.platform_data = &emi_norflash_data,
@@ -733,7 +733,7 @@ static struct resource i2c1_resources[] = {
},
};
-struct platform_device i2c1_device = {
+struct platform_device spear320_i2c1_device = {
.name = "i2c_designware",
.id = 1,
.dev = {
@@ -760,7 +760,7 @@ static struct resource nand_resources[] = {
},
};
-struct platform_device nand_device = {
+struct platform_device spear320_nand_device = {
.name = "nand",
.id = -1,
.resource = nand_resources,
@@ -771,8 +771,8 @@ struct platform_device nand_device = {
/* plgpio device registeration */
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
- .irq_base = SPEAR_PLGPIO_INT_BASE,
- .gpio_count = SPEAR_PLGPIO_COUNT,
+ .irq_base = SPEAR3XX_PLGPIO_INT_BASE,
+ .gpio_count = SPEAR3XX_PLGPIO_COUNT,
};
static struct resource plgpio_resources[] = {
@@ -786,7 +786,7 @@ static struct resource plgpio_resources[] = {
},
};
-struct platform_device plgpio_device = {
+struct platform_device spear320_plgpio_device = {
.name = "plgpio",
.id = -1,
.dev = {
@@ -805,7 +805,7 @@ static struct resource pwm_resources[] = {
},
};
-struct platform_device pwm_device = {
+struct platform_device spear320_pwm_device = {
.name = "pwm",
.id = -1,
.num_resources = ARRAY_SIZE(pwm_resources),
@@ -824,7 +824,7 @@ static struct resource sdhci_resources[] = {
}
};
-struct platform_device sdhci_device = {
+struct platform_device spear320_sdhci_device = {
.dev = {
.coherent_dma_mask = ~0,
},
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index a87c6a9..854a6d0 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -66,30 +66,30 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &uart_device,
- &wdt_device,
+ &spear3xx_gpio_device,
+ &spear3xx_uart_device,
+ &spear3xx_wdt_device,
/* spear320 specific devices */
- &clcd_device,
+ &spear320_clcd_device,
};
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
- &ehci_device,
- &i2c_device,
- &nand_device,
- &ohci0_device,
- &ohci1_device,
- &rtc_device,
+ &spear3xx_ehci_device,
+ &spear3xx_i2c_device,
+ &spear3xx_ohci0_device,
+ &spear3xx_ohci1_device,
+ &spear3xx_rtc_device,
/* spear320 specific devices */
- &can0_device,
- &can1_device,
- &i2c1_device,
- &plgpio_device,
- &pwm_device,
- &sdhci_device,
+ &spear320_can0_device,
+ &spear320_can1_device,
+ &spear320_i2c1_device,
+ &spear320_nand_device,
+ &spear320_plgpio_device,
+ &spear320_pwm_device,
+ &spear320_sdhci_device,
};
/* sdhci board specific information */
@@ -108,25 +108,27 @@ static void __init spear320_evb_init(void)
unsigned int i;
/* set sdhci device platform data */
- sdhci_set_plat_data(&sdhci_device, &sdhci_plat_data);
+ sdhci_set_plat_data(&spear320_sdhci_device, &sdhci_plat_data);
/* set nand device's plat data */
- fsmc_nand_set_plat_data(&nand_device, NULL, 0, NAND_SKIP_BBTSCAN,
- FSMC_NAND_BW8);
+ fsmc_nand_set_plat_data(&spear320_nand_device, NULL, 0,
+ NAND_SKIP_BBTSCAN, FSMC_NAND_BW8);
/* call spear320 machine init function */
- spear320_init(&auto_net_mii_mode, pmx_devs, ARRAY_SIZE(pmx_devs));
+ spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
+ ARRAY_SIZE(pmx_devs));
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
/* initialize emi related data in emi plat data */
- emi_init_board_info(&emi_nor_device, emi_nor_resources,
+ emi_init_board_info(&spear320_emi_nor_device, emi_nor_resources,
ARRAY_SIZE(emi_nor_resources), partition_info,
ARRAY_SIZE(partition_info), EMI_FLASH_WIDTH16);
/* Initialize emi regiters */
- emi_init(&emi_nor_device, SPEAR320_EMI_CTRL_BASE, 0, EMI_FLASH_WIDTH16);
+ emi_init(&spear320_emi_nor_device, SPEAR320_EMI_CTRL_BASE, 0,
+ EMI_FLASH_WIDTH16);
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 4ec916a..a6a6f5d 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -32,7 +32,7 @@ static struct pl061_platform_data gpio_plat_data = {
.irq_base = SPEAR3XX_GPIO_INT_BASE,
};
-struct amba_device gpio_device = {
+struct amba_device spear3xx_gpio_device = {
.dev = {
.init_name = "gpio",
.platform_data = &gpio_plat_data,
@@ -61,7 +61,7 @@ static struct pl022_ssp_controller ssp_platform_data = {
.num_chipselect = 2,
};
-struct amba_device ssp0_device = {
+struct amba_device spear3xx_ssp0_device = {
.dev = {
.coherent_dma_mask = ~0,
.init_name = "ssp-pl022.0",
@@ -76,7 +76,7 @@ struct amba_device ssp0_device = {
};
/* uart device registration */
-struct amba_device uart_device = {
+struct amba_device spear3xx_uart_device = {
.dev = {
.init_name = "uart",
},
@@ -89,7 +89,7 @@ struct amba_device uart_device = {
};
/* watchdog device registeration */
-struct amba_device wdt_device = {
+struct amba_device spear3xx_wdt_device = {
.dev = {
.init_name = "wdt",
},
@@ -112,7 +112,7 @@ static struct resource i2c_resources[] = {
},
};
-struct platform_device i2c_device = {
+struct platform_device spear3xx_i2c_device = {
.name = "i2c_designware",
.id = 0,
.dev = {
@@ -162,7 +162,7 @@ static struct resource ohci1_resources[] = {
static u64 ehci_dmamask = ~0;
static int usbh_id = -1;
-struct platform_device ehci_device = {
+struct platform_device spear3xx_ehci_device = {
.name = "spear-ehci",
.id = -1,
.dev = {
@@ -176,7 +176,7 @@ struct platform_device ehci_device = {
static u64 ohci0_dmamask = ~0;
-struct platform_device ohci0_device = {
+struct platform_device spear3xx_ohci0_device = {
.name = "spear-ohci",
.id = 0,
.dev = {
@@ -190,7 +190,7 @@ struct platform_device ohci0_device = {
static u64 ohci1_dmamask = ~0;
-struct platform_device ohci1_device = {
+struct platform_device spear3xx_ohci1_device = {
.name = "spear-ohci",
.id = 1,
.dev = {
@@ -214,7 +214,7 @@ static struct resource rtc_resources[] = {
},
};
-struct platform_device rtc_device = {
+struct platform_device spear3xx_rtc_device = {
.name = "rtc-spear",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 56/62] ST SPEAr3xx: Updating plgpio and emi source to make it compliant with single image strategy
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (53 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 55/62] ST SPEAr: Appending spear3** with global structures Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 57/62] SPEAr6xx: Rework Kconfig for single image solution Viresh Kumar
` (6 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/emi.c | 18 ++++++++++-
arch/arm/mach-spear3xx/include/mach/emi.h | 19 ++++++-----
arch/arm/mach-spear3xx/include/mach/gpio.h | 27 ++++++++--------
arch/arm/plat-spear/plgpio.c | 46 ++++++++++++++++++++-------
4 files changed, 75 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-spear3xx/emi.c b/arch/arm/mach-spear3xx/emi.c
index 7b62ff0..7d7cea7 100644
--- a/arch/arm/mach-spear3xx/emi.c
+++ b/arch/arm/mach-spear3xx/emi.c
@@ -15,6 +15,7 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <asm/mach-types.h>
#include <mach/emi.h>
int __init emi_init(struct platform_device *pdev, unsigned long base,
@@ -23,8 +24,23 @@ int __init emi_init(struct platform_device *pdev, unsigned long base,
void __iomem *emi_reg_base;
struct clk *clk;
int ret;
+ u32 ack_reg, max_banks;
+ /* u32 timeout_reg, irq_reg; */
+
+ /* fixing machine dependent values */
+ if (machine_is_spear310()) {
+ ack_reg = SPEAR310_ACK_REG;
+ max_banks = SPEAR310_EMI_MAX_BANKS;
+ /* timeout_reg = SPEAR310_TIMEOUT_REG; */
+ /* irq_reg = SPEAR310_IRQ_REG; */
+ } else {
+ ack_reg = SPEAR320_ACK_REG;
+ max_banks = SPEAR320_EMI_MAX_BANKS;
+ /* timeout_reg = SPEAR320_TIMEOUT_REG; */
+ /* irq_reg = SPEAR320_IRQ_REG; */
+ }
- if (bank > (EMI_MAX_BANKS - 1))
+ if (bank > (max_banks - 1))
return -EINVAL;
emi_reg_base = ioremap(base, EMI_REG_SIZE);
diff --git a/arch/arm/mach-spear3xx/include/mach/emi.h b/arch/arm/mach-spear3xx/include/mach/emi.h
index b620bf5..59f69c4 100644
--- a/arch/arm/mach-spear3xx/include/mach/emi.h
+++ b/arch/arm/mach-spear3xx/include/mach/emi.h
@@ -33,18 +33,19 @@
#define CTRL_REG (0x14)
#if defined(CONFIG_MACH_SPEAR310)
-#define TIMEOUT_REG (0x90)
-#define ACK_REG (0x94)
-#define IRQ_REG (0x98)
+#define SPEAR310_TIMEOUT_REG (0x90)
+#define SPEAR310_ACK_REG (0x94)
+#define SPEAR310_IRQ_REG (0x98)
-#define EMI_MAX_BANKS 6
+#define SPEAR310_EMI_MAX_BANKS 6
+#endif
-#elif defined(CONFIG_MACH_SPEAR320)
-#define TIMEOUT_REG (0x60)
-#define ACK_REG (0x64)
-#define IRQ_REG (0x68)
+#if defined(CONFIG_MACH_SPEAR320)
+#define SPEAR320_TIMEOUT_REG (0x60)
+#define SPEAR320_ACK_REG (0x64)
+#define SPEAR320_IRQ_REG (0x68)
-#define EMI_MAX_BANKS 4
+#define SPEAR320_EMI_MAX_BANKS 4
#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
index f15248c..0c13d8c 100644
--- a/arch/arm/mach-spear3xx/include/mach/gpio.h
+++ b/arch/arm/mach-spear3xx/include/mach/gpio.h
@@ -17,20 +17,21 @@
#include <plat/gpio.h>
#ifdef CONFIG_MACH_SPEAR310
-#define PLGPIO_ENB 0x0010
-#define PLGPIO_WDATA 0x0020
-#define PLGPIO_DIR 0x0030
-#define PLGPIO_IE 0x0040
-#define PLGPIO_RDATA 0x0050
-#define PLGPIO_MIS 0x0060
+#define SPEAR310_PLGPIO_ENB 0x0010
+#define SPEAR310_PLGPIO_WDATA 0x0020
+#define SPEAR310_PLGPIO_DIR 0x0030
+#define SPEAR310_PLGPIO_IE 0x0040
+#define SPEAR310_PLGPIO_RDATA 0x0050
+#define SPEAR310_PLGPIO_MIS 0x0060
+#endif
-#elif defined(CONFIG_MACH_SPEAR320)
-#define PLGPIO_ENB 0x0024
-#define PLGPIO_WDATA 0x0034
-#define PLGPIO_DIR 0x0044
-#define PLGPIO_RDATA 0x0054
-#define PLGPIO_IE 0x0064
-#define PLGPIO_MIS 0x0074
+#if defined(CONFIG_MACH_SPEAR320)
+#define SPEAR320_PLGPIO_ENB 0x0024
+#define SPEAR320_PLGPIO_WDATA 0x0034
+#define SPEAR320_PLGPIO_DIR 0x0044
+#define SPEAR320_PLGPIO_RDATA 0x0054
+#define SPEAR320_PLGPIO_IE 0x0064
+#define SPEAR320_PLGPIO_MIS 0x0074
#endif
#define BASIC_GPIO_0 0
diff --git a/arch/arm/plat-spear/plgpio.c b/arch/arm/plat-spear/plgpio.c
index 3080178..f5220c0 100644
--- a/arch/arm/plat-spear/plgpio.c
+++ b/arch/arm/plat-spear/plgpio.c
@@ -22,12 +22,16 @@
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
+#include <asm/mach-types.h>
#define MAX_GPIO_PER_REG 32
#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
#define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG)\
* sizeof(int *))
+static u32 plgpio_enb, plgpio_wdata, plgpio_dir, plgpio_rdata, plgpio_ie,
+ plgpio_mis;
+
/*
* struct plgpio: plgpio driver specific structure
*
@@ -96,7 +100,7 @@ static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
}
spin_lock_irqsave(&plgpio->lock, flags);
- plgpio_reg_set(plgpio->base, offset, PLGPIO_DIR);
+ plgpio_reg_set(plgpio->base, offset, plgpio_dir);
spin_unlock_irqrestore(&plgpio->lock, flags);
return 0;
@@ -125,11 +129,11 @@ static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
}
spin_lock_irqsave(&plgpio->lock, flags);
- plgpio_reg_reset(plgpio->base, dir_offset, PLGPIO_DIR);
+ plgpio_reg_reset(plgpio->base, dir_offset, plgpio_dir);
if (value)
- plgpio_reg_set(plgpio->base, wdata_offset, PLGPIO_WDATA);
+ plgpio_reg_set(plgpio->base, wdata_offset, plgpio_wdata);
else
- plgpio_reg_reset(plgpio->base, wdata_offset, PLGPIO_WDATA);
+ plgpio_reg_reset(plgpio->base, wdata_offset, plgpio_wdata);
spin_unlock_irqrestore(&plgpio->lock, flags);
return 0;
@@ -149,7 +153,7 @@ static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
return -EINVAL;
}
- return is_plgpio_set(plgpio->base, offset, PLGPIO_RDATA);
+ return is_plgpio_set(plgpio->base, offset, plgpio_rdata);
}
static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
@@ -167,9 +171,9 @@ static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
}
if (value)
- plgpio_reg_set(plgpio->base, offset, PLGPIO_WDATA);
+ plgpio_reg_set(plgpio->base, offset, plgpio_wdata);
else
- plgpio_reg_reset(plgpio->base, offset, PLGPIO_WDATA);
+ plgpio_reg_reset(plgpio->base, offset, plgpio_wdata);
}
static int plgpio_request(struct gpio_chip *chip, unsigned offset)
@@ -196,7 +200,7 @@ static int plgpio_request(struct gpio_chip *chip, unsigned offset)
}
spin_lock_irqsave(&plgpio->lock, flags);
- plgpio_reg_set(plgpio->base, offset, PLGPIO_ENB);
+ plgpio_reg_set(plgpio->base, offset, plgpio_enb);
spin_unlock_irqrestore(&plgpio->lock, flags);
return 0;
@@ -218,7 +222,7 @@ static void plgpio_free(struct gpio_chip *chip, unsigned offset)
}
spin_lock_irqsave(&plgpio->lock, flags);
- plgpio_reg_reset(plgpio->base, offset, PLGPIO_ENB);
+ plgpio_reg_reset(plgpio->base, offset, plgpio_enb);
spin_unlock_irqrestore(&plgpio->lock, flags);
}
@@ -247,7 +251,7 @@ static void plgpio_irq_mask(unsigned irq)
}
spin_lock_irqsave(&plgpio->lock, flags);
- plgpio_reg_set(plgpio->base, offset, PLGPIO_IE);
+ plgpio_reg_set(plgpio->base, offset, plgpio_ie);
spin_unlock_irqrestore(&plgpio->lock, flags);
}
@@ -265,7 +269,7 @@ static void plgpio_irq_unmask(unsigned irq)
}
spin_lock_irqsave(&plgpio->lock, flags);
- plgpio_reg_reset(plgpio->base, offset, PLGPIO_IE);
+ plgpio_reg_reset(plgpio->base, offset, plgpio_ie);
spin_unlock_irqrestore(&plgpio->lock, flags);
}
@@ -298,7 +302,7 @@ static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
/* check all plgpio MIS registers for a possible interrupt */
for (; i < regs_count; i++) {
- pending = readl(plgpio->base + PLGPIO_MIS + i * sizeof(int *));
+ pending = readl(plgpio->base + plgpio_mis + i * sizeof(int *));
if (!pending)
continue;
@@ -443,6 +447,24 @@ static struct platform_driver plgpio_driver = {
static int __init plgpio_init(void)
{
+ if (machine_is_spear310()) {
+ plgpio_enb = SPEAR310_PLGPIO_ENB;
+ plgpio_wdata = SPEAR310_PLGPIO_WDATA;
+ plgpio_dir = SPEAR310_PLGPIO_DIR;
+ plgpio_rdata = SPEAR310_PLGPIO_IE;
+ plgpio_ie = SPEAR310_PLGPIO_RDATA;
+ plgpio_mis = SPEAR310_PLGPIO_MIS;
+ } else if (machine_is_spear320()) {
+ plgpio_enb = SPEAR320_PLGPIO_ENB;
+ plgpio_wdata = SPEAR320_PLGPIO_WDATA;
+ plgpio_dir = SPEAR320_PLGPIO_DIR;
+ plgpio_rdata = SPEAR320_PLGPIO_IE;
+ plgpio_ie = SPEAR320_PLGPIO_RDATA;
+ plgpio_mis = SPEAR320_PLGPIO_MIS;
+ } else {
+ return 0;
+ }
+
return platform_driver_register(&plgpio_driver);
}
subsys_initcall(plgpio_init);
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 57/62] SPEAr6xx: Rework Kconfig for single image solution
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (54 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 56/62] ST SPEAr3xx: Updating plgpio and emi source to make it compliant with single image strategy Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 58/62] ST SPEAR6xx: renaming spear600_defconfig as spear6xx_defconfig Viresh Kumar
` (5 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear6xx/Kconfig | 15 ++++++++-------
arch/arm/mach-spear6xx/Kconfig600 | 17 -----------------
2 files changed, 8 insertions(+), 24 deletions(-)
delete mode 100644 arch/arm/mach-spear6xx/Kconfig600
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index bddba03..ff4ae5b 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -4,17 +4,18 @@
if ARCH_SPEAR6XX
-choice
- prompt "SPEAr6XX Family"
- default MACH_SPEAR600
+menu "SPEAr6xx Implementations"
+config BOARD_SPEAR600_EVB
+ bool "SPEAr600 Evaluation Board"
+ select MACH_SPEAR600
+ help
+ Supports ST SPEAr600 Evaluation Board
+
+endmenu
config MACH_SPEAR600
bool "SPEAr600"
help
Supports ST SPEAr600 Machine
-endchoice
-
-# Adding SPEAr6XX machine specific configuration files
-source "arch/arm/mach-spear6xx/Kconfig600"
endif #ARCH_SPEAR6XX
diff --git a/arch/arm/mach-spear6xx/Kconfig600 b/arch/arm/mach-spear6xx/Kconfig600
deleted file mode 100644
index 9e19f65..0000000
--- a/arch/arm/mach-spear6xx/Kconfig600
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr600 machine configuration file
-#
-
-if MACH_SPEAR600
-
-choice
- prompt "SPEAr600 Boards"
- default BOARD_SPEAR600_EVB
-
-config BOARD_SPEAR600_EVB
- bool "SPEAr600 Evaluation Board"
- help
- Supports ST SPEAr600 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR600
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 58/62] ST SPEAR6xx: renaming spear600_defconfig as spear6xx_defconfig
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (55 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 57/62] SPEAr6xx: Rework Kconfig for single image solution Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 59/62] ST SPEAr13xx: Pass default padmux settings as parameter to spear13**_init routine Viresh Kumar
` (4 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
.../{spear600_defconfig => spear6xx_defconfig} | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
rename arch/arm/configs/{spear600_defconfig => spear6xx_defconfig} (97%)
diff --git a/arch/arm/configs/spear600_defconfig b/arch/arm/configs/spear6xx_defconfig
similarity index 97%
rename from arch/arm/configs/spear600_defconfig
rename to arch/arm/configs/spear6xx_defconfig
index 6777c11..cef2e83 100644
--- a/arch/arm/configs/spear600_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR6XX=y
+CONFIG_BOARD_SPEAR600_EVB=y
CONFIG_BINFMT_MISC=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_RAM=y
@@ -22,7 +23,6 @@ CONFIG_MAX_RAW_DEVS=8192
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 59/62] ST SPEAr13xx: Pass default padmux settings as parameter to spear13**_init routine
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (56 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 58/62] ST SPEAR6xx: renaming spear600_defconfig as spear6xx_defconfig Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 60/62] ST SPEAr: Adding devices & clocks Viresh Kumar
` (3 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
This patch makes pmx_driver static to spear1300.c and spear1310.c, also now
default setting of padmux are sent to spear1300_init and spear1310_init routines
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 8 ++++----
arch/arm/mach-spear13xx/spear1300.c | 9 +++++++--
arch/arm/mach-spear13xx/spear1300_evb.c | 7 +------
arch/arm/mach-spear13xx/spear1310.c | 9 +++++++--
arch/arm/mach-spear13xx/spear1310_evb.c | 7 +------
5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 0551850..768759a 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -220,8 +220,6 @@ extern struct pmx_dev pmx_uart1_modem;
#define SPEAR_GPT0_CHAN0_IRQ IRQ_GPT0_TMR0
#define SPEAR_GPT0_CHAN1_IRQ IRQ_GPT0_TMR1
-extern struct pmx_driver pmx_driver;
-
/* Add spear13xx family device structure declarations here */
extern struct amba_device spear13xx_gpio_device[];
extern struct amba_device spear13xx_ssp_device;
@@ -250,7 +248,8 @@ void spear13xx_secondary_startup(void);
/* spear1300 declarations */
#ifdef CONFIG_MACH_SPEAR1300
/* Add spear1300 machine function declarations here */
-void __init spear1300_init(void);
+void __init spear1300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR1300 */
@@ -261,7 +260,8 @@ extern struct platform_device spear1310_can0_device;
extern struct platform_device spear1310_can1_device;
/* Add spear1310 machine function declarations here */
-void __init spear1310_init(void);
+void __init spear1310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
void __init spear1310_map_io(void);
#endif /* CONFIG_MACH_SPEAR1310 */
diff --git a/arch/arm/mach-spear13xx/spear1300.c b/arch/arm/mach-spear13xx/spear1300.c
index 28822a3..b10f7a0 100644
--- a/arch/arm/mach-spear13xx/spear1300.c
+++ b/arch/arm/mach-spear13xx/spear1300.c
@@ -15,11 +15,12 @@
#include <mach/spear.h>
/* pmx driver structure */
-struct pmx_driver pmx_driver;
+static struct pmx_driver pmx_driver;
/* Add spear1300 specific devices here */
-void __init spear1300_init(void)
+void __init spear1300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
int ret;
@@ -27,6 +28,10 @@ void __init spear1300_init(void)
spear13xx_init();
/* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
ret = pmx_register(&pmx_driver);
if (ret)
pr_err("padmux: registeration failed. err no: %d\n", ret);
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 09babdd..51d8744 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -107,11 +107,6 @@ static void __init spear1300_evb_init(void)
{
unsigned int i;
- /* padmux initialization, must be done before spear1300_init */
- pmx_driver.mode = NULL;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* set keyboard plat data */
kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
@@ -121,7 +116,7 @@ static void __init spear1300_evb_init(void)
nand_mach_init(FSMC_NAND_BW8);
/* call spear1300 machine init function */
- spear1300_init();
+ spear1300_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index db9bbdb..4f8ba02 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -17,7 +17,7 @@
#include <mach/hardware.h>
/* pmx driver structure */
-struct pmx_driver pmx_driver;
+static struct pmx_driver pmx_driver;
/* Pad multiplexing for uart1_modem device */
static struct pmx_mux_reg pmx_uart1_modem_mux[] = {
@@ -410,7 +410,8 @@ void __init spear1310_map_io(void)
iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
}
-void __init spear1310_init(void)
+void __init spear1310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
int ret;
@@ -418,6 +419,10 @@ void __init spear1310_init(void)
spear13xx_init();
/* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
ret = pmx_register(&pmx_driver);
if (ret)
pr_err("padmux: registeration failed. err no: %d\n", ret);
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
index 3a275c1..dfb1f73f 100644
--- a/arch/arm/mach-spear13xx/spear1310_evb.c
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -119,11 +119,6 @@ static void __init spear1310_evb_init(void)
{
unsigned int i;
- /* padmux initialization, must be done before spear1300_init */
- pmx_driver.mode = NULL;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* set keyboard plat data */
kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
@@ -133,7 +128,7 @@ static void __init spear1310_evb_init(void)
nand_mach_init(FSMC_NAND_BW8);
/* call spear1310 machine init function */
- spear1310_init();
+ spear1310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Register slave devices on the I2C buses */
i2c_register_default_devices();
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 60/62] ST SPEAr: Adding devices & clocks
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (57 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 59/62] ST SPEAr13xx: Pass default padmux settings as parameter to spear13**_init routine Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 61/62] ST SPEAr: Adding information in Documentation/ and MAINTAINERS Viresh Kumar
` (2 subsequent siblings)
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
---
arch/arm/mach-spear13xx/clock.c | 39 ++++++++++
arch/arm/mach-spear13xx/include/mach/generic.h | 6 ++
arch/arm/mach-spear13xx/include/mach/irqs.h | 10 +-
arch/arm/mach-spear13xx/include/mach/spear1310.h | 33 ++++++++
arch/arm/mach-spear13xx/spear1310.c | 87 ++++++++++++++++++++++
arch/arm/mach-spear13xx/spear1310_evb.c | 8 ++
arch/arm/mach-spear3xx/spear310_evb.c | 5 +
arch/arm/mach-spear3xx/spear320_evb.c | 6 ++
8 files changed, 189 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
index b022ee9..be150b2 100644
--- a/arch/arm/mach-spear13xx/clock.c
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -1025,6 +1025,40 @@ static struct clk gmac_phy4_clk = {
.recalc = &follow_parent,
};
+/* uart1 clock */
+static struct clk uart1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart2 clock */
+static struct clk uart2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart3 clock */
+static struct clk uart3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart4 clock */
+static struct clk uart4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart5 clock */
+static struct clk uart5_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
#endif
static struct clk dummy_apb_pclk;
@@ -1138,6 +1172,11 @@ static struct clk_lookup spear1310_clk_lookups[] = {
{.dev_id = "stmmacphy.2", .clk = &gmac_phy2_clk},
{.dev_id = "stmmacphy.3", .clk = &gmac_phy3_clk},
{.dev_id = "stmmacphy.4", .clk = &gmac_phy4_clk},
+ {.dev_id = "uart1", .clk = &uart1_clk},
+ {.dev_id = "uart2", .clk = &uart2_clk},
+ {.dev_id = "uart3", .clk = &uart3_clk},
+ {.dev_id = "uart4", .clk = &uart4_clk},
+ {.dev_id = "uart5", .clk = &uart5_clk},
};
#endif
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 768759a..70a4d64 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -256,8 +256,14 @@ void __init spear1300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
/* spear1310 declarations */
#ifdef CONFIG_MACH_SPEAR1310
/* Add spear1310 machine device structure declarations here */
+extern struct amba_device spear1310_uart1_device;
+extern struct amba_device spear1310_uart2_device;
+extern struct amba_device spear1310_uart3_device;
+extern struct amba_device spear1310_uart4_device;
+extern struct amba_device spear1310_uart5_device;
extern struct platform_device spear1310_can0_device;
extern struct platform_device spear1310_can1_device;
+extern struct platform_device spear1310_i2c1_device;
/* Add spear1310 machine function declarations here */
void __init spear1310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
index 1ca70a6..59bf61a 100644
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -97,11 +97,11 @@
#define IRQ_CCAN1 (IRQ_SHPI_START + 83)
#define IRQ_TDM0 (IRQ_SHPI_START + 84)
#define IRQ_TDM1 (IRQ_SHPI_START + 85)
-#define IRQ_UART0 (IRQ_SHPI_START + 86)
-#define IRQ_UART1 (IRQ_SHPI_START + 87)
-#define IRQ_UART2 (IRQ_SHPI_START + 88)
-#define IRQ_UART3 (IRQ_SHPI_START + 89)
-#define IRQ_UART4 (IRQ_SHPI_START + 90)
+#define IRQ_UART1 (IRQ_SHPI_START + 86)
+#define IRQ_UART2 (IRQ_SHPI_START + 87)
+#define IRQ_UART3 (IRQ_SHPI_START + 88)
+#define IRQ_UART4 (IRQ_SHPI_START + 89)
+#define IRQ_UART5 (IRQ_SHPI_START + 90)
#define IRQ_I2C_CNTR (IRQ_SHPI_START + 91)
#define IRQ_GMAC0_SBD (IRQ_SHPI_START + 92)
#define IRQ_GMAC0_PMT (IRQ_SHPI_START + 93)
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310.h b/arch/arm/mach-spear13xx/include/mach/spear1310.h
index e57c99a..34f0a27 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear1310.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear1310.h
@@ -16,9 +16,32 @@
#ifndef __MACH_SPEAR1310_H
#define __MACH_SPEAR1310_H
+#define SPEAR1310_TDM_E1_0_BASE UL(0x6C200000)
+#define SPEAR1310_TDM_E1_1_BASE UL(0x6C300000)
+#define SPEAR1310_RS485_0_BASE UL(0x6C400000)
+#define SPEAR1310_RS485_1_BASE UL(0x6C500000)
+#define SPEAR1310_GETH1_BASE UL(0x6D000000)
+#define SPEAR1310_GETH2_BASE UL(0x6D100000)
+#define SPEAR1310_GETH3_BASE UL(0x6D200000)
+#define SPEAR1310_GETH4_BASE UL(0x6D300000)
+#define SPEAR1310_UART1_BASE UL(0x6D400000)
+#define SPEAR1310_UART2_BASE UL(0x6D500000)
+#define SPEAR1310_UART3_BASE UL(0x6D600000)
+#define SPEAR1310_UART4_BASE UL(0x6D700000)
+#define SPEAR1310_UART5_BASE UL(0x6D800000)
+#define SPEAR1310_I2C1_BASE UL(0x6D900000)
#define SPEAR1310_CAN0_BASE UL(0x6DA00000)
#define SPEAR1310_CAN1_BASE UL(0x6DB00000)
#define SPEAR1310_RAS_BASE UL(0x6C800000)
+#define SPEAR1310_GETH1_BASE UL(0x6D000000)
+#define SPEAR1310_GETH2_BASE UL(0x6D100000)
+#define SPEAR1310_GETH3_BASE UL(0x6D200000)
+#define SPEAR1310_GETH4_BASE UL(0x6D300000)
+#define SPEAR1310_FSMC1_CS0_BASE UL(0x70000000)
+#define SPEAR1310_FSMC1_CS1_BASE UL(0x74000000)
+#define SPEAR1310_FSMC1_CS2_BASE UL(0x78000000)
+#define SPEAR1310_FSMC1_CS3_BASE UL(0x7C000000)
+#define SPEAR1310_FSMC1_BASE UL(0x6FF00000)
/* RAS Area Control Register */
#define SPEAR1310_RAS_CTRL_REG0 (SPEAR1310_RAS_BASE + 0x0)
@@ -26,6 +49,16 @@
#define SPEAR1310_PHY_CLK_MASK 0xF
#define SPEAR1310_PHY_CLK_SHIFT 0
+#define RAS_FSMC_MODE_MASK 0x3
+#define RAS_FSMC_MODE_NOR 0
+#define RAS_FSMC_MODE_NAND 1
+#define RAS_FSMC_MODE_SRAM 2
+#define RAS_FSMC_WIDTH_MASK 0x30
+#define RAS_FSMC_WIDTH_8 0x00
+#define RAS_FSMC_WIDTH_16 0x10
+#define RAS_FSMC_WIDTH_32 0x20
+#define RAS_FSMC_CS_SPLIT 0x40
+
#endif /* __MACH_SPEAR1310_H */
#endif /* CONFIG_MACH_SPEAR1310 */
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 4f8ba02..10f5879 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/clk.h>
#include <linux/ptrace.h>
#include <asm/irq.h>
#include <mach/generic.h>
@@ -355,6 +356,70 @@ struct pmx_dev pmx_can = {
};
/* Add spear1310 specific devices here */
+/* uart1 device registeration */
+struct amba_device spear1310_uart1_device = {
+ .dev = {
+ .init_name = "uart1",
+ },
+ .res = {
+ .start = SPEAR1310_UART1_BASE,
+ .end = SPEAR1310_UART1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART1, NO_IRQ},
+};
+
+/* uart2 device registeration */
+struct amba_device spear1310_uart2_device = {
+ .dev = {
+ .init_name = "uart2",
+ },
+ .res = {
+ .start = SPEAR1310_UART2_BASE,
+ .end = SPEAR1310_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART2, NO_IRQ},
+};
+
+/* uart3 device registeration */
+struct amba_device spear1310_uart3_device = {
+ .dev = {
+ .init_name = "uart3",
+ },
+ .res = {
+ .start = SPEAR1310_UART3_BASE,
+ .end = SPEAR1310_UART3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART3, NO_IRQ},
+};
+
+/* uart4 device registeration */
+struct amba_device spear1310_uart4_device = {
+ .dev = {
+ .init_name = "uart4",
+ },
+ .res = {
+ .start = SPEAR1310_UART4_BASE,
+ .end = SPEAR1310_UART4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART4, NO_IRQ},
+};
+
+/* uart5 device registeration */
+struct amba_device spear1310_uart5_device = {
+ .dev = {
+ .init_name = "uart5",
+ },
+ .res = {
+ .start = SPEAR1310_UART5_BASE,
+ .end = SPEAR1310_UART5_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART5, NO_IRQ},
+};
/* CAN device registeration */
static struct resource can0_resources[] = {
@@ -393,6 +458,28 @@ struct platform_device spear1310_can1_device = {
.resource = can1_resources,
};
+/* i2c1 device registeration */
+static struct resource i2c1_resources[] = {
+ {
+ .start = SPEAR1310_I2C1_BASE,
+ .end = SPEAR1310_I2C1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_I2C_CNTR,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear1310_i2c1_device = {
+ .name = "i2c_designware",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = ~0,
+ },
+ .num_resources = ARRAY_SIZE(i2c1_resources),
+ .resource = i2c1_resources,
+};
+
/* Following will create 1310 specific static virtual/physical mappings */
struct map_desc spear1310_io_desc[] __initdata = {
{
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
index dfb1f73f..c1bc727 100644
--- a/arch/arm/mach-spear13xx/spear1310_evb.c
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -57,6 +57,13 @@ static struct amba_device *amba_devs[] __initdata = {
&spear13xx_gpio_device[1],
&spear13xx_ssp_device,
&spear13xx_uart_device,
+
+ /* spear1310 specific devices */
+ &spear1310_uart1_device,
+ &spear1310_uart2_device,
+ &spear1310_uart3_device,
+ &spear1310_uart4_device,
+ &spear1310_uart5_device,
};
static struct platform_device *plat_devs[] __initdata = {
@@ -74,6 +81,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear1310 specific devices */
&spear1310_can0_device,
&spear1310_can1_device,
+ &spear1310_i2c1_device,
};
/* keyboard specific platform data */
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 3f929e6..46c1253 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -74,6 +74,11 @@ static struct amba_device *amba_devs[] __initdata = {
&spear3xx_wdt_device,
/* spear310 specific devices */
+ &spear310_uart1_device,
+ &spear310_uart2_device,
+ &spear310_uart3_device,
+ &spear310_uart4_device,
+ &spear310_uart5_device,
};
static struct platform_device *plat_devs[] __initdata = {
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 854a6d0..022a46a 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -67,11 +67,16 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&spear3xx_gpio_device,
+ &spear3xx_ssp0_device,
&spear3xx_uart_device,
&spear3xx_wdt_device,
/* spear320 specific devices */
&spear320_clcd_device,
+ &spear320_ssp_device[0],
+ &spear320_ssp_device[1],
+ &spear320_uart1_device,
+ &spear320_uart2_device,
};
static struct platform_device *plat_devs[] __initdata = {
@@ -85,6 +90,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear320 specific devices */
&spear320_can0_device,
&spear320_can1_device,
+ &spear320_emi_nor_device,
&spear320_i2c1_device,
&spear320_nand_device,
&spear320_plgpio_device,
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 61/62] ST SPEAr: Adding information in Documentation/ and MAINTAINERS
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (58 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 60/62] ST SPEAr: Adding devices & clocks Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 62/62] ST SPEAr: Updating defconfigs Viresh Kumar
2011-01-18 15:53 ` [PATCH V4 00/62] Updating SPEAr Support Russell King - ARM Linux
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
Documentation/arm/SPEAr/overview.txt | 34 +++++++++++++++++++++++-----------
MAINTAINERS | 6 ++++++
2 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c..4e510061 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -9,8 +9,9 @@ Introduction
The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
- SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
- series is in progress.
+ SPEAr310, SPEAr320, SPEAr600, SPEAr1300 and SPEAr1310 SOCs are supported.
+ SPEAr3XX and SPEAr6XX are based on ARM9 whereas SPEAr13XX is based on latest
+ ARM Cortex A9 CPUs.
Hierarchy in SPEAr is as follows:
@@ -27,16 +28,25 @@ Introduction
- SPEAr600_EVB (Evaluation Board)
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
+ - SPEAr1300_EVB (Evaluation Board)
+ - SPEAr1310 (SOC)
+ - SPEAr1310_EVB (Evaluation Board)
Configuration
-------------
- A generic configuration is provided for each machine, and can be used as the
+ A generic configuration is provided for each machine family, and can be used as the
default by
- make spear600_defconfig
- make spear300_defconfig
- make spear310_defconfig
- make spear320_defconfig
+ #make ARCH=arm spear13xx_defconfig
+ #make ARCH=arm spear3xx_defconfig
+ #make ARCH=arm spear6xx_defconfig
+
+ Compilation
+ -----------
+
+ After applying default configuration, Linux kernel for SPEAr architecture
+ can be compiled as
+ #make ARCH=arm CROSS_COMPILE=arm-linux- uImage
Layout
------
@@ -48,13 +58,15 @@ Introduction
Each machine series have a directory with name arch/arm/mach-spear followed by
series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
- Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
- spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
+ Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
+ spear6xx is mach-spear6xx/spear6xx.c and similarly for spear13xx is
+ mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
- mach-spear* also contains board specific files for each machine type.
+ Board specific files for each machine type is also contained in mach-spear*
+ folder.
Document Author
---------------
- Viresh Kumar, (c) 2010 ST Microelectronics
+ Viresh Kumar, Shiraz Hashim (c) 2010 ST Microelectronics
diff --git a/MAINTAINERS b/MAINTAINERS
index 1af022e..a62e783 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5802,6 +5802,12 @@ W: http://www.st.com/spear
S: Maintained
F: arch/arm/plat-spear/
+SPEAR13XX MACHINE SUPPORT
+M: Shiraz Hashim <shiraz.hashim@st.com>
+W: http://www.st.com/spear
+S: Maintained
+F: arch/arm/mach-spear13xx/
+
SPEAR3XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
W: http://www.st.com/spear
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 62/62] ST SPEAr: Updating defconfigs
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (59 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 61/62] ST SPEAr: Adding information in Documentation/ and MAINTAINERS Viresh Kumar
@ 2011-01-18 7:12 ` Viresh Kumar
2011-01-18 15:53 ` [PATCH V4 00/62] Updating SPEAr Support Russell King - ARM Linux
61 siblings, 0 replies; 90+ messages in thread
From: Viresh Kumar @ 2011-01-18 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
---
arch/arm/configs/spear13xx_defconfig | 78 ++++++++++++++++++++++++++++++---
arch/arm/configs/spear3xx_defconfig | 80 +++++++++++++++++++++++++++++++---
arch/arm/configs/spear6xx_defconfig | 72 ++++++++++++++++++++++++++++---
3 files changed, 211 insertions(+), 19 deletions(-)
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 9f3baf8..d764fee 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -10,31 +10,94 @@ CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR13XX=y
CONFIG_BOARD_SPEAR1300_EVB=y
CONFIG_BOARD_SPEAR1310_EVB=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEAER is not set
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_AEABI=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_VFP=y
CONFIG_BINFMT_MISC=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
+CONFIG_ARPD=y
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+# CONFIG_M25PXX_USE_FAST_READ is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_CHR_DEV_OSST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_NETDEVICES=y
+# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TEST=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
@@ -42,16 +105,18 @@ CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
+CONFIG_NLS_ASCII=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
@@ -59,3 +124,4 @@ CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
+# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f..5a210ce 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -10,13 +10,54 @@ CONFIG_PLAT_SPEAR=y
CONFIG_BOARD_SPEAR300_EVB=y
CONFIG_BOARD_SPEAR310_EVB=y
CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_AEABI=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_BINFMT_MISC=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_ARPD=y
+# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+# CONFIG_M25PXX_USE_FAST_READ is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_CHR_DEV_OSST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_NETDEVICES=y
+# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -24,30 +65,55 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_ARMCLCD_SAMSUNG_LMS700=y
# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TEST=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
+CONFIG_NLS_ASCII=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
+# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e83..5217396 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -9,10 +9,48 @@ CONFIG_MODVERSIONS=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR6XX=y
CONFIG_BOARD_SPEAR600_EVB=y
+CONFIG_AEABI=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_BINFMT_MISC=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_ARPD=y
+# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+# CONFIG_M25PXX_USE_FAST_READ is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_CHR_DEV_OSST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_NETDEVICES=y
+# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_SERIAL_AMBA_PL011=y
@@ -20,30 +58,52 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_ARMCLCD_SAMSUNG_LMS700=y
# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TEST=y
+CONFIG_RTC_CLASS=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
+CONFIG_NLS_ASCII=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
+# CONFIG_ARM_UNWIND is not set
--
1.7.2.2
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [PATCH V4 00/62] Updating SPEAr Support
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
` (60 preceding siblings ...)
2011-01-18 7:12 ` [PATCH V4 62/62] ST SPEAr: Updating defconfigs Viresh Kumar
@ 2011-01-18 15:53 ` Russell King - ARM Linux
2011-01-19 3:49 ` viresh kumar
61 siblings, 1 reply; 90+ messages in thread
From: Russell King - ARM Linux @ 2011-01-18 15:53 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 18, 2011 at 12:41:28PM +0530, Viresh Kumar wrote:
> Changes since V3:
> - SPEAr13xx: gic init, smp and hotplug code updated w.r.t. latest linus/master
> - Appending UL to VMALLOC_END Macros
> - readl & writle _relaxed used instread _raw in uncompress.h
> - infinite loop removed from arch_reset() in
> mach-spear13xx/include/mach/system.h
> - patch: ST-SPEAr13xx-Modified-static-mappings is broken into two patches.
> Now, static mapping for SPEAr1310 RAS will be present only on 1310 machine.
> - Updated commit message of: SPEAr Power Management: Added the support for
> Standby mode
> - Default ssp freq changed to 25MHz.
> - patch: ST-SPEAr-13xx-Adding-support-for-SPEAr1310 is splitted into two
> patches. Separate patch for 320 CAN is added.
> - Wrapper routine spi_init() in spear*evb.c files is removed.
> - routine i2c_register_board_devices() is renamed to
> i2c_register_default_devices() in arch/arm/plat-spear/i2c_eval_board.c file
> - Following patches are removed from this patchset, they will be added
> separately:
> ST-SPEAr-FSMC-Flexible-Static-Memory-Controller-NOR-.patch
> - Following patches are already present in linus-next or already Acked, so they
> are also removed from this patchset:
> Newly-erased-page-read-workaround.patch
Does this mean I can get rid of the entire set of spear patches in the
patch system now?
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 04/62] ST SPEAr: Making clock functions more generic
2011-01-18 7:11 ` [PATCH V4 04/62] ST SPEAr: Making clock functions more generic Viresh Kumar
@ 2011-01-18 15:56 ` Russell King - ARM Linux
2011-01-19 4:03 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: Russell King - ARM Linux @ 2011-01-18 15:56 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 18, 2011 at 12:41:32PM +0530, Viresh Kumar wrote:
> /* pll1 configuration structure */
> static struct pll_clk_config pll1_config = {
> .mode_reg = PLL1_CTR,
> .cfg_reg = PLL1_FRQ,
> + .masks = &pll1_masks,
> };
>
> /* PLL1 clock */
...
> - mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) &
> - PLL_MODE_MASK;
> + mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
> + config->masks->mode_mask;
>
...
> struct pll_clk_config {
> - unsigned int *mode_reg;
> - unsigned int *cfg_reg;
> + u32 *mode_reg;
> + u32 *cfg_reg;
> + struct pll_clk_masks *masks;
> };
Registers should have an __iomem attribute on them. Preferably, but
not absolutely necessary, should be void to prevent any direct
dereferencing.
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 06/62] ST SPEAr13XX: Adding machine specific header files
2011-01-18 7:11 ` [PATCH V4 06/62] ST SPEAr13XX: Adding machine specific header files Viresh Kumar
@ 2011-01-18 16:00 ` Russell King - ARM Linux
2011-01-19 4:38 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: Russell King - ARM Linux @ 2011-01-18 16:00 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 18, 2011 at 12:41:34PM +0530, Viresh Kumar wrote:
> +#define MISC_BASE VA_SPEAR13XX_MISC_BASE
> +
> +/* General Configuration */
> +#define SOC_CFG ((unsigned int *)(MISC_BASE + 0x000))
> +#define BOOTSTRAP_CFG ((unsigned int *)(MISC_BASE + 0x004))
You could really do with an IOMEM() macro, thus:
#ifndef __ASSEMBLY__
#define IOMEM(x) ((void __iomem __force *)(x))
#else
#define IOMEM(x) (x)
#endif
You can then use that for stuff like VA_SPEAR13XX_MISC_BASE, and all
these definitions then become:
#define SOC_CFG (MISC_BASE + 0x000)
because GCC allows void pointer arithmetic (treats it as char).
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files
2011-01-18 7:11 ` [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files Viresh Kumar
@ 2011-01-18 16:06 ` Russell King - ARM Linux
2011-01-19 6:03 ` Shiraz Hashim
0 siblings, 1 reply; 90+ messages in thread
From: Russell King - ARM Linux @ 2011-01-18 16:06 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 18, 2011 at 12:41:35PM +0530, Viresh Kumar wrote:
> diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
> new file mode 100644
> index 0000000..30761d3
> --- /dev/null
> +++ b/arch/arm/mach-spear13xx/headsmp.S
> @@ -0,0 +1,96 @@
> +/*
> + * arch/arm/mach-spear13XX/headsmp.S
> + *
> + * Picked from realview
> + * Copyright (c) 2010 ST Microelectronics Limited
> + * Shiraz Hashim <shiraz.hashim@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +
> + __INIT
Is this ever called after the kernel text is thrown away? What if we
add support in the generic code to start with secondary CPUs offline
as a power saving or boot time feature?
> +
> +/*
> + * This one is picked from Tegra :-
> + *
> + * The secondary kernel init calls v7_flush_dcache_all before it enables
> + * the L1; however, the L1 comes out of reset in an undefined state, so
> + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
> + * of cache lines with uninitialized data and uninitialized tags to get
> + * written out to memory, which does really unpleasant things to the ain
> + * processor. We fix this by performing an invalidate, rather than a
> + * clean + invalidate, before jumping into the kernel.
> + */
> +ENTRY(v7_invalidate_l1)
> + mov r0, #0
> + mcr p15, 2, r0, c0, c0, 0
> + mrc p15, 1, r0, c0, c0, 0
> +
> + ldr r1, =0x7fff
> + and r2, r1, r0, lsr #13
> +
> + ldr r1, =0x3ff
> +
> + and r3, r1, r0, lsr #3 @ NumWays - 1
> + add r2, r2, #1 @ NumSets
> +
> + and r0, r0, #0x7
> + add r0, r0, #4 @ SetShift
> +
> + clz r1, r3 @ WayShift
> + add r4, r3, #1 @ NumWays
> +1: sub r2, r2, #1 @ NumSets--
> + mov r3, r4 @ Temp = NumWays
> +2: subs r3, r3, #1 @ Temp--
> + mov r5, r3, lsl r1
> + mov r6, r2, lsl r0
> + orr r5, r5, r6 @ Reg = Temp<<WayShift)|(NumSets<<SetShift)
> + mcr p15, 0, r5, c7, c6, 2
> + bgt 2b
> + cmp r2, #0
> + bgt 1b
> + dsb
> + isb
> + mov pc, lr
> +ENDPROC(v7_invalidate_l1)
This code appears to have its only caller commented out. Should it be
removed?
> +
> +/*
> + * spear13xx specific entry point for secondary CPUs. This provides
> + * a "holding pen" into which all secondary cores are held until we're
> + * ready for them to initialise.
> + */
> +ENTRY(spear13xx_secondary_startup)
> + /* If we don't do this then we have a crash */
> +
> + /*
> + * Since now this is being called from xloader so removing it
> + * here
> + */
> +#if 0
> + bl v7_invalidate_l1
> +#endif
> +
> + mrc p15, 0, r0, c0, c0, 5
> + and r0, r0, #15
> + adr r4, 1f
> + ldmia r4, {r5, r6}
> + sub r4, r4, r5
> + add r6, r6, r4
> +pen: ldr r7, [r6]
> + cmp r7, r0
> + bne pen
> +
> + /*
> + * we've been released from the holding pen: secondary_stack
> + * should now contain the SVC stack for this core
> + */
> + b secondary_startup
> +
> + .align
> +1: .long .
> + .long pen_release
...
> +volatile int __cpuinitdata pen_release = -1;
> +static DEFINE_SPINLOCK(boot_lock);
> +
> +/*
> + * Write pen_release in a way that is guaranteed to be visible to all
> + * observers, irrespective of whether they're taking part in coherency
> + * or not. This is necessary for the hotplug code to work reliably.
> + */
> +static void write_pen_release(int val)
> +{
> + pen_release = val;
> + smp_wmb();
> + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
> + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
> +}
> +
> +static void __iomem *scu_base_addr(void)
> +{
> + return __io_address(SPEAR13XX_SCU_BASE);
> +}
> +
> +void __cpuinit platform_secondary_init(unsigned int cpu)
> +{
> + /*
> + * if any interrupts are already enabled for the primary
> + * core (e.g. timer irq), then they will not have been enabled
> + * for us: do so
> + */
> + gic_secondary_init(0);
> +
> + /*
> + * let the primary processor know we're out of the
> + * pen, then head off into the C entry point
> + */
> + write_pen_release(-1);
> +
> + /*
> + * Synchronise with the boot thread.
> + */
> + spin_lock(&boot_lock);
> + spin_unlock(&boot_lock);
> +}
> +
> +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + unsigned long timeout;
> +
> + /*
> + * set synchronisation state between this boot processor
> + * and the secondary one
> + */
> + spin_lock(&boot_lock);
> +
> + /*
> + * The secondary processor is waiting to be released from
> + * the holding pen - release it, then wait for it to flag
> + * that it has been released by resetting pen_release.
> + *
> + * Note that "pen_release" is the hardware CPU ID, whereas
> + * "cpu" is Linux's internal ID.
> + */
> + write_pen_release(cpu);
> +
> + timeout = jiffies + (1 * HZ);
> + while (time_before(jiffies, timeout)) {
> + smp_rmb();
> + if (pen_release == -1)
> + break;
> +
> + udelay(10);
> + }
> +
> + /*
> + * now the secondary core is starting up let it run its
> + * calibrations, then wait for it to finish
> + */
> + spin_unlock(&boot_lock);
> +
> + return pen_release != -1 ? -ENOSYS : 0;
> +}
> +
> +/*
> + * Initialise the CPU possible map early - this describes the CPUs
> + * which may be present or become present in the system.
> + */
> +void __init smp_init_cpus(void)
> +{
> + void __iomem *scu_base = scu_base_addr();
> + unsigned int i, ncores;
> +
> + ncores = scu_base ? scu_get_core_count(scu_base) : 1;
> +
> + for (i = 0; i < ncores; i++)
> + set_cpu_possible(i, true);
> +}
> +
> +static void __init wakeup_secondary(void)
> +{
> + /* nobody is to be released from the pen yet */
> + pen_release = -1;
But pen_release starts off as -1, so is this really needed?
> +
> + /*
> + * Write the address of secondary startup into the system-wide
> + * location (presently it is in SRAM). The BootMonitor waits
> + * for this register to become non-zero.
> + * We must also send an sev to wake it up
> + */
> + __raw_writel(BSYM(virt_to_phys(spear13xx_secondary_startup)),
> + __io_address(SPEAR13XX_SYS_LOCATION));
> +
> + mb();
Do you really need to sync back to L2, or will a dsb() do here - and
as the spinlock code uses dsb() + sev() together, would it make sense
to combine the two? (dsb() is required to ensure all previous writes
are visible prior to the sev() executing.)
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 26/62] ST SPEAr: Adding support for SSP PL022
2011-01-18 7:11 ` [PATCH V4 26/62] ST SPEAr: Adding support for SSP PL022 Viresh Kumar
@ 2011-01-18 16:18 ` Russell King - ARM Linux
2011-01-19 4:16 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: Russell King - ARM Linux @ 2011-01-18 16:18 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 18, 2011 at 12:41:53PM +0530, Viresh Kumar wrote:
> diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
> index ad1c6a0..088bf52 100644
> --- a/arch/arm/mach-spear13xx/spear1300_evb.c
> +++ b/arch/arm/mach-spear13xx/spear1300_evb.c
> @@ -12,7 +12,10 @@
> */
>
> #include <linux/types.h>
> +#include <linux/gpio.h>
:-)
> diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
> index c219691..0e3d8f3 100644
> --- a/arch/arm/mach-spear3xx/spear300_evb.c
> +++ b/arch/arm/mach-spear3xx/spear300_evb.c
> @@ -15,10 +15,14 @@
> #include <linux/mtd/fsmc.h>
> #include <asm/mach/arch.h>
> #include <asm/mach-types.h>
> +#include <linux/spi/flash.h>
> +#include <linux/spi/spi.h>
> #include <mach/generic.h>
> +#include <mach/gpio.h>
:-(
> diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
> index d216c94..6daacbb 100644
> --- a/arch/arm/mach-spear3xx/spear310_evb.c
> +++ b/arch/arm/mach-spear3xx/spear310_evb.c
> @@ -15,9 +15,13 @@
> #include <linux/mtd/fsmc.h>
> #include <asm/mach/arch.h>
> #include <asm/mach-types.h>
> +#include <linux/spi/flash.h>
> +#include <linux/spi/spi.h>
> #include <mach/generic.h>
> +#include <mach/gpio.h>
:-(
> diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
> index 15db267..baa4574 100644
> --- a/arch/arm/mach-spear3xx/spear320_evb.c
> +++ b/arch/arm/mach-spear3xx/spear320_evb.c
> @@ -15,9 +15,13 @@
> #include <linux/mtd/fsmc.h>
> #include <asm/mach/arch.h>
> #include <asm/mach-types.h>
> +#include <linux/spi/flash.h>
> +#include <linux/spi/spi.h>
> #include <mach/generic.h>
> +#include <mach/gpio.h>
:-(
> diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
> index 32d3855..fe9a8c8 100644
> --- a/arch/arm/mach-spear6xx/spear600_evb.c
> +++ b/arch/arm/mach-spear6xx/spear600_evb.c
> @@ -15,15 +15,23 @@
> #include <linux/mtd/fsmc.h>
> #include <asm/mach/arch.h>
> #include <asm/mach-types.h>
> +#include <linux/gpio.h>
> +#include <linux/spi/flash.h>
> +#include <linux/spi/spi.h>
> #include <mach/generic.h>
> +#include <mach/gpio.h>
:-(
> diff --git a/arch/arm/plat-spear/include/plat/spi.h b/arch/arm/plat-spear/include/plat/spi.h
> new file mode 100644
> index 0000000..24d57e1
> --- /dev/null
> +++ b/arch/arm/plat-spear/include/plat/spi.h
> @@ -0,0 +1,74 @@
> +/*
> + * arch/arm/plat-spear/include/plat/spi.h
> + *
> + * SPI board specific definitions common to multiple boards on multiple
> + * machines.
> + *
> + * Copyright (C) 2010 ST Microelectronics
> + * Viresh Kumar<viresh.kumar@st.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __PLAT_SPI_H
> +#define __PLAT_SPI_H
> +
> +#include <linux/amba/pl022.h>
> +#include <linux/gpio.h>
:-)
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 05/62] ST SPEAr: Formalized timer support
2011-01-18 7:11 ` [PATCH V4 05/62] ST SPEAr: Formalized timer support Viresh Kumar
@ 2011-01-18 23:50 ` Jamie Iles
2011-01-19 3:53 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: Jamie Iles @ 2011-01-18 23:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Tue, Jan 18, 2011 at 12:41:33PM +0530, Viresh Kumar wrote:
> --- a/arch/arm/mach-spear3xx/spear3xx.c
> +++ b/arch/arm/mach-spear3xx/spear3xx.c
> @@ -523,5 +523,35 @@ struct pmx_dev pmx_plgpio_45_46_49_50 = {
> .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
> .enb_on_reset = 1,
> };
> +#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
>
> -#endif
> +static void __init spear3xx_timer_init(void)
> +{
> + char pclk_name[] = "pll3_48m_clk";
> + struct clk *gpt_clk, *pclk;
> +
> + /* get the system timer clock */
> + gpt_clk = clk_get_sys("gpt0", NULL);
> + if (!gpt_clk) {
> + pr_err("%s:couldn't get clk for gpt\n", __func__);
> + BUG();
> + }
> +
> + /* get the suitable parent clock for timer*/
> + pclk = clk_get(NULL, pclk_name);
> + if (!pclk) {
> + pr_err("%s:couldn't get %s as parent for gpt\n",
> + __func__, pclk_name);
> + BUG();
> + }
These should probably be using IS_ERR() rather than checking against NULL to
be consistent with the API.
[...]
> diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
> index daff8d0..bdd5b76 100644
> --- a/arch/arm/mach-spear6xx/spear600_evb.c
> +++ b/arch/arm/mach-spear6xx/spear600_evb.c
> @@ -42,10 +42,11 @@ static void __init spear600_evb_init(void)
> amba_device_register(amba_devs[i], &iomem_resource);
> }
>
> +
Nitpick, why the extra newline?
> MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
> .boot_params = 0x00000100,
> .map_io = spear6xx_map_io,
> .init_irq = spear6xx_init_irq,
> - .timer = &spear_sys_timer,
> + .timer = &spear6xx_timer,
> .init_machine = spear600_evb_init,
> MACHINE_END
> diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
> index f2fe14e..ea4c356 100644
> --- a/arch/arm/mach-spear6xx/spear6xx.c
> +++ b/arch/arm/mach-spear6xx/spear6xx.c
> @@ -155,3 +155,34 @@ void __init spear6xx_map_io(void)
> /* This will initialize clock framework */
> clk_init();
> }
> +
> +static void __init spear6xx_timer_init(void)
> +{
> + char pclk_name[] = "pll3_48m_clk";
> + struct clk *gpt_clk, *pclk;
> +
> + /* get the system timer clock */
> + gpt_clk = clk_get_sys("gpt0", NULL);
> + if (!gpt_clk) {
> + pr_err("%s:couldn't get clk for gpt\n", __func__);
> + BUG();
> + }
> +
> + /* get the suitable parent clock for timer*/
> + pclk = clk_get(NULL, pclk_name);
> + if (!pclk) {
> + pr_err("%s:couldn't get %s as parent for gpt\n",
> + __func__, pclk_name);
> + BUG();
> + }
As above, IS_ERR() would be better here.
Jamie
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 25/62] ST SPEAr: Added PCIE host controller base driver support.
2011-01-18 7:11 ` [PATCH V4 25/62] ST SPEAr: Added PCIE host controller base driver support Viresh Kumar
@ 2011-01-19 0:05 ` Russell King - ARM Linux
2011-01-19 4:17 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: Russell King - ARM Linux @ 2011-01-19 0:05 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 18, 2011 at 12:41:52PM +0530, Viresh Kumar wrote:
> + clk = clk_get_sys("pcie1", NULL);
> + if (!clk) {
IS_ERR(clk)
> + pr_err("%s:couldn't get clk for pcie1\n",
> + __func__);
> + continue;
> + }
> + if (clk_enable(clk)) {
> + pr_err("%s:couldn't enable clk for pcie1\n",
> + __func__);
> + continue;
> + }
> + } else if (port == 2) {
> + /* Ideally CFG Clock should have been also enabled
> + * here. But it is done currently during board
> + * init routne*/
> + clk = clk_get_sys("pcie2", NULL);
> + if (!clk) {
IS_ERR(clk)
> + pr_err("%s:couldn't get clk for pcie2\n",
> + __func__);
> + continue;
> + }
> + if (clk_enable(clk)) {
> + pr_err("%s:couldn't enable clk for pcie2\n",
> + __func__);
> + continue;
> + }
> + }
> +
> + if ((*pcie_port_is_host)(port))
> + add_pcie_port(port, spr_pcie_base[port],
> + spr_pcie_app_base[port]);
> + }
...
> +#ifdef CONFIG_PCIEPORTBUS
> +/* PCIE0 clock always needs to be enabled if any of the three PCIE port
> + * have to be used. So call this function from the board initilization
> + * file. Ideally , all controller should have been independent from
> + * others with respect to clock.
> + */
> +int enable_pcie0_clk(void)
> +{
> + struct clk *clk;
> + /*Enable all CLK in CFG registers here only. Idealy only PCIE0
> + * should have been enabled. But Controler does not work
> + * properly if PCIE1 and PCIE2's CFG CLK is enabled in stages.
> + */
> + writel(PCIE0_CFG_VAL | PCIE1_CFG_VAL | PCIE2_CFG_VAL, PCIE_CFG);
> + clk = clk_get_sys("pcie0", NULL);
> + if (!clk) {
IS_ERR(clk)
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310
2011-01-18 7:11 ` [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310 Viresh Kumar
@ 2011-01-19 0:09 ` Jamie Iles
2011-01-19 4:39 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: Jamie Iles @ 2011-01-19 0:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Tue, Jan 18, 2011 at 12:41:59PM +0530, Viresh Kumar wrote:
> From: Bhupesh Sharma <bhupesh.sharma@st.com>
>
> This patch adds support for SPEAr1310 Machine and evaluation board
>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@st.com>
> Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
> ---
[...]
> diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c
> b/arch/arm/mach-spear13xx/spear1310_evb.c
> new file mode 100644
> index 0000000..1270b4d
> --- /dev/null
> +++ b/arch/arm/mach-spear13xx/spear1310_evb.c
> @@ -0,0 +1,133 @@
> +/*
> + * arch/arm/mach-spear13xx/spear1310_evb.c
> + *
> + * SPEAr1310 evaluation board source file
> + *
> + * Copyright (C) 2010 ST Microelectronics
> + * Bhupesh Sharma <bhupesh.sharma@st.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/types.h>
> +#include <linux/gpio.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/fsmc.h>
> +#include <linux/spi/flash.h>
> +#include <linux/spi/spi.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach-types.h>
> +#include <plat/fsmc.h>
> +#include <plat/keyboard.h>
> +#include <plat/spi.h>
> +#include <mach/generic.h>
> +#include <mach/spear.h>
> +#include <mach/pcie.h>
> +
> +static struct amba_device *amba_devs[] __initdata = {
> + /* spear13xx specific devices */
> + &spear13xx_gpio_device[0],
> + &spear13xx_gpio_device[1],
> + &spear13xx_ssp_device,
> + &spear13xx_uart_device,
> +};
> +
> +static struct platform_device *plat_devs[] __initdata = {
> + /* spear13xx specific devices */
> + &spear13xx_ehci0_device,
> + &spear13xx_ehci1_device,
> + &spear13xx_i2c_device,
> + &spear13xx_kbd_device,
> + &spear13xx_nand_device,
> + &spear13xx_ohci0_device,
> + &spear13xx_ohci1_device,
> + &spear13xx_rtc_device,
> + &spear13xx_sdhci_device,
> +
> + /* spear1310 specific devices */
> + &spear1310_can0_device,
> + &spear1310_can1_device,
> +};
> +
> +/* keyboard specific platform data */
> +static DECLARE_KEYMAP(keymap);
> +static struct matrix_keymap_data keymap_data = {
> + .keymap = keymap,
> + .keymap_size = ARRAY_SIZE(keymap),
> +};
> +
> +static struct kbd_platform_data kbd_data = {
> + .keymap = &keymap_data,
> + .rep = 1,
> +};
> +
> +static struct spi_board_info __initdata spi_board_info[] = {
> +};
AFAICT spi_register_board_info() doesn't do anything when passed this empty
array so both the array and call could be removed.
> +
> +#ifdef CONFIG_PCIEPORTBUS
> +/* this function is needed for PCIE host and device driver. Same
> + * controller can not be programmed as host as well as device. So host
> + * driver must call this function and if this function returns 1 then
> + * only host should add that particular port as RC.
> + * A port to be added as device, one must also add device's information
> + * in plat_devs array defined in this file.
> + * it is the responsibility of calling function to not send port number
> + * greter than max no of controller(3)
> + */
> +int spear1310_pcie_port_is_host(int port)
> +{
> + switch (port) {
> + case 0:
> + return 0;
> + case 1:
> + return 1;
> + case 2:
> + return 1;
> + }
> + return -EINVAL;
> +}
> +#endif
It looks like this can be made static. Also, given the comment, is it worth
adding a BUG_ON(port > 3)?
> +static void __init spear1310_evb_init(void)
> +{
> + unsigned int i;
> +
> + /* set keyboard plat data */
> + kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
> +
> + /* set nand device's plat data */
> + fsmc_nand_set_plat_data(&spear13xx_nand_device, NULL, 0,
> + NAND_SKIP_BBTSCAN, FSMC_NAND_BW8);
> + nand_mach_init(FSMC_NAND_BW8);
> +
> + /* call spear1310 machine init function */
> + spear1310_init();
> +
> + /* Register slave devices on the I2C buses */
> + i2c_register_default_devices();
> +
> +#ifdef CONFIG_PCIEPORTBUS
> + /* Enable PCIE0 clk */
> + enable_pcie0_clk();
> + pcie_init(&spear1310_pcie_port_is_host);
No '&' needed before function name.
Jamie
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework
2011-01-18 7:12 ` [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework Viresh Kumar
@ 2011-01-19 0:20 ` Jamie Iles
2011-01-19 2:13 ` deepaksi
0 siblings, 1 reply; 90+ messages in thread
From: Jamie Iles @ 2011-01-19 0:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Tue, Jan 18, 2011 at 12:42:05PM +0530, Viresh Kumar wrote:
> From: Deepak Sikri <deepak.sikri@st.com>
>
> Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
> Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
> ---
[...]
> diff --git a/arch/arm/plat-spear/cpufreq.c b/arch/arm/plat-spear/cpufreq.c
> new file mode 100644
> index 0000000..9384d65
> --- /dev/null
> +++ b/arch/arm/plat-spear/cpufreq.c
> @@ -0,0 +1,159 @@
> +/*
> + * arch/arm/plat-spear/cpufreq.c
> + *
> + * CPU Frequency Scaling for SPEAr platform
> + *
> + * Copyright (C) 2010 ST Microelectronics
> + * Deepak Sikri<deepak.sikri@st.com>
> + *
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/sched.h>
> +#include <linux/cpufreq.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/err.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <asm/system.h>
> +#include <mach/hardware.h>
> +
> +#define CPU_CLK "cpu_clk"
> +
> +#ifdef CONFIG_ARCH_SPEAR13XX
> +#define MIN_CPU_FREQ 200000
> +#define MAX_CPU_FREQ 500000
> +
> +static u32 spear_cpu_freq[] = {
> + 200000, /* 200 MHZ */
> + 250000, /* 250 MHZ */
> + 332000, /* 332 MHZ */
> + 400000, /* 400 MHZ */
> + 500000, /* 500 MHZ */
> +};
> +#elif defined(CONFIG_ARCH_SPEAR6XX) || defined(CONFIG_ARCH_SPEAR3XX)
> +#define MIN_CPU_FREQ 166000
> +#define MAX_CPU_FREQ 332000
> +
> +static u32 spear_cpu_freq[] = {
> + 166000, /* 166 MHZ */
> + 266000, /* 266 MHZ */
> + 332000, /* 333 MHZ */
> +};
> +#endif
> +
> +static struct
> + cpufreq_frequency_table spear_freq_tbl[ARRAY_SIZE(spear_cpu_freq) + 1];
> +static struct clk *cpu_clk;
> +
> +int spear_cpufreq_verify(struct cpufreq_policy *policy)
> +{
> + return cpufreq_frequency_table_verify(policy, spear_freq_tbl);
> +}
> +
> +unsigned int spear_cpufreq_get(unsigned int cpu)
> +{
> + unsigned long rate;
> +
> + if (cpu)
> + return 0;
> +
> + rate = clk_get_rate(cpu_clk) / 1000;
> + return rate;
> +}
Can this be simplified to:
unsigned int spear_cpufreq_get(unsigned int cpu)
{
return cpu ? 0 : clk_get_rate(cpu_clk) / 1000;
}
? It could also be made static.
> +
> +static int spear_cpufreq_target(struct cpufreq_policy *policy,
> + unsigned int target_freq, unsigned int relation)
> +{
> + struct cpufreq_freqs freqs;
> + int ret = 0;
> + int index;
> +
> + if (policy->cpu != 0)
> + return -EINVAL;
> +
> + if (cpufreq_frequency_table_target(policy, spear_freq_tbl,
> + target_freq, relation, &index))
> + return -EINVAL;
> +
> + freqs.old = spear_cpufreq_get(0);
> + freqs.new = spear_cpu_freq[index];
> + freqs.cpu = policy->cpu;
> +
> + if (freqs.old == target_freq)
> + return 0;
> +
> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> + ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
If clk_set_rate() failed then do you need to do freqs.new =
clk_get_rate(cpu_clk) before doing the CPUFREQ_POSTCHANGE to make sure you
don't notify the wrong frequency?
> +
> + return ret;
> +}
> +
> +static int spear_cpufreq_init(struct cpufreq_policy *policy)
> +{
> + int result;
> + int i = 0;
> +
> + if (policy->cpu != 0)
> + return -EINVAL;
> +
> + cpu_clk = clk_get(NULL, CPU_CLK);
> + if (IS_ERR(cpu_clk))
> + return PTR_ERR(cpu_clk);
> +
> + policy->cpuinfo.min_freq = MIN_CPU_FREQ;
> + policy->cpuinfo.max_freq = MAX_CPU_FREQ;
> + policy->cur = policy->min = policy->max = spear_cpufreq_get(0);
> +
> + for (i = 0; i < ARRAY_SIZE(spear_cpu_freq); i++) {
> + spear_freq_tbl[i].index = i;
> + spear_freq_tbl[i].frequency = spear_cpu_freq[i];
> + }
> +
> + spear_freq_tbl[i].index = i;
> + spear_freq_tbl[i].frequency = CPUFREQ_TABLE_END;
> + result = cpufreq_frequency_table_cpuinfo(policy, spear_freq_tbl);
> + if (!result)
> + cpufreq_frequency_table_get_attr(spear_freq_tbl,
> + policy->cpu);
result doesn't appear to be used to do anything other than check the return of
cpufreq_frequency_table_cpuinfo() so could tou just eliminate that local
variable?
> +
> + policy->cpuinfo.transition_latency = 300*1000; /*250 uS*/
The comment doesn't appear to match the value here.
> +
> + return 0;
> +}
> +
> +static int spear_cpufreq_exit(struct cpufreq_policy *policy)
> +{
> + clk_put(cpu_clk);
> + return 0;
> +}
> +
> +static struct freq_attr *spear_cpufreq_attr[] = {
> + &cpufreq_freq_attr_scaling_available_freqs,
> + NULL,
> +};
> +
> +static struct cpufreq_driver spear_driver = {
> + .flags = CPUFREQ_STICKY,
> + .verify = spear_cpufreq_verify,
> + .target = spear_cpufreq_target,
> + .get = spear_cpufreq_get,
> + .init = spear_cpufreq_init,
> + .exit = spear_cpufreq_exit,
> + .name = "spear_cpufreq",
> + .attr = spear_cpufreq_attr,
> +};
> +
> +static int __init spear_cpufreq_register(void)
> +{
> + return cpufreq_register_driver(&spear_driver);
> +}
> +
> +arch_initcall(spear_cpufreq_register);
Jamie
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework
2011-01-19 0:20 ` Jamie Iles
@ 2011-01-19 2:13 ` deepaksi
2011-01-19 8:35 ` Jamie Iles
0 siblings, 1 reply; 90+ messages in thread
From: deepaksi @ 2011-01-19 2:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi James,
On 1/19/2011 5:50 AM, Jamie Iles wrote:
> Hi,
>
> On Tue, Jan 18, 2011 at 12:42:05PM +0530, Viresh Kumar wrote:
>
>> From: Deepak Sikri <deepak.sikri@st.com>
>>
>> Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
>> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
>> Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
>> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
>> ---
>>
> [...]
>
>> diff --git a/arch/arm/plat-spear/cpufreq.c b/arch/arm/plat-spear/cpufreq.c
>> new file mode 100644
>> index 0000000..9384d65
>> --- /dev/null
>> +++ b/arch/arm/plat-spear/cpufreq.c
>> @@ -0,0 +1,159 @@
>> +/*
>> + * arch/arm/plat-spear/cpufreq.c
>> + *
>> + * CPU Frequency Scaling for SPEAr platform
>> + *
>> + * Copyright (C) 2010 ST Microelectronics
>> + * Deepak Sikri<deepak.sikri@st.com>
>> + *
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/types.h>
>> +#include <linux/kernel.h>
>> +#include <linux/sched.h>
>> +#include <linux/cpufreq.h>
>> +#include <linux/delay.h>
>> +#include <linux/init.h>
>> +#include <linux/err.h>
>> +#include <linux/clk.h>
>> +#include <linux/io.h>
>> +#include <asm/system.h>
>> +#include <mach/hardware.h>
>> +
>> +#define CPU_CLK "cpu_clk"
>> +
>> +#ifdef CONFIG_ARCH_SPEAR13XX
>> +#define MIN_CPU_FREQ 200000
>> +#define MAX_CPU_FREQ 500000
>> +
>> +static u32 spear_cpu_freq[] = {
>> + 200000, /* 200 MHZ */
>> + 250000, /* 250 MHZ */
>> + 332000, /* 332 MHZ */
>> + 400000, /* 400 MHZ */
>> + 500000, /* 500 MHZ */
>> +};
>> +#elif defined(CONFIG_ARCH_SPEAR6XX) || defined(CONFIG_ARCH_SPEAR3XX)
>> +#define MIN_CPU_FREQ 166000
>> +#define MAX_CPU_FREQ 332000
>> +
>> +static u32 spear_cpu_freq[] = {
>> + 166000, /* 166 MHZ */
>> + 266000, /* 266 MHZ */
>> + 332000, /* 333 MHZ */
>> +};
>> +#endif
>> +
>> +static struct
>> + cpufreq_frequency_table spear_freq_tbl[ARRAY_SIZE(spear_cpu_freq) + 1];
>> +static struct clk *cpu_clk;
>> +
>> +int spear_cpufreq_verify(struct cpufreq_policy *policy)
>> +{
>> + return cpufreq_frequency_table_verify(policy, spear_freq_tbl);
>> +}
>> +
>> +unsigned int spear_cpufreq_get(unsigned int cpu)
>> +{
>> + unsigned long rate;
>> +
>> + if (cpu)
>> + return 0;
>> +
>> + rate = clk_get_rate(cpu_clk) / 1000;
>> + return rate;
>> +}
>>
> Can this be simplified to:
>
> unsigned int spear_cpufreq_get(unsigned int cpu)
> {
> return cpu ? 0 : clk_get_rate(cpu_clk) / 1000;
> }
>
> ? It could also be made static.
>
>
Agreed, we will update this in the next patch
>> +
>> +static int spear_cpufreq_target(struct cpufreq_policy *policy,
>> + unsigned int target_freq, unsigned int relation)
>> +{
>> + struct cpufreq_freqs freqs;
>> + int ret = 0;
>> + int index;
>> +
>> + if (policy->cpu != 0)
>> + return -EINVAL;
>> +
>> + if (cpufreq_frequency_table_target(policy, spear_freq_tbl,
>> + target_freq, relation, &index))
>> + return -EINVAL;
>> +
>> + freqs.old = spear_cpufreq_get(0);
>> + freqs.new = spear_cpu_freq[index];
>> + freqs.cpu = policy->cpu;
>> +
>> + if (freqs.old == target_freq)
>> + return 0;
>> +
>> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
>> + ret = clk_set_rate(cpu_clk, freqs.new * 1000);
>> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
>>
> If clk_set_rate() failed then do you need to do freqs.new =
> clk_get_rate(cpu_clk) before doing the CPUFREQ_POSTCHANGE to make sure you
> don't notify the wrong frequency?
>
>
I do have a point over here. In few of the drivers where the the pre
notifiers have been added, the operations have been stopped (assume a
network driver where we stalled a dma operation), and then we set the
clock rate, followed by a post notifier where driver resumes it operations.
Now lets take the case, when the clock set rate fails ( Most failure
could only be when the driver is unable to find any clock rate which is
less then/equal to requested rate) .
The post transition notifier should happen so as to allow the driver to
resume its functions. If there are no clock rate changes because of set
rate failures, the driver would be aware of that by using calls such as
clk_get_rate, and would carry forward it's operations accordingly.
How do you suggest to go about it ?
>> +
>> + return ret;
>> +}
>> +
>> +static int spear_cpufreq_init(struct cpufreq_policy *policy)
>> +{
>> + int result;
>> + int i = 0;
>> +
>> + if (policy->cpu != 0)
>> + return -EINVAL;
>> +
>> + cpu_clk = clk_get(NULL, CPU_CLK);
>> + if (IS_ERR(cpu_clk))
>> + return PTR_ERR(cpu_clk);
>> +
>> + policy->cpuinfo.min_freq = MIN_CPU_FREQ;
>> + policy->cpuinfo.max_freq = MAX_CPU_FREQ;
>> + policy->cur = policy->min = policy->max = spear_cpufreq_get(0);
>> +
>> + for (i = 0; i < ARRAY_SIZE(spear_cpu_freq); i++) {
>> + spear_freq_tbl[i].index = i;
>> + spear_freq_tbl[i].frequency = spear_cpu_freq[i];
>> + }
>> +
>> + spear_freq_tbl[i].index = i;
>> + spear_freq_tbl[i].frequency = CPUFREQ_TABLE_END;
>> + result = cpufreq_frequency_table_cpuinfo(policy, spear_freq_tbl);
>> + if (!result)
>> + cpufreq_frequency_table_get_attr(spear_freq_tbl,
>> + policy->cpu);
>>
> result doesn't appear to be used to do anything other than check the return of
> cpufreq_frequency_table_cpuinfo() so could tou just eliminate that local
> variable?
>
>
We will do it
>> +
>> + policy->cpuinfo.transition_latency = 300*1000; /*250 uS*/
>>
> The comment doesn't appear to match the value here.
>
>
Will update the comment
>> +
>> + return 0;
>> +}
>> +
>> +static int spear_cpufreq_exit(struct cpufreq_policy *policy)
>> +{
>> + clk_put(cpu_clk);
>> + return 0;
>> +}
>> +
>> +static struct freq_attr *spear_cpufreq_attr[] = {
>> + &cpufreq_freq_attr_scaling_available_freqs,
>> + NULL,
>> +};
>> +
>> +static struct cpufreq_driver spear_driver = {
>> + .flags = CPUFREQ_STICKY,
>> + .verify = spear_cpufreq_verify,
>> + .target = spear_cpufreq_target,
>> + .get = spear_cpufreq_get,
>> + .init = spear_cpufreq_init,
>> + .exit = spear_cpufreq_exit,
>> + .name = "spear_cpufreq",
>> + .attr = spear_cpufreq_attr,
>> +};
>> +
>> +static int __init spear_cpufreq_register(void)
>> +{
>> + return cpufreq_register_driver(&spear_driver);
>> +}
>> +
>> +arch_initcall(spear_cpufreq_register);
>>
> Jamie
> .
>
>
regards
Deepak
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 00/62] Updating SPEAr Support
2011-01-18 15:53 ` [PATCH V4 00/62] Updating SPEAr Support Russell King - ARM Linux
@ 2011-01-19 3:49 ` viresh kumar
0 siblings, 0 replies; 90+ messages in thread
From: viresh kumar @ 2011-01-19 3:49 UTC (permalink / raw)
To: linux-arm-kernel
On 01/18/2011 09:23 PM, Russell King - ARM Linux wrote:
> Does this mean I can get rid of the entire set of spear patches in the
> patch system now?
> .
Ya. Sure.
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 05/62] ST SPEAr: Formalized timer support
2011-01-18 23:50 ` Jamie Iles
@ 2011-01-19 3:53 ` viresh kumar
0 siblings, 0 replies; 90+ messages in thread
From: viresh kumar @ 2011-01-19 3:53 UTC (permalink / raw)
To: linux-arm-kernel
Jamie,
Thanks for reviewing our patches.
On 01/19/2011 05:20 AM, Jamie Iles wrote:
> Hi,
>
> On Tue, Jan 18, 2011 at 12:41:33PM +0530, Viresh Kumar wrote:
>> --- a/arch/arm/mach-spear3xx/spear3xx.c
>> +++ b/arch/arm/mach-spear3xx/spear3xx.c
>> @@ -523,5 +523,35 @@ struct pmx_dev pmx_plgpio_45_46_49_50 = {
>> .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
>> .enb_on_reset = 1,
>> };
>> +#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
>>
>> -#endif
>> +static void __init spear3xx_timer_init(void)
>> +{
>> + char pclk_name[] = "pll3_48m_clk";
>> + struct clk *gpt_clk, *pclk;
>> +
>> + /* get the system timer clock */
>> + gpt_clk = clk_get_sys("gpt0", NULL);
>> + if (!gpt_clk) {
>> + pr_err("%s:couldn't get clk for gpt\n", __func__);
>> + BUG();
>> + }
>> +
>> + /* get the suitable parent clock for timer*/
>> + pclk = clk_get(NULL, pclk_name);
>> + if (!pclk) {
>> + pr_err("%s:couldn't get %s as parent for gpt\n",
>> + __func__, pclk_name);
>> + BUG();
>> + }
>
> These should probably be using IS_ERR() rather than checking against NULL to
> be consistent with the API.
>
Ok.
> [...]
>> diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
>> index daff8d0..bdd5b76 100644
>> --- a/arch/arm/mach-spear6xx/spear600_evb.c
>> +++ b/arch/arm/mach-spear6xx/spear600_evb.c
>> @@ -42,10 +42,11 @@ static void __init spear600_evb_init(void)
>> amba_device_register(amba_devs[i], &iomem_resource);
>> }
>>
>> +
>
> Nitpick, why the extra newline?
>
Will be removed.
>> MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
>> .boot_params = 0x00000100,
>> .map_io = spear6xx_map_io,
>> .init_irq = spear6xx_init_irq,
>> - .timer = &spear_sys_timer,
>> + .timer = &spear6xx_timer,
>> .init_machine = spear600_evb_init,
>> MACHINE_END
>> diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
>> index f2fe14e..ea4c356 100644
>> --- a/arch/arm/mach-spear6xx/spear6xx.c
>> +++ b/arch/arm/mach-spear6xx/spear6xx.c
>> @@ -155,3 +155,34 @@ void __init spear6xx_map_io(void)
>> /* This will initialize clock framework */
>> clk_init();
>> }
>> +
>> +static void __init spear6xx_timer_init(void)
>> +{
>> + char pclk_name[] = "pll3_48m_clk";
>> + struct clk *gpt_clk, *pclk;
>> +
>> + /* get the system timer clock */
>> + gpt_clk = clk_get_sys("gpt0", NULL);
>> + if (!gpt_clk) {
>> + pr_err("%s:couldn't get clk for gpt\n", __func__);
>> + BUG();
>> + }
>> +
>> + /* get the suitable parent clock for timer*/
>> + pclk = clk_get(NULL, pclk_name);
>> + if (!pclk) {
>> + pr_err("%s:couldn't get %s as parent for gpt\n",
>> + __func__, pclk_name);
>> + BUG();
>> + }
>
> As above, IS_ERR() would be better here.
>
Ok.
--
viresh
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 04/62] ST SPEAr: Making clock functions more generic
2011-01-18 15:56 ` Russell King - ARM Linux
@ 2011-01-19 4:03 ` viresh kumar
0 siblings, 0 replies; 90+ messages in thread
From: viresh kumar @ 2011-01-19 4:03 UTC (permalink / raw)
To: linux-arm-kernel
On 01/18/2011 09:26 PM, Russell King - ARM Linux wrote:
> On Tue, Jan 18, 2011 at 12:41:32PM +0530, Viresh Kumar wrote:
>> /* pll1 configuration structure */
>> static struct pll_clk_config pll1_config = {
>> .mode_reg = PLL1_CTR,
>> .cfg_reg = PLL1_FRQ,
>> + .masks = &pll1_masks,
>> };
>>
>> /* PLL1 clock */
> ...
>> - mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) &
>> - PLL_MODE_MASK;
>> + mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
>> + config->masks->mode_mask;
>>
> ...
>> struct pll_clk_config {
>> - unsigned int *mode_reg;
>> - unsigned int *cfg_reg;
>> + u32 *mode_reg;
>> + u32 *cfg_reg;
>> + struct pll_clk_masks *masks;
>> };
>
> Registers should have an __iomem attribute on them. Preferably, but
> not absolutely necessary, should be void to prevent any direct
> dereferencing.
> .
>
Yes, it should be void __iomem *
--
viresh
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 26/62] ST SPEAr: Adding support for SSP PL022
2011-01-18 16:18 ` Russell King - ARM Linux
@ 2011-01-19 4:16 ` viresh kumar
0 siblings, 0 replies; 90+ messages in thread
From: viresh kumar @ 2011-01-19 4:16 UTC (permalink / raw)
To: linux-arm-kernel
On 01/18/2011 09:48 PM, Russell King - ARM Linux wrote:
> On Tue, Jan 18, 2011 at 12:41:53PM +0530, Viresh Kumar wrote:
>> diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
>> index ad1c6a0..088bf52 100644
>> --- a/arch/arm/mach-spear13xx/spear1300_evb.c
>> +++ b/arch/arm/mach-spear13xx/spear1300_evb.c
>> @@ -12,7 +12,10 @@
>> */
>>
>> #include <linux/types.h>
>> +#include <linux/gpio.h>
>
> :-)
>
>> diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
>> index c219691..0e3d8f3 100644
>> --- a/arch/arm/mach-spear3xx/spear300_evb.c
>> +++ b/arch/arm/mach-spear3xx/spear300_evb.c
>> @@ -15,10 +15,14 @@
>> #include <linux/mtd/fsmc.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach-types.h>
>> +#include <linux/spi/flash.h>
>> +#include <linux/spi/spi.h>
>> #include <mach/generic.h>
>> +#include <mach/gpio.h>
>
> :-(
>
>> diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
>> index d216c94..6daacbb 100644
>> --- a/arch/arm/mach-spear3xx/spear310_evb.c
>> +++ b/arch/arm/mach-spear3xx/spear310_evb.c
>> @@ -15,9 +15,13 @@
>> #include <linux/mtd/fsmc.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach-types.h>
>> +#include <linux/spi/flash.h>
>> +#include <linux/spi/spi.h>
>> #include <mach/generic.h>
>> +#include <mach/gpio.h>
>
> :-(
>
>> diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
>> index 15db267..baa4574 100644
>> --- a/arch/arm/mach-spear3xx/spear320_evb.c
>> +++ b/arch/arm/mach-spear3xx/spear320_evb.c
>> @@ -15,9 +15,13 @@
>> #include <linux/mtd/fsmc.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach-types.h>
>> +#include <linux/spi/flash.h>
>> +#include <linux/spi/spi.h>
>> #include <mach/generic.h>
>> +#include <mach/gpio.h>
>
> :-(
>
>> diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
>> index 32d3855..fe9a8c8 100644
>> --- a/arch/arm/mach-spear6xx/spear600_evb.c
>> +++ b/arch/arm/mach-spear6xx/spear600_evb.c
>> @@ -15,15 +15,23 @@
>> #include <linux/mtd/fsmc.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach-types.h>
>> +#include <linux/gpio.h>
>> +#include <linux/spi/flash.h>
>> +#include <linux/spi/spi.h>
>> #include <mach/generic.h>
>> +#include <mach/gpio.h>
>
> :-(
>
>> diff --git a/arch/arm/plat-spear/include/plat/spi.h b/arch/arm/plat-spear/include/plat/spi.h
>> new file mode 100644
>> index 0000000..24d57e1
>> --- /dev/null
>> +++ b/arch/arm/plat-spear/include/plat/spi.h
>> @@ -0,0 +1,74 @@
>> +/*
>> + * arch/arm/plat-spear/include/plat/spi.h
>> + *
>> + * SPI board specific definitions common to multiple boards on multiple
>> + * machines.
>> + *
>> + * Copyright (C) 2010 ST Microelectronics
>> + * Viresh Kumar<viresh.kumar@st.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#ifndef __PLAT_SPI_H
>> +#define __PLAT_SPI_H
>> +
>> +#include <linux/amba/pl022.h>
>> +#include <linux/gpio.h>
>
> :-)
> .
Will use linux/gpio.h everywhere and not mach/gpio.h
--
viresh
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 25/62] ST SPEAr: Added PCIE host controller base driver support.
2011-01-19 0:05 ` Russell King - ARM Linux
@ 2011-01-19 4:17 ` viresh kumar
0 siblings, 0 replies; 90+ messages in thread
From: viresh kumar @ 2011-01-19 4:17 UTC (permalink / raw)
To: linux-arm-kernel
On 01/19/2011 05:35 AM, Russell King - ARM Linux wrote:
> On Tue, Jan 18, 2011 at 12:41:52PM +0530, Viresh Kumar wrote:
>> + clk = clk_get_sys("pcie1", NULL);
>> + if (!clk) {
>
> IS_ERR(clk)
>
>> + pr_err("%s:couldn't get clk for pcie1\n",
>> + __func__);
>> + continue;
>> + }
>> + if (clk_enable(clk)) {
>> + pr_err("%s:couldn't enable clk for pcie1\n",
>> + __func__);
>> + continue;
>> + }
>> + } else if (port == 2) {
>> + /* Ideally CFG Clock should have been also enabled
>> + * here. But it is done currently during board
>> + * init routne*/
>> + clk = clk_get_sys("pcie2", NULL);
>> + if (!clk) {
>
> IS_ERR(clk)
>
>> + pr_err("%s:couldn't get clk for pcie2\n",
>> + __func__);
>> + continue;
>> + }
>> + if (clk_enable(clk)) {
>> + pr_err("%s:couldn't enable clk for pcie2\n",
>> + __func__);
>> + continue;
>> + }
>> + }
>> +
>> + if ((*pcie_port_is_host)(port))
>> + add_pcie_port(port, spr_pcie_base[port],
>> + spr_pcie_app_base[port]);
>> + }
> ...
>> +#ifdef CONFIG_PCIEPORTBUS
>> +/* PCIE0 clock always needs to be enabled if any of the three PCIE port
>> + * have to be used. So call this function from the board initilization
>> + * file. Ideally , all controller should have been independent from
>> + * others with respect to clock.
>> + */
>> +int enable_pcie0_clk(void)
>> +{
>> + struct clk *clk;
>> + /*Enable all CLK in CFG registers here only. Idealy only PCIE0
>> + * should have been enabled. But Controler does not work
>> + * properly if PCIE1 and PCIE2's CFG CLK is enabled in stages.
>> + */
>> + writel(PCIE0_CFG_VAL | PCIE1_CFG_VAL | PCIE2_CFG_VAL, PCIE_CFG);
>> + clk = clk_get_sys("pcie0", NULL);
>> + if (!clk) {
>
> IS_ERR(clk)
>
Ok.
--
viresh
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 06/62] ST SPEAr13XX: Adding machine specific header files
2011-01-18 16:00 ` Russell King - ARM Linux
@ 2011-01-19 4:38 ` viresh kumar
2011-01-19 9:02 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: viresh kumar @ 2011-01-19 4:38 UTC (permalink / raw)
To: linux-arm-kernel
On 01/18/2011 09:30 PM, Russell King - ARM Linux wrote:
> On Tue, Jan 18, 2011 at 12:41:34PM +0530, Viresh Kumar wrote:
>> +#define MISC_BASE VA_SPEAR13XX_MISC_BASE
>> +
>> +/* General Configuration */
>> +#define SOC_CFG ((unsigned int *)(MISC_BASE + 0x000))
>> +#define BOOTSTRAP_CFG ((unsigned int *)(MISC_BASE + 0x004))
>
> You could really do with an IOMEM() macro, thus:
>
> #ifndef __ASSEMBLY__
> #define IOMEM(x) ((void __iomem __force *)(x))
> #else
> #define IOMEM(x) (x)
> #endif
>
> You can then use that for stuff like VA_SPEAR13XX_MISC_BASE, and all
> these definitions then become:
>
> #define SOC_CFG (MISC_BASE + 0x000)
>
> because GCC allows void pointer arithmetic (treats it as char).
>
Yes. I agree with this solution.
Actually the VA* macros are like:
#define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
Adding IOMEM() over IO_ADDRESS(SPEAR13XX_MISC_BASE) will make it too long.
And might cross 80 columns. Can we modify IO_ADDRESS() to use IOMEM()?
--
viresh
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310
2011-01-19 0:09 ` Jamie Iles
@ 2011-01-19 4:39 ` viresh kumar
2011-01-19 6:40 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: viresh kumar @ 2011-01-19 4:39 UTC (permalink / raw)
To: linux-arm-kernel
On 01/19/2011 05:39 AM, Jamie Iles wrote:
> On Tue, Jan 18, 2011 at 12:41:59PM +0530, Viresh Kumar wrote:
>> +static struct spi_board_info __initdata spi_board_info[] = {
>> +};
>
> AFAICT spi_register_board_info() doesn't do anything when passed this empty
> array so both the array and call could be removed.
>
Actually we don't have free gpio's in evb boards to use as chip select for ssp.
So didn't add any spi devices here in this array. It is just added here so that
anybody who needs to test it can simply come here, add a device and test.
Can we keep it as it is?
>> +
>> +#ifdef CONFIG_PCIEPORTBUS
>> +/* this function is needed for PCIE host and device driver. Same
>> + * controller can not be programmed as host as well as device. So host
>> + * driver must call this function and if this function returns 1 then
>> + * only host should add that particular port as RC.
>> + * A port to be added as device, one must also add device's information
>> + * in plat_devs array defined in this file.
>> + * it is the responsibility of calling function to not send port number
>> + * greter than max no of controller(3)
>> + */
>> +int spear1310_pcie_port_is_host(int port)
>> +{
>> + switch (port) {
>> + case 0:
>> + return 0;
>> + case 1:
>> + return 1;
>> + case 2:
>> + return 1;
>> + }
>> + return -EINVAL;
>> +}
>> +#endif
>
> It looks like this can be made static. Also, given the comment, is it worth
> adding a BUG_ON(port > 3)?
>
will be done. BUG_ON() can be added here.
>> +static void __init spear1310_evb_init(void)
>> +{
>> + unsigned int i;
>> +
>> + /* set keyboard plat data */
>> + kbd_set_plat_data(&spear13xx_kbd_device, &kbd_data);
>> +
>> + /* set nand device's plat data */
>> + fsmc_nand_set_plat_data(&spear13xx_nand_device, NULL, 0,
>> + NAND_SKIP_BBTSCAN, FSMC_NAND_BW8);
>> + nand_mach_init(FSMC_NAND_BW8);
>> +
>> + /* call spear1310 machine init function */
>> + spear1310_init();
>> +
>> + /* Register slave devices on the I2C buses */
>> + i2c_register_default_devices();
>> +
>> +#ifdef CONFIG_PCIEPORTBUS
>> + /* Enable PCIE0 clk */
>> + enable_pcie0_clk();
>> + pcie_init(&spear1310_pcie_port_is_host);
>
> No '&' needed before function name.
>
Ok.
--
viresh
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files
2011-01-18 16:06 ` Russell King - ARM Linux
@ 2011-01-19 6:03 ` Shiraz Hashim
2011-01-19 8:52 ` Russell King - ARM Linux
0 siblings, 1 reply; 90+ messages in thread
From: Shiraz Hashim @ 2011-01-19 6:03 UTC (permalink / raw)
To: linux-arm-kernel
Hello Russell,
On Wed, Jan 19, 2011 at 12:06:55AM +0800, Russell King - ARM Linux wrote:
> On Tue, Jan 18, 2011 at 12:41:35PM +0530, Viresh Kumar wrote:
> > diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
> > new file mode 100644
> > index 0000000..30761d3
> > --- /dev/null
> > +++ b/arch/arm/mach-spear13xx/headsmp.S
> > @@ -0,0 +1,96 @@
> > +/*
> > + * arch/arm/mach-spear13XX/headsmp.S
> > + *
> > + * Picked from realview
> > + * Copyright (c) 2010 ST Microelectronics Limited
> > + * Shiraz Hashim <shiraz.hashim@st.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#include <linux/linkage.h>
> > +#include <linux/init.h>
> > +
> > + __INIT
>
> Is this ever called after the kernel text is thrown away? What if we
> add support in the generic code to start with secondary CPUs offline
> as a power saving or boot time feature?
>
No. SPEAr platform has no additional feature to explicitly control
this aspect of secondary CPUs. Does ARMv7 itself provdes some features
for power management of secondary CPUs ?
> > +
> > +/*
> > + * This one is picked from Tegra :-
> > + *
> > + * The secondary kernel init calls v7_flush_dcache_all before it enables
> > + * the L1; however, the L1 comes out of reset in an undefined state, so
> > + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
> > + * of cache lines with uninitialized data and uninitialized tags to get
> > + * written out to memory, which does really unpleasant things to the ain
> > + * processor. We fix this by performing an invalidate, rather than a
> > + * clean + invalidate, before jumping into the kernel.
> > + */
> > +ENTRY(v7_invalidate_l1)
> > + mov r0, #0
> > + mcr p15, 2, r0, c0, c0, 0
> > + mrc p15, 1, r0, c0, c0, 0
> > +
> > + ldr r1, =0x7fff
> > + and r2, r1, r0, lsr #13
> > +
> > + ldr r1, =0x3ff
> > +
> > + and r3, r1, r0, lsr #3 @ NumWays - 1
> > + add r2, r2, #1 @ NumSets
> > +
> > + and r0, r0, #0x7
> > + add r0, r0, #4 @ SetShift
> > +
> > + clz r1, r3 @ WayShift
> > + add r4, r3, #1 @ NumWays
> > +1: sub r2, r2, #1 @ NumSets--
> > + mov r3, r4 @ Temp = NumWays
> > +2: subs r3, r3, #1 @ Temp--
> > + mov r5, r3, lsl r1
> > + mov r6, r2, lsl r0
> > + orr r5, r5, r6 @ Reg = Temp<<WayShift)|(NumSets<<SetShift)
> > + mcr p15, 0, r5, c7, c6, 2
> > + bgt 2b
> > + cmp r2, #0
> > + bgt 1b
> > + dsb
> > + isb
> > + mov pc, lr
> > +ENDPROC(v7_invalidate_l1)
>
> This code appears to have its only caller commented out. Should it be
> removed?
>
yes, would remove it.
> > +
> > +/*
> > + * spear13xx specific entry point for secondary CPUs. This provides
> > + * a "holding pen" into which all secondary cores are held until we're
> > + * ready for them to initialise.
> > + */
> > +ENTRY(spear13xx_secondary_startup)
> > + /* If we don't do this then we have a crash */
> > +
> > + /*
> > + * Since now this is being called from xloader so removing it
> > + * here
> > + */
> > +#if 0
> > + bl v7_invalidate_l1
> > +#endif
> > +
> > + mrc p15, 0, r0, c0, c0, 5
> > + and r0, r0, #15
> > + adr r4, 1f
> > + ldmia r4, {r5, r6}
> > + sub r4, r4, r5
> > + add r6, r6, r4
> > +pen: ldr r7, [r6]
> > + cmp r7, r0
> > + bne pen
> > +
> > + /*
> > + * we've been released from the holding pen: secondary_stack
> > + * should now contain the SVC stack for this core
> > + */
> > + b secondary_startup
> > +
> > + .align
> > +1: .long .
> > + .long pen_release
> ...
> > +volatile int __cpuinitdata pen_release = -1;
> > +static DEFINE_SPINLOCK(boot_lock);
> > +
> > +/*
> > + * Write pen_release in a way that is guaranteed to be visible to all
> > + * observers, irrespective of whether they're taking part in coherency
> > + * or not. This is necessary for the hotplug code to work reliably.
> > + */
> > +static void write_pen_release(int val)
> > +{
> > + pen_release = val;
> > + smp_wmb();
> > + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
> > + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
> > +}
> > +
> > +static void __iomem *scu_base_addr(void)
> > +{
> > + return __io_address(SPEAR13XX_SCU_BASE);
> > +}
> > +
> > +void __cpuinit platform_secondary_init(unsigned int cpu)
> > +{
> > + /*
> > + * if any interrupts are already enabled for the primary
> > + * core (e.g. timer irq), then they will not have been enabled
> > + * for us: do so
> > + */
> > + gic_secondary_init(0);
> > +
> > + /*
> > + * let the primary processor know we're out of the
> > + * pen, then head off into the C entry point
> > + */
> > + write_pen_release(-1);
> > +
> > + /*
> > + * Synchronise with the boot thread.
> > + */
> > + spin_lock(&boot_lock);
> > + spin_unlock(&boot_lock);
> > +}
> > +
> > +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> > +{
> > + unsigned long timeout;
> > +
> > + /*
> > + * set synchronisation state between this boot processor
> > + * and the secondary one
> > + */
> > + spin_lock(&boot_lock);
> > +
> > + /*
> > + * The secondary processor is waiting to be released from
> > + * the holding pen - release it, then wait for it to flag
> > + * that it has been released by resetting pen_release.
> > + *
> > + * Note that "pen_release" is the hardware CPU ID, whereas
> > + * "cpu" is Linux's internal ID.
> > + */
> > + write_pen_release(cpu);
> > +
> > + timeout = jiffies + (1 * HZ);
> > + while (time_before(jiffies, timeout)) {
> > + smp_rmb();
> > + if (pen_release == -1)
> > + break;
> > +
> > + udelay(10);
> > + }
> > +
> > + /*
> > + * now the secondary core is starting up let it run its
> > + * calibrations, then wait for it to finish
> > + */
> > + spin_unlock(&boot_lock);
> > +
> > + return pen_release != -1 ? -ENOSYS : 0;
> > +}
> > +
> > +/*
> > + * Initialise the CPU possible map early - this describes the CPUs
> > + * which may be present or become present in the system.
> > + */
> > +void __init smp_init_cpus(void)
> > +{
> > + void __iomem *scu_base = scu_base_addr();
> > + unsigned int i, ncores;
> > +
> > + ncores = scu_base ? scu_get_core_count(scu_base) : 1;
> > +
> > + for (i = 0; i < ncores; i++)
> > + set_cpu_possible(i, true);
> > +}
> > +
> > +static void __init wakeup_secondary(void)
> > +{
> > + /* nobody is to be released from the pen yet */
> > + pen_release = -1;
>
> But pen_release starts off as -1, so is this really needed?
>
Not required, would remove.
> > +
> > + /*
> > + * Write the address of secondary startup into the system-wide
> > + * location (presently it is in SRAM). The BootMonitor waits
> > + * for this register to become non-zero.
> > + * We must also send an sev to wake it up
> > + */
> > + __raw_writel(BSYM(virt_to_phys(spear13xx_secondary_startup)),
> > + __io_address(SPEAR13XX_SYS_LOCATION));
> > +
> > + mb();
>
> Do you really need to sync back to L2, or will a dsb() do here - and
> as the spinlock code uses dsb() + sev() together, would it make sense
> to combine the two? (dsb() is required to ensure all previous writes
> are visible prior to the sev() executing.)
Presently L2 cache is initialized after we bootup secondary CPU but
one can have the possibility of initializing L2 earlier also.
So this would be safer.
--
regards
Shiraz
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310
2011-01-19 4:39 ` viresh kumar
@ 2011-01-19 6:40 ` viresh kumar
2011-01-19 8:29 ` Jamie Iles
0 siblings, 1 reply; 90+ messages in thread
From: viresh kumar @ 2011-01-19 6:40 UTC (permalink / raw)
To: linux-arm-kernel
On 01/19/2011 10:09 AM, viresh kumar wrote:
>>> >> +
>>> >> +#ifdef CONFIG_PCIEPORTBUS
>>> >> +/* this function is needed for PCIE host and device driver. Same
>>> >> + * controller can not be programmed as host as well as device. So host
>>> >> + * driver must call this function and if this function returns 1 then
>>> >> + * only host should add that particular port as RC.
>>> >> + * A port to be added as device, one must also add device's information
>>> >> + * in plat_devs array defined in this file.
>>> >> + * it is the responsibility of calling function to not send port number
>>> >> + * greter than max no of controller(3)
>>> >> + */
>>> >> +int spear1310_pcie_port_is_host(int port)
>>> >> +{
>>> >> + switch (port) {
>>> >> + case 0:
>>> >> + return 0;
>>> >> + case 1:
>>> >> + return 1;
>>> >> + case 2:
>>> >> + return 1;
>>> >> + }
>>> >> + return -EINVAL;
>>> >> +}
>>> >> +#endif
>> >
>> > It looks like this can be made static. Also, given the comment, is it worth
>> > adding a BUG_ON(port > 3)?
>> >
> will be done. BUG_ON() can be added here.
>
There is another thought here. We may not require a BUG_ON here.
Returning error would be better, so that driver can take steps accordingly.
Also it is not that much blocking of a issue, that we need BUG_ON.
--
viresh
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310
2011-01-19 6:40 ` viresh kumar
@ 2011-01-19 8:29 ` Jamie Iles
0 siblings, 0 replies; 90+ messages in thread
From: Jamie Iles @ 2011-01-19 8:29 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 19, 2011 at 12:10:48PM +0530, viresh kumar wrote:
> On 01/19/2011 10:09 AM, viresh kumar wrote:
> >>> >> +
> >>> >> +#ifdef CONFIG_PCIEPORTBUS
> >>> >> +/* this function is needed for PCIE host and device driver. Same
> >>> >> + * controller can not be programmed as host as well as device. So host
> >>> >> + * driver must call this function and if this function returns 1 then
> >>> >> + * only host should add that particular port as RC.
> >>> >> + * A port to be added as device, one must also add device's information
> >>> >> + * in plat_devs array defined in this file.
> >>> >> + * it is the responsibility of calling function to not send port number
> >>> >> + * greter than max no of controller(3)
> >>> >> + */
> >>> >> +int spear1310_pcie_port_is_host(int port)
> >>> >> +{
> >>> >> + switch (port) {
> >>> >> + case 0:
> >>> >> + return 0;
> >>> >> + case 1:
> >>> >> + return 1;
> >>> >> + case 2:
> >>> >> + return 1;
> >>> >> + }
> >>> >> + return -EINVAL;
> >>> >> +}
> >>> >> +#endif
> >> >
> >> > It looks like this can be made static. Also, given the comment, is it worth
> >> > adding a BUG_ON(port > 3)?
> >> >
> > will be done. BUG_ON() can be added here.
> >
>
> There is another thought here. We may not require a BUG_ON here.
> Returning error would be better, so that driver can take steps accordingly.
> Also it is not that much blocking of a issue, that we need BUG_ON.
Ok, I don't have a problem with that!
Jamie
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework
2011-01-19 2:13 ` deepaksi
@ 2011-01-19 8:35 ` Jamie Iles
2011-01-19 9:00 ` Shiraz Hashim
0 siblings, 1 reply; 90+ messages in thread
From: Jamie Iles @ 2011-01-19 8:35 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 19, 2011 at 07:43:05AM +0530, deepaksi wrote:
> Hi James,
>
> On 1/19/2011 5:50 AM, Jamie Iles wrote:
> >> +static int spear_cpufreq_target(struct cpufreq_policy *policy,
> >> + unsigned int target_freq, unsigned int relation)
> >> +{
> >> + struct cpufreq_freqs freqs;
> >> + int ret = 0;
> >> + int index;
> >> +
> >> + if (policy->cpu != 0)
> >> + return -EINVAL;
> >> +
> >> + if (cpufreq_frequency_table_target(policy, spear_freq_tbl,
> >> + target_freq, relation, &index))
> >> + return -EINVAL;
> >> +
> >> + freqs.old = spear_cpufreq_get(0);
> >> + freqs.new = spear_cpu_freq[index];
> >> + freqs.cpu = policy->cpu;
> >> +
> >> + if (freqs.old == target_freq)
> >> + return 0;
> >> +
> >> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> >> + ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> >> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
> >>
> > If clk_set_rate() failed then do you need to do freqs.new =
> > clk_get_rate(cpu_clk) before doing the CPUFREQ_POSTCHANGE to make sure you
> > don't notify the wrong frequency?
> >
> >
> I do have a point over here. In few of the drivers where the the pre
> notifiers have been added, the operations have been stopped (assume a
> network driver where we stalled a dma operation), and then we set the
> clock rate, followed by a post notifier where driver resumes it operations.
>
> Now lets take the case, when the clock set rate fails ( Most failure
> could only be when the driver is unable to find any clock rate which is
> less then/equal to requested rate) .
> The post transition notifier should happen so as to allow the driver to
> resume its functions. If there are no clock rate changes because of set
> rate failures, the driver would be aware of that by using calls such as
> clk_get_rate, and would carry forward it's operations accordingly.
>
> How do you suggest to go about it ?
Sorry, I didn't mean to remove the post notifier, just do something like:
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
ret = clk_set_rate(cpu_clk, freqs.new * 1000);
if (ret)
freqs.new = clk_get_rate(cpu_clk);
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
Or:
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
ret = clk_set_rate(cpu_clk, freqs.new * 1000);
if (ret)
freqs.new = freqs.old;
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
So that you're notifying the cpufreq subsystem of the frequency that you're
actually running at with the post change notifier rather than the one you
tried to go for. If you don't do this then for UP you'll end up recaculating
lpj based on the wrong frequency.
Jamie
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files
2011-01-19 6:03 ` Shiraz Hashim
@ 2011-01-19 8:52 ` Russell King - ARM Linux
2011-01-19 9:20 ` Shiraz Hashim
0 siblings, 1 reply; 90+ messages in thread
From: Russell King - ARM Linux @ 2011-01-19 8:52 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 19, 2011 at 11:33:09AM +0530, Shiraz Hashim wrote:
> Hello Russell,
>
> On Wed, Jan 19, 2011 at 12:06:55AM +0800, Russell King - ARM Linux wrote:
> > Do you really need to sync back to L2, or will a dsb() do here - and
> > as the spinlock code uses dsb() + sev() together, would it make sense
> > to combine the two? (dsb() is required to ensure all previous writes
> > are visible prior to the sev() executing.)
>
> Presently L2 cache is initialized after we bootup secondary CPU but
> one can have the possibility of initializing L2 earlier also.
> So this would be safer.
It shouldn't make any difference as we explicitly flush the required
data for the secondary while it is incoherent out of L2 into RAM -
that being secondary_data and pen_release.
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework
2011-01-19 8:35 ` Jamie Iles
@ 2011-01-19 9:00 ` Shiraz Hashim
2011-01-19 9:39 ` Shiraz Hashim
0 siblings, 1 reply; 90+ messages in thread
From: Shiraz Hashim @ 2011-01-19 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi James,
On Wed, Jan 19, 2011 at 04:35:27PM +0800, Jamie Iles wrote:
> On Wed, Jan 19, 2011 at 07:43:05AM +0530, deepaksi wrote:
> > Hi James,
> >
> > On 1/19/2011 5:50 AM, Jamie Iles wrote:
> > >> +static int spear_cpufreq_target(struct cpufreq_policy *policy,
> > >> + unsigned int target_freq, unsigned int relation)
> > >> +{
> > >> + struct cpufreq_freqs freqs;
> > >> + int ret = 0;
> > >> + int index;
> > >> +
> > >> + if (policy->cpu != 0)
> > >> + return -EINVAL;
> > >> +
> > >> + if (cpufreq_frequency_table_target(policy, spear_freq_tbl,
> > >> + target_freq, relation, &index))
> > >> + return -EINVAL;
> > >> +
> > >> + freqs.old = spear_cpufreq_get(0);
> > >> + freqs.new = spear_cpu_freq[index];
> > >> + freqs.cpu = policy->cpu;
> > >> +
> > >> + if (freqs.old == target_freq)
> > >> + return 0;
> > >> +
> > >> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> > >> + ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> > >> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
> > >>
> > > If clk_set_rate() failed then do you need to do freqs.new =
> > > clk_get_rate(cpu_clk) before doing the CPUFREQ_POSTCHANGE to make sure you
> > > don't notify the wrong frequency?
> > >
> > >
> > I do have a point over here. In few of the drivers where the the pre
> > notifiers have been added, the operations have been stopped (assume a
> > network driver where we stalled a dma operation), and then we set the
> > clock rate, followed by a post notifier where driver resumes it operations.
> >
> > Now lets take the case, when the clock set rate fails ( Most failure
> > could only be when the driver is unable to find any clock rate which is
> > less then/equal to requested rate) .
> > The post transition notifier should happen so as to allow the driver to
> > resume its functions. If there are no clock rate changes because of set
> > rate failures, the driver would be aware of that by using calls such as
> > clk_get_rate, and would carry forward it's operations accordingly.
> >
> > How do you suggest to go about it ?
>
> Sorry, I didn't mean to remove the post notifier, just do something like:
>
> cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> if (ret)
> freqs.new = clk_get_rate(cpu_clk);
> cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
>
> Or:
>
> cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> if (ret)
> freqs.new = freqs.old;
> cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
>
> So that you're notifying the cpufreq subsystem of the frequency that you're
> actually running at with the post change notifier rather than the one you
> tried to go for. If you don't do this then for UP you'll end up recaculating
> lpj based on the wrong frequency.
Agree. We would add it here. Thanks for pointing out.
--
regards
Shiraz
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 06/62] ST SPEAr13XX: Adding machine specific header files
2011-01-19 4:38 ` viresh kumar
@ 2011-01-19 9:02 ` viresh kumar
0 siblings, 0 replies; 90+ messages in thread
From: viresh kumar @ 2011-01-19 9:02 UTC (permalink / raw)
To: linux-arm-kernel
On 01/19/2011 10:08 AM, viresh kumar wrote:
> On 01/18/2011 09:30 PM, Russell King - ARM Linux wrote:
>> On Tue, Jan 18, 2011 at 12:41:34PM +0530, Viresh Kumar wrote:
>>> +#define MISC_BASE VA_SPEAR13XX_MISC_BASE
>>> +
>>> +/* General Configuration */
>>> +#define SOC_CFG ((unsigned int *)(MISC_BASE + 0x000))
>>> +#define BOOTSTRAP_CFG ((unsigned int *)(MISC_BASE + 0x004))
>>
>> You could really do with an IOMEM() macro, thus:
>>
>> #ifndef __ASSEMBLY__
>> #define IOMEM(x) ((void __iomem __force *)(x))
>> #else
>> #define IOMEM(x) (x)
>> #endif
>>
>> You can then use that for stuff like VA_SPEAR13XX_MISC_BASE, and all
>> these definitions then become:
>>
>> #define SOC_CFG (MISC_BASE + 0x000)
>>
>> because GCC allows void pointer arithmetic (treats it as char).
>>
>
> Yes. I agree with this solution.
> Actually the VA* macros are like:
> #define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
>
> Adding IOMEM() over IO_ADDRESS(SPEAR13XX_MISC_BASE) will make it too long.
> And might cross 80 columns. Can we modify IO_ADDRESS() to use IOMEM()?
>
Russell,
I tried to change IO_ADDRESS() to use IOMEM. But even this doesn't seem to be a
good enough solution. __typesafe_io expects unsigned long and we have:
define __io_address(n) __io(IO_ADDRESS(n)).
Also, struct map_desc, .virtual field expects unsigned long, where we are getting
warnings.
I tried looking at what others did, and found either they are using (unsigned int *)
(as earlier done by us) or casting with (unsigned long) for new warnings mentioned
above.
Both didn't seem to be good enough to me. Maybe we can use IOMEM only for MISC_BASE
and similar places, where we had been using (unsigned int *).
I will do this in V5, unless you suggest something better.
--
viresh
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files
2011-01-19 8:52 ` Russell King - ARM Linux
@ 2011-01-19 9:20 ` Shiraz Hashim
0 siblings, 0 replies; 90+ messages in thread
From: Shiraz Hashim @ 2011-01-19 9:20 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 19, 2011 at 04:52:46PM +0800, Russell King - ARM Linux wrote:
> On Wed, Jan 19, 2011 at 11:33:09AM +0530, Shiraz Hashim wrote:
> > Hello Russell,
> >
> > On Wed, Jan 19, 2011 at 12:06:55AM +0800, Russell King - ARM Linux wrote:
> > > Do you really need to sync back to L2, or will a dsb() do here - and
> > > as the spinlock code uses dsb() + sev() together, would it make sense
> > > to combine the two? (dsb() is required to ensure all previous writes
> > > are visible prior to the sev() executing.)
> >
> > Presently L2 cache is initialized after we bootup secondary CPU but
> > one can have the possibility of initializing L2 earlier also.
> > So this would be safer.
>
> It shouldn't make any difference as we explicitly flush the required
> data for the secondary while it is incoherent out of L2 into RAM -
> that being secondary_data and pen_release.
OK, but sev must follow after the SPEAR13XX_SYS_LOCATION has been
updated as secondary CPU boot code is in wfe and expects the location
to be updated when it is woken.
--
regards
Shiraz
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework
2011-01-19 9:00 ` Shiraz Hashim
@ 2011-01-19 9:39 ` Shiraz Hashim
2011-01-19 9:53 ` Russell King - ARM Linux
0 siblings, 1 reply; 90+ messages in thread
From: Shiraz Hashim @ 2011-01-19 9:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jamie,
On Wed, Jan 19, 2011 at 02:30:08PM +0530, Shiraz Hashim wrote:
> Hi James,
>
> On Wed, Jan 19, 2011 at 04:35:27PM +0800, Jamie Iles wrote:
> > On Wed, Jan 19, 2011 at 07:43:05AM +0530, deepaksi wrote:
> > > Hi James,
> > >
> > > On 1/19/2011 5:50 AM, Jamie Iles wrote:
> > > >> +static int spear_cpufreq_target(struct cpufreq_policy *policy,
> > > >> + unsigned int target_freq, unsigned int relation)
> > > >> +{
> > > >> + struct cpufreq_freqs freqs;
> > > >> + int ret = 0;
> > > >> + int index;
> > > >> +
> > > >> + if (policy->cpu != 0)
> > > >> + return -EINVAL;
> > > >> +
> > > >> + if (cpufreq_frequency_table_target(policy, spear_freq_tbl,
> > > >> + target_freq, relation, &index))
> > > >> + return -EINVAL;
> > > >> +
> > > >> + freqs.old = spear_cpufreq_get(0);
> > > >> + freqs.new = spear_cpu_freq[index];
> > > >> + freqs.cpu = policy->cpu;
> > > >> +
> > > >> + if (freqs.old == target_freq)
> > > >> + return 0;
> > > >> +
> > > >> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> > > >> + ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> > > >> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
> > > >>
> > > > If clk_set_rate() failed then do you need to do freqs.new =
> > > > clk_get_rate(cpu_clk) before doing the CPUFREQ_POSTCHANGE to make sure you
> > > > don't notify the wrong frequency?
> > > >
> > > >
> > > I do have a point over here. In few of the drivers where the the pre
> > > notifiers have been added, the operations have been stopped (assume a
> > > network driver where we stalled a dma operation), and then we set the
> > > clock rate, followed by a post notifier where driver resumes it operations.
> > >
> > > Now lets take the case, when the clock set rate fails ( Most failure
> > > could only be when the driver is unable to find any clock rate which is
> > > less then/equal to requested rate) .
> > > The post transition notifier should happen so as to allow the driver to
> > > resume its functions. If there are no clock rate changes because of set
> > > rate failures, the driver would be aware of that by using calls such as
> > > clk_get_rate, and would carry forward it's operations accordingly.
> > >
> > > How do you suggest to go about it ?
> >
> > Sorry, I didn't mean to remove the post notifier, just do something like:
> >
> > cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> > ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> > if (ret)
> > freqs.new = clk_get_rate(cpu_clk);
> > cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
> >
> > Or:
> >
> > cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> > ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> > if (ret)
> > freqs.new = freqs.old;
> > cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
> >
> > So that you're notifying the cpufreq subsystem of the frequency that you're
> > actually running at with the post change notifier rather than the one you
> > tried to go for. If you don't do this then for UP you'll end up recaculating
> > lpj based on the wrong frequency.
>
> Agree. We would add it here. Thanks for pointing out.
On second thought it should always be there irrespective of failures
as in our case it may happen that eventually CPU sets to a clock <=
desired clock. So we would do following
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
ret = clk_set_rate(cpu_clk, freqs.new * 1000);
if (ret)
pr_err("Could not change cpu clk rate\n");
freqs.new = clk_get_rate(cpu_clk);
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
Is it fine?
--
regards
Shiraz
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework
2011-01-19 9:39 ` Shiraz Hashim
@ 2011-01-19 9:53 ` Russell King - ARM Linux
2011-01-19 11:14 ` viresh kumar
0 siblings, 1 reply; 90+ messages in thread
From: Russell King - ARM Linux @ 2011-01-19 9:53 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 19, 2011 at 03:09:42PM +0530, Shiraz Hashim wrote:
> On second thought it should always be there irrespective of failures
> as in our case it may happen that eventually CPU sets to a clock <=
> desired clock. So we would do following
>
> cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> ret = clk_set_rate(cpu_clk, freqs.new * 1000);
> if (ret)
> pr_err("Could not change cpu clk rate\n");
> freqs.new = clk_get_rate(cpu_clk);
> cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
It probably makes more sense to do:
newfreq = clk_round_rate(cpu_clk, freqs.new * 1000);
if (newfreq < 0) {
pr_err("Invalid frequency blah blah\n");
return newfreq;
}
freqs.new = newfreq / 1000;
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
ret = clk_set_rate(cpu_clk, newfreq);
if (ret) {
pr_err("Could not change cpu clk rate\n");
freqs.new = clk_get_rate(cpu_clk) / 1000;
}
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
so that the prechange notifier gets the actual frequency to be switched
to too. In theory clk_set_rate() should only fail if the new frequency
couldn't be set for some reason.
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework
2011-01-19 9:53 ` Russell King - ARM Linux
@ 2011-01-19 11:14 ` viresh kumar
0 siblings, 0 replies; 90+ messages in thread
From: viresh kumar @ 2011-01-19 11:14 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 19, 2011 at 3:23 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Wed, Jan 19, 2011 at 03:09:42PM +0530, Shiraz Hashim wrote:
>> On second thought it should always be there irrespective of failures
>> as in our case it may happen that eventually CPU sets to a clock <=
>> desired clock. So we would do following
>>
>> cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
>> ret = clk_set_rate(cpu_clk, freqs.new * 1000);
>> if (ret)
>> ? ? ? ? pr_err("Could not change cpu clk rate\n");
>> freqs.new = clk_get_rate(cpu_clk);
>> cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
>
> It probably makes more sense to do:
>
> ? ? ? ?newfreq = clk_round_rate(cpu_clk, freqs.new * 1000);
> ? ? ? ?if (newfreq < 0) {
> ? ? ? ? ? ? ? ?pr_err("Invalid frequency blah blah\n");
> ? ? ? ? ? ? ? ?return newfreq;
> ? ? ? ?}
>
> ? ? ? ?freqs.new = newfreq / 1000;
> ? ? ? ?cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> ? ? ? ?ret = clk_set_rate(cpu_clk, newfreq);
> ? ? ? ?if (ret) {
> ? ? ? ? ? ? ? ?pr_err("Could not change cpu clk rate\n");
> ? ? ? ? ? ? ? ?freqs.new = clk_get_rate(cpu_clk) / 1000;
> ? ? ? ?}
> ? ? ? ?cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
>
> so that the prechange notifier gets the actual frequency to be switched
> to too. ?In theory clk_set_rate() should only fail if the new frequency
> couldn't be set for some reason.
>
Ok.
^ permalink raw reply [flat|nested] 90+ messages in thread
end of thread, other threads:[~2011-01-19 11:14 UTC | newest]
Thread overview: 90+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-01-18 7:11 [PATCH V4 00/62] Updating SPEAr Support Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 01/62] spear/vmalloc.h: Appending UL to VMALLOC_END Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 02/62] sp810 Fix: Switch to slow mode before sysctl_soft_reset Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 03/62] ST SPEAr: Padmux code Updated Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 04/62] ST SPEAr: Making clock functions more generic Viresh Kumar
2011-01-18 15:56 ` Russell King - ARM Linux
2011-01-19 4:03 ` viresh kumar
2011-01-18 7:11 ` [PATCH V4 05/62] ST SPEAr: Formalized timer support Viresh Kumar
2011-01-18 23:50 ` Jamie Iles
2011-01-19 3:53 ` viresh kumar
2011-01-18 7:11 ` [PATCH V4 06/62] ST SPEAr13XX: Adding machine specific header files Viresh Kumar
2011-01-18 16:00 ` Russell King - ARM Linux
2011-01-19 4:38 ` viresh kumar
2011-01-19 9:02 ` viresh kumar
2011-01-18 7:11 ` [PATCH V4 07/62] ST SPEAr13XX: Adding machine specific src files Viresh Kumar
2011-01-18 16:06 ` Russell King - ARM Linux
2011-01-19 6:03 ` Shiraz Hashim
2011-01-19 8:52 ` Russell King - ARM Linux
2011-01-19 9:20 ` Shiraz Hashim
2011-01-18 7:11 ` [PATCH V4 08/62] ST SPEAr: Adding support for SPEAr13xx SoC in spear generic plat/ Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 09/62] ST SPEAr13XX: Added compilation support in arch/arm/ Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 10/62] ST SPEAr13xx: Adding default config file Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 11/62] ST SPEAr: Adding support for CLCD on SPEAr3xx/6xx Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 12/62] ST SPEAr: Updating Clock Support Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 13/62] ST SPEAr: Adding Debugfs support on clock framework Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 14/62] ST SPEAr: Correcting SOC Config base address for spear320 Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 15/62] ST SPEAr: Adding PLGPIO driver for spear platform Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 17/62] ST SPEAr: Adding machine support for rtc-spear Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 18/62] ST SPEAr: adding support for synopsis i2c designware Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 19/62] ST SPEAr: Adding machine support for USB host Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 20/62] ST SPEAr: Adding machine support for keyboard Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 21/62] ST SPEAr: Added ARM PL061 GPIO Support on SPEAr13xx and modified resource size Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 22/62] ST SPEAr: Adding support for ST's PWM IP Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 23/62] ST SPEAr: Adding Watchdog support Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 24/62] ST SPEAr: Adding machine support for nand Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 25/62] ST SPEAr: Added PCIE host controller base driver support Viresh Kumar
2011-01-19 0:05 ` Russell King - ARM Linux
2011-01-19 4:17 ` viresh kumar
2011-01-18 7:11 ` [PATCH V4 26/62] ST SPEAr: Adding support for SSP PL022 Viresh Kumar
2011-01-18 16:18 ` Russell King - ARM Linux
2011-01-19 4:16 ` viresh kumar
2011-01-18 7:11 ` [PATCH V4 27/62] ST SPEAr: Adding support for SDHCI (SDIO) Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 28/62] ST SPEAr: Changing resource size of amba devices to SZ_4K Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 29/62] ST SPEAr: Replacing SIZE macro's with actual required size Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 30/62] SPEAr: defines base addresses as ulong Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 31/62] ST SPEAr: Adding miscellaneous devices Viresh Kumar
2011-01-18 7:11 ` [PATCH V4 32/62] ST SPEAr 13xx : Adding support for SPEAr1310 Viresh Kumar
2011-01-19 0:09 ` Jamie Iles
2011-01-19 4:39 ` viresh kumar
2011-01-19 6:40 ` viresh kumar
2011-01-19 8:29 ` Jamie Iles
2011-01-18 7:12 ` [PATCH V4 33/62] SPEAr320: Adding support for CAN Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 34/62] ST SPEAr: Adding support for DDR in clock framework Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 35/62] ST SPEAr : EMI (Extrenal Memory Interface) controller driver Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 36/62] SPEAr Clock Framework: Adding support for PLL frequency change Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 37/62] SPEAr Power Management: Added the support for Standby mode Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 38/62] SPEAr CPU freq: Adding support for CPU Freq framework Viresh Kumar
2011-01-19 0:20 ` Jamie Iles
2011-01-19 2:13 ` deepaksi
2011-01-19 8:35 ` Jamie Iles
2011-01-19 9:00 ` Shiraz Hashim
2011-01-19 9:39 ` Shiraz Hashim
2011-01-19 9:53 ` Russell King - ARM Linux
2011-01-19 11:14 ` viresh kumar
2011-01-18 7:12 ` [PATCH V4 39/62] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 40/62] ST SPEAr: replace readl, writel with readl_relaxed, writel_relaxed in uncompress.h Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 41/62] ST SPEAr13xx: add L2 cache support Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 42/62] ST SPEAr13xx: Modified static mappings Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 43/62] SPEAr1310: Adding Static Mapping for RAS Area Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 44/62] SPEAr: Adding and Updating Clock definitions Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 45/62] SPEAr : Pad multiplexing handling modified Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 46/62] SPEAr13xx : Fixed part devices in SPEAr13xx addded to the generic implementation Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 47/62] SPEAr : Updating pad multiplexing support Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 48/62] ST SPEAr3xx: Passing pmx devices address from machine *.c files Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 49/62] ST SPEAr Clock Framework: Updating for single image solution Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 50/62] SPEAr3xx: Make local structures static Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 51/62] SPEAR3xx: Rename register/irq defines to remove naming conflicts Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 52/62] SPEAr3xx: Rework pmx_dev code to remove conflicts Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 53/62] SPEAr3xx: Rework KConfig to allow all boards to be compiled in Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 54/62] SPEAr3xx: Replace defconfigs with single unified defconfig Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 55/62] ST SPEAr: Appending spear3** with global structures Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 56/62] ST SPEAr3xx: Updating plgpio and emi source to make it compliant with single image strategy Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 57/62] SPEAr6xx: Rework Kconfig for single image solution Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 58/62] ST SPEAR6xx: renaming spear600_defconfig as spear6xx_defconfig Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 59/62] ST SPEAr13xx: Pass default padmux settings as parameter to spear13**_init routine Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 60/62] ST SPEAr: Adding devices & clocks Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 61/62] ST SPEAr: Adding information in Documentation/ and MAINTAINERS Viresh Kumar
2011-01-18 7:12 ` [PATCH V4 62/62] ST SPEAr: Updating defconfigs Viresh Kumar
2011-01-18 15:53 ` [PATCH V4 00/62] Updating SPEAr Support Russell King - ARM Linux
2011-01-19 3:49 ` viresh kumar
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