[PATCH 0/4] Add Mailbox nodes for TI K3 AM65x & J721E SoCs

[PATCH 0/4] Add Mailbox nodes for TI K3 AM65x & J721E SoCs

[Suman Anna]

Hi Tero,

The following series adds the Mailbox DT nodes and the sub-mailboxes
used to communicate between the main MPU processor running Linux and
the various R5F and DSP remote processors present on the TI K3 AM65x
and J721E SoC families. Patches are based on v5.3-rc1 + the HwSpinlock
DT node series [1], and are intended for the 5.4 merge window. 

The bindings and driver support for the same have already been merged
in v5.3-rc1. Functionality is verified using a out-of-tree unit-test
module and some additional loopback test nodes available here [2] for
reference.

regards
Suman

[1] https://patchwork.kernel.org/cover/11053311/
[2] https://github.com/sumananna/mailbox/commits/mbox/test/5.3-rc1-k3

Suman Anna (4):
  arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs
  arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs
    & DSPs

 arch/arm64/boot/dts/ti/k3-am65-main.dtsi  | 120 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 158 ++++++++++++++++++++++
 2 files changed, 278 insertions(+)

-- 
2.22.0

[PATCH 0/4] Add Mailbox nodes for TI K3 AM65x & J721E SoCs

[Suman Anna]

Hi Tero,

The following series adds the Mailbox DT nodes and the sub-mailboxes
used to communicate between the main MPU processor running Linux and
the various R5F and DSP remote processors present on the TI K3 AM65x
and J721E SoC families. Patches are based on v5.3-rc1 + the HwSpinlock
DT node series [1], and are intended for the 5.4 merge window. 

The bindings and driver support for the same have already been merged
in v5.3-rc1. Functionality is verified using a out-of-tree unit-test
module and some additional loopback test nodes available here [2] for
reference.

regards
Suman

[1] https://patchwork.kernel.org/cover/11053311/
[2] https://github.com/sumananna/mailbox/commits/mbox/test/5.3-rc1-k3

Suman Anna (4):
  arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs
  arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs
    & DSPs

 arch/arm64/boot/dts/ti/k3-am65-main.dtsi  | 120 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 158 ++++++++++++++++++++++
 2 files changed, 278 insertions(+)

-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

[Suman Anna]

The AM65x Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.

Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.

NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A53
GIC will need to be be added later on when some sub-mailbox
child nodes are added.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 8413e80f9d3a..0b3ea2a871ee 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -419,6 +419,114 @@
 			reg = <0x00 0x30e00000 0x00 0x1000>;
 			#hwlock-cells = <1>;
 		};
+
+		mailbox0_cluster0: mailbox@31f80000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f80000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster1: mailbox@31f81000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f81000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster2: mailbox@31f82000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f82000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster3: mailbox@31f83000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f83000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster4: mailbox@31f84000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f84000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster5: mailbox@31f85000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f85000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster6: mailbox@31f86000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f86000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster7: mailbox@31f87000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f87000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster8: mailbox@31f88000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f88000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster9: mailbox@31f89000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f89000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster10: mailbox@31f8a000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8a000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster11: mailbox@31f8b000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8b000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
 	};
 
 	main_gpio0:  main_gpio0@600000 {
-- 
2.22.0

[PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

[Suman Anna]

The AM65x Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.

Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.

NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A53
GIC will need to be be added later on when some sub-mailbox
child nodes are added.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 8413e80f9d3a..0b3ea2a871ee 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -419,6 +419,114 @@
 			reg = <0x00 0x30e00000 0x00 0x1000>;
 			#hwlock-cells = <1>;
 		};
+
+		mailbox0_cluster0: mailbox@31f80000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f80000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster1: mailbox@31f81000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f81000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster2: mailbox@31f82000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f82000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster3: mailbox@31f83000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f83000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster4: mailbox@31f84000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f84000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster5: mailbox@31f85000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f85000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster6: mailbox@31f86000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f86000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster7: mailbox@31f87000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f87000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster8: mailbox@31f88000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f88000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster9: mailbox@31f89000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f89000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster10: mailbox@31f8a000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8a000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster11: mailbox@31f8b000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8b000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
 	};
 
 	main_gpio0:  main_gpio0@600000 {
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between
MPU and the two R5F remote processors present in the MCU domain.
The parent mailbox cluster nodes are enabled and the interrupts
associated with the Mailbox Cluster User interrupt used by the
sub-mailbox nodes are also added. The GIC_SPI interrupt to be
used is dynamically allocated and managed by the System Firmware
through the ti-sci-intr irqchip driver.

The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI RTOS IPC software packages. The
Cortex R5F processor sub-system is assumed to be running in Split
mode, so a sub-mailbox node is used by each of the R5F cores. Only
the sub-mailbox node from cluster 0 is used in case of Lockstep
mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 0b3ea2a871ee..317563c995b1 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -426,7 +426,13 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&intr_main_navss>;
+			interrupts = <164 0>;
+
+			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+				ti,mbox-tx = <1 0 0>;
+				ti,mbox-rx = <0 0 0>;
+			};
 		};
 
 		mailbox0_cluster1: mailbox@31f81000 {
@@ -435,7 +441,13 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&intr_main_navss>;
+			interrupts = <165 0>;
+
+			mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+				ti,mbox-tx = <1 0 0>;
+				ti,mbox-rx = <0 0 0>;
+			};
 		};
 
 		mailbox0_cluster2: mailbox@31f82000 {
-- 
2.22.0

[PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between
MPU and the two R5F remote processors present in the MCU domain.
The parent mailbox cluster nodes are enabled and the interrupts
associated with the Mailbox Cluster User interrupt used by the
sub-mailbox nodes are also added. The GIC_SPI interrupt to be
used is dynamically allocated and managed by the System Firmware
through the ti-sci-intr irqchip driver.

The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI RTOS IPC software packages. The
Cortex R5F processor sub-system is assumed to be running in Split
mode, so a sub-mailbox node is used by each of the R5F cores. Only
the sub-mailbox node from cluster 0 is used in case of Lockstep
mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 0b3ea2a871ee..317563c995b1 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -426,7 +426,13 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&intr_main_navss>;
+			interrupts = <164 0>;
+
+			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+				ti,mbox-tx = <1 0 0>;
+				ti,mbox-rx = <0 0 0>;
+			};
 		};
 
 		mailbox0_cluster1: mailbox@31f81000 {
@@ -435,7 +441,13 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&intr_main_navss>;
+			interrupts = <165 0>;
+
+			mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+				ti,mbox-tx = <1 0 0>;
+				ti,mbox-rx = <0 0 0>;
+			};
 		};
 
 		mailbox0_cluster2: mailbox@31f82000 {
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes

[Suman Anna]

The J721E Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.

Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.

NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A72
GIC will need to be be added later on when some sub-mailbox
child nodes are added.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 108 ++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index a2e031f7d88e..319d423b3440 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -95,6 +95,114 @@
 			reg = <0x00 0x30e00000 0x00 0x1000>;
 			#hwlock-cells = <1>;
 		};
+
+		mailbox0_cluster0: mailbox@31f80000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f80000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster1: mailbox@31f81000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f81000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster2: mailbox@31f82000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f82000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster3: mailbox@31f83000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f83000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster4: mailbox@31f84000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f84000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster5: mailbox@31f85000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f85000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster6: mailbox@31f86000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f86000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster7: mailbox@31f87000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f87000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster8: mailbox@31f88000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f88000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster9: mailbox@31f89000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f89000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster10: mailbox@31f8a000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8a000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster11: mailbox@31f8b000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8b000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
 	};
 
 	secure_proxy_main: mailbox@32c00000 {
-- 
2.22.0

[PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes

[Suman Anna]

The J721E Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.

Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.

NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A72
GIC will need to be be added later on when some sub-mailbox
child nodes are added.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 108 ++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index a2e031f7d88e..319d423b3440 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -95,6 +95,114 @@
 			reg = <0x00 0x30e00000 0x00 0x1000>;
 			#hwlock-cells = <1>;
 		};
+
+		mailbox0_cluster0: mailbox@31f80000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f80000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster1: mailbox@31f81000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f81000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster2: mailbox@31f82000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f82000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster3: mailbox@31f83000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f83000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster4: mailbox@31f84000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f84000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster5: mailbox@31f85000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f85000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster6: mailbox@31f86000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f86000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster7: mailbox@31f87000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f87000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster8: mailbox@31f88000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f88000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster9: mailbox@31f89000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f89000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster10: mailbox@31f8a000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8a000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster11: mailbox@31f8b000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8b000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
 	};
 
 	secure_proxy_main: mailbox@32c00000 {
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 4/4] arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs & DSPs

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J721E SoCs. These include the
R5F remote processors in the dual-R5F cluster (MCU_R5FSS0) in the MCU
domain and the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the
MAIN domain; the two C66x DSP remote processors and the single C71x DSP
remote processor in the MAIN domain. The parent mailbox cluster nodes
are also enabled.

The sub-mailbox nodes utilize the System Mailbox clusters 0 through 4.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI RTOS IPC software packages. The R5F
processor sub-systems are assumed to be running in Split mode, so a
sub-mailbox node is used by each of the R5F cores. The sub-mailbox node
for the first R5F core in each cluster is used in case of Lockstep mode.

NOTE:
The GIC_SPI interrupts to be used are dynamically allocated and managed
by the System Firmware through the ti-sci-intr irqchip driver. So, only
valid interrupts (each cluster's User 0 IRQ output) that are used by the
sub-mailbox devices are enabled. This is done to minimize the number of
NavSS Interrupt Router outputs utilized.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 60 +++++++++++++++++++++--
 1 file changed, 55 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 319d423b3440..2985c73154fd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -102,7 +102,18 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <214 0>;
+
+			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
+
+			mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+				ti,mbox-rx = <2 0 0>;
+				ti,mbox-tx = <3 0 0>;
+			};
 		};
 
 		mailbox0_cluster1: mailbox@31f81000 {
@@ -111,7 +122,18 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <215 0>;
+
+			mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
+
+			mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+				ti,mbox-rx = <2 0 0>;
+				ti,mbox-tx = <3 0 0>;
+			};
 		};
 
 		mailbox0_cluster2: mailbox@31f82000 {
@@ -120,7 +142,18 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <216 0>;
+
+			mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
+
+			mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+				ti,mbox-rx = <2 0 0>;
+				ti,mbox-tx = <3 0 0>;
+			};
 		};
 
 		mailbox0_cluster3: mailbox@31f83000 {
@@ -129,7 +162,18 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <217 0>;
+
+			mbox_c66_0: mbox-c66-0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
+
+			mbox_c66_1: mbox-c66-1 {
+				ti,mbox-rx = <2 0 0>;
+				ti,mbox-tx = <3 0 0>;
+			};
 		};
 
 		mailbox0_cluster4: mailbox@31f84000 {
@@ -138,7 +182,13 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <218 0>;
+
+			mbox_c71_0: mbox-c71-0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
 		};
 
 		mailbox0_cluster5: mailbox@31f85000 {
-- 
2.22.0

[PATCH 4/4] arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs & DSPs

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J721E SoCs. These include the
R5F remote processors in the dual-R5F cluster (MCU_R5FSS0) in the MCU
domain and the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the
MAIN domain; the two C66x DSP remote processors and the single C71x DSP
remote processor in the MAIN domain. The parent mailbox cluster nodes
are also enabled.

The sub-mailbox nodes utilize the System Mailbox clusters 0 through 4.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI RTOS IPC software packages. The R5F
processor sub-systems are assumed to be running in Split mode, so a
sub-mailbox node is used by each of the R5F cores. The sub-mailbox node
for the first R5F core in each cluster is used in case of Lockstep mode.

NOTE:
The GIC_SPI interrupts to be used are dynamically allocated and managed
by the System Firmware through the ti-sci-intr irqchip driver. So, only
valid interrupts (each cluster's User 0 IRQ output) that are used by the
sub-mailbox devices are enabled. This is done to minimize the number of
NavSS Interrupt Router outputs utilized.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 60 +++++++++++++++++++++--
 1 file changed, 55 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 319d423b3440..2985c73154fd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -102,7 +102,18 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <214 0>;
+
+			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
+
+			mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+				ti,mbox-rx = <2 0 0>;
+				ti,mbox-tx = <3 0 0>;
+			};
 		};
 
 		mailbox0_cluster1: mailbox@31f81000 {
@@ -111,7 +122,18 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <215 0>;
+
+			mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
+
+			mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+				ti,mbox-rx = <2 0 0>;
+				ti,mbox-tx = <3 0 0>;
+			};
 		};
 
 		mailbox0_cluster2: mailbox@31f82000 {
@@ -120,7 +142,18 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <216 0>;
+
+			mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
+
+			mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+				ti,mbox-rx = <2 0 0>;
+				ti,mbox-tx = <3 0 0>;
+			};
 		};
 
 		mailbox0_cluster3: mailbox@31f83000 {
@@ -129,7 +162,18 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <217 0>;
+
+			mbox_c66_0: mbox-c66-0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
+
+			mbox_c66_1: mbox-c66-1 {
+				ti,mbox-rx = <2 0 0>;
+				ti,mbox-tx = <3 0 0>;
+			};
 		};
 
 		mailbox0_cluster4: mailbox@31f84000 {
@@ -138,7 +182,13 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <16>;
-			status = "disabled";
+			interrupt-parent = <&main_navss_intr>;
+			interrupts = <218 0>;
+
+			mbox_c71_0: mbox-c71-0 {
+				ti,mbox-rx = <0 0 0>;
+				ti,mbox-tx = <1 0 0>;
+			};
 		};
 
 		mailbox0_cluster5: mailbox@31f85000 {
-- 
2.22.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

[Nishanth Menon]

On 15:20-20190722, Suman Anna wrote:
> The AM65x Main NavSS block contains a Mailbox IP instance with
> multiple clusters. Each cluster is equivalent to an Mailbox IP
> instance on OMAP platforms.
> 
> Add all the Mailbox clusters as their own nodes under the MAIN
> NavSS cbass_main_navss interconnect node instead of creating an
> almost empty parent node for the new K3 mailbox IP and the clusters
> as its child nodes. All these nodes are marked as disabled, and
> they need to be enabled along with the appropriate child nodes
> on a need basis.
> 
> NOTE:
> The NavSS only has a limited number of interrupts, so all the
> interrupts generated by a Mailbox IP are not added by default.
> Only the needed interrupts that are targeted towards the A53
> GIC will need to be be added later on when some sub-mailbox
> child nodes are added.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 8413e80f9d3a..0b3ea2a871ee 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -419,6 +419,114 @@
>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>  			#hwlock-cells = <1>;
>  		};
> +
> +		mailbox0_cluster0: mailbox@31f80000 {
> +			compatible = "ti,am654-mailbox";
> +			reg = <0x00 0x31f80000 0x00 0x200>;
> +			#mbox-cells = <1>;
> +			ti,mbox-num-users = <4>;
> +			ti,mbox-num-fifos = <16>;
> +			status = "disabled";

We don't use status="disabled" as default so far.


-- 
Regards,
Nishanth Menon

Re: [PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

[Nishanth Menon]

On 15:20-20190722, Suman Anna wrote:
> The AM65x Main NavSS block contains a Mailbox IP instance with
> multiple clusters. Each cluster is equivalent to an Mailbox IP
> instance on OMAP platforms.
> 
> Add all the Mailbox clusters as their own nodes under the MAIN
> NavSS cbass_main_navss interconnect node instead of creating an
> almost empty parent node for the new K3 mailbox IP and the clusters
> as its child nodes. All these nodes are marked as disabled, and
> they need to be enabled along with the appropriate child nodes
> on a need basis.
> 
> NOTE:
> The NavSS only has a limited number of interrupts, so all the
> interrupts generated by a Mailbox IP are not added by default.
> Only the needed interrupts that are targeted towards the A53
> GIC will need to be be added later on when some sub-mailbox
> child nodes are added.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 8413e80f9d3a..0b3ea2a871ee 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -419,6 +419,114 @@
>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>  			#hwlock-cells = <1>;
>  		};
> +
> +		mailbox0_cluster0: mailbox@31f80000 {
> +			compatible = "ti,am654-mailbox";
> +			reg = <0x00 0x31f80000 0x00 0x200>;
> +			#mbox-cells = <1>;
> +			ti,mbox-num-users = <4>;
> +			ti,mbox-num-fifos = <16>;
> +			status = "disabled";

We don't use status="disabled" as default so far.


-- 
Regards,
Nishanth Menon

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs

[Nishanth Menon]

On 15:20-20190722, Suman Anna wrote:
> Add the sub-mailbox nodes that are used to communicate between
> MPU and the two R5F remote processors present in the MCU domain.
> The parent mailbox cluster nodes are enabled and the interrupts
> associated with the Mailbox Cluster User interrupt used by the
> sub-mailbox nodes are also added. The GIC_SPI interrupt to be
> used is dynamically allocated and managed by the System Firmware
> through the ti-sci-intr irqchip driver.
> 
> The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
> These sub-mailbox nodes are added to match the hard-coded mailbox
> configuration used within the TI RTOS IPC software packages. The
> Cortex R5F processor sub-system is assumed to be running in Split
> mode, so a sub-mailbox node is used by each of the R5F cores. Only
> the sub-mailbox node from cluster 0 is used in case of Lockstep
> mode.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 0b3ea2a871ee..317563c995b1 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -426,7 +426,13 @@
>  			#mbox-cells = <1>;
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
> -			status = "disabled";
> +			interrupt-parent = <&intr_main_navss>;
> +			interrupts = <164 0>;
> +
> +			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
> +				ti,mbox-tx = <1 0 0>;
> +				ti,mbox-rx = <0 0 0>;
> +			};

Should'nt this rather be a board specific node? This is completely
dependent on the pre-defined communication scheme with R5F firmware?

>  		};
>  
>  		mailbox0_cluster1: mailbox@31f81000 {
> @@ -435,7 +441,13 @@
>  			#mbox-cells = <1>;
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
> -			status = "disabled";
> +			interrupt-parent = <&intr_main_navss>;
> +			interrupts = <165 0>;
> +
> +			mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
> +				ti,mbox-tx = <1 0 0>;
> +				ti,mbox-rx = <0 0 0>;
> +			};
>  		};
>  
>  		mailbox0_cluster2: mailbox@31f82000 {
> -- 
> 2.22.0
> 

-- 
Regards,
Nishanth Menon

Re: [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs

[Nishanth Menon]

On 15:20-20190722, Suman Anna wrote:
> Add the sub-mailbox nodes that are used to communicate between
> MPU and the two R5F remote processors present in the MCU domain.
> The parent mailbox cluster nodes are enabled and the interrupts
> associated with the Mailbox Cluster User interrupt used by the
> sub-mailbox nodes are also added. The GIC_SPI interrupt to be
> used is dynamically allocated and managed by the System Firmware
> through the ti-sci-intr irqchip driver.
> 
> The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
> These sub-mailbox nodes are added to match the hard-coded mailbox
> configuration used within the TI RTOS IPC software packages. The
> Cortex R5F processor sub-system is assumed to be running in Split
> mode, so a sub-mailbox node is used by each of the R5F cores. Only
> the sub-mailbox node from cluster 0 is used in case of Lockstep
> mode.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 0b3ea2a871ee..317563c995b1 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -426,7 +426,13 @@
>  			#mbox-cells = <1>;
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
> -			status = "disabled";
> +			interrupt-parent = <&intr_main_navss>;
> +			interrupts = <164 0>;
> +
> +			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
> +				ti,mbox-tx = <1 0 0>;
> +				ti,mbox-rx = <0 0 0>;
> +			};

Should'nt this rather be a board specific node? This is completely
dependent on the pre-defined communication scheme with R5F firmware?

>  		};
>  
>  		mailbox0_cluster1: mailbox@31f81000 {
> @@ -435,7 +441,13 @@
>  			#mbox-cells = <1>;
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
> -			status = "disabled";
> +			interrupt-parent = <&intr_main_navss>;
> +			interrupts = <165 0>;
> +
> +			mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
> +				ti,mbox-tx = <1 0 0>;
> +				ti,mbox-rx = <0 0 0>;
> +			};
>  		};
>  
>  		mailbox0_cluster2: mailbox@31f82000 {
> -- 
> 2.22.0
> 

-- 
Regards,
Nishanth Menon

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes

[Nishanth Menon]

On 15:20-20190722, Suman Anna wrote:
> The J721E Main NavSS block contains a Mailbox IP instance with
> multiple clusters. Each cluster is equivalent to an Mailbox IP
> instance on OMAP platforms.
> 
> Add all the Mailbox clusters as their own nodes under the MAIN
> NavSS cbass_main_navss interconnect node instead of creating an
> almost empty parent node for the new K3 mailbox IP and the clusters
> as its child nodes. All these nodes are marked as disabled, and
> they need to be enabled along with the appropriate child nodes
> on a need basis.
> 
> NOTE:
> The NavSS only has a limited number of interrupts, so all the
> interrupts generated by a Mailbox IP are not added by default.
> Only the needed interrupts that are targeted towards the A72
> GIC will need to be be added later on when some sub-mailbox
> child nodes are added.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 108 ++++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index a2e031f7d88e..319d423b3440 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -95,6 +95,114 @@
>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>  			#hwlock-cells = <1>;
>  		};
> +
> +		mailbox0_cluster0: mailbox@31f80000 {
> +			compatible = "ti,am654-mailbox";
> +			reg = <0x00 0x31f80000 0x00 0x200>;
> +			#mbox-cells = <1>;
> +			ti,mbox-num-users = <4>;
> +			ti,mbox-num-fifos = <16>;
> +			status = "disabled";

Please drop disabled.

-- 
Regards,
Nishanth Menon

Re: [PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes

[Nishanth Menon]

On 15:20-20190722, Suman Anna wrote:
> The J721E Main NavSS block contains a Mailbox IP instance with
> multiple clusters. Each cluster is equivalent to an Mailbox IP
> instance on OMAP platforms.
> 
> Add all the Mailbox clusters as their own nodes under the MAIN
> NavSS cbass_main_navss interconnect node instead of creating an
> almost empty parent node for the new K3 mailbox IP and the clusters
> as its child nodes. All these nodes are marked as disabled, and
> they need to be enabled along with the appropriate child nodes
> on a need basis.
> 
> NOTE:
> The NavSS only has a limited number of interrupts, so all the
> interrupts generated by a Mailbox IP are not added by default.
> Only the needed interrupts that are targeted towards the A72
> GIC will need to be be added later on when some sub-mailbox
> child nodes are added.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 108 ++++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index a2e031f7d88e..319d423b3440 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -95,6 +95,114 @@
>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>  			#hwlock-cells = <1>;
>  		};
> +
> +		mailbox0_cluster0: mailbox@31f80000 {
> +			compatible = "ti,am654-mailbox";
> +			reg = <0x00 0x31f80000 0x00 0x200>;
> +			#mbox-cells = <1>;
> +			ti,mbox-num-users = <4>;
> +			ti,mbox-num-fifos = <16>;
> +			status = "disabled";

Please drop disabled.

-- 
Regards,
Nishanth Menon

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

[Suman Anna]

Hi Nishanth,

On 7/23/19 6:35 AM, Nishanth Menon wrote:
> On 15:20-20190722, Suman Anna wrote:
>> The AM65x Main NavSS block contains a Mailbox IP instance with
>> multiple clusters. Each cluster is equivalent to an Mailbox IP
>> instance on OMAP platforms.
>>
>> Add all the Mailbox clusters as their own nodes under the MAIN
>> NavSS cbass_main_navss interconnect node instead of creating an
>> almost empty parent node for the new K3 mailbox IP and the clusters
>> as its child nodes. All these nodes are marked as disabled, and
>> they need to be enabled along with the appropriate child nodes
>> on a need basis.
>>
>> NOTE:
>> The NavSS only has a limited number of interrupts, so all the
>> interrupts generated by a Mailbox IP are not added by default.
>> Only the needed interrupts that are targeted towards the A53
>> GIC will need to be be added later on when some sub-mailbox
>> child nodes are added.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
>>  1 file changed, 108 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> index 8413e80f9d3a..0b3ea2a871ee 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> @@ -419,6 +419,114 @@
>>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>>  			#hwlock-cells = <1>;
>>  		};
>> +
>> +		mailbox0_cluster0: mailbox@31f80000 {
>> +			compatible = "ti,am654-mailbox";
>> +			reg = <0x00 0x31f80000 0x00 0x200>;
>> +			#mbox-cells = <1>;
>> +			ti,mbox-num-users = <4>;
>> +			ti,mbox-num-fifos = <16>;
>> +			status = "disabled";
> 
> We don't use status="disabled" as default so far.
> 

For the OMAP mailboxes, we do not want to enable just the cluster. A
cluster without any enabled sub-mailboxes or interrupts will fail the probe.

There are 12 clusters but we won't be enabling all clusters for the MPU
core running Linux. There are some clusters that are dedicated to
RTOS-to-RTOS IPC which we don't want to even probe on Linux. This patch
adds all the clusters, and the next patch enables only the clusters used
by Linux that have the proper sub-mailboxes and interrupts. Please see
the NOTE above for the reason why not all the 4 interrupts from each
cluster are added here.

regards
Suman

Re: [PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

[Suman Anna]

Hi Nishanth,

On 7/23/19 6:35 AM, Nishanth Menon wrote:
> On 15:20-20190722, Suman Anna wrote:
>> The AM65x Main NavSS block contains a Mailbox IP instance with
>> multiple clusters. Each cluster is equivalent to an Mailbox IP
>> instance on OMAP platforms.
>>
>> Add all the Mailbox clusters as their own nodes under the MAIN
>> NavSS cbass_main_navss interconnect node instead of creating an
>> almost empty parent node for the new K3 mailbox IP and the clusters
>> as its child nodes. All these nodes are marked as disabled, and
>> they need to be enabled along with the appropriate child nodes
>> on a need basis.
>>
>> NOTE:
>> The NavSS only has a limited number of interrupts, so all the
>> interrupts generated by a Mailbox IP are not added by default.
>> Only the needed interrupts that are targeted towards the A53
>> GIC will need to be be added later on when some sub-mailbox
>> child nodes are added.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
>>  1 file changed, 108 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> index 8413e80f9d3a..0b3ea2a871ee 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> @@ -419,6 +419,114 @@
>>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>>  			#hwlock-cells = <1>;
>>  		};
>> +
>> +		mailbox0_cluster0: mailbox@31f80000 {
>> +			compatible = "ti,am654-mailbox";
>> +			reg = <0x00 0x31f80000 0x00 0x200>;
>> +			#mbox-cells = <1>;
>> +			ti,mbox-num-users = <4>;
>> +			ti,mbox-num-fifos = <16>;
>> +			status = "disabled";
> 
> We don't use status="disabled" as default so far.
> 

For the OMAP mailboxes, we do not want to enable just the cluster. A
cluster without any enabled sub-mailboxes or interrupts will fail the probe.

There are 12 clusters but we won't be enabling all clusters for the MPU
core running Linux. There are some clusters that are dedicated to
RTOS-to-RTOS IPC which we don't want to even probe on Linux. This patch
adds all the clusters, and the next patch enables only the clusters used
by Linux that have the proper sub-mailboxes and interrupts. Please see
the NOTE above for the reason why not all the 4 interrupts from each
cluster are added here.

regards
Suman

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs

[Suman Anna]

Hi Nishanth,

On 7/23/19 6:37 AM, Nishanth Menon wrote:
> On 15:20-20190722, Suman Anna wrote:
>> Add the sub-mailbox nodes that are used to communicate between
>> MPU and the two R5F remote processors present in the MCU domain.
>> The parent mailbox cluster nodes are enabled and the interrupts
>> associated with the Mailbox Cluster User interrupt used by the
>> sub-mailbox nodes are also added. The GIC_SPI interrupt to be
>> used is dynamically allocated and managed by the System Firmware
>> through the ti-sci-intr irqchip driver.
>>
>> The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
>> These sub-mailbox nodes are added to match the hard-coded mailbox
>> configuration used within the TI RTOS IPC software packages. The
>> Cortex R5F processor sub-system is assumed to be running in Split
>> mode, so a sub-mailbox node is used by each of the R5F cores. Only
>> the sub-mailbox node from cluster 0 is used in case of Lockstep
>> mode.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
>>  1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> index 0b3ea2a871ee..317563c995b1 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> @@ -426,7 +426,13 @@
>>  			#mbox-cells = <1>;
>>  			ti,mbox-num-users = <4>;
>>  			ti,mbox-num-fifos = <16>;
>> -			status = "disabled";
>> +			interrupt-parent = <&intr_main_navss>;
>> +			interrupts = <164 0>;
>> +
>> +			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
>> +				ti,mbox-tx = <1 0 0>;
>> +				ti,mbox-rx = <0 0 0>;
>> +			};
> 
> Should'nt this rather be a board specific node? This is completely
> dependent on the pre-defined communication scheme with R5F firmware?

These are the default assignments we are using and inherited by all
derivative boards leveraging the TI RTOS-side firmwares/stacks.
Otherwise, these sub-mailboxes have to be added to every board dts file.
One can always overwrite the values or disable the nodes if they chose a
different configuration.

regards
Suman

> 
>>  		};
>>  
>>  		mailbox0_cluster1: mailbox@31f81000 {
>> @@ -435,7 +441,13 @@
>>  			#mbox-cells = <1>;
>>  			ti,mbox-num-users = <4>;
>>  			ti,mbox-num-fifos = <16>;
>> -			status = "disabled";
>> +			interrupt-parent = <&intr_main_navss>;
>> +			interrupts = <165 0>;
>> +
>> +			mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
>> +				ti,mbox-tx = <1 0 0>;
>> +				ti,mbox-rx = <0 0 0>;
>> +			};
>>  		};
>>  
>>  		mailbox0_cluster2: mailbox@31f82000 {
>> -- 
>> 2.22.0
>>
> 

Re: [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs

[Suman Anna]

Hi Nishanth,

On 7/23/19 6:37 AM, Nishanth Menon wrote:
> On 15:20-20190722, Suman Anna wrote:
>> Add the sub-mailbox nodes that are used to communicate between
>> MPU and the two R5F remote processors present in the MCU domain.
>> The parent mailbox cluster nodes are enabled and the interrupts
>> associated with the Mailbox Cluster User interrupt used by the
>> sub-mailbox nodes are also added. The GIC_SPI interrupt to be
>> used is dynamically allocated and managed by the System Firmware
>> through the ti-sci-intr irqchip driver.
>>
>> The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
>> These sub-mailbox nodes are added to match the hard-coded mailbox
>> configuration used within the TI RTOS IPC software packages. The
>> Cortex R5F processor sub-system is assumed to be running in Split
>> mode, so a sub-mailbox node is used by each of the R5F cores. Only
>> the sub-mailbox node from cluster 0 is used in case of Lockstep
>> mode.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
>>  1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> index 0b3ea2a871ee..317563c995b1 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> @@ -426,7 +426,13 @@
>>  			#mbox-cells = <1>;
>>  			ti,mbox-num-users = <4>;
>>  			ti,mbox-num-fifos = <16>;
>> -			status = "disabled";
>> +			interrupt-parent = <&intr_main_navss>;
>> +			interrupts = <164 0>;
>> +
>> +			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
>> +				ti,mbox-tx = <1 0 0>;
>> +				ti,mbox-rx = <0 0 0>;
>> +			};
> 
> Should'nt this rather be a board specific node? This is completely
> dependent on the pre-defined communication scheme with R5F firmware?

These are the default assignments we are using and inherited by all
derivative boards leveraging the TI RTOS-side firmwares/stacks.
Otherwise, these sub-mailboxes have to be added to every board dts file.
One can always overwrite the values or disable the nodes if they chose a
different configuration.

regards
Suman

> 
>>  		};
>>  
>>  		mailbox0_cluster1: mailbox@31f81000 {
>> @@ -435,7 +441,13 @@
>>  			#mbox-cells = <1>;
>>  			ti,mbox-num-users = <4>;
>>  			ti,mbox-num-fifos = <16>;
>> -			status = "disabled";
>> +			interrupt-parent = <&intr_main_navss>;
>> +			interrupts = <165 0>;
>> +
>> +			mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
>> +				ti,mbox-tx = <1 0 0>;
>> +				ti,mbox-rx = <0 0 0>;
>> +			};
>>  		};
>>  
>>  		mailbox0_cluster2: mailbox@31f82000 {
>> -- 
>> 2.22.0
>>
> 


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes

[Suman Anna]

On 7/23/19 6:37 AM, Nishanth Menon wrote:
> On 15:20-20190722, Suman Anna wrote:
>> The J721E Main NavSS block contains a Mailbox IP instance with
>> multiple clusters. Each cluster is equivalent to an Mailbox IP
>> instance on OMAP platforms.
>>
>> Add all the Mailbox clusters as their own nodes under the MAIN
>> NavSS cbass_main_navss interconnect node instead of creating an
>> almost empty parent node for the new K3 mailbox IP and the clusters
>> as its child nodes. All these nodes are marked as disabled, and
>> they need to be enabled along with the appropriate child nodes
>> on a need basis.
>>
>> NOTE:
>> The NavSS only has a limited number of interrupts, so all the
>> interrupts generated by a Mailbox IP are not added by default.
>> Only the needed interrupts that are targeted towards the A72
>> GIC will need to be be added later on when some sub-mailbox
>> child nodes are added.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 108 ++++++++++++++++++++++
>>  1 file changed, 108 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index a2e031f7d88e..319d423b3440 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -95,6 +95,114 @@
>>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>>  			#hwlock-cells = <1>;
>>  		};
>> +
>> +		mailbox0_cluster0: mailbox@31f80000 {
>> +			compatible = "ti,am654-mailbox";
>> +			reg = <0x00 0x31f80000 0x00 0x200>;
>> +			#mbox-cells = <1>;
>> +			ti,mbox-num-users = <4>;
>> +			ti,mbox-num-fifos = <16>;
>> +			status = "disabled";
> 
> Please drop disabled.

Same comment as on the AM65x patch (patch 1).

regards
Suman

Re: [PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes

[Suman Anna]

On 7/23/19 6:37 AM, Nishanth Menon wrote:
> On 15:20-20190722, Suman Anna wrote:
>> The J721E Main NavSS block contains a Mailbox IP instance with
>> multiple clusters. Each cluster is equivalent to an Mailbox IP
>> instance on OMAP platforms.
>>
>> Add all the Mailbox clusters as their own nodes under the MAIN
>> NavSS cbass_main_navss interconnect node instead of creating an
>> almost empty parent node for the new K3 mailbox IP and the clusters
>> as its child nodes. All these nodes are marked as disabled, and
>> they need to be enabled along with the appropriate child nodes
>> on a need basis.
>>
>> NOTE:
>> The NavSS only has a limited number of interrupts, so all the
>> interrupts generated by a Mailbox IP are not added by default.
>> Only the needed interrupts that are targeted towards the A72
>> GIC will need to be be added later on when some sub-mailbox
>> child nodes are added.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 108 ++++++++++++++++++++++
>>  1 file changed, 108 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index a2e031f7d88e..319d423b3440 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -95,6 +95,114 @@
>>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>>  			#hwlock-cells = <1>;
>>  		};
>> +
>> +		mailbox0_cluster0: mailbox@31f80000 {
>> +			compatible = "ti,am654-mailbox";
>> +			reg = <0x00 0x31f80000 0x00 0x200>;
>> +			#mbox-cells = <1>;
>> +			ti,mbox-num-users = <4>;
>> +			ti,mbox-num-fifos = <16>;
>> +			status = "disabled";
> 
> Please drop disabled.

Same comment as on the AM65x patch (patch 1).

regards
Suman

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

[Nishanth Menon]

On 12:50-20190723, Suman Anna wrote:
> For the OMAP mailboxes, we do not want to enable just the cluster. A
> cluster without any enabled sub-mailboxes or interrupts will fail the probe.
> 
> There are 12 clusters but we won't be enabling all clusters for the MPU
> core running Linux. There are some clusters that are dedicated to
> RTOS-to-RTOS IPC which we don't want to even probe on Linux. This patch
> adds all the clusters, and the next patch enables only the clusters used
> by Linux that have the proper sub-mailboxes and interrupts. Please see
> the NOTE above for the reason why not all the 4 interrupts from each
> cluster are added here.

Please follow the example of uart and disable in the board file. Please
see existing code when posting new nodes.

-- 
Regards,
Nishanth Menon

Re: [PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

[Nishanth Menon]

On 12:50-20190723, Suman Anna wrote:
> For the OMAP mailboxes, we do not want to enable just the cluster. A
> cluster without any enabled sub-mailboxes or interrupts will fail the probe.
> 
> There are 12 clusters but we won't be enabling all clusters for the MPU
> core running Linux. There are some clusters that are dedicated to
> RTOS-to-RTOS IPC which we don't want to even probe on Linux. This patch
> adds all the clusters, and the next patch enables only the clusters used
> by Linux that have the proper sub-mailboxes and interrupts. Please see
> the NOTE above for the reason why not all the 4 interrupts from each
> cluster are added here.

Please follow the example of uart and disable in the board file. Please
see existing code when posting new nodes.

-- 
Regards,
Nishanth Menon

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs

[Nishanth Menon]

On 12:54-20190723, Suman Anna wrote:
> Hi Nishanth,
> 
> On 7/23/19 6:37 AM, Nishanth Menon wrote:
> > On 15:20-20190722, Suman Anna wrote:
> >> Add the sub-mailbox nodes that are used to communicate between
> >> MPU and the two R5F remote processors present in the MCU domain.
> >> The parent mailbox cluster nodes are enabled and the interrupts
> >> associated with the Mailbox Cluster User interrupt used by the
> >> sub-mailbox nodes are also added. The GIC_SPI interrupt to be
> >> used is dynamically allocated and managed by the System Firmware
> >> through the ti-sci-intr irqchip driver.
> >>
> >> The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
> >> These sub-mailbox nodes are added to match the hard-coded mailbox
> >> configuration used within the TI RTOS IPC software packages. The
> >> Cortex R5F processor sub-system is assumed to be running in Split
> >> mode, so a sub-mailbox node is used by each of the R5F cores. Only
> >> the sub-mailbox node from cluster 0 is used in case of Lockstep
> >> mode.
> >>
> >> Signed-off-by: Suman Anna <s-anna@ti.com>
> >> ---
> >>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
> >>  1 file changed, 14 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> >> index 0b3ea2a871ee..317563c995b1 100644
> >> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> >> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> >> @@ -426,7 +426,13 @@
> >>  			#mbox-cells = <1>;
> >>  			ti,mbox-num-users = <4>;
> >>  			ti,mbox-num-fifos = <16>;
> >> -			status = "disabled";
> >> +			interrupt-parent = <&intr_main_navss>;
> >> +			interrupts = <164 0>;
> >> +
> >> +			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
> >> +				ti,mbox-tx = <1 0 0>;
> >> +				ti,mbox-rx = <0 0 0>;
> >> +			};
> > 
> > Should'nt this rather be a board specific node? This is completely
> > dependent on the pre-defined communication scheme with R5F firmware?
> 
> These are the default assignments we are using and inherited by all
> derivative boards leveraging the TI RTOS-side firmwares/stacks.
> Otherwise, these sub-mailboxes have to be added to every board dts file.
> One can always overwrite the values or disable the nodes if they chose a
> different configuration.


This looks strongly  like a case that is to be described in board.dts
files.

-- 
Regards,
Nishanth Menon

Re: [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs

[Nishanth Menon]

On 12:54-20190723, Suman Anna wrote:
> Hi Nishanth,
> 
> On 7/23/19 6:37 AM, Nishanth Menon wrote:
> > On 15:20-20190722, Suman Anna wrote:
> >> Add the sub-mailbox nodes that are used to communicate between
> >> MPU and the two R5F remote processors present in the MCU domain.
> >> The parent mailbox cluster nodes are enabled and the interrupts
> >> associated with the Mailbox Cluster User interrupt used by the
> >> sub-mailbox nodes are also added. The GIC_SPI interrupt to be
> >> used is dynamically allocated and managed by the System Firmware
> >> through the ti-sci-intr irqchip driver.
> >>
> >> The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
> >> These sub-mailbox nodes are added to match the hard-coded mailbox
> >> configuration used within the TI RTOS IPC software packages. The
> >> Cortex R5F processor sub-system is assumed to be running in Split
> >> mode, so a sub-mailbox node is used by each of the R5F cores. Only
> >> the sub-mailbox node from cluster 0 is used in case of Lockstep
> >> mode.
> >>
> >> Signed-off-by: Suman Anna <s-anna@ti.com>
> >> ---
> >>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
> >>  1 file changed, 14 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> >> index 0b3ea2a871ee..317563c995b1 100644
> >> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> >> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> >> @@ -426,7 +426,13 @@
> >>  			#mbox-cells = <1>;
> >>  			ti,mbox-num-users = <4>;
> >>  			ti,mbox-num-fifos = <16>;
> >> -			status = "disabled";
> >> +			interrupt-parent = <&intr_main_navss>;
> >> +			interrupts = <164 0>;
> >> +
> >> +			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
> >> +				ti,mbox-tx = <1 0 0>;
> >> +				ti,mbox-rx = <0 0 0>;
> >> +			};
> > 
> > Should'nt this rather be a board specific node? This is completely
> > dependent on the pre-defined communication scheme with R5F firmware?
> 
> These are the default assignments we are using and inherited by all
> derivative boards leveraging the TI RTOS-side firmwares/stacks.
> Otherwise, these sub-mailboxes have to be added to every board dts file.
> One can always overwrite the values or disable the nodes if they chose a
> different configuration.


This looks strongly  like a case that is to be described in board.dts
files.

-- 
Regards,
Nishanth Menon

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel