* [PATCH] drm/amdgpu: setup the shared and private apertures on gfx9
@ 2017-12-08 20:10 Alex Deucher
[not found] ` <20171208201046.14655-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2017-12-08 20:10 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Same as previous asics. This was not yet set for gfx9.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 ++++++++++++-----
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++++
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3fd13b77e71e..7564f87b084e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1529,11 +1529,18 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
for (i = 0; i < 16; i++) {
soc15_grbm_select(adev, 0, 0, 0, i);
/* CP and shaders */
- tmp = 0;
- tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
- SH_MEM_ALIGNMENT_MODE_UNALIGNED);
- WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
- WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
+ if (i == 0) {
+ tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
+ SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+ WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
+ WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
+ } else {
+ tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
+ SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+ WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
+ tmp = adev->mc.shared_aperture_start >> 48;
+ WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
+ }
}
soc15_grbm_select(adev, 0, 0, 0, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 695e0eada1cd..dbfb746a390c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -497,6 +497,14 @@ static int gmc_v9_0_early_init(void *handle)
gmc_v9_0_set_gart_funcs(adev);
gmc_v9_0_set_irq_funcs(adev);
+ adev->mc.shared_aperture_start = 0x2000000000000000ULL;
+ adev->mc.shared_aperture_end =
+ adev->mc.shared_aperture_start + (4ULL << 30) - 1;
+ adev->mc.private_aperture_start =
+ adev->mc.shared_aperture_end + 1;
+ adev->mc.private_aperture_end =
+ adev->mc.private_aperture_start + (4ULL << 30) - 1;
+
return 0;
}
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread[parent not found: <20171208201046.14655-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: setup the shared and private apertures on gfx9 [not found] ` <20171208201046.14655-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org> @ 2017-12-14 15:25 ` Alex Deucher [not found] ` <CADnq5_MyzRY1EivgbBehFRL_FJnQmCbV1VJZqvR4gVhVmGTSzA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2017-12-29 19:23 ` Felix Kuehling 1 sibling, 1 reply; 4+ messages in thread From: Alex Deucher @ 2017-12-14 15:25 UTC (permalink / raw) To: amd-gfx list; +Cc: Alex Deucher On Fri, Dec 8, 2017 at 3:10 PM, Alex Deucher <alexdeucher@gmail.com> wrote: > Same as previous asics. This was not yet set for gfx9. Ping? > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 ++++++++++++----- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++++ > 2 files changed, 20 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 3fd13b77e71e..7564f87b084e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1529,11 +1529,18 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) > for (i = 0; i < 16; i++) { > soc15_grbm_select(adev, 0, 0, 0, i); > /* CP and shaders */ > - tmp = 0; > - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, > - SH_MEM_ALIGNMENT_MODE_UNALIGNED); > - WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); > - WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); > + if (i == 0) { > + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, > + SH_MEM_ALIGNMENT_MODE_UNALIGNED); > + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); > + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); > + } else { > + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, > + SH_MEM_ALIGNMENT_MODE_UNALIGNED); > + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); > + tmp = adev->mc.shared_aperture_start >> 48; > + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); > + } > } > soc15_grbm_select(adev, 0, 0, 0, 0); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 695e0eada1cd..dbfb746a390c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -497,6 +497,14 @@ static int gmc_v9_0_early_init(void *handle) > gmc_v9_0_set_gart_funcs(adev); > gmc_v9_0_set_irq_funcs(adev); > > + adev->mc.shared_aperture_start = 0x2000000000000000ULL; > + adev->mc.shared_aperture_end = > + adev->mc.shared_aperture_start + (4ULL << 30) - 1; > + adev->mc.private_aperture_start = > + adev->mc.shared_aperture_end + 1; > + adev->mc.private_aperture_end = > + adev->mc.private_aperture_start + (4ULL << 30) - 1; > + > return 0; > } > > -- > 2.13.6 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
[parent not found: <CADnq5_MyzRY1EivgbBehFRL_FJnQmCbV1VJZqvR4gVhVmGTSzA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: setup the shared and private apertures on gfx9 [not found] ` <CADnq5_MyzRY1EivgbBehFRL_FJnQmCbV1VJZqvR4gVhVmGTSzA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2017-12-15 10:04 ` Christian König 0 siblings, 0 replies; 4+ messages in thread From: Christian König @ 2017-12-15 10:04 UTC (permalink / raw) To: Alex Deucher, amd-gfx list; +Cc: Alex Deucher Am 14.12.2017 um 16:25 schrieb Alex Deucher: > On Fri, Dec 8, 2017 at 3:10 PM, Alex Deucher <alexdeucher@gmail.com> wrote: >> Same as previous asics. This was not yet set for gfx9. > Ping? Acked-by: Christian König <christian.koenig@amd.com> > >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 ++++++++++++----- >> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++++ >> 2 files changed, 20 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> index 3fd13b77e71e..7564f87b084e 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> @@ -1529,11 +1529,18 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) >> for (i = 0; i < 16; i++) { >> soc15_grbm_select(adev, 0, 0, 0, i); >> /* CP and shaders */ >> - tmp = 0; >> - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, >> - SH_MEM_ALIGNMENT_MODE_UNALIGNED); >> - WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); >> - WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); >> + if (i == 0) { >> + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, >> + SH_MEM_ALIGNMENT_MODE_UNALIGNED); >> + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); >> + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); >> + } else { >> + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, >> + SH_MEM_ALIGNMENT_MODE_UNALIGNED); >> + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); >> + tmp = adev->mc.shared_aperture_start >> 48; >> + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); >> + } >> } >> soc15_grbm_select(adev, 0, 0, 0, 0); >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> index 695e0eada1cd..dbfb746a390c 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> @@ -497,6 +497,14 @@ static int gmc_v9_0_early_init(void *handle) >> gmc_v9_0_set_gart_funcs(adev); >> gmc_v9_0_set_irq_funcs(adev); >> >> + adev->mc.shared_aperture_start = 0x2000000000000000ULL; >> + adev->mc.shared_aperture_end = >> + adev->mc.shared_aperture_start + (4ULL << 30) - 1; >> + adev->mc.private_aperture_start = >> + adev->mc.shared_aperture_end + 1; >> + adev->mc.private_aperture_end = >> + adev->mc.private_aperture_start + (4ULL << 30) - 1; >> + >> return 0; >> } >> >> -- >> 2.13.6 >> > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: setup the shared and private apertures on gfx9 [not found] ` <20171208201046.14655-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org> 2017-12-14 15:25 ` Alex Deucher @ 2017-12-29 19:23 ` Felix Kuehling 1 sibling, 0 replies; 4+ messages in thread From: Felix Kuehling @ 2017-12-29 19:23 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Deucher, Alexander On 2017-12-08 03:10 PM, Alex Deucher wrote: > Same as previous asics. This was not yet set for gfx9. > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 ++++++++++++----- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++++ > 2 files changed, 20 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 3fd13b77e71e..7564f87b084e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1529,11 +1529,18 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) > for (i = 0; i < 16; i++) { On GFXv8 this loop uses adev->vm_manager.id_mgr[0].num_ids instead of hard-coded 16. No need for you to initialize the VMIDs used by KFD. Regards, Felix > soc15_grbm_select(adev, 0, 0, 0, i); > /* CP and shaders */ > - tmp = 0; > - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, > - SH_MEM_ALIGNMENT_MODE_UNALIGNED); > - WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); > - WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); > + if (i == 0) { > + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, > + SH_MEM_ALIGNMENT_MODE_UNALIGNED); > + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); > + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); > + } else { > + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, > + SH_MEM_ALIGNMENT_MODE_UNALIGNED); > + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); > + tmp = adev->mc.shared_aperture_start >> 48; > + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); > + } > } > soc15_grbm_select(adev, 0, 0, 0, 0); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 695e0eada1cd..dbfb746a390c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -497,6 +497,14 @@ static int gmc_v9_0_early_init(void *handle) > gmc_v9_0_set_gart_funcs(adev); > gmc_v9_0_set_irq_funcs(adev); > > + adev->mc.shared_aperture_start = 0x2000000000000000ULL; > + adev->mc.shared_aperture_end = > + adev->mc.shared_aperture_start + (4ULL << 30) - 1; > + adev->mc.private_aperture_start = > + adev->mc.shared_aperture_end + 1; > + adev->mc.private_aperture_end = > + adev->mc.private_aperture_start + (4ULL << 30) - 1; > + > return 0; > } > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-12-08 20:10 [PATCH] drm/amdgpu: setup the shared and private apertures on gfx9 Alex Deucher
[not found] ` <20171208201046.14655-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2017-12-14 15:25 ` Alex Deucher
[not found] ` <CADnq5_MyzRY1EivgbBehFRL_FJnQmCbV1VJZqvR4gVhVmGTSzA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-12-15 10:04 ` Christian König
2017-12-29 19:23 ` Felix Kuehling
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