* [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-09 17:46 ` Sai Prakash Ranjan
0 siblings, 0 replies; 36+ messages in thread
From: Sai Prakash Ranjan @ 2019-01-09 17:46 UTC (permalink / raw)
To: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Andy Gross, David Brown, devicetree,
Mark Rutland
Cc: Sai Prakash Ranjan, Rajendra Nayak, linux-arm-msm, linux-kernel,
Sibi Sankar, Vivek Gautam, linux-arm-kernel
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
.../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +
2 files changed, 439 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
new file mode 100644
index 000000000000..b6ef250b9186
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SDM845 Coresight DTS
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+&soc {
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x06002000 0x1000>,
+ <0x16280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x06041000 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6043000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x06043000 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ funnel2_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in2>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@5 {
+ reg = <5>;
+ funnel2_in5: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x06045000 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint = <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ merge_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel2_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x06046000 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@6047000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x06047000 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint = <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ etf_in: endpoint {
+ remote-endpoint = <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x06048000 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint = <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x07040000 0x1000>;
+
+ cpu = <&CPU0>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x07140000 0x1000>;
+
+ cpu = <&CPU1>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x07240000 0x1000>;
+
+ cpu = <&CPU2>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x07340000 0x1000>;
+
+ cpu = <&CPU3>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ etm@7440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x07440000 0x1000>;
+
+ cpu = <&CPU4>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&apss_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ etm@7540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x07540000 0x1000>;
+
+ cpu = <&CPU5>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&apss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ etm@7640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x07640000 0x1000>;
+
+ cpu = <&CPU6>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&apss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ etm@7740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x07740000 0x1000>;
+
+ cpu = <&CPU7>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&apss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@7800000 { /* APSS Funnel */
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x07800000 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7810000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x07810000 0x1000>;
+
+ power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel2_in5>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint =
+ <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c27cbd3bcb0a..03683179b8f7 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1853,3 +1853,5 @@
};
};
};
+
+#include "sdm845-coresight.dtsi"
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
2019-01-09 17:46 ` Sai Prakash Ranjan
@ 2019-01-11 18:46 ` Mathieu Poirier
-1 siblings, 0 replies; 36+ messages in thread
From: Mathieu Poirier @ 2019-01-11 18:46 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Rob Herring, Suzuki K Poulose, Leo Yan, Alexander Shishkin,
Andy Gross, David Brown, devicetree, Mark Rutland,
Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm
Hi Sai,
On Wed, Jan 09, 2019 at 11:16:47PM +0530, Sai Prakash Ranjan wrote:
> Add coresight components found on Qualcomm SDM845 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> .../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +
> 2 files changed, 439 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> new file mode 100644
> index 000000000000..b6ef250b9186
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> @@ -0,0 +1,437 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM845 Coresight DTS
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +&soc {
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x06002000 0x1000>,
> + <0x16280000 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint = <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06041000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6043000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06043000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel2_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in2>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> + funnel2_in5: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06045000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint = <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + merge_funnel_in2: endpoint {
> + remote-endpoint =
> + <&funnel2_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x06046000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6047000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06047000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint = <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + etf_in: endpoint {
> + remote-endpoint = <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06048000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint = <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
I'm a little curious as to why you need to bypass the normal AMBA bus discovery
method by forcing the peripheral ID. Tracers don't show up the way other
coresight devices do at boot time?
> + reg = <0x07040000 0x1000>;
> +
> + cpu = <&CPU0>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint = <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07140000 0x1000>;
> +
> + cpu = <&CPU1>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint = <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07240000 0x1000>;
> +
> + cpu = <&CPU2>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint = <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07340000 0x1000>;
> +
> + cpu = <&CPU3>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint = <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + etm@7440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07440000 0x1000>;
> +
> + cpu = <&CPU4>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint = <&apss_funnel_in4>;
> + };
> + };
> + };
> + };
> +
> + etm@7540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07540000 0x1000>;
> +
> + cpu = <&CPU5>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint = <&apss_funnel_in5>;
> + };
> + };
> + };
> + };
> +
> + etm@7640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07640000 0x1000>;
> +
> + cpu = <&CPU6>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint = <&apss_funnel_in6>;
> + };
> + };
> + };
> + };
> +
> + etm@7740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07740000 0x1000>;
> +
> + cpu = <&CPU7>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint = <&apss_funnel_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@7800000 { /* APSS Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07800000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7810000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07810000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel2_in5>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index c27cbd3bcb0a..03683179b8f7 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1853,3 +1853,5 @@
> };
> };
> };
> +
> +#include "sdm845-coresight.dtsi"
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-11 18:46 ` Mathieu Poirier
0 siblings, 0 replies; 36+ messages in thread
From: Mathieu Poirier @ 2019-01-11 18:46 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Mark Rutland, devicetree, Rajendra Nayak, Suzuki K Poulose,
Alexander Shishkin, linux-arm-msm, linux-kernel, David Brown,
Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Andy Gross,
linux-arm-kernel
Hi Sai,
On Wed, Jan 09, 2019 at 11:16:47PM +0530, Sai Prakash Ranjan wrote:
> Add coresight components found on Qualcomm SDM845 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> .../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +
> 2 files changed, 439 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> new file mode 100644
> index 000000000000..b6ef250b9186
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> @@ -0,0 +1,437 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM845 Coresight DTS
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +&soc {
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x06002000 0x1000>,
> + <0x16280000 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint = <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06041000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6043000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06043000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel2_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in2>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> + funnel2_in5: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06045000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint = <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + merge_funnel_in2: endpoint {
> + remote-endpoint =
> + <&funnel2_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x06046000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6047000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06047000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint = <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + etf_in: endpoint {
> + remote-endpoint = <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06048000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint = <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
I'm a little curious as to why you need to bypass the normal AMBA bus discovery
method by forcing the peripheral ID. Tracers don't show up the way other
coresight devices do at boot time?
> + reg = <0x07040000 0x1000>;
> +
> + cpu = <&CPU0>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint = <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07140000 0x1000>;
> +
> + cpu = <&CPU1>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint = <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07240000 0x1000>;
> +
> + cpu = <&CPU2>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint = <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07340000 0x1000>;
> +
> + cpu = <&CPU3>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint = <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + etm@7440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07440000 0x1000>;
> +
> + cpu = <&CPU4>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint = <&apss_funnel_in4>;
> + };
> + };
> + };
> + };
> +
> + etm@7540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07540000 0x1000>;
> +
> + cpu = <&CPU5>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint = <&apss_funnel_in5>;
> + };
> + };
> + };
> + };
> +
> + etm@7640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07640000 0x1000>;
> +
> + cpu = <&CPU6>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint = <&apss_funnel_in6>;
> + };
> + };
> + };
> + };
> +
> + etm@7740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07740000 0x1000>;
> +
> + cpu = <&CPU7>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint = <&apss_funnel_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@7800000 { /* APSS Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07800000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7810000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07810000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel2_in5>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index c27cbd3bcb0a..03683179b8f7 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1853,3 +1853,5 @@
> };
> };
> };
> +
> +#include "sdm845-coresight.dtsi"
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
2019-01-11 18:46 ` Mathieu Poirier
(?)
@ 2019-01-12 12:51 ` saiprakash.ranjan
-1 siblings, 0 replies; 36+ messages in thread
From: saiprakash.ranjan @ 2019-01-12 12:51 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Mark Rutland, devicetree, Rajendra Nayak, Suzuki K Poulose,
Alexander Shishkin, linux-arm-msm, linux-kernel, David Brown,
Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Andy Gross,
linux-arm-msm-owner, linux-arm-kernel
Hi Mathieu,
>> +
>> + etm@7040000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + arm,primecell-periphid = <0x000bb95d>;
>
> I'm a little curious as to why you need to bypass the normal AMBA bus
> discovery
> method by forcing the peripheral ID. Tracers don't show up the way
> other
> coresight devices do at boot time?
>
Yes on some Qcom SoC's like SDM845 and also on some previous ones, for
ETM(only) amba bus discovery method fails because of wrong pid read from
the registers. So we have to force this primecell peripheral ids to
probe etm.
- Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-12 12:51 ` saiprakash.ranjan
0 siblings, 0 replies; 36+ messages in thread
From: saiprakash.ranjan @ 2019-01-12 12:51 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Mark Rutland, devicetree, Rajendra Nayak, Suzuki K Poulose,
Alexander Shishkin, linux-arm-msm, linux-kernel, David Brown,
Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Andy Gross,
linux-arm-msm-owner, linux-arm-kernel
Hi Mathieu,
>> +
>> + etm@7040000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + arm,primecell-periphid = <0x000bb95d>;
>
> I'm a little curious as to why you need to bypass the normal AMBA bus
> discovery
> method by forcing the peripheral ID. Tracers don't show up the way
> other
> coresight devices do at boot time?
>
Yes on some Qcom SoC's like SDM845 and also on some previous ones, for
ETM(only) amba bus discovery method fails because of wrong pid read from
the registers. So we have to force this primecell peripheral ids to
probe etm.
- Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-12 12:51 ` saiprakash.ranjan
0 siblings, 0 replies; 36+ messages in thread
From: saiprakash.ranjan @ 2019-01-12 12:51 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Rob Herring, Suzuki K Poulose, Leo Yan, Alexander Shishkin,
Andy Gross, David Brown, devicetree, Mark Rutland,
Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, linux-arm-msm-owner
Hi Mathieu,
>> +
>> + etm@7040000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + arm,primecell-periphid = <0x000bb95d>;
>
> I'm a little curious as to why you need to bypass the normal AMBA bus
> discovery
> method by forcing the peripheral ID. Tracers don't show up the way
> other
> coresight devices do at boot time?
>
Yes on some Qcom SoC's like SDM845 and also on some previous ones, for
ETM(only) amba bus discovery method fails because of wrong pid read from
the registers. So we have to force this primecell peripheral ids to
probe etm.
- Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
2019-01-12 12:51 ` saiprakash.ranjan
@ 2019-01-14 15:35 ` Mathieu Poirier
-1 siblings, 0 replies; 36+ messages in thread
From: Mathieu Poirier @ 2019-01-14 15:35 UTC (permalink / raw)
To: saiprakash.ranjan
Cc: Rob Herring, Suzuki K Poulose, Leo Yan, Alexander Shishkin,
Andy Gross, David Brown, devicetree, Mark Rutland,
Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, linux-arm-msm-owner
On Sat, Jan 12, 2019 at 06:21:00PM +0530, saiprakash.ranjan@codeaurora.org wrote:
> Hi Mathieu,
>
> > > +
> > > + etm@7040000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + arm,primecell-periphid = <0x000bb95d>;
> >
> > I'm a little curious as to why you need to bypass the normal AMBA bus
> > discovery
> > method by forcing the peripheral ID. Tracers don't show up the way
> > other
> > coresight devices do at boot time?
> >
>
> Yes on some Qcom SoC's like SDM845 and also on some previous ones, for
> ETM(only) amba bus discovery method fails because of wrong pid read from the
> registers. So we have to force this primecell peripheral ids to probe etm.
Ok, if that is the case please add a comment to explain the situation.
Otherwise someone will assuredly ask again in the future.
Mathieu
>
> - Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
> Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-14 15:35 ` Mathieu Poirier
0 siblings, 0 replies; 36+ messages in thread
From: Mathieu Poirier @ 2019-01-14 15:35 UTC (permalink / raw)
To: saiprakash.ranjan
Cc: Mark Rutland, devicetree, Rajendra Nayak, Suzuki K Poulose,
Alexander Shishkin, linux-arm-msm, linux-kernel, David Brown,
Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Andy Gross,
linux-arm-msm-owner, linux-arm-kernel
On Sat, Jan 12, 2019 at 06:21:00PM +0530, saiprakash.ranjan@codeaurora.org wrote:
> Hi Mathieu,
>
> > > +
> > > + etm@7040000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + arm,primecell-periphid = <0x000bb95d>;
> >
> > I'm a little curious as to why you need to bypass the normal AMBA bus
> > discovery
> > method by forcing the peripheral ID. Tracers don't show up the way
> > other
> > coresight devices do at boot time?
> >
>
> Yes on some Qcom SoC's like SDM845 and also on some previous ones, for
> ETM(only) amba bus discovery method fails because of wrong pid read from the
> registers. So we have to force this primecell peripheral ids to probe etm.
Ok, if that is the case please add a comment to explain the situation.
Otherwise someone will assuredly ask again in the future.
Mathieu
>
> - Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
> Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
2019-01-14 15:35 ` Mathieu Poirier
@ 2019-01-15 16:29 ` Sai Prakash Ranjan
-1 siblings, 0 replies; 36+ messages in thread
From: Sai Prakash Ranjan @ 2019-01-15 16:29 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Mark Rutland, devicetree, Rajendra Nayak, Suzuki K Poulose,
Alexander Shishkin, linux-arm-msm, linux-kernel, David Brown,
Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Andy Gross,
linux-arm-msm-owner, linux-arm-kernel
Hi Mathieu,
On 1/14/2019 9:05 PM, Mathieu Poirier wrote:
> On Sat, Jan 12, 2019 at 06:21:00PM +0530, saiprakash.ranjan@codeaurora.org wrote:
>> Hi Mathieu,
>>
>>>> +
>>>> + etm@7040000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + arm,primecell-periphid = <0x000bb95d>;
>>>
>>> I'm a little curious as to why you need to bypass the normal AMBA bus
>>> discovery
>>> method by forcing the peripheral ID. Tracers don't show up the way
>>> other
>>> coresight devices do at boot time?
>>>
>>
>> Yes on some Qcom SoC's like SDM845 and also on some previous ones, for
>> ETM(only) amba bus discovery method fails because of wrong pid read from the
>> registers. So we have to force this primecell peripheral ids to probe etm.
>
> Ok, if that is the case please add a comment to explain the situation.
> Otherwise someone will assuredly ask again in the future.
>
Sure, will add it in the next version.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-15 16:29 ` Sai Prakash Ranjan
0 siblings, 0 replies; 36+ messages in thread
From: Sai Prakash Ranjan @ 2019-01-15 16:29 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Mark Rutland, devicetree, Rajendra Nayak, Suzuki K Poulose,
Alexander Shishkin, linux-arm-msm, linux-kernel, David Brown,
Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Andy Gross,
linux-arm-msm-owner, linux-arm-kernel
Hi Mathieu,
On 1/14/2019 9:05 PM, Mathieu Poirier wrote:
> On Sat, Jan 12, 2019 at 06:21:00PM +0530, saiprakash.ranjan@codeaurora.org wrote:
>> Hi Mathieu,
>>
>>>> +
>>>> + etm@7040000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + arm,primecell-periphid = <0x000bb95d>;
>>>
>>> I'm a little curious as to why you need to bypass the normal AMBA bus
>>> discovery
>>> method by forcing the peripheral ID. Tracers don't show up the way
>>> other
>>> coresight devices do at boot time?
>>>
>>
>> Yes on some Qcom SoC's like SDM845 and also on some previous ones, for
>> ETM(only) amba bus discovery method fails because of wrong pid read from the
>> registers. So we have to force this primecell peripheral ids to probe etm.
>
> Ok, if that is the case please add a comment to explain the situation.
> Otherwise someone will assuredly ask again in the future.
>
Sure, will add it in the next version.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
2019-01-09 17:46 ` Sai Prakash Ranjan
(?)
@ 2019-01-13 7:23 ` Bjorn Andersson
-1 siblings, 0 replies; 36+ messages in thread
From: Bjorn Andersson @ 2019-01-13 7:23 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Mark Rutland, devicetree, Rajendra Nayak, Mathieu Poirier,
Suzuki K Poulose, Alexander Shishkin, linux-arm-msm,
linux-kernel, David Brown, Rob Herring, Sibi Sankar,
Vivek Gautam, Leo Yan, Andy Gross, linux-arm-kernel
On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote:
> Add coresight components found on Qualcomm SDM845 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Hi Sai,
The content of this patch looks good, but please fold it into
sdm845.dtsi (keep the nodes sorted by address).
And mention below the --- that this depends on my AMBA bus pclk change
and include the URL:
https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/
Regards,
Bjorn
> ---
> .../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +
> 2 files changed, 439 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> new file mode 100644
> index 000000000000..b6ef250b9186
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> @@ -0,0 +1,437 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM845 Coresight DTS
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +&soc {
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x06002000 0x1000>,
> + <0x16280000 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint = <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06041000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6043000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06043000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel2_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in2>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> + funnel2_in5: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06045000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint = <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + merge_funnel_in2: endpoint {
> + remote-endpoint =
> + <&funnel2_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x06046000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6047000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06047000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint = <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + etf_in: endpoint {
> + remote-endpoint = <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06048000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint = <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07040000 0x1000>;
> +
> + cpu = <&CPU0>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint = <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07140000 0x1000>;
> +
> + cpu = <&CPU1>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint = <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07240000 0x1000>;
> +
> + cpu = <&CPU2>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint = <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07340000 0x1000>;
> +
> + cpu = <&CPU3>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint = <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + etm@7440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07440000 0x1000>;
> +
> + cpu = <&CPU4>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint = <&apss_funnel_in4>;
> + };
> + };
> + };
> + };
> +
> + etm@7540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07540000 0x1000>;
> +
> + cpu = <&CPU5>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint = <&apss_funnel_in5>;
> + };
> + };
> + };
> + };
> +
> + etm@7640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07640000 0x1000>;
> +
> + cpu = <&CPU6>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint = <&apss_funnel_in6>;
> + };
> + };
> + };
> + };
> +
> + etm@7740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07740000 0x1000>;
> +
> + cpu = <&CPU7>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint = <&apss_funnel_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@7800000 { /* APSS Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07800000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7810000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07810000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel2_in5>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index c27cbd3bcb0a..03683179b8f7 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1853,3 +1853,5 @@
> };
> };
> };
> +
> +#include "sdm845-coresight.dtsi"
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-13 7:23 ` Bjorn Andersson
0 siblings, 0 replies; 36+ messages in thread
From: Bjorn Andersson @ 2019-01-13 7:23 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Mark Rutland, devicetree, Rajendra Nayak, Mathieu Poirier,
Suzuki K Poulose, Alexander Shishkin, linux-arm-msm,
linux-kernel, David Brown, Rob Herring, Sibi Sankar,
Vivek Gautam, Leo Yan, Andy Gross, linux-arm-kernel
On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote:
> Add coresight components found on Qualcomm SDM845 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Hi Sai,
The content of this patch looks good, but please fold it into
sdm845.dtsi (keep the nodes sorted by address).
And mention below the --- that this depends on my AMBA bus pclk change
and include the URL:
https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/
Regards,
Bjorn
> ---
> .../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +
> 2 files changed, 439 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> new file mode 100644
> index 000000000000..b6ef250b9186
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> @@ -0,0 +1,437 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM845 Coresight DTS
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +&soc {
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x06002000 0x1000>,
> + <0x16280000 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint = <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06041000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6043000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06043000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel2_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in2>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> + funnel2_in5: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06045000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint = <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + merge_funnel_in2: endpoint {
> + remote-endpoint =
> + <&funnel2_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x06046000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6047000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06047000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint = <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + etf_in: endpoint {
> + remote-endpoint = <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06048000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint = <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07040000 0x1000>;
> +
> + cpu = <&CPU0>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint = <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07140000 0x1000>;
> +
> + cpu = <&CPU1>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint = <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07240000 0x1000>;
> +
> + cpu = <&CPU2>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint = <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07340000 0x1000>;
> +
> + cpu = <&CPU3>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint = <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + etm@7440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07440000 0x1000>;
> +
> + cpu = <&CPU4>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint = <&apss_funnel_in4>;
> + };
> + };
> + };
> + };
> +
> + etm@7540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07540000 0x1000>;
> +
> + cpu = <&CPU5>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint = <&apss_funnel_in5>;
> + };
> + };
> + };
> + };
> +
> + etm@7640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07640000 0x1000>;
> +
> + cpu = <&CPU6>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint = <&apss_funnel_in6>;
> + };
> + };
> + };
> + };
> +
> + etm@7740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07740000 0x1000>;
> +
> + cpu = <&CPU7>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint = <&apss_funnel_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@7800000 { /* APSS Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07800000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7810000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07810000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel2_in5>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index c27cbd3bcb0a..03683179b8f7 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1853,3 +1853,5 @@
> };
> };
> };
> +
> +#include "sdm845-coresight.dtsi"
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-13 7:23 ` Bjorn Andersson
0 siblings, 0 replies; 36+ messages in thread
From: Bjorn Andersson @ 2019-01-13 7:23 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Andy Gross, David Brown, devicetree,
Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar,
linux-arm-kernel, linux-kernel, linux-arm-msm
On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote:
> Add coresight components found on Qualcomm SDM845 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Hi Sai,
The content of this patch looks good, but please fold it into
sdm845.dtsi (keep the nodes sorted by address).
And mention below the --- that this depends on my AMBA bus pclk change
and include the URL:
https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/
Regards,
Bjorn
> ---
> .../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +
> 2 files changed, 439 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> new file mode 100644
> index 000000000000..b6ef250b9186
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
> @@ -0,0 +1,437 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM845 Coresight DTS
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +&soc {
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x06002000 0x1000>,
> + <0x16280000 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint = <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06041000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6043000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06043000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + funnel2_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in2>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@5 {
> + reg = <5>;
> + funnel2_in5: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x06045000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint = <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + merge_funnel_in2: endpoint {
> + remote-endpoint =
> + <&funnel2_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x06046000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6047000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06047000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint = <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + etf_in: endpoint {
> + remote-endpoint = <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06048000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint = <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07040000 0x1000>;
> +
> + cpu = <&CPU0>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint = <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07140000 0x1000>;
> +
> + cpu = <&CPU1>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint = <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07240000 0x1000>;
> +
> + cpu = <&CPU2>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint = <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07340000 0x1000>;
> +
> + cpu = <&CPU3>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint = <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + etm@7440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07440000 0x1000>;
> +
> + cpu = <&CPU4>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint = <&apss_funnel_in4>;
> + };
> + };
> + };
> + };
> +
> + etm@7540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07540000 0x1000>;
> +
> + cpu = <&CPU5>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint = <&apss_funnel_in5>;
> + };
> + };
> + };
> + };
> +
> + etm@7640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07640000 0x1000>;
> +
> + cpu = <&CPU6>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint = <&apss_funnel_in6>;
> + };
> + };
> + };
> + };
> +
> + etm@7740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + arm,primecell-periphid = <0x000bb95d>;
> + reg = <0x07740000 0x1000>;
> +
> + cpu = <&CPU7>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint = <&apss_funnel_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@7800000 { /* APSS Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07800000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7810000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x07810000 0x1000>;
> +
> + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>;
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel2_in5>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index c27cbd3bcb0a..03683179b8f7 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1853,3 +1853,5 @@
> };
> };
> };
> +
> +#include "sdm845-coresight.dtsi"
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
2019-01-13 7:23 ` Bjorn Andersson
@ 2019-01-15 16:27 ` Sai Prakash Ranjan
-1 siblings, 0 replies; 36+ messages in thread
From: Sai Prakash Ranjan @ 2019-01-15 16:27 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Andy Gross, David Brown, devicetree,
Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar,
linux-arm-kernel, linux-kernel, linux-arm-msm
Hi Bjorn,
Thanks for the review. Please find my comments inline.
On 1/13/2019 12:53 PM, Bjorn Andersson wrote:
> On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote:
>
>> Add coresight components found on Qualcomm SDM845 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>
> Hi Sai,
>
> The content of this patch looks good, but please fold it into
> sdm845.dtsi (keep the nodes sorted by address).
>
I had looked at the sample from hi6220 for coresight and
decided to keep sdm845 coresight dtsi in separate file as it
would look much cleaner than mixing it with main dtsi file.
Also I guess it would make coresight topology more understandable
if we keep it separately (plus there are about 400+ lines of coresight
dt entries). Is there any reason for wanting coresight entries merged
into sdm845.dtsi file? If you still prefer it, I can make the
change in the next version.
> And mention below the --- that this depends on my AMBA bus pclk change
> and include the URL:
>
> https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/
>
I had mentioned this dependency in the cover letter. But I suppose
I can mention it here as well.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-15 16:27 ` Sai Prakash Ranjan
0 siblings, 0 replies; 36+ messages in thread
From: Sai Prakash Ranjan @ 2019-01-15 16:27 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Mark Rutland, devicetree, Rajendra Nayak, Mathieu Poirier,
Suzuki K Poulose, Alexander Shishkin, linux-arm-msm,
linux-kernel, David Brown, Rob Herring, Sibi Sankar,
Vivek Gautam, Leo Yan, Andy Gross, linux-arm-kernel
Hi Bjorn,
Thanks for the review. Please find my comments inline.
On 1/13/2019 12:53 PM, Bjorn Andersson wrote:
> On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote:
>
>> Add coresight components found on Qualcomm SDM845 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>
> Hi Sai,
>
> The content of this patch looks good, but please fold it into
> sdm845.dtsi (keep the nodes sorted by address).
>
I had looked at the sample from hi6220 for coresight and
decided to keep sdm845 coresight dtsi in separate file as it
would look much cleaner than mixing it with main dtsi file.
Also I guess it would make coresight topology more understandable
if we keep it separately (plus there are about 400+ lines of coresight
dt entries). Is there any reason for wanting coresight entries merged
into sdm845.dtsi file? If you still prefer it, I can make the
change in the next version.
> And mention below the --- that this depends on my AMBA bus pclk change
> and include the URL:
>
> https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/
>
I had mentioned this dependency in the cover letter. But I suppose
I can mention it here as well.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
2019-01-15 16:27 ` Sai Prakash Ranjan
@ 2019-01-17 19:50 ` Bjorn Andersson
-1 siblings, 0 replies; 36+ messages in thread
From: Bjorn Andersson @ 2019-01-17 19:50 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Andy Gross, David Brown, devicetree,
Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar,
linux-arm-kernel, linux-kernel, linux-arm-msm
On Tue 15 Jan 08:27 PST 2019, Sai Prakash Ranjan wrote:
> Hi Bjorn,
>
> Thanks for the review. Please find my comments inline.
>
> On 1/13/2019 12:53 PM, Bjorn Andersson wrote:
> > On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote:
> >
> > > Add coresight components found on Qualcomm SDM845 SoC.
> > >
> > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> >
> > Hi Sai,
> >
> > The content of this patch looks good, but please fold it into
> > sdm845.dtsi (keep the nodes sorted by address).
> >
>
> I had looked at the sample from hi6220 for coresight and
> decided to keep sdm845 coresight dtsi in separate file as it
> would look much cleaner than mixing it with main dtsi file.
> Also I guess it would make coresight topology more understandable
> if we keep it separately (plus there are about 400+ lines of coresight
> dt entries). Is there any reason for wanting coresight entries merged
> into sdm845.dtsi file? If you still prefer it, I can make the
> change in the next version.
>
There seems to be some variations of this, but we try to keep everything
sorted in sdm845.dtsi to avoid having to jump around between the various
files. So please merge it into sdm845.dtsi (sorted by address).
Regards,
Bjorn
> > And mention below the --- that this depends on my AMBA bus pclk change
> > and include the URL:
> >
> > https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/
> >
>
> I had mentioned this dependency in the cover letter. But I suppose
> I can mention it here as well.
>
> Thanks,
> Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-17 19:50 ` Bjorn Andersson
0 siblings, 0 replies; 36+ messages in thread
From: Bjorn Andersson @ 2019-01-17 19:50 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Mark Rutland, devicetree, Rajendra Nayak, Mathieu Poirier,
Suzuki K Poulose, Alexander Shishkin, linux-arm-msm,
linux-kernel, David Brown, Rob Herring, Sibi Sankar,
Vivek Gautam, Leo Yan, Andy Gross, linux-arm-kernel
On Tue 15 Jan 08:27 PST 2019, Sai Prakash Ranjan wrote:
> Hi Bjorn,
>
> Thanks for the review. Please find my comments inline.
>
> On 1/13/2019 12:53 PM, Bjorn Andersson wrote:
> > On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote:
> >
> > > Add coresight components found on Qualcomm SDM845 SoC.
> > >
> > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> >
> > Hi Sai,
> >
> > The content of this patch looks good, but please fold it into
> > sdm845.dtsi (keep the nodes sorted by address).
> >
>
> I had looked at the sample from hi6220 for coresight and
> decided to keep sdm845 coresight dtsi in separate file as it
> would look much cleaner than mixing it with main dtsi file.
> Also I guess it would make coresight topology more understandable
> if we keep it separately (plus there are about 400+ lines of coresight
> dt entries). Is there any reason for wanting coresight entries merged
> into sdm845.dtsi file? If you still prefer it, I can make the
> change in the next version.
>
There seems to be some variations of this, but we try to keep everything
sorted in sdm845.dtsi to avoid having to jump around between the various
files. So please merge it into sdm845.dtsi (sorted by address).
Regards,
Bjorn
> > And mention below the --- that this depends on my AMBA bus pclk change
> > and include the URL:
> >
> > https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/
> >
>
> I had mentioned this dependency in the cover letter. But I suppose
> I can mention it here as well.
>
> Thanks,
> Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
2019-01-17 19:50 ` Bjorn Andersson
@ 2019-01-18 3:00 ` Sai Prakash Ranjan
-1 siblings, 0 replies; 36+ messages in thread
From: Sai Prakash Ranjan @ 2019-01-18 3:00 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Andy Gross, David Brown, devicetree,
Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar,
linux-arm-kernel, linux-kernel, linux-arm-msm
On 1/18/2019 1:20 AM, Bjorn Andersson wrote:
>
> There seems to be some variations of this, but we try to keep everything
> sorted in sdm845.dtsi to avoid having to jump around between the various
> files. So please merge it into sdm845.dtsi (sorted by address).
>
Sure will do it.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support
@ 2019-01-18 3:00 ` Sai Prakash Ranjan
0 siblings, 0 replies; 36+ messages in thread
From: Sai Prakash Ranjan @ 2019-01-18 3:00 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Mark Rutland, devicetree, Rajendra Nayak, Mathieu Poirier,
Suzuki K Poulose, Alexander Shishkin, linux-arm-msm,
linux-kernel, David Brown, Rob Herring, Sibi Sankar,
Vivek Gautam, Leo Yan, Andy Gross, linux-arm-kernel
On 1/18/2019 1:20 AM, Bjorn Andersson wrote:
>
> There seems to be some variations of this, but we try to keep everything
> sorted in sdm845.dtsi to avoid having to jump around between the various
> files. So please merge it into sdm845.dtsi (sorted by address).
>
Sure will do it.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 36+ messages in thread