* [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support
@ 2019-12-31 23:37 Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 1/7] drm/i915: Add support for non-power-of-2 FB plane alignment Imre Deak
` (9 more replies)
0 siblings, 10 replies; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Nanley G Chery, Dhinakaran Pandiyan, Ville Syrjala
This is the second part of [1] with media decompression enabled. I left
the third part with render decompression/color clear functionality for
later - once we have the IGT test for it in place.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Dhinakaran Pandiyan (3):
drm/framebuffer: Format modifier for Intel Gen-12 media compression
drm/fb: Extend format_info member arrays to handle four planes
drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the
media engine
Imre Deak (4):
drm/i915: Add support for non-power-of-2 FB plane alignment
drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
drm/i915: Add debug message for FB plane[0].offset!=0 error
drm/i915: Make sure plane dims are correct for UV CCS planes
drivers/gpu/drm/i915/display/intel_display.c | 246 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_display.h | 1 +
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 55 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
include/drm/drm_fourcc.h | 8 +-
include/uapi/drm/drm_fourcc.h | 13 +
7 files changed, 262 insertions(+), 68 deletions(-)
--
2.23.1
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 1/7] drm/i915: Add support for non-power-of-2 FB plane alignment
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
@ 2019-12-31 23:37 ` Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned Imre Deak
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx
At least one framebuffer plane on TGL - the UV plane of YUV semiplanar
FBs - requires a non-power-of-2 alignment, so add support for this. This
new alignment restriction applies only to an offset within an FB, so the
GEM buffer itself containing the FB must still be power-of-2 aligned.
Add a check for this (in practice plane 0, since the plane 0 offset must
be 0).
v2:
- Fix WARN check for alignment=0.
v3:
- Return error for alignment programming bugs. (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +++++++++++++-------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index da5266e76738..6e4152770c15 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2194,6 +2194,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
return ERR_PTR(-EINVAL);
alignment = intel_surf_alignment(fb, 0);
+ if (WARN_ON(alignment && !is_power_of_2(alignment)))
+ return ERR_PTR(-EINVAL);
/* Note that the w/a also requires 64 PTE of padding following the
* bo. We currently fill all unused PTE with the shadow page and so
@@ -2432,9 +2434,6 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
unsigned int cpp = fb->format->cpp[color_plane];
u32 offset, offset_aligned;
- if (alignment)
- alignment--;
-
if (!is_surface_linear(fb, color_plane)) {
unsigned int tile_size, tile_width, tile_height;
unsigned int tile_rows, tiles, pitch_tiles;
@@ -2456,17 +2455,24 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
*x %= tile_width;
offset = (tile_rows * pitch_tiles + tiles) * tile_size;
- offset_aligned = offset & ~alignment;
+
+ offset_aligned = offset;
+ if (alignment)
+ offset_aligned = rounddown(offset_aligned, alignment);
intel_adjust_tile_offset(x, y, tile_width, tile_height,
tile_size, pitch_tiles,
offset, offset_aligned);
} else {
offset = *y * pitch + *x * cpp;
- offset_aligned = offset & ~alignment;
-
- *y = (offset & alignment) / pitch;
- *x = ((offset & alignment) - *y * pitch) / cpp;
+ offset_aligned = offset;
+ if (alignment) {
+ offset_aligned = rounddown(offset_aligned, alignment);
+ *y = (offset % alignment) / pitch;
+ *x = ((offset % alignment) - *y * pitch) / cpp;
+ } else {
+ *y = *x = 0;
+ }
}
return offset_aligned;
@@ -3738,6 +3744,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
intel_add_fb_offsets(&x, &y, plane_state, 0);
offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
alignment = intel_surf_alignment(fb, 0);
+ if (WARN_ON(alignment && !is_power_of_2(alignment)))
+ return -EINVAL;
/*
* AUX surface offset is specified as the distance from the
--
2.23.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 1/7] drm/i915: Add support for non-power-of-2 FB plane alignment Imre Deak
@ 2019-12-31 23:37 ` Imre Deak
2020-01-02 14:12 ` Kahola, Mika
2019-12-31 23:37 ` [Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error Imre Deak
` (7 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx
Currently the GGTT offset of a UV plane in a semiplanar YUV FB is tile
size (4kB) aligned. I noticed, that enforcing only this alignment leads
oddly to random memory corruptions on TGL while scanning out Y-tiled
FBs. This issue can be easily reproduced with a UV plane offset that is
not aligned to the plane's tile row size.
Some experiments showed the correct alignment to be tile row size
indeed. This also makes sense, since the de-tiling fence created for the
object - with its own stride and so "left" and "right" edge - applies to
all the planes in the FB, so each tile row of all planes should be tile
row aligned.
In fact BSpec requires this alignment since SKL. On SKL we may enforce
this due to the AUX plane x,y coords check, but on ICL and TGL we don't.
For now enforce this only on TGL; I can follow up with any necessary
change for ICL after more tests.
BSpec requires a stricter alignment for linear UV planes too (kind of a
tile row alignment), but it's unclear whether that's really needed
(couldn't be explained with the de-tiling fence as above) and enforcing
that could break existing user space; so avoid that too for now until
more tests.
v2:
- Clarify the commit log wrt. the address space the alignment applies to.
(Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++++++++++++--
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6e4152770c15..bbc9cf288067 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1995,6 +1995,13 @@ intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
}
+static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
+ color_plane == 1;
+}
+
static unsigned int
intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
{
@@ -2069,6 +2076,16 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
*tile_height = intel_tile_height(fb, color_plane);
}
+static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ unsigned int tile_width, tile_height;
+
+ intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
+
+ return fb->pitches[color_plane] * tile_height;
+}
+
unsigned int
intel_fb_align_height(const struct drm_framebuffer *fb,
int color_plane, unsigned int height)
@@ -2143,7 +2160,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
struct drm_i915_private *dev_priv = to_i915(fb->dev);
/* AUX_DIST needs only 4K alignment */
- if (is_aux_plane(fb, color_plane))
+ if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
+ is_ccs_plane(fb, color_plane))
return 4096;
switch (fb->modifier) {
@@ -2158,6 +2176,10 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ is_semiplanar_uv_plane(fb, color_plane))
+ return intel_tile_row_size(fb, color_plane);
+ /* Fall-through */
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
@@ -2505,9 +2527,17 @@ static int intel_fb_offset_to_xy(int *x, int *y,
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
unsigned int height;
+ u32 alignment;
+
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ is_semiplanar_uv_plane(fb, color_plane))
+ alignment = intel_tile_row_size(fb, color_plane);
+ else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
+ alignment = intel_tile_size(dev_priv);
+ else
+ alignment = 0;
- if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
- fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
+ if (alignment != 0 && fb->offsets[color_plane] % alignment) {
DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
fb->offsets[color_plane], color_plane);
return -EINVAL;
--
2.23.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 1/7] drm/i915: Add support for non-power-of-2 FB plane alignment Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned Imre Deak
@ 2019-12-31 23:37 ` Imre Deak
2020-01-02 11:50 ` Kahola, Mika
2019-12-31 23:37 ` [Intel-gfx] [PATCH 4/7] drm/i915: Make sure plane dims are correct for UV CCS planes Imre Deak
` (6 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx
Print a debug message if the FB plane[0] offset is not 0 as expected, to
help understainding an add FB IOCTL fail.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bbc9cf288067..2c2450d3469b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16912,8 +16912,11 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
}
/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
- if (mode_cmd->offsets[0] != 0)
+ if (mode_cmd->offsets[0] != 0) {
+ DRM_DEBUG_KMS("plane 0 offset (0x%08x) must be 0\n",
+ mode_cmd->offsets[0]);
goto err;
+ }
drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
--
2.23.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 4/7] drm/i915: Make sure plane dims are correct for UV CCS planes
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
` (2 preceding siblings ...)
2019-12-31 23:37 ` [Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error Imre Deak
@ 2019-12-31 23:37 ` Imre Deak
2020-01-02 13:48 ` Kahola, Mika
2019-12-31 23:37 ` [Intel-gfx] " Imre Deak
` (5 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
As intel_fb_plane_get_subsampling() returns the subsampling factor wrt.
its main plane, for a CCS plane we need to apply both the main and the
CCS plane's subsampling factor on the FB's dimensions to get the CCS
plane's dimensions.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2c2450d3469b..d5128e900660 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2913,11 +2913,15 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
static void
intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
{
+ int main_plane = is_ccs_plane(fb, color_plane) ?
+ ccs_to_main_plane(fb, color_plane) : 0;
+ int main_hsub, main_vsub;
int hsub, vsub;
+ intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
- *w = fb->width / hsub;
- *h = fb->height / vsub;
+ *w = fb->width / main_hsub / hsub;
+ *h = fb->height / main_vsub / vsub;
}
/*
--
2.23.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/7] drm/framebuffer: Format modifier for Intel Gen-12 media compression
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
@ 2019-12-31 23:37 ` Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned Imre Deak
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx
Cc: Nanley G Chery, Lucas De Marchi, dri-devel, Dhinakaran Pandiyan,
Mika Kahola
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
v2: Update code comment describing the color plane order for YUV
semiplanar formats.
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..8bc0b31597d8 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.23.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 5/7] drm/framebuffer: Format modifier for Intel Gen-12 media compression
@ 2019-12-31 23:37 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Nanley G Chery, Lucas De Marchi, dri-devel, Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
v2: Update code comment describing the color plane order for YUV
semiplanar formats.
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..8bc0b31597d8 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.23.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 6/7] drm/fb: Extend format_info member arrays to handle four planes
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
@ 2019-12-31 23:37 ` Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned Imre Deak
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Dhinakaran Pandiyan, Mika Kahola
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
include/drm/drm_fourcc.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
* triplet @char_per_block, @block_w, @block_h for better
* describing the pixel format.
*/
- u8 cpp[3];
+ u8 cpp[4];
/**
* @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
* information from their drm_mode_config.get_format_info hook
* if they want the core to be validating the pitch.
*/
- u8 char_per_block[3];
+ u8 char_per_block[4];
};
/**
@@ -113,7 +113,7 @@ struct drm_format_info {
* Block width in pixels, this is intended to be accessed through
* drm_format_info_block_width()
*/
- u8 block_w[3];
+ u8 block_w[4];
/**
* @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
* Block height in pixels, this is intended to be accessed through
* drm_format_info_block_height()
*/
- u8 block_h[3];
+ u8 block_h[4];
/** @hsub: Horizontal chroma subsampling factor */
u8 hsub;
--
2.23.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 6/7] drm/fb: Extend format_info member arrays to handle four planes
@ 2019-12-31 23:37 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
include/drm/drm_fourcc.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
* triplet @char_per_block, @block_w, @block_h for better
* describing the pixel format.
*/
- u8 cpp[3];
+ u8 cpp[4];
/**
* @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
* information from their drm_mode_config.get_format_info hook
* if they want the core to be validating the pitch.
*/
- u8 char_per_block[3];
+ u8 char_per_block[4];
};
/**
@@ -113,7 +113,7 @@ struct drm_format_info {
* Block width in pixels, this is intended to be accessed through
* drm_format_info_block_width()
*/
- u8 block_w[3];
+ u8 block_w[4];
/**
* @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
* Block height in pixels, this is intended to be accessed through
* drm_format_info_block_height()
*/
- u8 block_h[3];
+ u8 block_h[4];
/** @hsub: Horizontal chroma subsampling factor */
u8 hsub;
--
2.23.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 7/7] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
` (5 preceding siblings ...)
2019-12-31 23:37 ` [Intel-gfx] " Imre Deak
@ 2019-12-31 23:37 ` Imre Deak
2020-01-06 15:58 ` Radhakrishna Sripada
2020-01-01 0:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Media decompression support Patchwork
` (2 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Imre Deak @ 2019-12-31 23:37 UTC (permalink / raw)
To: intel-gfx
Cc: Nanley G Chery, Yang A Shi, Lucas De Marchi, Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
support media decompression.
v2: Fix checkpatch warnings on code style (Lucas)
From DK:
Separate modifier array for planes that cannot decompress media (Ville)
v3: Support planar formats
v4: Switch plane order
v5:
- Use format block descriptors to get CCS subsampling calculation right
everywhere.
- Extend the plane state normal view array to accommodate 4 color planes.
- Use helpers to convert between main and CCS planes.
v6: Add missing packed YUV formats to the MC format list. (Yang)
v7: Align UV planes to tile-row size.
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Yang A Shi <yang.a.shi@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> (v6)
---
drivers/gpu/drm/i915/display/intel_display.c | 176 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_display.h | 1 +
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 55 ++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 188 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5128e900660..da4db5052579 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1945,7 +1945,9 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
static bool is_gen12_ccs_modifier(u64 modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+
}
static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
@@ -1978,8 +1980,7 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
}
/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
-static int
-intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
+int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
{
if (is_ccs_modifier(fb->modifier))
return main_to_ccs_plane(fb, main_plane);
@@ -2021,6 +2022,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (is_ccs_plane(fb, color_plane))
return 64;
/* fall through */
@@ -2171,6 +2173,10 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (is_semiplanar_uv_plane(fb, color_plane))
+ return intel_tile_row_size(fb, color_plane);
+ /* Fall-through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
@@ -2574,6 +2580,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2625,6 +2632,30 @@ static const struct drm_format_info gen12_ccs_formats[] = {
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
.char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
.hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_YUYV, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_YVYU, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_UYVY, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_VYUY, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_NV12, .num_planes = 4,
+ .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P010, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P012, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P016, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
};
static const struct drm_format_info *
@@ -2651,6 +2682,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
ARRAY_SIZE(skl_ccs_formats),
cmd->pixel_format);
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
@@ -2662,6 +2694,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2735,7 +2768,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
}
tile_width = intel_tile_width_bytes(fb, color_plane);
- if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+ if (is_ccs_modifier(fb->modifier)) {
/*
* Display WA #0531: skl,bxt,kbl,glk
*
@@ -2745,7 +2778,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+ if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
tile_width *= 4;
/*
* The main surface pitch must be padded to a multiple of four
@@ -3639,6 +3672,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
return 5120;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
/* FIXME AUX plane? */
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
@@ -3697,11 +3731,12 @@ static int icl_max_plane_height(void)
return 4320;
}
-static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
- int main_x, int main_y, u32 main_offset)
+static bool
+skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
+ int main_x, int main_y, u32 main_offset,
+ int ccs_plane)
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
- int ccs_plane = main_to_ccs_plane(fb, 0);
int aux_x = plane_state->color_plane[ccs_plane].x;
int aux_y = plane_state->color_plane[ccs_plane].y;
u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
@@ -3815,7 +3850,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
* they match with the main surface x/y offsets.
*/
if (is_ccs_modifier(fb->modifier)) {
- while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+ while (!skl_check_main_ccs_coordinates(plane_state, x, y,
+ offset, aux_plane)) {
if (offset == 0)
break;
@@ -3848,7 +3884,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int rotation = plane_state->hw.rotation;
- int max_width = skl_max_plane_width(fb, 1, rotation);
+ int uv_plane = 1;
+ int max_width = skl_max_plane_width(fb, uv_plane, rotation);
int max_height = 4096;
int x = plane_state->uapi.src.x1 >> 17;
int y = plane_state->uapi.src.y1 >> 17;
@@ -3856,8 +3893,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
int h = drm_rect_height(&plane_state->uapi.src) >> 17;
u32 offset;
- intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+ intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
+ offset = intel_plane_compute_aligned_offset(&x, &y,
+ plane_state, uv_plane);
/* FIXME not quite sure how/if these apply to the chroma plane */
if (w > max_width || h > max_height) {
@@ -3866,9 +3904,39 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
return -EINVAL;
}
- plane_state->color_plane[1].offset = offset;
- plane_state->color_plane[1].x = x;
- plane_state->color_plane[1].y = y;
+ if (is_ccs_modifier(fb->modifier)) {
+ int ccs_plane = main_to_ccs_plane(fb, uv_plane);
+ int aux_offset = plane_state->color_plane[ccs_plane].offset;
+ int alignment = intel_surf_alignment(fb, uv_plane);
+
+ if (offset > aux_offset)
+ offset = intel_plane_adjust_aligned_offset(&x, &y,
+ plane_state,
+ uv_plane,
+ offset,
+ aux_offset & ~(alignment - 1));
+
+ while (!skl_check_main_ccs_coordinates(plane_state, x, y,
+ offset, ccs_plane)) {
+ if (offset == 0)
+ break;
+
+ offset = intel_plane_adjust_aligned_offset(&x, &y,
+ plane_state,
+ uv_plane,
+ offset, offset - alignment);
+ }
+
+ if (x != plane_state->color_plane[ccs_plane].x ||
+ y != plane_state->color_plane[ccs_plane].y) {
+ DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+ return -EINVAL;
+ }
+ }
+
+ plane_state->color_plane[uv_plane].offset = offset;
+ plane_state->color_plane[uv_plane].x = x;
+ plane_state->color_plane[uv_plane].y = y;
return 0;
}
@@ -3878,21 +3946,40 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
const struct drm_framebuffer *fb = plane_state->hw.fb;
int src_x = plane_state->uapi.src.x1 >> 16;
int src_y = plane_state->uapi.src.y1 >> 16;
- int hsub;
- int vsub;
- int x;
- int y;
u32 offset;
+ int ccs_plane;
+
+ for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
+ int main_hsub, main_vsub;
+ int hsub, vsub;
+ int x, y;
- intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
- x = src_x / hsub;
- y = src_y / vsub;
- intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+ if (!is_ccs_plane(fb, ccs_plane))
+ continue;
+
+ intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
+ ccs_to_main_plane(fb, ccs_plane));
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
+
+ hsub *= main_hsub;
+ vsub *= main_vsub;
+ x = src_x / hsub;
+ y = src_y / vsub;
+
+ intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
- plane_state->color_plane[1].offset = offset;
- plane_state->color_plane[1].x = x * hsub + src_x % hsub;
- plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+ offset = intel_plane_compute_aligned_offset(&x, &y,
+ plane_state,
+ ccs_plane);
+
+ plane_state->color_plane[ccs_plane].offset = offset;
+ plane_state->color_plane[ccs_plane].x = (x * hsub +
+ src_x % hsub) /
+ main_hsub;
+ plane_state->color_plane[ccs_plane].y = (y * vsub +
+ src_y % vsub) /
+ main_vsub;
+ }
return 0;
}
@@ -3901,6 +3988,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
int ret;
+ bool needs_aux = false;
ret = intel_plane_compute_gtt(plane_state);
if (ret)
@@ -3910,22 +3998,32 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
return 0;
/*
- * Handle the AUX surface first since
- * the main surface setup depends on it.
+ * Handle the AUX surface first since the main surface setup depends on
+ * it.
*/
+ if (is_ccs_modifier(fb->modifier)) {
+ needs_aux = true;
+ ret = skl_check_ccs_aux_surface(plane_state);
+ if (ret)
+ return ret;
+ }
+
if (intel_format_info_is_yuv_semiplanar(fb->format,
fb->modifier)) {
+ needs_aux = true;
ret = skl_check_nv12_aux_surface(plane_state);
if (ret)
return ret;
- } else if (is_ccs_modifier(fb->modifier)) {
- ret = skl_check_ccs_aux_surface(plane_state);
- if (ret)
- return ret;
- } else {
- plane_state->color_plane[1].offset = ~0xfff;
- plane_state->color_plane[1].x = 0;
- plane_state->color_plane[1].y = 0;
+ }
+
+ if (!needs_aux) {
+ int i;
+
+ for (i = 1; i < fb->format->num_planes; i++) {
+ plane_state->color_plane[i].offset = ~0xfff;
+ plane_state->color_plane[i].x = 0;
+ plane_state->color_plane[i].y = 0;
+ }
}
ret = skl_check_main_surface(plane_state);
@@ -4515,6 +4613,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -10236,6 +10336,8 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
I915_FORMAT_MOD_Y_TILED_CCS;
+ else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index bc2c5104f755..028aab728514 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -474,6 +474,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
struct intel_link_m_n *m_n,
bool constant_n, bool fec_enable);
bool is_ccs_modifier(u64 modifier);
+int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane);
void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 630a94892b7b..a1a73209d824 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -90,8 +90,8 @@ struct intel_framebuffer {
/* for each plane in the normal GTT view */
struct {
unsigned int x, y;
- } normal[2];
- /* for each plane in the rotated GTT view */
+ } normal[4];
+ /* for each plane in the rotated GTT view for no-CCS formats */
struct {
unsigned int x, y;
unsigned int pitch; /* pixels */
@@ -555,7 +555,7 @@ struct intel_plane_state {
*/
u32 stride;
int x, y;
- } color_plane[2];
+ } color_plane[4];
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 3f7b8f2ff671..fca77ec1e0dd 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -583,15 +583,16 @@ skl_program_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
- u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
- u32 aux_stride = skl_plane_stride(plane_state, 1);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int aux_plane = intel_main_to_aux_plane(fb, color_plane);
+ u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
+ u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
u32 x = plane_state->color_plane[color_plane].x;
u32 y = plane_state->color_plane[color_plane].y;
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- const struct drm_framebuffer *fb = plane_state->hw.fb;
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0;
unsigned long irqflags;
@@ -2106,7 +2107,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2578,7 +2580,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
@@ -2743,10 +2754,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
}
}
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+ return plane_id < PLANE_SPRITE4;
+}
+
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
+ struct intel_plane *plane = to_intel_plane(_plane);
+
switch (modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (!gen12_plane_supports_mc_ccs(plane->id))
+ return false;
+ /* fall through */
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
@@ -2764,11 +2786,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
if (is_ccs_modifier(modifier))
return true;
/* fall through */
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
- case DRM_FORMAT_ARGB2101010:
- case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
@@ -2777,6 +2794,14 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
+ if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return true;
+ /* fall through */
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_XVYU2101010:
case DRM_FORMAT_C8:
case DRM_FORMAT_XBGR16161616F:
@@ -2910,6 +2935,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
}
}
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+ if (gen12_plane_supports_mc_ccs(plane_id))
+ return gen12_plane_format_modifiers_mc_ccs;
+ else
+ return gen12_plane_format_modifiers_rc_ccs;
+}
+
static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
@@ -2975,7 +3008,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- modifiers = gen12_plane_format_modifiers_ccs;
+ modifiers = gen12_get_plane_modifiers(plane_id);
plane_funcs = &gen12_plane_funcs;
} else {
if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 030a3f3e69af..36d631273684 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6813,6 +6813,7 @@ enum {
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
--
2.23.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Media decompression support
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
` (6 preceding siblings ...)
2019-12-31 23:37 ` [Intel-gfx] [PATCH 7/7] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine Imre Deak
@ 2020-01-01 0:17 ` Patchwork
2020-01-01 0:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-01 7:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-01-01 0:17 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Media decompression support
URL : https://patchwork.freedesktop.org/series/71535/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
33c7be81f878 drm/i915: Add support for non-power-of-2 FB plane alignment
fdf7e1ca3344 drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
cdc1c53c61f4 drm/i915: Add debug message for FB plane[0].offset!=0 error
877d8123db86 drm/i915: Make sure plane dims are correct for UV CCS planes
3224c01082d0 drm/framebuffer: Format modifier for Intel Gen-12 media compression
e101ef87bf8a drm/fb: Extend format_info member arrays to handle four planes
046f9d49ca43 drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:128: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#128: FILE: drivers/gpu/drm/i915/display/intel_display.c:2685:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
total: 0 errors, 2 warnings, 0 checks, 458 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Media decompression support
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
` (7 preceding siblings ...)
2020-01-01 0:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Media decompression support Patchwork
@ 2020-01-01 0:52 ` Patchwork
2020-01-01 7:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-01-01 0:52 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Media decompression support
URL : https://patchwork.freedesktop.org/series/71535/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7660 -> Patchwork_15961
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/index.html
Known issues
------------
Here are the changes found in Patchwork_15961 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-cfl-8700k: [PASS][1] -> [INCOMPLETE][2] ([i915#505])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-cfl-8700k/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-cfl-8700k/igt@i915_module_load@reload-with-fault-injection.html
- fi-skl-6700k2: [PASS][3] -> [INCOMPLETE][4] ([i915#671])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-n2820: [PASS][5] -> [DMESG-FAIL][6] ([i915#722])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
#### Possible fixes ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [TIMEOUT][7] ([i915#816]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-byt-j1900/igt@gem_close_race@basic-threads.html
* igt@gem_exec_suspend@basic-s3:
- fi-icl-u2: [FAIL][9] ([fdo#103375]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u2: [FAIL][11] ([fdo#111550]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [DMESG-WARN][13] ([i915#889]) -> [PASS][14] +23 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
- fi-skl-lmem: [DMESG-WARN][15] ([i915#889]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [DMESG-FAIL][17] ([i915#553] / [i915#725]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-hsw-4770r/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][19] ([i915#725]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-hsw-4770/igt@i915_selftest@live_blt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-kbl-soraka: [DMESG-FAIL][21] ([fdo#112406]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-kbl-soraka/igt@i915_selftest@live_gt_heartbeat.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-kbl-soraka/igt@i915_selftest@live_gt_heartbeat.html
* igt@i915_selftest@live_gt_lrc:
- fi-skl-6600u: [DMESG-FAIL][23] ([i915#889]) -> [PASS][24] +7 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
* igt@i915_selftest@live_sanitycheck:
- fi-skl-lmem: [INCOMPLETE][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-lmem/igt@i915_selftest@live_sanitycheck.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-lmem/igt@i915_selftest@live_sanitycheck.html
#### Warnings ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-bxt-dsi: [DMESG-WARN][27] ([i915#889]) -> [INCOMPLETE][28] ([fdo#103927])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [FAIL][29] ([fdo#103375]) -> [DMESG-WARN][30] ([IGT#4] / [i915#263])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550
[fdo#112406]: https://bugs.freedesktop.org/show_bug.cgi?id=112406
[i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
[i915#505]: https://gitlab.freedesktop.org/drm/intel/issues/505
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889
Participating hosts (45 -> 43)
------------------------------
Additional (5): fi-tgl-u fi-kbl-7500u fi-kbl-x1275 fi-blb-e6850 fi-kbl-r
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-skl-guc fi-byt-squawks fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7660 -> Patchwork_15961
CI-20190529: 20190529
CI_DRM_7660: 8e0504773b4e7f0102b6926d69db3dd58e6db52e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5356: 62146738c68abfa7497b023a049163932f5a9aa0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15961: 046f9d49ca43290bc9a2badbc533ee3ba1b588a5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
046f9d49ca43 drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
e101ef87bf8a drm/fb: Extend format_info member arrays to handle four planes
3224c01082d0 drm/framebuffer: Format modifier for Intel Gen-12 media compression
877d8123db86 drm/i915: Make sure plane dims are correct for UV CCS planes
cdc1c53c61f4 drm/i915: Add debug message for FB plane[0].offset!=0 error
fdf7e1ca3344 drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
33c7be81f878 drm/i915: Add support for non-power-of-2 FB plane alignment
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Media decompression support
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
` (8 preceding siblings ...)
2020-01-01 0:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-01-01 7:34 ` Patchwork
2020-01-07 11:57 ` Imre Deak
9 siblings, 1 reply; 18+ messages in thread
From: Patchwork @ 2020-01-01 7:34 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Media decompression support
URL : https://patchwork.freedesktop.org/series/71535/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7660_full -> Patchwork_15961_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
New tests
---------
New tests have been introduced between CI_DRM_7660_full and Patchwork_15961_full:
### New Piglit tests (7) ###
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_float-position-double_dvec4_array2:
- Statuses : 1 fail(s)
- Exec time: [0.13] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat4x3_array3-position-double_dvec2:
- Statuses : 1 fail(s)
- Exec time: [0.14] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_int_array3-position-double_dmat3x2:
- Statuses : 1 fail(s)
- Exec time: [0.14] s
* spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dvec4_array5-uint_uvec2:
- Statuses : 1 fail(s)
- Exec time: [0.16] s
* spec@glsl-4.20@execution@vs_in@vs-input-double_dmat2_array5-uint_uint-position:
- Statuses : 1 fail(s)
- Exec time: [0.13] s
* spec@glsl-4.20@execution@vs_in@vs-input-float_mat3_array3-double_dmat2-position:
- Statuses : 1 fail(s)
- Exec time: [0.13] s
* spec@glsl-4.20@execution@vs_in@vs-input-int_ivec3-double_dmat3x2-position:
- Statuses : 1 fail(s)
- Exec time: [0.13] s
Known issues
------------
Here are the changes found in Patchwork_15961_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +8 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb2/igt@gem_busy@busy-vcs1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_busy@busy-vcs1.html
* igt@gem_busy@close-race:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#435])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb5/igt@gem_busy@close-race.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb6/igt@gem_busy@close-race.html
* igt@gem_ctx_isolation@vcs1-clean:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_ctx_isolation@vcs1-clean.html
* igt@gem_eio@reset-stress:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#470])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb8/igt@gem_eio@reset-stress.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb5/igt@gem_eio@reset-stress.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][9] -> [FAIL][10] ([i915#232])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-snb1/igt@gem_eio@unwedge-stress.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-snb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#110854])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb1/igt@gem_exec_balancer@smoke.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb8/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_gttfill@basic:
- shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111593])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb2/igt@gem_exec_gttfill@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb6/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_schedule@preempt-queue-blt:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111677])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb2/igt@gem_exec_schedule@preempt-queue-blt.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb8/igt@gem_exec_schedule@preempt-queue-blt.html
* igt@gem_exec_schedule@preempt-queue-contexts-render:
- shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([fdo#111606] / [fdo#111677]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-render.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb5/igt@gem_exec_schedule@preempt-queue-contexts-render.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112146]) +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_exec_schedule@smoketest-all:
- shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#463])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb7/igt@gem_exec_schedule@smoketest-all.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb2/igt@gem_exec_schedule@smoketest-all.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-apl7/igt@gem_softpin@noreloc-s3.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-apl4/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [PASS][25] -> [FAIL][26] ([i915#413])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@i915_pm_rps@waitboost.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@i915_pm_rps@waitboost.html
* igt@i915_selftest@live_requests:
- shard-tglb: [PASS][27] -> [INCOMPLETE][28] ([i915#472])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb3/igt@i915_selftest@live_requests.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb3/igt@i915_selftest@live_requests.html
* igt@kms_color@pipe-a-ctm-0-25:
- shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#109])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-skl7/igt@kms_color@pipe-a-ctm-0-25.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-skl5/igt@kms_color@pipe-a-ctm-0-25.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- shard-tglb: [PASS][31] -> [FAIL][32] ([i915#49]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([fdo#111764])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +5 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +5 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf_pmu@enable-race-vcs0:
- shard-tglb: [PASS][41] -> [INCOMPLETE][42] ([i915#480])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb2/igt@perf_pmu@enable-race-vcs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb3/igt@perf_pmu@enable-race-vcs0.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109276]) +10 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries_display_on:
- shard-skl: [DMESG-WARN][45] ([i915#109]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-skl9/igt@debugfs_test@read_all_entries_display_on.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-skl8/igt@debugfs_test@read_all_entries_display_on.html
* igt@gem_busy@extended-parallel-vcs1:
- shard-iclb: [SKIP][47] ([fdo#112080]) -> [PASS][48] +6 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb5/igt@gem_busy@extended-parallel-vcs1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb4/igt@gem_busy@extended-parallel-vcs1.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [SKIP][49] ([fdo#109276] / [fdo#112080]) -> [PASS][50] +6 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@gem_ctx_persistence@vcs1-queued.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_exec_balancer@full-late:
- shard-tglb: [INCOMPLETE][51] ([i915#435]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb3/igt@gem_exec_balancer@full-late.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb8/igt@gem_exec_balancer@full-late.html
* igt@gem_exec_balancer@smoke:
- shard-tglb: [INCOMPLETE][53] ([fdo#111593]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb6/igt@gem_exec_balancer@smoke.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb6/igt@gem_exec_balancer@smoke.html
* {igt@gem_exec_schedule@pi-distinct-iova-bsd}:
- shard-iclb: [SKIP][55] ([i915#677]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][57] ([fdo#112146]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-vebox:
- shard-tglb: [INCOMPLETE][59] ([fdo#111677]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb5/igt@gem_exec_schedule@preempt-queue-vebox.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb2/igt@gem_exec_schedule@preempt-queue-vebox.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][61] ([i915#644]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_sync@basic-many-each:
- shard-tglb: [INCOMPLETE][63] ([i915#472] / [i915#707]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb8/igt@gem_sync@basic-many-each.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb2/igt@gem_sync@basic-many-each.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][65] ([i915#454]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][67] ([i915#72]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][69] ([i915#221]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-skl2/igt@kms_flip@flip-vs-suspend.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-skl1/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +5 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-tglb: [FAIL][73] ([i915#49]) -> [PASS][74] +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][75] ([i915#180]) -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [SKIP][77] ([fdo#109441]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@kms_psr@psr2_sprite_render.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][79] ([i915#31]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-apl4/igt@kms_setmode@basic.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-apl3/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][81] ([i915#31]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-kbl1/igt@kms_setmode@basic.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-kbl7/igt@kms_setmode@basic.html
* igt@perf_pmu@enable-race-vecs0:
- shard-tglb: [INCOMPLETE][83] ([i915#470]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb8/igt@perf_pmu@enable-race-vecs0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb3/igt@perf_pmu@enable-race-vecs0.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][85] ([fdo#109276]) -> [PASS][86] +19 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@prime_busy@hang-bsd2.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-iclb: [FAIL][87] ([IGT#28]) -> [SKIP][88] ([fdo#109276] / [fdo#112080])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@gem_tiled_blits@normal:
- shard-hsw: [FAIL][89] ([i915#832]) -> [FAIL][90] ([i915#818])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-hsw6/igt@gem_tiled_blits@normal.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-hsw8/igt@gem_tiled_blits@normal.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [FAIL][91] ([fdo#103375]) -> [DMESG-WARN][92] ([i915#180]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#463]: https://gitlab.freedesktop.org/drm/intel/issues/463
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#480]: https://gitlab.freedesktop.org/drm/intel/issues/480
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
[i915#832]: https://gitlab.freedesktop.org/drm/intel/issues/832
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7660 -> Patchwork_15961
CI-20190529: 20190529
CI_DRM_7660: 8e0504773b4e7f0102b6926d69db3dd58e6db52e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5356: 62146738c68abfa7497b023a049163932f5a9aa0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15961: 046f9d49ca43290bc9a2badbc533ee3ba1b588a5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/index.html
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error
2019-12-31 23:37 ` [Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error Imre Deak
@ 2020-01-02 11:50 ` Kahola, Mika
0 siblings, 0 replies; 18+ messages in thread
From: Kahola, Mika @ 2020-01-02 11:50 UTC (permalink / raw)
To: intel-gfx, Deak, Imre
On Wed, 2020-01-01 at 01:37 +0200, Imre Deak wrote:
> Print a debug message if the FB plane[0] offset is not 0 as expected,
> to
> help understainding an add FB IOCTL fail.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index bbc9cf288067..2c2450d3469b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16912,8 +16912,11 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> }
>
> /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
> - if (mode_cmd->offsets[0] != 0)
> + if (mode_cmd->offsets[0] != 0) {
> + DRM_DEBUG_KMS("plane 0 offset (0x%08x) must be 0\n",
> + mode_cmd->offsets[0]);
> goto err;
> + }
>
> drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915: Make sure plane dims are correct for UV CCS planes
2019-12-31 23:37 ` [Intel-gfx] [PATCH 4/7] drm/i915: Make sure plane dims are correct for UV CCS planes Imre Deak
@ 2020-01-02 13:48 ` Kahola, Mika
0 siblings, 0 replies; 18+ messages in thread
From: Kahola, Mika @ 2020-01-02 13:48 UTC (permalink / raw)
To: intel-gfx, Deak, Imre; +Cc: Pandiyan, Dhinakaran
On Wed, 2020-01-01 at 01:37 +0200, Imre Deak wrote:
> As intel_fb_plane_get_subsampling() returns the subsampling factor
> wrt.
> its main plane, for a CCS plane we need to apply both the main and
> the
> CCS plane's subsampling factor on the FB's dimensions to get the CCS
> plane's dimensions.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 2c2450d3469b..d5128e900660 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2913,11 +2913,15 @@ intel_fb_check_ccs_xy(struct drm_framebuffer
> *fb, int ccs_plane, int x, int y)
> static void
> intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int
> color_plane)
> {
> + int main_plane = is_ccs_plane(fb, color_plane) ?
> + ccs_to_main_plane(fb, color_plane) : 0;
> + int main_hsub, main_vsub;
> int hsub, vsub;
>
> + intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
> main_plane);
> intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
> - *w = fb->width / hsub;
> - *h = fb->height / vsub;
> + *w = fb->width / main_hsub / hsub;
> + *h = fb->height / main_vsub / vsub;
> }
>
> /*
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
2019-12-31 23:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned Imre Deak
@ 2020-01-02 14:12 ` Kahola, Mika
0 siblings, 0 replies; 18+ messages in thread
From: Kahola, Mika @ 2020-01-02 14:12 UTC (permalink / raw)
To: intel-gfx, Deak, Imre
On Wed, 2020-01-01 at 01:37 +0200, Imre Deak wrote:
> Currently the GGTT offset of a UV plane in a semiplanar YUV FB is
> tile
> size (4kB) aligned. I noticed, that enforcing only this alignment
> leads
> oddly to random memory corruptions on TGL while scanning out Y-tiled
> FBs. This issue can be easily reproduced with a UV plane offset that
> is
> not aligned to the plane's tile row size.
>
> Some experiments showed the correct alignment to be tile row size
> indeed. This also makes sense, since the de-tiling fence created for
> the
> object - with its own stride and so "left" and "right" edge - applies
> to
> all the planes in the FB, so each tile row of all planes should be
> tile
> row aligned.
>
> In fact BSpec requires this alignment since SKL. On SKL we may
> enforce
> this due to the AUX plane x,y coords check, but on ICL and TGL we
> don't.
> For now enforce this only on TGL; I can follow up with any necessary
> change for ICL after more tests.
>
> BSpec requires a stricter alignment for linear UV planes too (kind of
> a
> tile row alignment), but it's unclear whether that's really needed
> (couldn't be explained with the de-tiling fence as above) and
> enforcing
> that could break existing user space; so avoid that too for now until
> more tests.
>
> v2:
> - Clarify the commit log wrt. the address space the alignment applies
> to.
> (Chris)
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 36
> ++++++++++++++++++--
> 1 file changed, 33 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6e4152770c15..bbc9cf288067 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1995,6 +1995,13 @@ intel_format_info_is_yuv_semiplanar(const
> struct drm_format_info *info,
> info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
> }
>
> +static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
> + int color_plane)
> +{
> + return intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier) &&
> + color_plane == 1;
> +}
> +
> static unsigned int
> intel_tile_width_bytes(const struct drm_framebuffer *fb, int
> color_plane)
> {
> @@ -2069,6 +2076,16 @@ static void intel_tile_dims(const struct
> drm_framebuffer *fb, int color_plane,
> *tile_height = intel_tile_height(fb, color_plane);
> }
>
> +static unsigned int intel_tile_row_size(const struct drm_framebuffer
> *fb,
> + int color_plane)
> +{
> + unsigned int tile_width, tile_height;
> +
> + intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
> +
> + return fb->pitches[color_plane] * tile_height;
> +}
> +
> unsigned int
> intel_fb_align_height(const struct drm_framebuffer *fb,
> int color_plane, unsigned int height)
> @@ -2143,7 +2160,8 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
>
> /* AUX_DIST needs only 4K alignment */
> - if (is_aux_plane(fb, color_plane))
> + if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane))
> ||
> + is_ccs_plane(fb, color_plane))
> return 4096;
>
> switch (fb->modifier) {
> @@ -2158,6 +2176,10 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> + if (INTEL_GEN(dev_priv) >= 12 &&
> + is_semiplanar_uv_plane(fb, color_plane))
> + return intel_tile_row_size(fb, color_plane);
> + /* Fall-through */
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> default:
> @@ -2505,9 +2527,17 @@ static int intel_fb_offset_to_xy(int *x, int
> *y,
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
> unsigned int height;
> + u32 alignment;
> +
> + if (INTEL_GEN(dev_priv) >= 12 &&
> + is_semiplanar_uv_plane(fb, color_plane))
> + alignment = intel_tile_row_size(fb, color_plane);
> + else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
> + alignment = intel_tile_size(dev_priv);
> + else
> + alignment = 0;
>
> - if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
> - fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
> + if (alignment != 0 && fb->offsets[color_plane] % alignment) {
> DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane
> %d\n",
> fb->offsets[color_plane], color_plane);
> return -EINVAL;
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 7/7] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
2019-12-31 23:37 ` [Intel-gfx] [PATCH 7/7] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine Imre Deak
@ 2020-01-06 15:58 ` Radhakrishna Sripada
0 siblings, 0 replies; 18+ messages in thread
From: Radhakrishna Sripada @ 2020-01-06 15:58 UTC (permalink / raw)
To: Imre Deak
Cc: Nanley G Chery, Yang A Shi, intel-gfx, Lucas De Marchi,
Dhinakaran Pandiyan
On Wed, Jan 01, 2020 at 01:37:56AM +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
> Detect the modifier corresponding to media compression to enable
> display decompression for YUV and xRGB packed formats. A new modifier is
> added so that the driver can distinguish between media and render
> compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
> support media decompression.
>
> v2: Fix checkpatch warnings on code style (Lucas)
>
> From DK:
> Separate modifier array for planes that cannot decompress media (Ville)
>
> v3: Support planar formats
> v4: Switch plane order
> v5:
> - Use format block descriptors to get CCS subsampling calculation right
> everywhere.
> - Extend the plane state normal view array to accommodate 4 color planes.
> - Use helpers to convert between main and CCS planes.
> v6: Add missing packed YUV formats to the MC format list. (Yang)
> v7: Align UV planes to tile-row size.
>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Yang A Shi <yang.a.shi@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> (v6)
For v7,
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
- Radhakrishna(RK) Sripada
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 176 ++++++++++++++----
> drivers/gpu/drm/i915/display/intel_display.h | 1 +
> .../drm/i915/display/intel_display_types.h | 6 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 55 ++++--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 5 files changed, 188 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d5128e900660..da4db5052579 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1945,7 +1945,9 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
>
> static bool is_gen12_ccs_modifier(u64 modifier)
> {
> - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> +
> }
>
> static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> @@ -1978,8 +1980,7 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
> }
>
> /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
> -static int
> -intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
> +int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
> {
> if (is_ccs_modifier(fb->modifier))
> return main_to_ccs_plane(fb, main_plane);
> @@ -2021,6 +2022,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> /* fall through */
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> if (is_ccs_plane(fb, color_plane))
> return 64;
> /* fall through */
> @@ -2171,6 +2173,10 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> return 0;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + if (is_semiplanar_uv_plane(fb, color_plane))
> + return intel_tile_row_size(fb, color_plane);
> + /* Fall-through */
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> @@ -2574,6 +2580,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2625,6 +2632,30 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_YUYV, .num_planes = 2,
> + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 2, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_YVYU, .num_planes = 2,
> + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 2, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_UYVY, .num_planes = 2,
> + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 2, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_VYUY, .num_planes = 2,
> + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 2, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_NV12, .num_planes = 4,
> + .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
> + .hsub = 2, .vsub = 2, .is_yuv = true },
> + { .format = DRM_FORMAT_P010, .num_planes = 4,
> + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> + .hsub = 2, .vsub = 2, .is_yuv = true },
> + { .format = DRM_FORMAT_P012, .num_planes = 4,
> + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> + .hsub = 2, .vsub = 2, .is_yuv = true },
> + { .format = DRM_FORMAT_P016, .num_planes = 4,
> + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> + .hsub = 2, .vsub = 2, .is_yuv = true },
> };
>
> static const struct drm_format_info *
> @@ -2651,6 +2682,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> ARRAY_SIZE(skl_ccs_formats),
> cmd->pixel_format);
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return lookup_format_info(gen12_ccs_formats,
> ARRAY_SIZE(gen12_ccs_formats),
> cmd->pixel_format);
> @@ -2662,6 +2694,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> bool is_ccs_modifier(u64 modifier)
> {
> return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
> @@ -2735,7 +2768,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> }
>
> tile_width = intel_tile_width_bytes(fb, color_plane);
> - if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
> + if (is_ccs_modifier(fb->modifier)) {
> /*
> * Display WA #0531: skl,bxt,kbl,glk
> *
> @@ -2745,7 +2778,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> * require the entire fb to accommodate that to avoid
> * potential runtime errors at plane configuration time.
> */
> - if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> + if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
> tile_width *= 4;
> /*
> * The main surface pitch must be padded to a multiple of four
> @@ -3639,6 +3672,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
> return 5120;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> /* FIXME AUX plane? */
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> @@ -3697,11 +3731,12 @@ static int icl_max_plane_height(void)
> return 4320;
> }
>
> -static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
> - int main_x, int main_y, u32 main_offset)
> +static bool
> +skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
> + int main_x, int main_y, u32 main_offset,
> + int ccs_plane)
> {
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> - int ccs_plane = main_to_ccs_plane(fb, 0);
> int aux_x = plane_state->color_plane[ccs_plane].x;
> int aux_y = plane_state->color_plane[ccs_plane].y;
> u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
> @@ -3815,7 +3850,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> * they match with the main surface x/y offsets.
> */
> if (is_ccs_modifier(fb->modifier)) {
> - while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
> + while (!skl_check_main_ccs_coordinates(plane_state, x, y,
> + offset, aux_plane)) {
> if (offset == 0)
> break;
>
> @@ -3848,7 +3884,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
> {
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> unsigned int rotation = plane_state->hw.rotation;
> - int max_width = skl_max_plane_width(fb, 1, rotation);
> + int uv_plane = 1;
> + int max_width = skl_max_plane_width(fb, uv_plane, rotation);
> int max_height = 4096;
> int x = plane_state->uapi.src.x1 >> 17;
> int y = plane_state->uapi.src.y1 >> 17;
> @@ -3856,8 +3893,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
> int h = drm_rect_height(&plane_state->uapi.src) >> 17;
> u32 offset;
>
> - intel_add_fb_offsets(&x, &y, plane_state, 1);
> - offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
> + intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
> + offset = intel_plane_compute_aligned_offset(&x, &y,
> + plane_state, uv_plane);
>
> /* FIXME not quite sure how/if these apply to the chroma plane */
> if (w > max_width || h > max_height) {
> @@ -3866,9 +3904,39 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
> return -EINVAL;
> }
>
> - plane_state->color_plane[1].offset = offset;
> - plane_state->color_plane[1].x = x;
> - plane_state->color_plane[1].y = y;
> + if (is_ccs_modifier(fb->modifier)) {
> + int ccs_plane = main_to_ccs_plane(fb, uv_plane);
> + int aux_offset = plane_state->color_plane[ccs_plane].offset;
> + int alignment = intel_surf_alignment(fb, uv_plane);
> +
> + if (offset > aux_offset)
> + offset = intel_plane_adjust_aligned_offset(&x, &y,
> + plane_state,
> + uv_plane,
> + offset,
> + aux_offset & ~(alignment - 1));
> +
> + while (!skl_check_main_ccs_coordinates(plane_state, x, y,
> + offset, ccs_plane)) {
> + if (offset == 0)
> + break;
> +
> + offset = intel_plane_adjust_aligned_offset(&x, &y,
> + plane_state,
> + uv_plane,
> + offset, offset - alignment);
> + }
> +
> + if (x != plane_state->color_plane[ccs_plane].x ||
> + y != plane_state->color_plane[ccs_plane].y) {
> + DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
> + return -EINVAL;
> + }
> + }
> +
> + plane_state->color_plane[uv_plane].offset = offset;
> + plane_state->color_plane[uv_plane].x = x;
> + plane_state->color_plane[uv_plane].y = y;
>
> return 0;
> }
> @@ -3878,21 +3946,40 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> int src_x = plane_state->uapi.src.x1 >> 16;
> int src_y = plane_state->uapi.src.y1 >> 16;
> - int hsub;
> - int vsub;
> - int x;
> - int y;
> u32 offset;
> + int ccs_plane;
> +
> + for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
> + int main_hsub, main_vsub;
> + int hsub, vsub;
> + int x, y;
>
> - intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
> - x = src_x / hsub;
> - y = src_y / vsub;
> - intel_add_fb_offsets(&x, &y, plane_state, 1);
> - offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
> + if (!is_ccs_plane(fb, ccs_plane))
> + continue;
> +
> + intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
> + ccs_to_main_plane(fb, ccs_plane));
> + intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
> +
> + hsub *= main_hsub;
> + vsub *= main_vsub;
> + x = src_x / hsub;
> + y = src_y / vsub;
> +
> + intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
>
> - plane_state->color_plane[1].offset = offset;
> - plane_state->color_plane[1].x = x * hsub + src_x % hsub;
> - plane_state->color_plane[1].y = y * vsub + src_y % vsub;
> + offset = intel_plane_compute_aligned_offset(&x, &y,
> + plane_state,
> + ccs_plane);
> +
> + plane_state->color_plane[ccs_plane].offset = offset;
> + plane_state->color_plane[ccs_plane].x = (x * hsub +
> + src_x % hsub) /
> + main_hsub;
> + plane_state->color_plane[ccs_plane].y = (y * vsub +
> + src_y % vsub) /
> + main_vsub;
> + }
>
> return 0;
> }
> @@ -3901,6 +3988,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
> {
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> int ret;
> + bool needs_aux = false;
>
> ret = intel_plane_compute_gtt(plane_state);
> if (ret)
> @@ -3910,22 +3998,32 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
> return 0;
>
> /*
> - * Handle the AUX surface first since
> - * the main surface setup depends on it.
> + * Handle the AUX surface first since the main surface setup depends on
> + * it.
> */
> + if (is_ccs_modifier(fb->modifier)) {
> + needs_aux = true;
> + ret = skl_check_ccs_aux_surface(plane_state);
> + if (ret)
> + return ret;
> + }
> +
> if (intel_format_info_is_yuv_semiplanar(fb->format,
> fb->modifier)) {
> + needs_aux = true;
> ret = skl_check_nv12_aux_surface(plane_state);
> if (ret)
> return ret;
> - } else if (is_ccs_modifier(fb->modifier)) {
> - ret = skl_check_ccs_aux_surface(plane_state);
> - if (ret)
> - return ret;
> - } else {
> - plane_state->color_plane[1].offset = ~0xfff;
> - plane_state->color_plane[1].x = 0;
> - plane_state->color_plane[1].y = 0;
> + }
> +
> + if (!needs_aux) {
> + int i;
> +
> + for (i = 1; i < fb->format->num_planes; i++) {
> + plane_state->color_plane[i].offset = ~0xfff;
> + plane_state->color_plane[i].x = 0;
> + plane_state->color_plane[i].y = 0;
> + }
> }
>
> ret = skl_check_main_surface(plane_state);
> @@ -4515,6 +4613,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> PLANE_CTL_CLEAR_COLOR_DISABLE;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Yf_TILED:
> return PLANE_CTL_TILED_YF;
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -10236,6 +10336,8 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> I915_FORMAT_MOD_Y_TILED_CCS;
> + else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> + fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index bc2c5104f755..028aab728514 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -474,6 +474,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
> struct intel_link_m_n *m_n,
> bool constant_n, bool fec_enable);
> bool is_ccs_modifier(u64 modifier);
> +int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane);
> void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 630a94892b7b..a1a73209d824 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -90,8 +90,8 @@ struct intel_framebuffer {
> /* for each plane in the normal GTT view */
> struct {
> unsigned int x, y;
> - } normal[2];
> - /* for each plane in the rotated GTT view */
> + } normal[4];
> + /* for each plane in the rotated GTT view for no-CCS formats */
> struct {
> unsigned int x, y;
> unsigned int pitch; /* pixels */
> @@ -555,7 +555,7 @@ struct intel_plane_state {
> */
> u32 stride;
> int x, y;
> - } color_plane[2];
> + } color_plane[4];
>
> /* plane control register */
> u32 ctl;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 3f7b8f2ff671..fca77ec1e0dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -583,15 +583,16 @@ skl_program_plane(struct intel_plane *plane,
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> u32 surf_addr = plane_state->color_plane[color_plane].offset;
> u32 stride = skl_plane_stride(plane_state, color_plane);
> - u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
> - u32 aux_stride = skl_plane_stride(plane_state, 1);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> + u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
> + u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> u32 x = plane_state->color_plane[color_plane].x;
> u32 y = plane_state->color_plane[color_plane].y;
> u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - const struct drm_framebuffer *fb = plane_state->hw.fb;
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_color_ctl = 0;
> unsigned long irqflags;
> @@ -2106,7 +2107,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> return -EINVAL;
> }
> @@ -2578,7 +2580,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> DRM_FORMAT_MOD_INVALID
> };
>
> -static const u64 gen12_plane_format_modifiers_ccs[] = {
> +static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> + I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + I915_FORMAT_MOD_Y_TILED,
> + I915_FORMAT_MOD_X_TILED,
> + DRM_FORMAT_MOD_LINEAR,
> + DRM_FORMAT_MOD_INVALID
> +};
> +
> +static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> I915_FORMAT_MOD_Y_TILED,
> I915_FORMAT_MOD_X_TILED,
> @@ -2743,10 +2754,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> }
> }
>
> +static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
> +{
> + return plane_id < PLANE_SPRITE4;
> +}
> +
> static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> + struct intel_plane *plane = to_intel_plane(_plane);
> +
> switch (modifier) {
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + if (!gen12_plane_supports_mc_ccs(plane->id))
> + return false;
> + /* fall through */
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> @@ -2764,11 +2786,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> if (is_ccs_modifier(modifier))
> return true;
> /* fall through */
> - case DRM_FORMAT_RGB565:
> - case DRM_FORMAT_XRGB2101010:
> - case DRM_FORMAT_XBGR2101010:
> - case DRM_FORMAT_ARGB2101010:
> - case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
> @@ -2777,6 +2794,14 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_P010:
> case DRM_FORMAT_P012:
> case DRM_FORMAT_P016:
> + if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> + return true;
> + /* fall through */
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_XVYU2101010:
> case DRM_FORMAT_C8:
> case DRM_FORMAT_XBGR16161616F:
> @@ -2910,6 +2935,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
> }
> }
>
> +static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
> +{
> + if (gen12_plane_supports_mc_ccs(plane_id))
> + return gen12_plane_format_modifiers_mc_ccs;
> + else
> + return gen12_plane_format_modifiers_rc_ccs;
> +}
> +
> static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id)
> {
> @@ -2975,7 +3008,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>
> plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> if (INTEL_GEN(dev_priv) >= 12) {
> - modifiers = gen12_plane_format_modifiers_ccs;
> + modifiers = gen12_get_plane_modifiers(plane_id);
> plane_funcs = &gen12_plane_funcs;
> } else {
> if (plane->has_ccs)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 030a3f3e69af..36d631273684 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6813,6 +6813,7 @@ enum {
> #define PLANE_CTL_TILED_Y (4 << 10)
> #define PLANE_CTL_TILED_YF (5 << 10)
> #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> +#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
> #define PLANE_CTL_ALPHA_DISABLE (0 << 4)
> #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
> --
> 2.23.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Media decompression support
2020-01-01 7:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-01-07 11:57 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2020-01-07 11:57 UTC (permalink / raw)
To: intel-gfx, Mika Kahola, Radhakrishna Sripada, Chris Wilson
Cc: Dhinakaran Pandiyan
On Wed, Jan 01, 2020 at 07:34:13AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Media decompression support
> URL : https://patchwork.freedesktop.org/series/71535/
> State : success
Thanks for the reviews, pushed to -dinq.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7660_full -> Patchwork_15961_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_7660_full and Patchwork_15961_full:
>
> ### New Piglit tests (7) ###
>
> * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_float-position-double_dvec4_array2:
> - Statuses : 1 fail(s)
> - Exec time: [0.13] s
>
> * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat4x3_array3-position-double_dvec2:
> - Statuses : 1 fail(s)
> - Exec time: [0.14] s
>
> * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_int_array3-position-double_dmat3x2:
> - Statuses : 1 fail(s)
> - Exec time: [0.14] s
>
> * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dvec4_array5-uint_uvec2:
> - Statuses : 1 fail(s)
> - Exec time: [0.16] s
>
> * spec@glsl-4.20@execution@vs_in@vs-input-double_dmat2_array5-uint_uint-position:
> - Statuses : 1 fail(s)
> - Exec time: [0.13] s
>
> * spec@glsl-4.20@execution@vs_in@vs-input-float_mat3_array3-double_dmat2-position:
> - Statuses : 1 fail(s)
> - Exec time: [0.13] s
>
> * spec@glsl-4.20@execution@vs_in@vs-input-int_ivec3-double_dmat3x2-position:
> - Statuses : 1 fail(s)
> - Exec time: [0.13] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_15961_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_busy@busy-vcs1:
> - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +8 similar issues
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb2/igt@gem_busy@busy-vcs1.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_busy@busy-vcs1.html
>
> * igt@gem_busy@close-race:
> - shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#435])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb5/igt@gem_busy@close-race.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb6/igt@gem_busy@close-race.html
>
> * igt@gem_ctx_isolation@vcs1-clean:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +1 similar issue
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_ctx_isolation@vcs1-clean.html
>
> * igt@gem_eio@reset-stress:
> - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#470])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb8/igt@gem_eio@reset-stress.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb5/igt@gem_eio@reset-stress.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-snb: [PASS][9] -> [FAIL][10] ([i915#232])
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-snb1/igt@gem_eio@unwedge-stress.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-snb5/igt@gem_eio@unwedge-stress.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#110854])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb1/igt@gem_exec_balancer@smoke.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb8/igt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_gttfill@basic:
> - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111593])
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb2/igt@gem_exec_gttfill@basic.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb6/igt@gem_exec_gttfill@basic.html
>
> * igt@gem_exec_schedule@preempt-queue-blt:
> - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111677])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb2/igt@gem_exec_schedule@preempt-queue-blt.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb8/igt@gem_exec_schedule@preempt-queue-blt.html
>
> * igt@gem_exec_schedule@preempt-queue-contexts-render:
> - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([fdo#111606] / [fdo#111677]) +1 similar issue
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-render.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb5/igt@gem_exec_schedule@preempt-queue-contexts-render.html
>
> * igt@gem_exec_schedule@reorder-wide-bsd:
> - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112146]) +4 similar issues
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
>
> * igt@gem_exec_schedule@smoketest-all:
> - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#463])
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb7/igt@gem_exec_schedule@smoketest-all.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb2/igt@gem_exec_schedule@smoketest-all.html
>
> * igt@gem_softpin@noreloc-s3:
> - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-apl7/igt@gem_softpin@noreloc-s3.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-apl4/igt@gem_softpin@noreloc-s3.html
>
> * igt@i915_pm_rps@waitboost:
> - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#413])
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@i915_pm_rps@waitboost.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@i915_pm_rps@waitboost.html
>
> * igt@i915_selftest@live_requests:
> - shard-tglb: [PASS][27] -> [INCOMPLETE][28] ([i915#472])
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb3/igt@i915_selftest@live_requests.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb3/igt@i915_selftest@live_requests.html
>
> * igt@kms_color@pipe-a-ctm-0-25:
> - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#109])
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-skl7/igt@kms_color@pipe-a-ctm-0-25.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-skl5/igt@kms_color@pipe-a-ctm-0-25.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
> - shard-tglb: [PASS][31] -> [FAIL][32] ([i915#49]) +3 similar issues
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
> - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([fdo#111764])
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
> - shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +5 similar issues
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
> - shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145])
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
>
> * igt@kms_psr@psr2_sprite_plane_move:
> - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +5 similar issues
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
>
> * igt@perf_pmu@enable-race-vcs0:
> - shard-tglb: [PASS][41] -> [INCOMPLETE][42] ([i915#480])
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb2/igt@perf_pmu@enable-race-vcs0.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb3/igt@perf_pmu@enable-race-vcs0.html
>
> * igt@prime_vgem@fence-wait-bsd2:
> - shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109276]) +10 similar issues
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html
>
>
> #### Possible fixes ####
>
> * igt@debugfs_test@read_all_entries_display_on:
> - shard-skl: [DMESG-WARN][45] ([i915#109]) -> [PASS][46] +1 similar issue
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-skl9/igt@debugfs_test@read_all_entries_display_on.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-skl8/igt@debugfs_test@read_all_entries_display_on.html
>
> * igt@gem_busy@extended-parallel-vcs1:
> - shard-iclb: [SKIP][47] ([fdo#112080]) -> [PASS][48] +6 similar issues
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb5/igt@gem_busy@extended-parallel-vcs1.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb4/igt@gem_busy@extended-parallel-vcs1.html
>
> * igt@gem_ctx_persistence@vcs1-queued:
> - shard-iclb: [SKIP][49] ([fdo#109276] / [fdo#112080]) -> [PASS][50] +6 similar issues
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@gem_ctx_persistence@vcs1-queued.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
>
> * igt@gem_exec_balancer@full-late:
> - shard-tglb: [INCOMPLETE][51] ([i915#435]) -> [PASS][52]
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb3/igt@gem_exec_balancer@full-late.html
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb8/igt@gem_exec_balancer@full-late.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-tglb: [INCOMPLETE][53] ([fdo#111593]) -> [PASS][54]
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb6/igt@gem_exec_balancer@smoke.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb6/igt@gem_exec_balancer@smoke.html
>
> * {igt@gem_exec_schedule@pi-distinct-iova-bsd}:
> - shard-iclb: [SKIP][55] ([i915#677]) -> [PASS][56] +1 similar issue
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
>
> * igt@gem_exec_schedule@preempt-other-chain-bsd:
> - shard-iclb: [SKIP][57] ([fdo#112146]) -> [PASS][58] +1 similar issue
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>
> * igt@gem_exec_schedule@preempt-queue-vebox:
> - shard-tglb: [INCOMPLETE][59] ([fdo#111677]) -> [PASS][60]
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb5/igt@gem_exec_schedule@preempt-queue-vebox.html
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb2/igt@gem_exec_schedule@preempt-queue-vebox.html
>
> * igt@gem_ppgtt@flink-and-close-vma-leak:
> - shard-glk: [FAIL][61] ([i915#644]) -> [PASS][62]
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html
>
> * igt@gem_sync@basic-many-each:
> - shard-tglb: [INCOMPLETE][63] ([i915#472] / [i915#707]) -> [PASS][64]
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb8/igt@gem_sync@basic-many-each.html
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb2/igt@gem_sync@basic-many-each.html
>
> * igt@i915_pm_dc@dc6-dpms:
> - shard-iclb: [FAIL][65] ([i915#454]) -> [PASS][66]
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html
>
> * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
> - shard-glk: [FAIL][67] ([i915#72]) -> [PASS][68]
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
>
> * igt@kms_flip@flip-vs-suspend:
> - shard-skl: [INCOMPLETE][69] ([i915#221]) -> [PASS][70]
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-skl2/igt@kms_flip@flip-vs-suspend.html
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-skl1/igt@kms_flip@flip-vs-suspend.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-kbl: [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +5 similar issues
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
> - shard-tglb: [FAIL][73] ([i915#49]) -> [PASS][74] +2 similar issues
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-apl: [DMESG-WARN][75] ([i915#180]) -> [PASS][76] +2 similar issues
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_psr@psr2_sprite_render:
> - shard-iclb: [SKIP][77] ([fdo#109441]) -> [PASS][78]
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@kms_psr@psr2_sprite_render.html
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
>
> * igt@kms_setmode@basic:
> - shard-apl: [FAIL][79] ([i915#31]) -> [PASS][80]
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-apl4/igt@kms_setmode@basic.html
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-apl3/igt@kms_setmode@basic.html
> - shard-kbl: [FAIL][81] ([i915#31]) -> [PASS][82]
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-kbl1/igt@kms_setmode@basic.html
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-kbl7/igt@kms_setmode@basic.html
>
> * igt@perf_pmu@enable-race-vecs0:
> - shard-tglb: [INCOMPLETE][83] ([i915#470]) -> [PASS][84]
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb8/igt@perf_pmu@enable-race-vecs0.html
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb3/igt@perf_pmu@enable-race-vecs0.html
>
> * igt@prime_busy@hang-bsd2:
> - shard-iclb: [SKIP][85] ([fdo#109276]) -> [PASS][86] +19 similar issues
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@prime_busy@hang-bsd2.html
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb2/igt@prime_busy@hang-bsd2.html
>
>
> #### Warnings ####
>
> * igt@gem_ctx_isolation@vcs1-nonpriv-switch:
> - shard-iclb: [FAIL][87] ([IGT#28]) -> [SKIP][88] ([fdo#109276] / [fdo#112080])
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
>
> * igt@gem_tiled_blits@normal:
> - shard-hsw: [FAIL][89] ([i915#832]) -> [FAIL][90] ([i915#818])
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-hsw6/igt@gem_tiled_blits@normal.html
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-hsw8/igt@gem_tiled_blits@normal.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-kbl: [FAIL][91] ([fdo#103375]) -> [DMESG-WARN][92] ([i915#180]) +1 similar issue
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
> [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
> [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
> [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
> [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
> [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
> [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
> [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
> [i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
> [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
> [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
> [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#463]: https://gitlab.freedesktop.org/drm/intel/issues/463
> [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
> [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
> [i915#480]: https://gitlab.freedesktop.org/drm/intel/issues/480
> [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
> [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
> [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
> [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
> [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
> [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
> [i915#832]: https://gitlab.freedesktop.org/drm/intel/issues/832
>
>
> Participating hosts (11 -> 11)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_7660 -> Patchwork_15961
>
> CI-20190529: 20190529
> CI_DRM_7660: 8e0504773b4e7f0102b6926d69db3dd58e6db52e @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5356: 62146738c68abfa7497b023a049163932f5a9aa0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_15961: 046f9d49ca43290bc9a2badbc533ee3ba1b588a5 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/index.html
_______________________________________________
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Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-31 23:37 [Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 1/7] drm/i915: Add support for non-power-of-2 FB plane alignment Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned Imre Deak
2020-01-02 14:12 ` Kahola, Mika
2019-12-31 23:37 ` [Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error Imre Deak
2020-01-02 11:50 ` Kahola, Mika
2019-12-31 23:37 ` [Intel-gfx] [PATCH 4/7] drm/i915: Make sure plane dims are correct for UV CCS planes Imre Deak
2020-01-02 13:48 ` Kahola, Mika
2019-12-31 23:37 ` [PATCH 5/7] drm/framebuffer: Format modifier for Intel Gen-12 media compression Imre Deak
2019-12-31 23:37 ` [Intel-gfx] " Imre Deak
2019-12-31 23:37 ` [PATCH 6/7] drm/fb: Extend format_info member arrays to handle four planes Imre Deak
2019-12-31 23:37 ` [Intel-gfx] " Imre Deak
2019-12-31 23:37 ` [Intel-gfx] [PATCH 7/7] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine Imre Deak
2020-01-06 15:58 ` Radhakrishna Sripada
2020-01-01 0:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Media decompression support Patchwork
2020-01-01 0:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-01 7:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-01-07 11:57 ` Imre Deak
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