* [PATCH 01/10] bnx2x: Set cache line based on build configuration
@ 2016-07-11 21:11 Chas Williams
2016-07-12 5:39 ` Harish Patil
0 siblings, 1 reply; 4+ messages in thread
From: Chas Williams @ 2016-07-11 21:11 UTC (permalink / raw)
To: dev; +Cc: harish.patil, Chas Williams
Correctly hint the cache line size. Remove unused macros associated
with the cache line size.
Fixes: 540a211084a7 ("bnx2x: driver core")
Signed-off-by: Chas Williams <3chas3@gmail.com>
---
drivers/net/bnx2x/bnx2x.h | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 135a6eb..852ec94 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -302,10 +302,7 @@ struct bnx2x_device_type {
/* TCP with Timestamp Option (32) + IPv6 (40) */
/* max supported alignment is 256 (8 shift) */
-#define BNX2X_RX_ALIGN_SHIFT 8
-/* FW uses 2 cache lines alignment for start packet and size */
-#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
-#define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT)
+#define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
--
2.5.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 01/10] bnx2x: Set cache line based on build configuration
2016-07-11 21:11 [PATCH 01/10] bnx2x: Set cache line based on build configuration Chas Williams
@ 2016-07-12 5:39 ` Harish Patil
2016-09-14 13:17 ` Ferruh Yigit
0 siblings, 1 reply; 4+ messages in thread
From: Harish Patil @ 2016-07-12 5:39 UTC (permalink / raw)
To: Chas Williams, dev
>
>Correctly hint the cache line size. Remove unused macros associated
>with the cache line size.
>
>Fixes: 540a211084a7 ("bnx2x: driver core")
>
>Signed-off-by: Chas Williams <3chas3@gmail.com>
>---
> drivers/net/bnx2x/bnx2x.h | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
>diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
>index 135a6eb..852ec94 100644
>--- a/drivers/net/bnx2x/bnx2x.h
>+++ b/drivers/net/bnx2x/bnx2x.h
>@@ -302,10 +302,7 @@ struct bnx2x_device_type {
> /* TCP with Timestamp Option (32) + IPv6 (40) */
>
> /* max supported alignment is 256 (8 shift) */
>-#define BNX2X_RX_ALIGN_SHIFT 8
>-/* FW uses 2 cache lines alignment for start packet and size */
>-#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
>-#define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT)
>+#define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
>
> #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
>
>--
>2.5.5
>
>
Acked-by: Harish Patil <harish.patil@qlogic.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 01/10] bnx2x: Set cache line based on build configuration
2016-07-12 5:39 ` Harish Patil
@ 2016-09-14 13:17 ` Ferruh Yigit
2016-09-30 14:36 ` Patil, Harish
0 siblings, 1 reply; 4+ messages in thread
From: Ferruh Yigit @ 2016-09-14 13:17 UTC (permalink / raw)
To: Harish Patil, Chas Williams, dev
Hi Harish,
On 7/12/2016 6:39 AM, Harish Patil wrote:
>>
>> Correctly hint the cache line size. Remove unused macros associated
>> with the cache line size.
>>
>> Fixes: 540a211084a7 ("bnx2x: driver core")
>>
>> Signed-off-by: Chas Williams <3chas3@gmail.com>
>> ---
>> drivers/net/bnx2x/bnx2x.h | 5 +----
>> 1 file changed, 1 insertion(+), 4 deletions(-)
>>
>> diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
>> index 135a6eb..852ec94 100644
>> --- a/drivers/net/bnx2x/bnx2x.h
>> +++ b/drivers/net/bnx2x/bnx2x.h
>> @@ -302,10 +302,7 @@ struct bnx2x_device_type {
>> /* TCP with Timestamp Option (32) + IPv6 (40) */
>>
>> /* max supported alignment is 256 (8 shift) */
>> -#define BNX2X_RX_ALIGN_SHIFT 8
>> -/* FW uses 2 cache lines alignment for start packet and size */
>> -#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
>> -#define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT)
>> +#define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
>>
>> #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
>>
>> --
>> 2.5.5
>>
>>
>
> Acked-by: Harish Patil <harish.patil@qlogic.com>
>
Is the Ack for this patch (01/10) or for the series?
Thanks,
ferruh
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 01/10] bnx2x: Set cache line based on build configuration
2016-09-14 13:17 ` Ferruh Yigit
@ 2016-09-30 14:36 ` Patil, Harish
0 siblings, 0 replies; 4+ messages in thread
From: Patil, Harish @ 2016-09-30 14:36 UTC (permalink / raw)
To: Ferruh Yigit, Harish Patil, Chas Williams, dev
>
>Hi Harish,
>
>On 7/12/2016 6:39 AM, Harish Patil wrote:
>>>
>>> Correctly hint the cache line size. Remove unused macros associated
>>> with the cache line size.
>>>
>>> Fixes: 540a211084a7 ("bnx2x: driver core")
>>>
>>> Signed-off-by: Chas Williams <3chas3@gmail.com>
>>> ---
>>> drivers/net/bnx2x/bnx2x.h | 5 +----
>>> 1 file changed, 1 insertion(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
>>> index 135a6eb..852ec94 100644
>>> --- a/drivers/net/bnx2x/bnx2x.h
>>> +++ b/drivers/net/bnx2x/bnx2x.h
>>> @@ -302,10 +302,7 @@ struct bnx2x_device_type {
>>> /* TCP with Timestamp Option (32) + IPv6 (40) */
>>>
>>> /* max supported alignment is 256 (8 shift) */
>>> -#define BNX2X_RX_ALIGN_SHIFT 8
>>> -/* FW uses 2 cache lines alignment for start packet and size */
>>> -#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
>>> -#define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT)
>>> +#define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8,
>>>RTE_CACHE_LINE_SIZE_LOG2))
>>>
>>> #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
>>>
>>> --
>>> 2.5.5
>>>
>>>
>>
>> Acked-by: Harish Patil <harish.patil@qlogic.com>
>>
>
>Is the Ack for this patch (01/10) or for the series?
>
>Thanks,
>ferruh
>
>
Hi Ferruh,
I meant it for only this patch.
Let me scan thru’ for the series and ack.
Thanks,
Harish
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-09-30 14:36 UTC | newest]
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2016-07-11 21:11 [PATCH 01/10] bnx2x: Set cache line based on build configuration Chas Williams
2016-07-12 5:39 ` Harish Patil
2016-09-14 13:17 ` Ferruh Yigit
2016-09-30 14:36 ` Patil, Harish
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