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* [PATCH 0/4] Add rt-thread art-pi board support
@ 2021-03-11  6:43 dillon.minfei at gmail.com
  2021-03-11  6:43 ` [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts dillon.minfei at gmail.com
                   ` (5 more replies)
  0 siblings, 6 replies; 12+ messages in thread
From: dillon.minfei at gmail.com @ 2021-03-11  6:43 UTC (permalink / raw)
  To: u-boot

From: dillon min <dillon.minfei@gmail.com>

These patches aim to adds u-boot support on art-pi board.

the board resources:
- stm32h750xbh6 128k flash, 1024k sram
- 32MiB sdram
- 16MiB spi flash
- 8MiB qspi flash
- onboard wifi, bt, fm

the detail board information can be found at:
https://art-pi.gitee.io/website/

dillon min (4):
  ARM: dts: stm32: split sdram pin & timing parameter into specific
    board dts
  ARM: dts: stm32: Add RT-Thread art-pi board support
  board: Add rt-thread art-pi board support
  ram: stm32: fix strsep failed on read only memory

 arch/arm/dts/Makefile                        |   3 +-
 arch/arm/dts/stm32h7-u-boot.dtsi             |  95 --------
 arch/arm/dts/stm32h743.dtsi                  |   8 +
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi    |  98 ++++++++
 arch/arm/dts/stm32h743i-eval-u-boot.dtsi     |  98 ++++++++
 arch/arm/dts/stm32h750-pinctrl.dtsi          | 319 +++++++++++++++++++++++++++
 arch/arm/dts/stm32h750.dtsi                  |   5 +
 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi   |  81 +++++++
 arch/arm/dts/stm32h750i-art-pi.dts           |  75 +++++++
 arch/arm/mach-stm32/stm32h7/Kconfig          |   4 +
 board/st/stm32h750-art-pi/Kconfig            |  19 ++
 board/st/stm32h750-art-pi/MAINTAINERS        |   7 +
 board/st/stm32h750-art-pi/Makefile           |   6 +
 board/st/stm32h750-art-pi/stm32h750-art-pi.c |  58 +++++
 configs/stm32h750-art-pi_defconfig           |  51 +++++
 drivers/ram/stm32_sdram.c                    |   3 +
 include/configs/stm32h750-art-pi.h           |  48 ++++
 include/dt-bindings/memory/stm32-sdram.h     |   2 +
 18 files changed, 884 insertions(+), 96 deletions(-)
 create mode 100644 arch/arm/dts/stm32h750-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32h750.dtsi
 create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts
 create mode 100644 board/st/stm32h750-art-pi/Kconfig
 create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
 create mode 100644 board/st/stm32h750-art-pi/Makefile
 create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
 create mode 100644 configs/stm32h750-art-pi_defconfig
 create mode 100644 include/configs/stm32h750-art-pi.h

-- 
2.7.4

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts
  2021-03-11  6:43 [PATCH 0/4] Add rt-thread art-pi board support dillon.minfei at gmail.com
@ 2021-03-11  6:43 ` dillon.minfei at gmail.com
  2021-03-25 14:46   ` Patrice CHOTARD
  2021-03-11  6:43 ` [PATCH 2/4] ARM: dts: stm32: Add RT-Thread art-pi board support dillon.minfei at gmail.com
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 12+ messages in thread
From: dillon.minfei at gmail.com @ 2021-03-11  6:43 UTC (permalink / raw)
  To: u-boot

From: dillon min <dillon.minfei@gmail.com>

As different boards has their own sdram hw connection, mount different
sdram modules, so move sdram timing parameter and pin configuration
to their board device tree.

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/dts/stm32h7-u-boot.dtsi          | 95 ------------------------------
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 98 +++++++++++++++++++++++++++++++
 arch/arm/dts/stm32h743i-eval-u-boot.dtsi  | 98 +++++++++++++++++++++++++++++++
 3 files changed, 196 insertions(+), 95 deletions(-)

diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 54dd406..e34d066 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -36,30 +36,6 @@
 			pinctrl-0 = <&fmc_pins>;
 			pinctrl-names = "default";
 			status = "okay";
-
-			/*
-			 * Memory configuration from sdram datasheet IS42S32800G-6BLI
-			 * first bank is bank at 0
-			 * second bank is bank at 1
-			 */
-			bank1: bank at 1 {
-				st,sdram-control = /bits/ 8 <NO_COL_9
-							     NO_ROW_12
-							     MWIDTH_32
-							     BANKS_4
-							     CAS_2
-							     SDCLK_3
-							     RD_BURST_EN
-							     RD_PIPE_DL_0>;
-				st,sdram-timing = /bits/ 8 <TMRD_1
-							    TXSR_1
-							    TRAS_1
-							    TRC_6
-							    TRP_2
-							    TWR_1
-							    TRCD_1>;
-				st,sdram-refcount = <1539>;
-			};
 		};
 	};
 };
@@ -136,77 +112,6 @@
 	compatible = "st,stm32-gpio";
 };
 
-&pinctrl {
-	fmc_pins: fmc at 0 {
-		pins {
-			pinmux = <STM32_PINMUX('D', 0, AF12)>,
-				 <STM32_PINMUX('D', 1, AF12)>,
-				 <STM32_PINMUX('D', 8, AF12)>,
-				 <STM32_PINMUX('D', 9, AF12)>,
-				 <STM32_PINMUX('D',10, AF12)>,
-				 <STM32_PINMUX('D',14, AF12)>,
-				 <STM32_PINMUX('D',15, AF12)>,
-
-				 <STM32_PINMUX('E', 0, AF12)>,
-				 <STM32_PINMUX('E', 1, AF12)>,
-				 <STM32_PINMUX('E', 7, AF12)>,
-				 <STM32_PINMUX('E', 8, AF12)>,
-				 <STM32_PINMUX('E', 9, AF12)>,
-				 <STM32_PINMUX('E',10, AF12)>,
-				 <STM32_PINMUX('E',11, AF12)>,
-				 <STM32_PINMUX('E',12, AF12)>,
-				 <STM32_PINMUX('E',13, AF12)>,
-				 <STM32_PINMUX('E',14, AF12)>,
-				 <STM32_PINMUX('E',15, AF12)>,
-
-				 <STM32_PINMUX('F', 0, AF12)>,
-				 <STM32_PINMUX('F', 1, AF12)>,
-				 <STM32_PINMUX('F', 2, AF12)>,
-				 <STM32_PINMUX('F', 3, AF12)>,
-				 <STM32_PINMUX('F', 4, AF12)>,
-				 <STM32_PINMUX('F', 5, AF12)>,
-				 <STM32_PINMUX('F',11, AF12)>,
-				 <STM32_PINMUX('F',12, AF12)>,
-				 <STM32_PINMUX('F',13, AF12)>,
-				 <STM32_PINMUX('F',14, AF12)>,
-				 <STM32_PINMUX('F',15, AF12)>,
-
-				 <STM32_PINMUX('G', 0, AF12)>,
-				 <STM32_PINMUX('G', 1, AF12)>,
-				 <STM32_PINMUX('G', 2, AF12)>,
-				 <STM32_PINMUX('G', 4, AF12)>,
-				 <STM32_PINMUX('G', 5, AF12)>,
-				 <STM32_PINMUX('G', 8, AF12)>,
-				 <STM32_PINMUX('G',15, AF12)>,
-
-				 <STM32_PINMUX('H', 5, AF12)>,
-				 <STM32_PINMUX('H', 6, AF12)>,
-				 <STM32_PINMUX('H', 7, AF12)>,
-				 <STM32_PINMUX('H', 8, AF12)>,
-				 <STM32_PINMUX('H', 9, AF12)>,
-				 <STM32_PINMUX('H',10, AF12)>,
-				 <STM32_PINMUX('H',11, AF12)>,
-				 <STM32_PINMUX('H',12, AF12)>,
-				 <STM32_PINMUX('H',13, AF12)>,
-				 <STM32_PINMUX('H',14, AF12)>,
-				 <STM32_PINMUX('H',15, AF12)>,
-
-				 <STM32_PINMUX('I', 0, AF12)>,
-				 <STM32_PINMUX('I', 1, AF12)>,
-				 <STM32_PINMUX('I', 2, AF12)>,
-				 <STM32_PINMUX('I', 3, AF12)>,
-				 <STM32_PINMUX('I', 4, AF12)>,
-				 <STM32_PINMUX('I', 5, AF12)>,
-				 <STM32_PINMUX('I', 6, AF12)>,
-				 <STM32_PINMUX('I', 7, AF12)>,
-				 <STM32_PINMUX('I', 9, AF12)>,
-				 <STM32_PINMUX('I',10, AF12)>;
-
-			slew-rate = <3>;
-		};
-	};
-};
-
 &pwrcfg {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
index 5965afc..02e28c6 100644
--- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
@@ -1,3 +1,101 @@
 // SPDX-License-Identifier: GPL-2.0+
 
 #include <stm32h7-u-boot.dtsi>
+
+&fmc {
+
+	/*
+	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
+	 * first bank is bank at 0
+	 * second bank is bank at 1
+	 */
+	bank1: bank at 1 {
+		st,sdram-control = /bits/ 8 <NO_COL_9
+					     NO_ROW_12
+					     MWIDTH_32
+					     BANKS_4
+					     CAS_2
+					     SDCLK_3
+					     RD_BURST_EN
+					     RD_PIPE_DL_0>;
+		st,sdram-timing = /bits/ 8 <TMRD_1
+					    TXSR_1
+					    TRAS_1
+					    TRC_6
+					    TRP_2
+					    TWR_1
+					    TRCD_1>;
+		st,sdram-refcount = <1539>;
+	};
+};
+
+&pinctrl {
+	fmc_pins: fmc at 0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 0, AF12)>,
+				 <STM32_PINMUX('D', 1, AF12)>,
+				 <STM32_PINMUX('D', 8, AF12)>,
+				 <STM32_PINMUX('D', 9, AF12)>,
+				 <STM32_PINMUX('D',10, AF12)>,
+				 <STM32_PINMUX('D',14, AF12)>,
+				 <STM32_PINMUX('D',15, AF12)>,
+
+				 <STM32_PINMUX('E', 0, AF12)>,
+				 <STM32_PINMUX('E', 1, AF12)>,
+				 <STM32_PINMUX('E', 7, AF12)>,
+				 <STM32_PINMUX('E', 8, AF12)>,
+				 <STM32_PINMUX('E', 9, AF12)>,
+				 <STM32_PINMUX('E',10, AF12)>,
+				 <STM32_PINMUX('E',11, AF12)>,
+				 <STM32_PINMUX('E',12, AF12)>,
+				 <STM32_PINMUX('E',13, AF12)>,
+				 <STM32_PINMUX('E',14, AF12)>,
+				 <STM32_PINMUX('E',15, AF12)>,
+
+				 <STM32_PINMUX('F', 0, AF12)>,
+				 <STM32_PINMUX('F', 1, AF12)>,
+				 <STM32_PINMUX('F', 2, AF12)>,
+				 <STM32_PINMUX('F', 3, AF12)>,
+				 <STM32_PINMUX('F', 4, AF12)>,
+				 <STM32_PINMUX('F', 5, AF12)>,
+				 <STM32_PINMUX('F',11, AF12)>,
+				 <STM32_PINMUX('F',12, AF12)>,
+				 <STM32_PINMUX('F',13, AF12)>,
+				 <STM32_PINMUX('F',14, AF12)>,
+				 <STM32_PINMUX('F',15, AF12)>,
+
+				 <STM32_PINMUX('G', 0, AF12)>,
+				 <STM32_PINMUX('G', 1, AF12)>,
+				 <STM32_PINMUX('G', 2, AF12)>,
+				 <STM32_PINMUX('G', 4, AF12)>,
+				 <STM32_PINMUX('G', 5, AF12)>,
+				 <STM32_PINMUX('G', 8, AF12)>,
+				 <STM32_PINMUX('G',15, AF12)>,
+
+				 <STM32_PINMUX('H', 5, AF12)>,
+				 <STM32_PINMUX('H', 6, AF12)>,
+				 <STM32_PINMUX('H', 7, AF12)>,
+				 <STM32_PINMUX('H', 8, AF12)>,
+				 <STM32_PINMUX('H', 9, AF12)>,
+				 <STM32_PINMUX('H',10, AF12)>,
+				 <STM32_PINMUX('H',11, AF12)>,
+				 <STM32_PINMUX('H',12, AF12)>,
+				 <STM32_PINMUX('H',13, AF12)>,
+				 <STM32_PINMUX('H',14, AF12)>,
+				 <STM32_PINMUX('H',15, AF12)>,
+
+				 <STM32_PINMUX('I', 0, AF12)>,
+				 <STM32_PINMUX('I', 1, AF12)>,
+				 <STM32_PINMUX('I', 2, AF12)>,
+				 <STM32_PINMUX('I', 3, AF12)>,
+				 <STM32_PINMUX('I', 4, AF12)>,
+				 <STM32_PINMUX('I', 5, AF12)>,
+				 <STM32_PINMUX('I', 6, AF12)>,
+				 <STM32_PINMUX('I', 7, AF12)>,
+				 <STM32_PINMUX('I', 9, AF12)>,
+				 <STM32_PINMUX('I',10, AF12)>;
+
+			slew-rate = <3>;
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
index 5965afc..02e28c6 100644
--- a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
@@ -1,3 +1,101 @@
 // SPDX-License-Identifier: GPL-2.0+
 
 #include <stm32h7-u-boot.dtsi>
+
+&fmc {
+
+	/*
+	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
+	 * first bank is bank at 0
+	 * second bank is bank at 1
+	 */
+	bank1: bank at 1 {
+		st,sdram-control = /bits/ 8 <NO_COL_9
+					     NO_ROW_12
+					     MWIDTH_32
+					     BANKS_4
+					     CAS_2
+					     SDCLK_3
+					     RD_BURST_EN
+					     RD_PIPE_DL_0>;
+		st,sdram-timing = /bits/ 8 <TMRD_1
+					    TXSR_1
+					    TRAS_1
+					    TRC_6
+					    TRP_2
+					    TWR_1
+					    TRCD_1>;
+		st,sdram-refcount = <1539>;
+	};
+};
+
+&pinctrl {
+	fmc_pins: fmc at 0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 0, AF12)>,
+				 <STM32_PINMUX('D', 1, AF12)>,
+				 <STM32_PINMUX('D', 8, AF12)>,
+				 <STM32_PINMUX('D', 9, AF12)>,
+				 <STM32_PINMUX('D',10, AF12)>,
+				 <STM32_PINMUX('D',14, AF12)>,
+				 <STM32_PINMUX('D',15, AF12)>,
+
+				 <STM32_PINMUX('E', 0, AF12)>,
+				 <STM32_PINMUX('E', 1, AF12)>,
+				 <STM32_PINMUX('E', 7, AF12)>,
+				 <STM32_PINMUX('E', 8, AF12)>,
+				 <STM32_PINMUX('E', 9, AF12)>,
+				 <STM32_PINMUX('E',10, AF12)>,
+				 <STM32_PINMUX('E',11, AF12)>,
+				 <STM32_PINMUX('E',12, AF12)>,
+				 <STM32_PINMUX('E',13, AF12)>,
+				 <STM32_PINMUX('E',14, AF12)>,
+				 <STM32_PINMUX('E',15, AF12)>,
+
+				 <STM32_PINMUX('F', 0, AF12)>,
+				 <STM32_PINMUX('F', 1, AF12)>,
+				 <STM32_PINMUX('F', 2, AF12)>,
+				 <STM32_PINMUX('F', 3, AF12)>,
+				 <STM32_PINMUX('F', 4, AF12)>,
+				 <STM32_PINMUX('F', 5, AF12)>,
+				 <STM32_PINMUX('F',11, AF12)>,
+				 <STM32_PINMUX('F',12, AF12)>,
+				 <STM32_PINMUX('F',13, AF12)>,
+				 <STM32_PINMUX('F',14, AF12)>,
+				 <STM32_PINMUX('F',15, AF12)>,
+
+				 <STM32_PINMUX('G', 0, AF12)>,
+				 <STM32_PINMUX('G', 1, AF12)>,
+				 <STM32_PINMUX('G', 2, AF12)>,
+				 <STM32_PINMUX('G', 4, AF12)>,
+				 <STM32_PINMUX('G', 5, AF12)>,
+				 <STM32_PINMUX('G', 8, AF12)>,
+				 <STM32_PINMUX('G',15, AF12)>,
+
+				 <STM32_PINMUX('H', 5, AF12)>,
+				 <STM32_PINMUX('H', 6, AF12)>,
+				 <STM32_PINMUX('H', 7, AF12)>,
+				 <STM32_PINMUX('H', 8, AF12)>,
+				 <STM32_PINMUX('H', 9, AF12)>,
+				 <STM32_PINMUX('H',10, AF12)>,
+				 <STM32_PINMUX('H',11, AF12)>,
+				 <STM32_PINMUX('H',12, AF12)>,
+				 <STM32_PINMUX('H',13, AF12)>,
+				 <STM32_PINMUX('H',14, AF12)>,
+				 <STM32_PINMUX('H',15, AF12)>,
+
+				 <STM32_PINMUX('I', 0, AF12)>,
+				 <STM32_PINMUX('I', 1, AF12)>,
+				 <STM32_PINMUX('I', 2, AF12)>,
+				 <STM32_PINMUX('I', 3, AF12)>,
+				 <STM32_PINMUX('I', 4, AF12)>,
+				 <STM32_PINMUX('I', 5, AF12)>,
+				 <STM32_PINMUX('I', 6, AF12)>,
+				 <STM32_PINMUX('I', 7, AF12)>,
+				 <STM32_PINMUX('I', 9, AF12)>,
+				 <STM32_PINMUX('I',10, AF12)>;
+
+			slew-rate = <3>;
+		};
+	};
+};
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 2/4] ARM: dts: stm32: Add RT-Thread art-pi board support
  2021-03-11  6:43 [PATCH 0/4] Add rt-thread art-pi board support dillon.minfei at gmail.com
  2021-03-11  6:43 ` [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts dillon.minfei at gmail.com
@ 2021-03-11  6:43 ` dillon.minfei at gmail.com
  2021-03-25 15:13   ` Patrice CHOTARD
  2021-03-11  6:43 ` [PATCH 3/4] board: Add rt-thread " dillon.minfei at gmail.com
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 12+ messages in thread
From: dillon.minfei at gmail.com @ 2021-03-11  6:43 UTC (permalink / raw)
  To: u-boot

From: dillon min <dillon.minfei@gmail.com>

All these files are add for support rt-thread art-pi board

the detail board information can be found at:
https://art-pi.gitee.io/website/

board resources:
- stm32h750xbh6 128k flash, 1024k sram
- 32MiB sdram
- 16MiB spi flash
- 8MiB qspi flash
- onboard wifi, bt, fm
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/dts/Makefile                      |   3 +-
 arch/arm/dts/stm32h743.dtsi                |   8 +
 arch/arm/dts/stm32h750-pinctrl.dtsi        | 319 +++++++++++++++++++++++++++++
 arch/arm/dts/stm32h750.dtsi                |   5 +
 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi |  81 ++++++++
 arch/arm/dts/stm32h750i-art-pi.dts         |  75 +++++++
 include/dt-bindings/memory/stm32-sdram.h   |   2 +
 7 files changed, 492 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/stm32h750-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32h750.dtsi
 create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c671082..0f54801 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -454,7 +454,8 @@ dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
 	stm32f769-disco.dtb \
 	stm32746g-eval.dtb
 dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
-	stm32h743i-eval.dtb
+	stm32h743i-eval.dtb \
+	stm32h750i-art-pi.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index e4e4723..bb3e2bf 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -99,6 +99,14 @@
 			clocks = <&rcc USART2_CK>;
 		};
 
+		uart4: serial at 40004c00 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <52>;
+			status = "disabled";
+			clocks = <&rcc UART4_CK>;
+		};
+
 		i2c1: i2c at 40005400 {
 			compatible = "st,stm32f7-i2c";
 			#address-cells = <1>;
diff --git a/arch/arm/dts/stm32h750-pinctrl.dtsi b/arch/arm/dts/stm32h750-pinctrl.dtsi
new file mode 100644
index 0000000..dd88ace
--- /dev/null
+++ b/arch/arm/dts/stm32h750-pinctrl.dtsi
@@ -0,0 +1,319 @@
+/*
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "st,stm32h743-pinctrl";
+			ranges = <0 0x58020000 0x3000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x8>;
+			pins-are-numbered;
+
+			gpioa: gpio at 58020000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x0 0x400>;
+				clocks = <&rcc GPIOA_CK>;
+				st,bank-name = "GPIOA";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiob: gpio at 58020400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x400 0x400>;
+				clocks = <&rcc GPIOB_CK>;
+				st,bank-name = "GPIOB";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioc: gpio at 58020800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x800 0x400>;
+				clocks = <&rcc GPIOC_CK>;
+				st,bank-name = "GPIOC";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiod: gpio at 58020c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0xc00 0x400>;
+				clocks = <&rcc GPIOD_CK>;
+				st,bank-name = "GPIOD";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioe: gpio at 58021000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1000 0x400>;
+				clocks = <&rcc GPIOE_CK>;
+				st,bank-name = "GPIOE";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiof: gpio at 58021400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1400 0x400>;
+				clocks = <&rcc GPIOF_CK>;
+				st,bank-name = "GPIOF";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiog: gpio at 58021800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1800 0x400>;
+				clocks = <&rcc GPIOG_CK>;
+				st,bank-name = "GPIOG";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioh: gpio at 58021c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1c00 0x400>;
+				clocks = <&rcc GPIOH_CK>;
+				st,bank-name = "GPIOH";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioi: gpio at 58022000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2000 0x400>;
+				clocks = <&rcc GPIOI_CK>;
+				st,bank-name = "GPIOI";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioj: gpio at 58022400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2400 0x400>;
+				clocks = <&rcc GPIOJ_CK>;
+				st,bank-name = "GPIOJ";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiok: gpio at 58022800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2800 0x400>;
+				clocks = <&rcc GPIOK_CK>;
+				st,bank-name = "GPIOK";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			i2c1_pins_a: i2c1-0 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
+						 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
+					bias-disable;
+					drive-open-drain;
+					slew-rate = <0>;
+				};
+			};
+
+			ethernet_rmii: rmii-0 {
+				pins {
+					pinmux = <STM32_PINMUX('G', 11, AF11)>,
+						 <STM32_PINMUX('G', 13, AF11)>,
+						 <STM32_PINMUX('G', 12, AF11)>,
+						 <STM32_PINMUX('C', 4, AF11)>,
+						 <STM32_PINMUX('C', 5, AF11)>,
+						 <STM32_PINMUX('A', 7, AF11)>,
+						 <STM32_PINMUX('C', 1, AF11)>,
+						 <STM32_PINMUX('A', 2, AF11)>,
+						 <STM32_PINMUX('A', 1, AF11)>;
+					slew-rate = <2>;
+				};
+			};
+
+			sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+					slew-rate = <3>;
+					drive-push-pull;
+					bias-disable;
+				};
+			};
+
+			sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+					slew-rate = <3>;
+					drive-push-pull;
+					bias-disable;
+				};
+				pins2{
+					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+					slew-rate = <3>;
+					drive-open-drain;
+					bias-disable;
+				};
+			};
+
+			sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+						 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+						 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+				};
+			};
+
+			sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
+						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+						 <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
+					slew-rate = <3>;
+					drive-push-pull;
+					bias-pull-up;
+				};
+				pins2{
+					pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
+					bias-pull-up;
+				};
+			};
+
+			sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
+						 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
+						 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+						 <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
+				};
+			};
+
+			usart1_pins: usart1-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
+					bias-disable;
+				};
+			};
+
+			usart2_pins: usart2-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
+					bias-disable;
+				};
+			};
+
+			uart4_pins: uart4-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
+					bias-disable;
+				};
+			};
+
+			usbotg_hs_pins_a: usbotg-hs-0 {
+				pins {
+					pinmux = <STM32_PINMUX('H', 4, AF10)>,	/* ULPI_NXT */
+							 <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
+							 <STM32_PINMUX('C', 0, AF10)>,	/* ULPI_STP> */
+							 <STM32_PINMUX('A', 5, AF10)>,	/* ULPI_CK> */
+							 <STM32_PINMUX('A', 3, AF10)>,	/* ULPI_D0> */
+							 <STM32_PINMUX('B', 0, AF10)>,	/* ULPI_D1> */
+							 <STM32_PINMUX('B', 1, AF10)>,	/* ULPI_D2> */
+							 <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
+							 <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
+							 <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
+							 <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
+							 <STM32_PINMUX('B', 5, AF10)>;	/* ULPI_D7> */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32h750.dtsi b/arch/arm/dts/stm32h750.dtsi
new file mode 100644
index 0000000..99533f3
--- /dev/null
+++ b/arch/arm/dts/stm32h750.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
+
+#include "stm32h743.dtsi"
+
diff --git a/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi b/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
new file mode 100644
index 0000000..326a553
--- /dev/null
+++ b/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32h7-u-boot.dtsi>
+
+&fmc {
+	/*
+	 * Memory configuration from sdram datasheet W9825G6KH
+	 * first bank is bank at 0
+	 * second bank is bank at 1
+	 */
+	bank1: bank at 0 {
+		st,sdram-control = /bits/ 8 <NO_COL_9
+					     NO_ROW_13
+					     MWIDTH_16
+					     BANKS_4
+					     CAS_2
+					     SDCLK_3
+					     RD_BURST_EN
+					     RD_PIPE_DL_0>;
+		st,sdram-timing = /bits/ 8 <TMRD_2
+					    TXSR_6
+					    TRAS_6
+					    TRC_6
+					    TRP_2
+					    TWR_2
+					    TRCD_2>;
+		st,sdram-refcount = <677>;
+	};
+};
+
+&pinctrl {
+	fmc_pins: fmc at 0 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 0, AF12)>,
+				 <STM32_PINMUX('D', 1, AF12)>,
+				 <STM32_PINMUX('D', 8, AF12)>,
+				 <STM32_PINMUX('D', 9, AF12)>,
+				 <STM32_PINMUX('D',10, AF12)>,
+				 <STM32_PINMUX('D',14, AF12)>,
+				 <STM32_PINMUX('D',15, AF12)>,
+
+				 <STM32_PINMUX('E', 0, AF12)>,
+				 <STM32_PINMUX('E', 1, AF12)>,
+				 <STM32_PINMUX('E', 7, AF12)>,
+				 <STM32_PINMUX('E', 8, AF12)>,
+				 <STM32_PINMUX('E', 9, AF12)>,
+				 <STM32_PINMUX('E',10, AF12)>,
+				 <STM32_PINMUX('E',11, AF12)>,
+				 <STM32_PINMUX('E',12, AF12)>,
+				 <STM32_PINMUX('E',13, AF12)>,
+				 <STM32_PINMUX('E',14, AF12)>,
+				 <STM32_PINMUX('E',15, AF12)>,
+
+				 <STM32_PINMUX('F', 0, AF12)>,
+				 <STM32_PINMUX('F', 1, AF12)>,
+				 <STM32_PINMUX('F', 2, AF12)>,
+				 <STM32_PINMUX('F', 3, AF12)>,
+				 <STM32_PINMUX('F', 4, AF12)>,
+				 <STM32_PINMUX('F', 5, AF12)>,
+				 <STM32_PINMUX('F',11, AF12)>,
+				 <STM32_PINMUX('F',12, AF12)>,
+				 <STM32_PINMUX('F',13, AF12)>,
+				 <STM32_PINMUX('F',14, AF12)>,
+				 <STM32_PINMUX('F',15, AF12)>,
+
+				 <STM32_PINMUX('G', 0, AF12)>,
+				 <STM32_PINMUX('G', 1, AF12)>,
+				 <STM32_PINMUX('G', 2, AF12)>,
+				 <STM32_PINMUX('G', 4, AF12)>,
+				 <STM32_PINMUX('G', 5, AF12)>,
+				 <STM32_PINMUX('G', 8, AF12)>,
+				 <STM32_PINMUX('G',15, AF12)>,
+
+				 <STM32_PINMUX('H', 5, AF12)>,
+				 <STM32_PINMUX('C', 2, AF12)>,
+				 <STM32_PINMUX('C', 3, AF12)>;
+
+			slew-rate = <3>;
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts
new file mode 100644
index 0000000..79e8ba5
--- /dev/null
+++ b/arch/arm/dts/stm32h750i-art-pi.dts
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
+ *
+ */
+
+/dts-v1/;
+#include "stm32h750.dtsi"
+#include "stm32h750-pinctrl.dtsi"
+
+/ {
+	model = "RT-Thread STM32H750i-Art-Pi board";
+	compatible = "st,stm32h750i-art-pi", "st,stm32h750";
+
+	chosen {
+		bootargs = "root=/dev/ram";
+		stdout-path = "serial0:2000000n8";
+	};
+
+	memory at c0000000 {
+		device_type = "memory";
+		reg = <0xc0000000 0x2000000>;
+	};
+
+	aliases {
+		serial0 = &uart4;
+	};
+
+	v3v3: regulator-v3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "v3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <25000000>;
+};
+
+&mac {
+	status = "disabled";
+	pinctrl-0	= <&ethernet_rmii>;
+	pinctrl-names	= "default";
+	phy-mode	= "rmii";
+	phy-handle	= <&phy0>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy0: ethernet-phy at 0 {
+			reg = <0>;
+		};
+	};
+};
+
+&sdmmc1 {
+	pinctrl-names = "default", "opendrain", "sleep";
+	pinctrl-0 = <&sdmmc1_b4_pins_a>;
+	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+	broken-cd;
+	st,neg-edge;
+	bus-width = <4>;
+	vmmc-supply = <&v3v3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-0 = <&uart4_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
index ab91d2b..90ef2e1 100644
--- a/include/dt-bindings/memory/stm32-sdram.h
+++ b/include/dt-bindings/memory/stm32-sdram.h
@@ -34,8 +34,10 @@
 #define TXSR_1		(1 - 1)
 #define TXSR_6		(6 - 1)
 #define TXSR_7		(7 - 1)
+#define TXSR_8		(8 - 1)
 #define TRAS_1		(1 - 1)
 #define TRAS_4		(4 - 1)
+#define TRAS_6		(6 - 1)
 #define TRC_6		(6 - 1)
 #define TWR_1		(1 - 1)
 #define TWR_2		(2 - 1)
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 3/4] board: Add rt-thread art-pi board support
  2021-03-11  6:43 [PATCH 0/4] Add rt-thread art-pi board support dillon.minfei at gmail.com
  2021-03-11  6:43 ` [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts dillon.minfei at gmail.com
  2021-03-11  6:43 ` [PATCH 2/4] ARM: dts: stm32: Add RT-Thread art-pi board support dillon.minfei at gmail.com
@ 2021-03-11  6:43 ` dillon.minfei at gmail.com
  2021-03-25 15:16   ` Patrice CHOTARD
  2021-03-11  6:44 ` [PATCH 4/4] ram: stm32: fix strsep failed on read only memory dillon.minfei at gmail.com
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 12+ messages in thread
From: dillon.minfei at gmail.com @ 2021-03-11  6:43 UTC (permalink / raw)
  To: u-boot

From: dillon min <dillon.minfei@gmail.com>

This patch adds support for rt-thread art-pi board.

for more information about art-pi, please goto:
https://art-pi.gitee.io/website/
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/mach-stm32/stm32h7/Kconfig          |  4 ++
 board/st/stm32h750-art-pi/Kconfig            | 19 +++++++++
 board/st/stm32h750-art-pi/MAINTAINERS        |  7 ++++
 board/st/stm32h750-art-pi/Makefile           |  6 +++
 board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58 ++++++++++++++++++++++++++++
 configs/stm32h750-art-pi_defconfig           | 51 ++++++++++++++++++++++++
 include/configs/stm32h750-art-pi.h           | 48 +++++++++++++++++++++++
 7 files changed, 193 insertions(+)
 create mode 100644 board/st/stm32h750-art-pi/Kconfig
 create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
 create mode 100644 board/st/stm32h750-art-pi/Makefile
 create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
 create mode 100644 configs/stm32h750-art-pi_defconfig
 create mode 100644 include/configs/stm32h750-art-pi.h

diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig b/arch/arm/mach-stm32/stm32h7/Kconfig
index 55e6217..70233a4 100644
--- a/arch/arm/mach-stm32/stm32h7/Kconfig
+++ b/arch/arm/mach-stm32/stm32h7/Kconfig
@@ -6,7 +6,11 @@ config TARGET_STM32H743_DISCO
 config TARGET_STM32H743_EVAL
 	bool "STM32H743 Evaluation board"
 
+config TARGET_STM32H750_ART_PI
+	bool "STM32H750 ART Pi board"
+
 source "board/st/stm32h743-eval/Kconfig"
 source "board/st/stm32h743-disco/Kconfig"
+source "board/st/stm32h750-art-pi/Kconfig"
 
 endif
diff --git a/board/st/stm32h750-art-pi/Kconfig b/board/st/stm32h750-art-pi/Kconfig
new file mode 100644
index 0000000..c31b984
--- /dev/null
+++ b/board/st/stm32h750-art-pi/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32H750_ART_PI
+
+config SYS_BOARD
+	string
+	default "stm32h750-art-pi"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32h7"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32h750-art-pi"
+
+endif
diff --git a/board/st/stm32h750-art-pi/MAINTAINERS b/board/st/stm32h750-art-pi/MAINTAINERS
new file mode 100644
index 0000000..9578833
--- /dev/null
+++ b/board/st/stm32h750-art-pi/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32H750 ART PI BOARD
+M:	Dillon Min <dillon.minfei@gmail.com>
+S:	Maintained
+F:	board/st/stm32h750-art-pi
+F:	include/configs/stm32h750-art-pi.h
+F:	configs/stm32h750-art-pi_defconfig
+F:	arch/arm/dts/stm32h7*
diff --git a/board/st/stm32h750-art-pi/Makefile b/board/st/stm32h750-art-pi/Makefile
new file mode 100644
index 0000000..a06de87
--- /dev/null
+++ b/board/st/stm32h750-art-pi/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021, RT-Thread - All Rights Reserved
+# Author(s): Dillon Min, <dillon.minfei@gmail.com> for RT-Thread.
+
+obj-y	:= stm32h750-art-pi.o
diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
new file mode 100644
index 0000000..405836a
--- /dev/null
+++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	if (fdtdec_setup_mem_size_base() != 0)
+		ret = -EINVAL;
+
+	return ret;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	return 0;
+}
diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig
new file mode 100644
index 0000000..a5c4cd7
--- /dev/null
+++ b/configs/stm32h750-art-pi_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32=y
+CONFIG_SYS_TEXT_BASE=0x90000000
+CONFIG_SYS_MALLOC_F_LEN=0xF00
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_STM32H7=y
+CONFIG_TARGET_STM32H750_ART_PI=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+CONFIG_DM_MMC=y
+CONFIG_STM32_SDMMC2=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_BAUDRATE=2000000
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttySTM0,2000000 root=/dev/ram rdinit=/linuxrc loglevel=8"
+CONFIG_BOOTCOMMAND="bootm 90080000"
+CONFIG_REQUIRE_SERIAL_CONSOLE=y
+CONFIG_SERIAL_PRESENT=y
+CONFIG_DM_SERIAL=y
+CONFIG_STM32_SERIAL=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x0
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_FIT_FULL_CHECK=y
+CONFIG_FIT_PRINT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_DM_DMA=y
diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h
new file mode 100644
index 0000000..55132ac
--- /dev/null
+++ b/include/configs/stm32h750-art-pi.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config.h>
+#include <linux/sizes.h>
+
+/* For booting Linux, use the first 16MB of memory */
+#define CONFIG_SYS_BOOTMAPSZ		(SZ_16M + SZ_8M)
+
+#define CONFIG_SYS_FLASH_BASE		0x90000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x24040000
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_LOAD_ADDR		0xC1800000
+#define CONFIG_LOADADDR			0xC1800000
+
+#define CONFIG_SYS_HZ_CLOCK		1000000
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+			"kernel_addr_r=0xC0008000\0"		\
+			"fdtfile=stm32h743i-disco.dtb\0"	\
+			"fdt_addr_r=0xC0408000\0"		\
+			"scriptaddr=0xC0418000\0"		\
+			"pxefile_addr_r=0xC0428000\0" \
+			"ramdisk_addr_r=0xC0438000\0"		\
+			BOOTENV
+
+#endif /* __CONFIG_H */
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 4/4] ram: stm32: fix strsep failed on read only memory
  2021-03-11  6:43 [PATCH 0/4] Add rt-thread art-pi board support dillon.minfei at gmail.com
                   ` (2 preceding siblings ...)
  2021-03-11  6:43 ` [PATCH 3/4] board: Add rt-thread " dillon.minfei at gmail.com
@ 2021-03-11  6:44 ` dillon.minfei at gmail.com
  2021-03-25 15:17   ` Patrice CHOTARD
  2021-03-22  8:28 ` [PATCH 0/4] Add rt-thread art-pi board support dillon min
  2021-03-25 14:40 ` Patrice CHOTARD
  5 siblings, 1 reply; 12+ messages in thread
From: dillon.minfei at gmail.com @ 2021-03-11  6:44 UTC (permalink / raw)
  To: u-boot

From: dillon min <dillon.minfei@gmail.com>

strsep will change data from original memory address,
in case the memory is in non-sdram/sram place, will
run into a bug(hang at SDRAM: )

just add a temporary array to store bank_name[] to fix this
bug.

Fixes: f303aaf ("ram: stm32: add second SDRAM bank management")
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 drivers/ram/stm32_sdram.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 540ad85..da27677 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -268,6 +268,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
 	u32 swp_fmc;
 	ofnode bank_node;
 	char *bank_name;
+	char _bank_name[128] = {0};
 	u8 bank = 0;
 	int ret;
 
@@ -300,6 +301,8 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
 	dev_for_each_subnode(bank_node, dev) {
 		/* extract the bank index from DT */
 		bank_name = (char *)ofnode_get_name(bank_node);
+		strcpy(_bank_name, bank_name);
+		bank_name = _bank_name;
 		strsep(&bank_name, "@");
 		if (!bank_name) {
 			pr_err("missing sdram bank index");
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 0/4] Add rt-thread art-pi board support
  2021-03-11  6:43 [PATCH 0/4] Add rt-thread art-pi board support dillon.minfei at gmail.com
                   ` (3 preceding siblings ...)
  2021-03-11  6:44 ` [PATCH 4/4] ram: stm32: fix strsep failed on read only memory dillon.minfei at gmail.com
@ 2021-03-22  8:28 ` dillon min
  2021-03-25 14:40 ` Patrice CHOTARD
  5 siblings, 0 replies; 12+ messages in thread
From: dillon min @ 2021-03-22  8:28 UTC (permalink / raw)
  To: u-boot

Hi,

Just a gentle ping.

On Thu, Mar 11, 2021 at 2:44 PM <dillon.minfei@gmail.com> wrote:
>
> From: dillon min <dillon.minfei@gmail.com>
>
> These patches aim to adds u-boot support on art-pi board.
>
> the board resources:
> - stm32h750xbh6 128k flash, 1024k sram
> - 32MiB sdram
> - 16MiB spi flash
> - 8MiB qspi flash
> - onboard wifi, bt, fm
>
> the detail board information can be found at:
> https://art-pi.gitee.io/website/
>
> dillon min (4):
>   ARM: dts: stm32: split sdram pin & timing parameter into specific
>     board dts
>   ARM: dts: stm32: Add RT-Thread art-pi board support
>   board: Add rt-thread art-pi board support
>   ram: stm32: fix strsep failed on read only memory
>
>  arch/arm/dts/Makefile                        |   3 +-
>  arch/arm/dts/stm32h7-u-boot.dtsi             |  95 --------
>  arch/arm/dts/stm32h743.dtsi                  |   8 +
>  arch/arm/dts/stm32h743i-disco-u-boot.dtsi    |  98 ++++++++
>  arch/arm/dts/stm32h743i-eval-u-boot.dtsi     |  98 ++++++++
>  arch/arm/dts/stm32h750-pinctrl.dtsi          | 319 +++++++++++++++++++++++++++
>  arch/arm/dts/stm32h750.dtsi                  |   5 +
>  arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi   |  81 +++++++
>  arch/arm/dts/stm32h750i-art-pi.dts           |  75 +++++++
>  arch/arm/mach-stm32/stm32h7/Kconfig          |   4 +
>  board/st/stm32h750-art-pi/Kconfig            |  19 ++
>  board/st/stm32h750-art-pi/MAINTAINERS        |   7 +
>  board/st/stm32h750-art-pi/Makefile           |   6 +
>  board/st/stm32h750-art-pi/stm32h750-art-pi.c |  58 +++++
>  configs/stm32h750-art-pi_defconfig           |  51 +++++
>  drivers/ram/stm32_sdram.c                    |   3 +
>  include/configs/stm32h750-art-pi.h           |  48 ++++
>  include/dt-bindings/memory/stm32-sdram.h     |   2 +
>  18 files changed, 884 insertions(+), 96 deletions(-)
>  create mode 100644 arch/arm/dts/stm32h750-pinctrl.dtsi
>  create mode 100644 arch/arm/dts/stm32h750.dtsi
>  create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts
>  create mode 100644 board/st/stm32h750-art-pi/Kconfig
>  create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
>  create mode 100644 board/st/stm32h750-art-pi/Makefile
>  create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
>  create mode 100644 configs/stm32h750-art-pi_defconfig
>  create mode 100644 include/configs/stm32h750-art-pi.h
>
> --
> 2.7.4
>

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 0/4] Add rt-thread art-pi board support
  2021-03-11  6:43 [PATCH 0/4] Add rt-thread art-pi board support dillon.minfei at gmail.com
                   ` (4 preceding siblings ...)
  2021-03-22  8:28 ` [PATCH 0/4] Add rt-thread art-pi board support dillon min
@ 2021-03-25 14:40 ` Patrice CHOTARD
  2021-03-26 10:26   ` dillon min
  5 siblings, 1 reply; 12+ messages in thread
From: Patrice CHOTARD @ 2021-03-25 14:40 UTC (permalink / raw)
  To: u-boot

Hi Dillon

One general remark, i saw that you have submitted a similar serie on kernel side
to add rt_thread art-pi board support.
On this kernel series, you split the DT pinctrl files by introducing stm32h7-pinctrl.dtsi file. 
Can you apply the same device tree files split between kernel and u-boot please.

The idea is that u-boot and kernel device tree files are in sync.

Thanks
Patrice



On 3/11/21 7:43 AM, dillon.minfei at gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> These patches aim to adds u-boot support on art-pi board.
> 
> the board resources:
> - stm32h750xbh6 128k flash, 1024k sram
> - 32MiB sdram
> - 16MiB spi flash
> - 8MiB qspi flash
> - onboard wifi, bt, fm
> 
> the detail board information can be found at:
> https://art-pi.gitee.io/website/
> 
> dillon min (4):
>   ARM: dts: stm32: split sdram pin & timing parameter into specific
>     board dts
>   ARM: dts: stm32: Add RT-Thread art-pi board support
>   board: Add rt-thread art-pi board support
>   ram: stm32: fix strsep failed on read only memory
> 
>  arch/arm/dts/Makefile                        |   3 +-
>  arch/arm/dts/stm32h7-u-boot.dtsi             |  95 --------
>  arch/arm/dts/stm32h743.dtsi                  |   8 +
>  arch/arm/dts/stm32h743i-disco-u-boot.dtsi    |  98 ++++++++
>  arch/arm/dts/stm32h743i-eval-u-boot.dtsi     |  98 ++++++++
>  arch/arm/dts/stm32h750-pinctrl.dtsi          | 319 +++++++++++++++++++++++++++
>  arch/arm/dts/stm32h750.dtsi                  |   5 +
>  arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi   |  81 +++++++
>  arch/arm/dts/stm32h750i-art-pi.dts           |  75 +++++++
>  arch/arm/mach-stm32/stm32h7/Kconfig          |   4 +
>  board/st/stm32h750-art-pi/Kconfig            |  19 ++
>  board/st/stm32h750-art-pi/MAINTAINERS        |   7 +
>  board/st/stm32h750-art-pi/Makefile           |   6 +
>  board/st/stm32h750-art-pi/stm32h750-art-pi.c |  58 +++++
>  configs/stm32h750-art-pi_defconfig           |  51 +++++
>  drivers/ram/stm32_sdram.c                    |   3 +
>  include/configs/stm32h750-art-pi.h           |  48 ++++
>  include/dt-bindings/memory/stm32-sdram.h     |   2 +
>  18 files changed, 884 insertions(+), 96 deletions(-)
>  create mode 100644 arch/arm/dts/stm32h750-pinctrl.dtsi
>  create mode 100644 arch/arm/dts/stm32h750.dtsi
>  create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts
>  create mode 100644 board/st/stm32h750-art-pi/Kconfig
>  create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
>  create mode 100644 board/st/stm32h750-art-pi/Makefile
>  create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
>  create mode 100644 configs/stm32h750-art-pi_defconfig
>  create mode 100644 include/configs/stm32h750-art-pi.h
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts
  2021-03-11  6:43 ` [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts dillon.minfei at gmail.com
@ 2021-03-25 14:46   ` Patrice CHOTARD
  0 siblings, 0 replies; 12+ messages in thread
From: Patrice CHOTARD @ 2021-03-25 14:46 UTC (permalink / raw)
  To: u-boot

Hi Dillon

On 3/11/21 7:43 AM, dillon.minfei at gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> As different boards has their own sdram hw connection, mount different
> sdram modules, so move sdram timing parameter and pin configuration
> to their board device tree.
> 
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>  arch/arm/dts/stm32h7-u-boot.dtsi          | 95 ------------------------------
>  arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 98 +++++++++++++++++++++++++++++++
>  arch/arm/dts/stm32h743i-eval-u-boot.dtsi  | 98 +++++++++++++++++++++++++++++++
>  3 files changed, 196 insertions(+), 95 deletions(-)
> 
> diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
> index 54dd406..e34d066 100644
> --- a/arch/arm/dts/stm32h7-u-boot.dtsi
> +++ b/arch/arm/dts/stm32h7-u-boot.dtsi
> @@ -36,30 +36,6 @@
>  			pinctrl-0 = <&fmc_pins>;
>  			pinctrl-names = "default";
>  			status = "okay";
> -
> -			/*
> -			 * Memory configuration from sdram datasheet IS42S32800G-6BLI
> -			 * first bank is bank at 0
> -			 * second bank is bank at 1
> -			 */
> -			bank1: bank at 1 {
> -				st,sdram-control = /bits/ 8 <NO_COL_9
> -							     NO_ROW_12
> -							     MWIDTH_32
> -							     BANKS_4
> -							     CAS_2
> -							     SDCLK_3
> -							     RD_BURST_EN
> -							     RD_PIPE_DL_0>;
> -				st,sdram-timing = /bits/ 8 <TMRD_1
> -							    TXSR_1
> -							    TRAS_1
> -							    TRC_6
> -							    TRP_2
> -							    TWR_1
> -							    TRCD_1>;
> -				st,sdram-refcount = <1539>;
> -			};
>  		};
>  	};
>  };
> @@ -136,77 +112,6 @@
>  	compatible = "st,stm32-gpio";
>  };
>  
> -&pinctrl {
> -	fmc_pins: fmc at 0 {
> -		pins {
> -			pinmux = <STM32_PINMUX('D', 0, AF12)>,
> -				 <STM32_PINMUX('D', 1, AF12)>,
> -				 <STM32_PINMUX('D', 8, AF12)>,
> -				 <STM32_PINMUX('D', 9, AF12)>,
> -				 <STM32_PINMUX('D',10, AF12)>,
> -				 <STM32_PINMUX('D',14, AF12)>,
> -				 <STM32_PINMUX('D',15, AF12)>,
> -
> -				 <STM32_PINMUX('E', 0, AF12)>,
> -				 <STM32_PINMUX('E', 1, AF12)>,
> -				 <STM32_PINMUX('E', 7, AF12)>,
> -				 <STM32_PINMUX('E', 8, AF12)>,
> -				 <STM32_PINMUX('E', 9, AF12)>,
> -				 <STM32_PINMUX('E',10, AF12)>,
> -				 <STM32_PINMUX('E',11, AF12)>,
> -				 <STM32_PINMUX('E',12, AF12)>,
> -				 <STM32_PINMUX('E',13, AF12)>,
> -				 <STM32_PINMUX('E',14, AF12)>,
> -				 <STM32_PINMUX('E',15, AF12)>,
> -
> -				 <STM32_PINMUX('F', 0, AF12)>,
> -				 <STM32_PINMUX('F', 1, AF12)>,
> -				 <STM32_PINMUX('F', 2, AF12)>,
> -				 <STM32_PINMUX('F', 3, AF12)>,
> -				 <STM32_PINMUX('F', 4, AF12)>,
> -				 <STM32_PINMUX('F', 5, AF12)>,
> -				 <STM32_PINMUX('F',11, AF12)>,
> -				 <STM32_PINMUX('F',12, AF12)>,
> -				 <STM32_PINMUX('F',13, AF12)>,
> -				 <STM32_PINMUX('F',14, AF12)>,
> -				 <STM32_PINMUX('F',15, AF12)>,
> -
> -				 <STM32_PINMUX('G', 0, AF12)>,
> -				 <STM32_PINMUX('G', 1, AF12)>,
> -				 <STM32_PINMUX('G', 2, AF12)>,
> -				 <STM32_PINMUX('G', 4, AF12)>,
> -				 <STM32_PINMUX('G', 5, AF12)>,
> -				 <STM32_PINMUX('G', 8, AF12)>,
> -				 <STM32_PINMUX('G',15, AF12)>,
> -
> -				 <STM32_PINMUX('H', 5, AF12)>,
> -				 <STM32_PINMUX('H', 6, AF12)>,
> -				 <STM32_PINMUX('H', 7, AF12)>,
> -				 <STM32_PINMUX('H', 8, AF12)>,
> -				 <STM32_PINMUX('H', 9, AF12)>,
> -				 <STM32_PINMUX('H',10, AF12)>,
> -				 <STM32_PINMUX('H',11, AF12)>,
> -				 <STM32_PINMUX('H',12, AF12)>,
> -				 <STM32_PINMUX('H',13, AF12)>,
> -				 <STM32_PINMUX('H',14, AF12)>,
> -				 <STM32_PINMUX('H',15, AF12)>,
> -
> -				 <STM32_PINMUX('I', 0, AF12)>,
> -				 <STM32_PINMUX('I', 1, AF12)>,
> -				 <STM32_PINMUX('I', 2, AF12)>,
> -				 <STM32_PINMUX('I', 3, AF12)>,
> -				 <STM32_PINMUX('I', 4, AF12)>,
> -				 <STM32_PINMUX('I', 5, AF12)>,
> -				 <STM32_PINMUX('I', 6, AF12)>,
> -				 <STM32_PINMUX('I', 7, AF12)>,
> -				 <STM32_PINMUX('I', 9, AF12)>,
> -				 <STM32_PINMUX('I',10, AF12)>;
> -
> -			slew-rate = <3>;
> -		};
> -	};
> -};
> -
>  &pwrcfg {
>  	u-boot,dm-pre-reloc;
>  };
> diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
> index 5965afc..02e28c6 100644
> --- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
> +++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
> @@ -1,3 +1,101 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  
>  #include <stm32h7-u-boot.dtsi>
> +
> +&fmc {
> +
> +	/*
> +	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
> +	 * first bank is bank at 0
> +	 * second bank is bank at 1
> +	 */
> +	bank1: bank at 1 {
> +		st,sdram-control = /bits/ 8 <NO_COL_9
> +					     NO_ROW_12
> +					     MWIDTH_32
> +					     BANKS_4
> +					     CAS_2
> +					     SDCLK_3
> +					     RD_BURST_EN
> +					     RD_PIPE_DL_0>;
> +		st,sdram-timing = /bits/ 8 <TMRD_1
> +					    TXSR_1
> +					    TRAS_1
> +					    TRC_6
> +					    TRP_2
> +					    TWR_1
> +					    TRCD_1>;
> +		st,sdram-refcount = <1539>;
> +	};
> +};
> +
> +&pinctrl {
> +	fmc_pins: fmc at 0 {
> +		pins {
> +			pinmux = <STM32_PINMUX('D', 0, AF12)>,
> +				 <STM32_PINMUX('D', 1, AF12)>,
> +				 <STM32_PINMUX('D', 8, AF12)>,
> +				 <STM32_PINMUX('D', 9, AF12)>,
> +				 <STM32_PINMUX('D',10, AF12)>,
> +				 <STM32_PINMUX('D',14, AF12)>,
> +				 <STM32_PINMUX('D',15, AF12)>,
> +
> +				 <STM32_PINMUX('E', 0, AF12)>,
> +				 <STM32_PINMUX('E', 1, AF12)>,
> +				 <STM32_PINMUX('E', 7, AF12)>,
> +				 <STM32_PINMUX('E', 8, AF12)>,
> +				 <STM32_PINMUX('E', 9, AF12)>,
> +				 <STM32_PINMUX('E',10, AF12)>,
> +				 <STM32_PINMUX('E',11, AF12)>,
> +				 <STM32_PINMUX('E',12, AF12)>,
> +				 <STM32_PINMUX('E',13, AF12)>,
> +				 <STM32_PINMUX('E',14, AF12)>,
> +				 <STM32_PINMUX('E',15, AF12)>,
> +
> +				 <STM32_PINMUX('F', 0, AF12)>,
> +				 <STM32_PINMUX('F', 1, AF12)>,
> +				 <STM32_PINMUX('F', 2, AF12)>,
> +				 <STM32_PINMUX('F', 3, AF12)>,
> +				 <STM32_PINMUX('F', 4, AF12)>,
> +				 <STM32_PINMUX('F', 5, AF12)>,
> +				 <STM32_PINMUX('F',11, AF12)>,
> +				 <STM32_PINMUX('F',12, AF12)>,
> +				 <STM32_PINMUX('F',13, AF12)>,
> +				 <STM32_PINMUX('F',14, AF12)>,
> +				 <STM32_PINMUX('F',15, AF12)>,
> +
> +				 <STM32_PINMUX('G', 0, AF12)>,
> +				 <STM32_PINMUX('G', 1, AF12)>,
> +				 <STM32_PINMUX('G', 2, AF12)>,
> +				 <STM32_PINMUX('G', 4, AF12)>,
> +				 <STM32_PINMUX('G', 5, AF12)>,
> +				 <STM32_PINMUX('G', 8, AF12)>,
> +				 <STM32_PINMUX('G',15, AF12)>,
> +
> +				 <STM32_PINMUX('H', 5, AF12)>,
> +				 <STM32_PINMUX('H', 6, AF12)>,
> +				 <STM32_PINMUX('H', 7, AF12)>,
> +				 <STM32_PINMUX('H', 8, AF12)>,
> +				 <STM32_PINMUX('H', 9, AF12)>,
> +				 <STM32_PINMUX('H',10, AF12)>,
> +				 <STM32_PINMUX('H',11, AF12)>,
> +				 <STM32_PINMUX('H',12, AF12)>,
> +				 <STM32_PINMUX('H',13, AF12)>,
> +				 <STM32_PINMUX('H',14, AF12)>,
> +				 <STM32_PINMUX('H',15, AF12)>,
> +
> +				 <STM32_PINMUX('I', 0, AF12)>,
> +				 <STM32_PINMUX('I', 1, AF12)>,
> +				 <STM32_PINMUX('I', 2, AF12)>,
> +				 <STM32_PINMUX('I', 3, AF12)>,
> +				 <STM32_PINMUX('I', 4, AF12)>,
> +				 <STM32_PINMUX('I', 5, AF12)>,
> +				 <STM32_PINMUX('I', 6, AF12)>,
> +				 <STM32_PINMUX('I', 7, AF12)>,
> +				 <STM32_PINMUX('I', 9, AF12)>,
> +				 <STM32_PINMUX('I',10, AF12)>;
> +
> +			slew-rate = <3>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
> index 5965afc..02e28c6 100644
> --- a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
> +++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
> @@ -1,3 +1,101 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  
>  #include <stm32h7-u-boot.dtsi>
> +
> +&fmc {
> +
> +	/*
> +	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
> +	 * first bank is bank at 0
> +	 * second bank is bank at 1
> +	 */
> +	bank1: bank at 1 {
> +		st,sdram-control = /bits/ 8 <NO_COL_9
> +					     NO_ROW_12
> +					     MWIDTH_32
> +					     BANKS_4
> +					     CAS_2
> +					     SDCLK_3
> +					     RD_BURST_EN
> +					     RD_PIPE_DL_0>;
> +		st,sdram-timing = /bits/ 8 <TMRD_1
> +					    TXSR_1
> +					    TRAS_1
> +					    TRC_6
> +					    TRP_2
> +					    TWR_1
> +					    TRCD_1>;
> +		st,sdram-refcount = <1539>;
> +	};
> +};
> +
> +&pinctrl {
> +	fmc_pins: fmc at 0 {
> +		pins {
> +			pinmux = <STM32_PINMUX('D', 0, AF12)>,
> +				 <STM32_PINMUX('D', 1, AF12)>,
> +				 <STM32_PINMUX('D', 8, AF12)>,
> +				 <STM32_PINMUX('D', 9, AF12)>,
> +				 <STM32_PINMUX('D',10, AF12)>,
> +				 <STM32_PINMUX('D',14, AF12)>,
> +				 <STM32_PINMUX('D',15, AF12)>,
> +
> +				 <STM32_PINMUX('E', 0, AF12)>,
> +				 <STM32_PINMUX('E', 1, AF12)>,
> +				 <STM32_PINMUX('E', 7, AF12)>,
> +				 <STM32_PINMUX('E', 8, AF12)>,
> +				 <STM32_PINMUX('E', 9, AF12)>,
> +				 <STM32_PINMUX('E',10, AF12)>,
> +				 <STM32_PINMUX('E',11, AF12)>,
> +				 <STM32_PINMUX('E',12, AF12)>,
> +				 <STM32_PINMUX('E',13, AF12)>,
> +				 <STM32_PINMUX('E',14, AF12)>,
> +				 <STM32_PINMUX('E',15, AF12)>,
> +
> +				 <STM32_PINMUX('F', 0, AF12)>,
> +				 <STM32_PINMUX('F', 1, AF12)>,
> +				 <STM32_PINMUX('F', 2, AF12)>,
> +				 <STM32_PINMUX('F', 3, AF12)>,
> +				 <STM32_PINMUX('F', 4, AF12)>,
> +				 <STM32_PINMUX('F', 5, AF12)>,
> +				 <STM32_PINMUX('F',11, AF12)>,
> +				 <STM32_PINMUX('F',12, AF12)>,
> +				 <STM32_PINMUX('F',13, AF12)>,
> +				 <STM32_PINMUX('F',14, AF12)>,
> +				 <STM32_PINMUX('F',15, AF12)>,
> +
> +				 <STM32_PINMUX('G', 0, AF12)>,
> +				 <STM32_PINMUX('G', 1, AF12)>,
> +				 <STM32_PINMUX('G', 2, AF12)>,
> +				 <STM32_PINMUX('G', 4, AF12)>,
> +				 <STM32_PINMUX('G', 5, AF12)>,
> +				 <STM32_PINMUX('G', 8, AF12)>,
> +				 <STM32_PINMUX('G',15, AF12)>,
> +
> +				 <STM32_PINMUX('H', 5, AF12)>,
> +				 <STM32_PINMUX('H', 6, AF12)>,
> +				 <STM32_PINMUX('H', 7, AF12)>,
> +				 <STM32_PINMUX('H', 8, AF12)>,
> +				 <STM32_PINMUX('H', 9, AF12)>,
> +				 <STM32_PINMUX('H',10, AF12)>,
> +				 <STM32_PINMUX('H',11, AF12)>,
> +				 <STM32_PINMUX('H',12, AF12)>,
> +				 <STM32_PINMUX('H',13, AF12)>,
> +				 <STM32_PINMUX('H',14, AF12)>,
> +				 <STM32_PINMUX('H',15, AF12)>,
> +
> +				 <STM32_PINMUX('I', 0, AF12)>,
> +				 <STM32_PINMUX('I', 1, AF12)>,
> +				 <STM32_PINMUX('I', 2, AF12)>,
> +				 <STM32_PINMUX('I', 3, AF12)>,
> +				 <STM32_PINMUX('I', 4, AF12)>,
> +				 <STM32_PINMUX('I', 5, AF12)>,
> +				 <STM32_PINMUX('I', 6, AF12)>,
> +				 <STM32_PINMUX('I', 7, AF12)>,
> +				 <STM32_PINMUX('I', 9, AF12)>,
> +				 <STM32_PINMUX('I',10, AF12)>;
> +
> +			slew-rate = <3>;
> +		};
> +	};
> +};
> 

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 2/4] ARM: dts: stm32: Add RT-Thread art-pi board support
  2021-03-11  6:43 ` [PATCH 2/4] ARM: dts: stm32: Add RT-Thread art-pi board support dillon.minfei at gmail.com
@ 2021-03-25 15:13   ` Patrice CHOTARD
  0 siblings, 0 replies; 12+ messages in thread
From: Patrice CHOTARD @ 2021-03-25 15:13 UTC (permalink / raw)
  To: u-boot

Some remarks below

On 3/11/21 7:43 AM, dillon.minfei at gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> All these files are add for support rt-thread art-pi board
> 
> the detail board information can be found at:
> https://art-pi.gitee.io/website/
> 
> board resources:
> - stm32h750xbh6 128k flash, 1024k sram
> - 32MiB sdram
> - 16MiB spi flash
> - 8MiB qspi flash
> - onboard wifi, bt, fm
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>  arch/arm/dts/Makefile                      |   3 +-
>  arch/arm/dts/stm32h743.dtsi                |   8 +
>  arch/arm/dts/stm32h750-pinctrl.dtsi        | 319 +++++++++++++++++++++++++++++
>  arch/arm/dts/stm32h750.dtsi                |   5 +
>  arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi |  81 ++++++++
>  arch/arm/dts/stm32h750i-art-pi.dts         |  75 +++++++
>  include/dt-bindings/memory/stm32-sdram.h   |   2 +
>  7 files changed, 492 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/stm32h750-pinctrl.dtsi
>  create mode 100644 arch/arm/dts/stm32h750.dtsi
>  create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index c671082..0f54801 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -454,7 +454,8 @@ dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
>  	stm32f769-disco.dtb \
>  	stm32746g-eval.dtb
>  dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
> -	stm32h743i-eval.dtb
> +	stm32h743i-eval.dtb \
> +	stm32h750i-art-pi.dtb
>  
>  dtb-$(CONFIG_MACH_SUN4I) += \
>  	sun4i-a10-a1000.dtb \
> diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
> index e4e4723..bb3e2bf 100644
> --- a/arch/arm/dts/stm32h743.dtsi
> +++ b/arch/arm/dts/stm32h743.dtsi
> @@ -99,6 +99,14 @@
>  			clocks = <&rcc USART2_CK>;
>  		};
>  
> +		uart4: serial at 40004c00 {
> +			compatible = "st,stm32h7-uart";
> +			reg = <0x40004c00 0x400>;
> +			interrupts = <52>;
> +			status = "disabled";
> +			clocks = <&rcc UART4_CK>;
> +		};
> +
>  		i2c1: i2c at 40005400 {
>  			compatible = "st,stm32f7-i2c";
>  			#address-cells = <1>;
> diff --git a/arch/arm/dts/stm32h750-pinctrl.dtsi b/arch/arm/dts/stm32h750-pinctrl.dtsi
> new file mode 100644
> index 0000000..dd88ace
> --- /dev/null
> +++ b/arch/arm/dts/stm32h750-pinctrl.dtsi
> @@ -0,0 +1,319 @@
> +/*
> + * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
> + *


Should be your name here. But this file should be replaced by the kernel version as i explained in the cover-letter

> diff --git a/arch/arm/dts/stm32h750.dtsi b/arch/arm/dts/stm32h750.dtsi
> new file mode 100644
> index 0000000..99533f3
> --- /dev/null
> +++ b/arch/arm/dts/stm32h750.dtsi
> @@ -0,0 +1,5 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
> +
> +#include "stm32h743.dtsi"
> +
> diff --git a/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi b/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
> new file mode 100644
> index 0000000..326a553
> --- /dev/null
> +++ b/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <stm32h7-u-boot.dtsi>
> +
> +&fmc {
> +	/*
> +	 * Memory configuration from sdram datasheet W9825G6KH
> +	 * first bank is bank at 0
> +	 * second bank is bank at 1
> +	 */
> +	bank1: bank at 0 {
> +		st,sdram-control = /bits/ 8 <NO_COL_9
> +					     NO_ROW_13
> +					     MWIDTH_16
> +					     BANKS_4
> +					     CAS_2
> +					     SDCLK_3
> +					     RD_BURST_EN
> +					     RD_PIPE_DL_0>;
> +		st,sdram-timing = /bits/ 8 <TMRD_2
> +					    TXSR_6
> +					    TRAS_6
> +					    TRC_6
> +					    TRP_2
> +					    TWR_2
> +					    TRCD_2>;
> +		st,sdram-refcount = <677>;
> +	};
> +};
> +
> +&pinctrl {
> +	fmc_pins: fmc at 0 {
> +		pins {
> +			pinmux = <STM32_PINMUX('D', 0, AF12)>,
> +				 <STM32_PINMUX('D', 1, AF12)>,
> +				 <STM32_PINMUX('D', 8, AF12)>,
> +				 <STM32_PINMUX('D', 9, AF12)>,
> +				 <STM32_PINMUX('D',10, AF12)>,
> +				 <STM32_PINMUX('D',14, AF12)>,
> +				 <STM32_PINMUX('D',15, AF12)>,
> +
> +				 <STM32_PINMUX('E', 0, AF12)>,
> +				 <STM32_PINMUX('E', 1, AF12)>,
> +				 <STM32_PINMUX('E', 7, AF12)>,
> +				 <STM32_PINMUX('E', 8, AF12)>,
> +				 <STM32_PINMUX('E', 9, AF12)>,
> +				 <STM32_PINMUX('E',10, AF12)>,
> +				 <STM32_PINMUX('E',11, AF12)>,
> +				 <STM32_PINMUX('E',12, AF12)>,
> +				 <STM32_PINMUX('E',13, AF12)>,
> +				 <STM32_PINMUX('E',14, AF12)>,
> +				 <STM32_PINMUX('E',15, AF12)>,
> +
> +				 <STM32_PINMUX('F', 0, AF12)>,
> +				 <STM32_PINMUX('F', 1, AF12)>,
> +				 <STM32_PINMUX('F', 2, AF12)>,
> +				 <STM32_PINMUX('F', 3, AF12)>,
> +				 <STM32_PINMUX('F', 4, AF12)>,
> +				 <STM32_PINMUX('F', 5, AF12)>,
> +				 <STM32_PINMUX('F',11, AF12)>,
> +				 <STM32_PINMUX('F',12, AF12)>,
> +				 <STM32_PINMUX('F',13, AF12)>,
> +				 <STM32_PINMUX('F',14, AF12)>,
> +				 <STM32_PINMUX('F',15, AF12)>,
> +
> +				 <STM32_PINMUX('G', 0, AF12)>,
> +				 <STM32_PINMUX('G', 1, AF12)>,
> +				 <STM32_PINMUX('G', 2, AF12)>,
> +				 <STM32_PINMUX('G', 4, AF12)>,
> +				 <STM32_PINMUX('G', 5, AF12)>,
> +				 <STM32_PINMUX('G', 8, AF12)>,
> +				 <STM32_PINMUX('G',15, AF12)>,
> +
> +				 <STM32_PINMUX('H', 5, AF12)>,
> +				 <STM32_PINMUX('C', 2, AF12)>,
> +				 <STM32_PINMUX('C', 3, AF12)>;
> +
> +			slew-rate = <3>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts
> new file mode 100644
> index 0000000..79e8ba5
> --- /dev/null
> +++ b/arch/arm/dts/stm32h750i-art-pi.dts
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +/*
> + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
> + *
> + */
> +
> +/dts-v1/;
> +#include "stm32h750.dtsi"
> +#include "stm32h750-pinctrl.dtsi"
> +
> +/ {
> +	model = "RT-Thread STM32H750i-Art-Pi board";
> +	compatible = "st,stm32h750i-art-pi", "st,stm32h750";
> +
> +	chosen {
> +		bootargs = "root=/dev/ram";
> +		stdout-path = "serial0:2000000n8";
> +	};
> +
> +	memory at c0000000 {
> +		device_type = "memory";
> +		reg = <0xc0000000 0x2000000>;
> +	};
> +
> +	aliases {
> +		serial0 = &uart4;
> +	};
> +
> +	v3v3: regulator-v3v3 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "v3v3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +	};
> +};
> +
> +&clk_hse {
> +	clock-frequency = <25000000>;
> +};
> +
> +&mac {
> +	status = "disabled";
> +	pinctrl-0	= <&ethernet_rmii>;
> +	pinctrl-names	= "default";
> +	phy-mode	= "rmii";
> +	phy-handle	= <&phy0>;
> +
> +	mdio0 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "snps,dwmac-mdio";
> +		phy0: ethernet-phy at 0 {
> +			reg = <0>;
> +		};
> +	};
> +};
> +
> +&sdmmc1 {
> +	pinctrl-names = "default", "opendrain", "sleep";
> +	pinctrl-0 = <&sdmmc1_b4_pins_a>;
> +	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
> +	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> +	broken-cd;
> +	st,neg-edge;
> +	bus-width = <4>;
> +	vmmc-supply = <&v3v3>;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-0 = <&uart4_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
> index ab91d2b..90ef2e1 100644
> --- a/include/dt-bindings/memory/stm32-sdram.h
> +++ b/include/dt-bindings/memory/stm32-sdram.h
> @@ -34,8 +34,10 @@
>  #define TXSR_1		(1 - 1)
>  #define TXSR_6		(6 - 1)
>  #define TXSR_7		(7 - 1)
> +#define TXSR_8		(8 - 1)
>  #define TRAS_1		(1 - 1)
>  #define TRAS_4		(4 - 1)
> +#define TRAS_6		(6 - 1)
>  #define TRC_6		(6 - 1)
>  #define TWR_1		(1 - 1)
>  #define TWR_2		(2 - 1)
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 3/4] board: Add rt-thread art-pi board support
  2021-03-11  6:43 ` [PATCH 3/4] board: Add rt-thread " dillon.minfei at gmail.com
@ 2021-03-25 15:16   ` Patrice CHOTARD
  0 siblings, 0 replies; 12+ messages in thread
From: Patrice CHOTARD @ 2021-03-25 15:16 UTC (permalink / raw)
  To: u-boot

Hi Dillon

some remarks below

On 3/11/21 7:43 AM, dillon.minfei at gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> This patch adds support for rt-thread art-pi board.
> 
> for more information about art-pi, please goto:
> https://art-pi.gitee.io/website/
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>  arch/arm/mach-stm32/stm32h7/Kconfig          |  4 ++
>  board/st/stm32h750-art-pi/Kconfig            | 19 +++++++++
>  board/st/stm32h750-art-pi/MAINTAINERS        |  7 ++++
>  board/st/stm32h750-art-pi/Makefile           |  6 +++
>  board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58 ++++++++++++++++++++++++++++
>  configs/stm32h750-art-pi_defconfig           | 51 ++++++++++++++++++++++++
>  include/configs/stm32h750-art-pi.h           | 48 +++++++++++++++++++++++
>  7 files changed, 193 insertions(+)
>  create mode 100644 board/st/stm32h750-art-pi/Kconfig
>  create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
>  create mode 100644 board/st/stm32h750-art-pi/Makefile
>  create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
>  create mode 100644 configs/stm32h750-art-pi_defconfig
>  create mode 100644 include/configs/stm32h750-art-pi.h
> 
> diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig b/arch/arm/mach-stm32/stm32h7/Kconfig
> index 55e6217..70233a4 100644
> --- a/arch/arm/mach-stm32/stm32h7/Kconfig
> +++ b/arch/arm/mach-stm32/stm32h7/Kconfig
> @@ -6,7 +6,11 @@ config TARGET_STM32H743_DISCO
>  config TARGET_STM32H743_EVAL
>  	bool "STM32H743 Evaluation board"
>  
> +config TARGET_STM32H750_ART_PI
> +	bool "STM32H750 ART Pi board"
> +
>  source "board/st/stm32h743-eval/Kconfig"
>  source "board/st/stm32h743-disco/Kconfig"
> +source "board/st/stm32h750-art-pi/Kconfig"
>  
>  endif
> diff --git a/board/st/stm32h750-art-pi/Kconfig b/board/st/stm32h750-art-pi/Kconfig
> new file mode 100644
> index 0000000..c31b984
> --- /dev/null
> +++ b/board/st/stm32h750-art-pi/Kconfig
> @@ -0,0 +1,19 @@
> +if TARGET_STM32H750_ART_PI
> +
> +config SYS_BOARD
> +	string
> +	default "stm32h750-art-pi"
> +
> +config SYS_VENDOR
> +	string
> +	default "st"
> +
> +config SYS_SOC
> +	string
> +	default "stm32h7"
> +
> +config SYS_CONFIG_NAME
> +	string
> +	default "stm32h750-art-pi"
> +
> +endif
> diff --git a/board/st/stm32h750-art-pi/MAINTAINERS b/board/st/stm32h750-art-pi/MAINTAINERS
> new file mode 100644
> index 0000000..9578833
> --- /dev/null
> +++ b/board/st/stm32h750-art-pi/MAINTAINERS
> @@ -0,0 +1,7 @@
> +STM32H750 ART PI BOARD
> +M:	Dillon Min <dillon.minfei@gmail.com>
> +S:	Maintained
> +F:	board/st/stm32h750-art-pi
> +F:	include/configs/stm32h750-art-pi.h
> +F:	configs/stm32h750-art-pi_defconfig
> +F:	arch/arm/dts/stm32h7*
> diff --git a/board/st/stm32h750-art-pi/Makefile b/board/st/stm32h750-art-pi/Makefile
> new file mode 100644
> index 0000000..a06de87
> --- /dev/null
> +++ b/board/st/stm32h750-art-pi/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2021, RT-Thread - All Rights Reserved
> +# Author(s): Dillon Min, <dillon.minfei@gmail.com> for RT-Thread.
> +
> +obj-y	:= stm32h750-art-pi.o
> diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
> new file mode 100644
> index 0000000..405836a
> --- /dev/null
> +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
> + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.

Update with 2021 and with your name.

> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <init.h>
> +#include <log.h>
> +#include <asm/global_data.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> +	struct udevice *dev;
> +	int ret;
> +
> +	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> +	if (ret) {
> +		debug("DRAM init failed: %d\n", ret);
> +		return ret;
> +	}
> +
> +	if (fdtdec_setup_mem_size_base() != 0)
> +		ret = -EINVAL;
> +
> +	return ret;
> +}
> +
> +int dram_init_banksize(void)
> +{
> +	fdtdec_setup_memory_banksize();
> +
> +	return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> +	return 0;
> +}
> +
> +u32 get_board_rev(void)
> +{
> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
> +	return 0;
> +}
> diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig
> new file mode 100644
> index 0000000..a5c4cd7
> --- /dev/null
> +++ b/configs/stm32h750-art-pi_defconfig
> @@ -0,0 +1,51 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_STM32=y
> +CONFIG_SYS_TEXT_BASE=0x90000000
> +CONFIG_SYS_MALLOC_F_LEN=0xF00
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_ENV_SIZE=0x2000
> +CONFIG_STM32H7=y
> +CONFIG_TARGET_STM32H750_ART_PI=y
> +CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_AUTOBOOT_KEYED=y
> +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
> +CONFIG_AUTOBOOT_STOP_STR=" "
> +# CONFIG_USE_BOOTCOMMAND is not set
> +CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_BOARD_LATE_INIT=y
> +CONFIG_SYS_PROMPT="U-Boot > "
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MMC=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIMER=y
> +CONFIG_CMD_EXT4_WRITE=y
> +# CONFIG_ISO_PARTITION is not set
> +CONFIG_OF_CONTROL=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +# CONFIG_NET is not set
> +CONFIG_DM_MMC=y
> +CONFIG_STM32_SDMMC2=y
> +# CONFIG_PINCTRL_FULL is not set
> +CONFIG_OF_LIBFDT_OVERLAY=y
> +CONFIG_BAUDRATE=2000000
> +CONFIG_USE_BOOTARGS=y
> +CONFIG_BOOTARGS="console=ttySTM0,2000000 root=/dev/ram rdinit=/linuxrc loglevel=8"
> +CONFIG_BOOTCOMMAND="bootm 90080000"
> +CONFIG_REQUIRE_SERIAL_CONSOLE=y
> +CONFIG_SERIAL_PRESENT=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_STM32_SERIAL=y
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x0
> +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
> +CONFIG_FIT_FULL_CHECK=y
> +CONFIG_FIT_PRINT=y
> +CONFIG_LEGACY_IMAGE_FORMAT=y
> +CONFIG_SUPPORT_RAW_INITRD=y
> +CONFIG_USE_BOOTCOMMAND=y
> +CONFIG_DM_DMA=y
> diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h
> new file mode 100644
> index 0000000..55132ac
> --- /dev/null
> +++ b/include/configs/stm32h750-art-pi.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
> + * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.

ditto

> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <config.h>
> +#include <linux/sizes.h>
> +
> +/* For booting Linux, use the first 16MB of memory */
> +#define CONFIG_SYS_BOOTMAPSZ		(SZ_16M + SZ_8M)
> +
> +#define CONFIG_SYS_FLASH_BASE		0x90000000
> +#define CONFIG_SYS_INIT_SP_ADDR		0x24040000
> +
> +/*
> + * Configuration of the external SDRAM memory
> + */
> +#define CONFIG_SYS_LOAD_ADDR		0xC1800000
> +#define CONFIG_LOADADDR			0xC1800000
> +
> +#define CONFIG_SYS_HZ_CLOCK		1000000
> +
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
> +
> +#define CONFIG_SYS_MAXARGS		16
> +#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +	func(MMC, mmc, 0)
> +
> +#include <config_distro_bootcmd.h>
> +#define CONFIG_EXTRA_ENV_SETTINGS				\
> +			"kernel_addr_r=0xC0008000\0"		\
> +			"fdtfile=stm32h743i-disco.dtb\0"	\

"fdtfile=stm32h750i-art-pi.dtb\0"

> +			"fdt_addr_r=0xC0408000\0"		\
> +			"scriptaddr=0xC0418000\0"		\
> +			"pxefile_addr_r=0xC0428000\0" \
> +			"ramdisk_addr_r=0xC0438000\0"		\
> +			BOOTENV
> +
> +#endif /* __CONFIG_H */
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 4/4] ram: stm32: fix strsep failed on read only memory
  2021-03-11  6:44 ` [PATCH 4/4] ram: stm32: fix strsep failed on read only memory dillon.minfei at gmail.com
@ 2021-03-25 15:17   ` Patrice CHOTARD
  0 siblings, 0 replies; 12+ messages in thread
From: Patrice CHOTARD @ 2021-03-25 15:17 UTC (permalink / raw)
  To: u-boot

Hi Dillon

On 3/11/21 7:44 AM, dillon.minfei at gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> strsep will change data from original memory address,
> in case the memory is in non-sdram/sram place, will
> run into a bug(hang at SDRAM: )
> 
> just add a temporary array to store bank_name[] to fix this
> bug.
> 
> Fixes: f303aaf ("ram: stm32: add second SDRAM bank management")
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>  drivers/ram/stm32_sdram.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
> index 540ad85..da27677 100644
> --- a/drivers/ram/stm32_sdram.c
> +++ b/drivers/ram/stm32_sdram.c
> @@ -268,6 +268,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
>  	u32 swp_fmc;
>  	ofnode bank_node;
>  	char *bank_name;
> +	char _bank_name[128] = {0};
>  	u8 bank = 0;
>  	int ret;
>  
> @@ -300,6 +301,8 @@ static int stm32_fmc_of_to_plat(struct udevice *dev)
>  	dev_for_each_subnode(bank_node, dev) {
>  		/* extract the bank index from DT */
>  		bank_name = (char *)ofnode_get_name(bank_node);
> +		strcpy(_bank_name, bank_name);
> +		bank_name = _bank_name;
>  		strsep(&bank_name, "@");
>  		if (!bank_name) {
>  			pr_err("missing sdram bank index");
> 

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 0/4] Add rt-thread art-pi board support
  2021-03-25 14:40 ` Patrice CHOTARD
@ 2021-03-26 10:26   ` dillon min
  0 siblings, 0 replies; 12+ messages in thread
From: dillon min @ 2021-03-26 10:26 UTC (permalink / raw)
  To: u-boot

Hi Patrice,

Thanks for your review.

On Thu, Mar 25, 2021 at 10:41 PM Patrice CHOTARD
<patrice.chotard@foss.st.com> wrote:
>
> Hi Dillon
>
> One general remark, i saw that you have submitted a similar serie on kernel side
> to add rt_thread art-pi board support.
> On this kernel series, you split the DT pinctrl files by introducing stm32h7-pinctrl.dtsi file.
> Can you apply the same device tree files split between kernel and u-boot please.
>
> The idea is that u-boot and kernel device tree files are in sync.
>
> Thanks
> Patrice
>
Agree, i just send out patch v2 for sync with kernel device tree files, and fix
incorrect author name & date.

thanks again.
regards.
>
>
> On 3/11/21 7:43 AM, dillon.minfei at gmail.com wrote:
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > These patches aim to adds u-boot support on art-pi board.
> >
> > the board resources:
> > - stm32h750xbh6 128k flash, 1024k sram
> > - 32MiB sdram
> > - 16MiB spi flash
> > - 8MiB qspi flash
> > - onboard wifi, bt, fm
> >
> > the detail board information can be found at:
> > https://art-pi.gitee.io/website/
> >
> > dillon min (4):
> >   ARM: dts: stm32: split sdram pin & timing parameter into specific
> >     board dts
> >   ARM: dts: stm32: Add RT-Thread art-pi board support
> >   board: Add rt-thread art-pi board support
> >   ram: stm32: fix strsep failed on read only memory
> >
> >  arch/arm/dts/Makefile                        |   3 +-
> >  arch/arm/dts/stm32h7-u-boot.dtsi             |  95 --------
> >  arch/arm/dts/stm32h743.dtsi                  |   8 +
> >  arch/arm/dts/stm32h743i-disco-u-boot.dtsi    |  98 ++++++++
> >  arch/arm/dts/stm32h743i-eval-u-boot.dtsi     |  98 ++++++++
> >  arch/arm/dts/stm32h750-pinctrl.dtsi          | 319 +++++++++++++++++++++++++++
> >  arch/arm/dts/stm32h750.dtsi                  |   5 +
> >  arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi   |  81 +++++++
> >  arch/arm/dts/stm32h750i-art-pi.dts           |  75 +++++++
> >  arch/arm/mach-stm32/stm32h7/Kconfig          |   4 +
> >  board/st/stm32h750-art-pi/Kconfig            |  19 ++
> >  board/st/stm32h750-art-pi/MAINTAINERS        |   7 +
> >  board/st/stm32h750-art-pi/Makefile           |   6 +
> >  board/st/stm32h750-art-pi/stm32h750-art-pi.c |  58 +++++
> >  configs/stm32h750-art-pi_defconfig           |  51 +++++
> >  drivers/ram/stm32_sdram.c                    |   3 +
> >  include/configs/stm32h750-art-pi.h           |  48 ++++
> >  include/dt-bindings/memory/stm32-sdram.h     |   2 +
> >  18 files changed, 884 insertions(+), 96 deletions(-)
> >  create mode 100644 arch/arm/dts/stm32h750-pinctrl.dtsi
> >  create mode 100644 arch/arm/dts/stm32h750.dtsi
> >  create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi
> >  create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts
> >  create mode 100644 board/st/stm32h750-art-pi/Kconfig
> >  create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS
> >  create mode 100644 board/st/stm32h750-art-pi/Makefile
> >  create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c
> >  create mode 100644 configs/stm32h750-art-pi_defconfig
> >  create mode 100644 include/configs/stm32h750-art-pi.h
> >

^ permalink raw reply	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-03-26 10:26 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-11  6:43 [PATCH 0/4] Add rt-thread art-pi board support dillon.minfei at gmail.com
2021-03-11  6:43 ` [PATCH 1/4] ARM: dts: stm32: split sdram pin & timing parameter into specific board dts dillon.minfei at gmail.com
2021-03-25 14:46   ` Patrice CHOTARD
2021-03-11  6:43 ` [PATCH 2/4] ARM: dts: stm32: Add RT-Thread art-pi board support dillon.minfei at gmail.com
2021-03-25 15:13   ` Patrice CHOTARD
2021-03-11  6:43 ` [PATCH 3/4] board: Add rt-thread " dillon.minfei at gmail.com
2021-03-25 15:16   ` Patrice CHOTARD
2021-03-11  6:44 ` [PATCH 4/4] ram: stm32: fix strsep failed on read only memory dillon.minfei at gmail.com
2021-03-25 15:17   ` Patrice CHOTARD
2021-03-22  8:28 ` [PATCH 0/4] Add rt-thread art-pi board support dillon min
2021-03-25 14:40 ` Patrice CHOTARD
2021-03-26 10:26   ` dillon min

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