* [PATCH] drm/i915: fix backlight after resume on 855gm
@ 2015-06-26 10:54 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2015-06-26 10:54 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, chris, stable, phg, jani.nikula
Some 855gm models (at least ThinkPad X40) regressed because of
commit b0cd324faed23d10d66ba6ade66579c681feef6f
Author: Jani Nikula <jani.nikula@intel.com>
Date: Wed Nov 12 16:25:43 2014 +0200
drm/i915: don't save/restore backlight hist ctl registers
which tried to make our driver more robust by not blindly saving and
restoring registers, but it failed to take into account
commit 0eb96d6ed38430b72897adde58f5477a6b71757a
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed Oct 14 12:33:41 2009 -0700
drm/i915: save/restore BLC histogram control reg across suspend/resume
Fix the regression by enabling hist ctl on gen2.
v2: Improved the comment.
Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net>
References: http://mid.gmane.org/20150623222648.GD12335@acheron
Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_panel.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa9ccb87eb66..bf7c08b94088 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3507,6 +3507,7 @@ enum skl_disp_power_wells {
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
+#define BLM_HISTOGRAM_ENABLE (1 << 31)
/* New registers for PCH-split platforms. Safe where new bits show up, the
* register layout machtes with gen4 BLC_PWM_CTL[12]. */
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 7d83527f95f7..a55477c59559 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -907,6 +907,13 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
/* XXX: combine this into above write? */
intel_panel_actually_set_backlight(connector, panel->backlight.level);
+
+ /*
+ * Needed to enable backlight on some 855gm models. Checking for gen2 is
+ * safe, as 855gm is the only gen2 that has backlight.
+ */
+ if (IS_GEN2(dev))
+ I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
}
static void i965_enable_backlight(struct intel_connector *connector)
--
2.1.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH] drm/i915: fix backlight after resume on 855gm
@ 2015-06-26 10:54 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2015-06-26 10:54 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, phg, stable
Some 855gm models (at least ThinkPad X40) regressed because of
commit b0cd324faed23d10d66ba6ade66579c681feef6f
Author: Jani Nikula <jani.nikula@intel.com>
Date: Wed Nov 12 16:25:43 2014 +0200
drm/i915: don't save/restore backlight hist ctl registers
which tried to make our driver more robust by not blindly saving and
restoring registers, but it failed to take into account
commit 0eb96d6ed38430b72897adde58f5477a6b71757a
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed Oct 14 12:33:41 2009 -0700
drm/i915: save/restore BLC histogram control reg across suspend/resume
Fix the regression by enabling hist ctl on gen2.
v2: Improved the comment.
Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net>
References: http://mid.gmane.org/20150623222648.GD12335@acheron
Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_panel.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa9ccb87eb66..bf7c08b94088 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3507,6 +3507,7 @@ enum skl_disp_power_wells {
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
+#define BLM_HISTOGRAM_ENABLE (1 << 31)
/* New registers for PCH-split platforms. Safe where new bits show up, the
* register layout machtes with gen4 BLC_PWM_CTL[12]. */
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 7d83527f95f7..a55477c59559 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -907,6 +907,13 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
/* XXX: combine this into above write? */
intel_panel_actually_set_backlight(connector, panel->backlight.level);
+
+ /*
+ * Needed to enable backlight on some 855gm models. Checking for gen2 is
+ * safe, as 855gm is the only gen2 that has backlight.
+ */
+ if (IS_GEN2(dev))
+ I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
}
static void i965_enable_backlight(struct intel_connector *connector)
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: fix backlight after resume on 855gm
2015-06-26 10:54 ` Jani Nikula
@ 2015-06-26 11:03 ` Chris Wilson
-1 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2015-06-26 11:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, ville.syrjala, stable, phg
On Fri, Jun 26, 2015 at 01:54:18PM +0300, Jani Nikula wrote:
> Some 855gm models (at least ThinkPad X40) regressed because of
>
> commit b0cd324faed23d10d66ba6ade66579c681feef6f
> Author: Jani Nikula <jani.nikula@intel.com>
> Date: Wed Nov 12 16:25:43 2014 +0200
>
> drm/i915: don't save/restore backlight hist ctl registers
>
> which tried to make our driver more robust by not blindly saving and
> restoring registers, but it failed to take into account
>
> commit 0eb96d6ed38430b72897adde58f5477a6b71757a
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Wed Oct 14 12:33:41 2009 -0700
>
> drm/i915: save/restore BLC histogram control reg across suspend/resume
>
> Fix the regression by enabling hist ctl on gen2.
>
> v2: Improved the comment.
>
> Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net>
> References: http://mid.gmane.org/20150623222648.GD12335@acheron
> Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers")
> Cc: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> Cc: stable@vger.kernel.org
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_panel.c | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa9ccb87eb66..bf7c08b94088 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells {
> #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
>
> #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
> +#define BLM_HISTOGRAM_ENABLE (1 << 31)
>
> /* New registers for PCH-split platforms. Safe where new bits show up, the
> * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 7d83527f95f7..a55477c59559 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -907,6 +907,13 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
>
> /* XXX: combine this into above write? */
> intel_panel_actually_set_backlight(connector, panel->backlight.level);
> +
> + /*
> + * Needed to enable backlight on some 855gm models.
* BLC_HIST_CTL is 855gm only, but checking for gen2 is
> + * safe, as 855gm is the only gen2 that has backlight.
> + */
I just felt the second sentence lacked a little context to justify
itself.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: fix backlight after resume on 855gm
@ 2015-06-26 11:03 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2015-06-26 11:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, ville.syrjala, stable, phg
On Fri, Jun 26, 2015 at 01:54:18PM +0300, Jani Nikula wrote:
> Some 855gm models (at least ThinkPad X40) regressed because of
>
> commit b0cd324faed23d10d66ba6ade66579c681feef6f
> Author: Jani Nikula <jani.nikula@intel.com>
> Date: Wed Nov 12 16:25:43 2014 +0200
>
> drm/i915: don't save/restore backlight hist ctl registers
>
> which tried to make our driver more robust by not blindly saving and
> restoring registers, but it failed to take into account
>
> commit 0eb96d6ed38430b72897adde58f5477a6b71757a
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Wed Oct 14 12:33:41 2009 -0700
>
> drm/i915: save/restore BLC histogram control reg across suspend/resume
>
> Fix the regression by enabling hist ctl on gen2.
>
> v2: Improved the comment.
>
> Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net>
> References: http://mid.gmane.org/20150623222648.GD12335@acheron
> Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers")
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: stable@vger.kernel.org
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_panel.c | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa9ccb87eb66..bf7c08b94088 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells {
> #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
>
> #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
> +#define BLM_HISTOGRAM_ENABLE (1 << 31)
>
> /* New registers for PCH-split platforms. Safe where new bits show up, the
> * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 7d83527f95f7..a55477c59559 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -907,6 +907,13 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
>
> /* XXX: combine this into above write? */
> intel_panel_actually_set_backlight(connector, panel->backlight.level);
> +
> + /*
> + * Needed to enable backlight on some 855gm models.
* BLC_HIST_CTL is 855gm only, but checking for gen2 is
> + * safe, as 855gm is the only gen2 that has backlight.
> + */
I just felt the second sentence lacked a little context to justify
itself.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3] drm/i915: fix backlight after resume on 855gm
2015-06-26 11:03 ` Chris Wilson
(?)
@ 2015-06-26 11:18 ` Jani Nikula
2015-06-28 17:12 ` shuang.he
2015-06-29 11:32 ` Jani Nikula
-1 siblings, 2 replies; 9+ messages in thread
From: Jani Nikula @ 2015-06-26 11:18 UTC (permalink / raw)
To: Chris Wilson, Jani Nikula; +Cc: intel-gfx, ville.syrjala, stable, phg
Some 855gm models (at least ThinkPad X40) regressed because of
commit b0cd324faed23d10d66ba6ade66579c681feef6f
Author: Jani Nikula <jani.nikula@intel.com>
Date: Wed Nov 12 16:25:43 2014 +0200
drm/i915: don't save/restore backlight hist ctl registers
which tried to make our driver more robust by not blindly saving and
restoring registers, but it failed to take into account
commit 0eb96d6ed38430b72897adde58f5477a6b71757a
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed Oct 14 12:33:41 2009 -0700
drm/i915: save/restore BLC histogram control reg across suspend/resume
Fix the regression by enabling hist ctl on gen2.
v2: Improved the comment.
v3: Improved the comment, again.
Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net>
References: http://mid.gmane.org/20150623222648.GD12335@acheron
Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_panel.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa9ccb87eb66..bf7c08b94088 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3507,6 +3507,7 @@ enum skl_disp_power_wells {
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
+#define BLM_HISTOGRAM_ENABLE (1 << 31)
/* New registers for PCH-split platforms. Safe where new bits show up, the
* register layout machtes with gen4 BLC_PWM_CTL[12]. */
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 7d83527f95f7..55aad2322e10 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
/* XXX: combine this into above write? */
intel_panel_actually_set_backlight(connector, panel->backlight.level);
+
+ /*
+ * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is
+ * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
+ * that has backlight.
+ */
+ if (IS_GEN2(dev))
+ I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
}
static void i965_enable_backlight(struct intel_connector *connector)
--
2.1.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: fix backlight after resume on 855gm
2015-06-26 10:54 ` Jani Nikula
(?)
(?)
@ 2015-06-28 12:08 ` shuang.he
-1 siblings, 0 replies; 9+ messages in thread
From: shuang.he @ 2015-06-28 12:08 UTC (permalink / raw)
To: shuang.he, lei.a.liu, intel-gfx, jani.nikula
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6611
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 302/302 302/302
SNB 312/316 312/316
IVB 343/343 343/343
BYT 287/287 287/287
HSW 380/380 380/380
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3] drm/i915: fix backlight after resume on 855gm
2015-06-26 11:18 ` [PATCH v3] " Jani Nikula
@ 2015-06-28 17:12 ` shuang.he
2015-06-29 11:32 ` Jani Nikula
1 sibling, 0 replies; 9+ messages in thread
From: shuang.he @ 2015-06-28 17:12 UTC (permalink / raw)
To: shuang.he, lei.a.liu, intel-gfx, jani.nikula
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6566
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 303/303 303/303
SNB 312/312 312/312
IVB 343/343 343/343
BYT -1 284/284 283/284
HSW 380/380 380/380
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BYT igt@gem_partial_pwrite_pread@reads-display PASS(1) FAIL(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3] drm/i915: fix backlight after resume on 855gm
2015-06-26 11:18 ` [PATCH v3] " Jani Nikula
@ 2015-06-29 11:32 ` Jani Nikula
2015-06-29 11:32 ` Jani Nikula
1 sibling, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2015-06-29 11:32 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, ville.syrjala, stable, phg
On Fri, 26 Jun 2015, Jani Nikula <jani.nikula@intel.com> wrote:
> Some 855gm models (at least ThinkPad X40) regressed because of
>
> commit b0cd324faed23d10d66ba6ade66579c681feef6f
> Author: Jani Nikula <jani.nikula@intel.com>
> Date: Wed Nov 12 16:25:43 2014 +0200
>
> drm/i915: don't save/restore backlight hist ctl registers
>
> which tried to make our driver more robust by not blindly saving and
> restoring registers, but it failed to take into account
>
> commit 0eb96d6ed38430b72897adde58f5477a6b71757a
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Wed Oct 14 12:33:41 2009 -0700
>
> drm/i915: save/restore BLC histogram control reg across suspend/resume
>
> Fix the regression by enabling hist ctl on gen2.
>
> v2: Improved the comment.
>
> v3: Improved the comment, again.
>
> Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net>
> References: http://mid.gmane.org/20150623222648.GD12335@acheron
> Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers")
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: stable@vger.kernel.org
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Pushed to drm-intel-next-fixes, assuming Chris' ack and Philipp's
tested-by are enough.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_panel.c | 8 ++++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa9ccb87eb66..bf7c08b94088 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells {
> #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
>
> #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
> +#define BLM_HISTOGRAM_ENABLE (1 << 31)
>
> /* New registers for PCH-split platforms. Safe where new bits show up, the
> * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 7d83527f95f7..55aad2322e10 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
>
> /* XXX: combine this into above write? */
> intel_panel_actually_set_backlight(connector, panel->backlight.level);
> +
> + /*
> + * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is
> + * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
> + * that has backlight.
> + */
> + if (IS_GEN2(dev))
> + I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
> }
>
> static void i965_enable_backlight(struct intel_connector *connector)
> --
> 2.1.4
>
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3] drm/i915: fix backlight after resume on 855gm
@ 2015-06-29 11:32 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2015-06-29 11:32 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, phg, stable
On Fri, 26 Jun 2015, Jani Nikula <jani.nikula@intel.com> wrote:
> Some 855gm models (at least ThinkPad X40) regressed because of
>
> commit b0cd324faed23d10d66ba6ade66579c681feef6f
> Author: Jani Nikula <jani.nikula@intel.com>
> Date: Wed Nov 12 16:25:43 2014 +0200
>
> drm/i915: don't save/restore backlight hist ctl registers
>
> which tried to make our driver more robust by not blindly saving and
> restoring registers, but it failed to take into account
>
> commit 0eb96d6ed38430b72897adde58f5477a6b71757a
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Wed Oct 14 12:33:41 2009 -0700
>
> drm/i915: save/restore BLC histogram control reg across suspend/resume
>
> Fix the regression by enabling hist ctl on gen2.
>
> v2: Improved the comment.
>
> v3: Improved the comment, again.
>
> Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net>
> References: http://mid.gmane.org/20150623222648.GD12335@acheron
> Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers")
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: stable@vger.kernel.org
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Pushed to drm-intel-next-fixes, assuming Chris' ack and Philipp's
tested-by are enough.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_panel.c | 8 ++++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa9ccb87eb66..bf7c08b94088 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells {
> #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
>
> #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
> +#define BLM_HISTOGRAM_ENABLE (1 << 31)
>
> /* New registers for PCH-split platforms. Safe where new bits show up, the
> * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 7d83527f95f7..55aad2322e10 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
>
> /* XXX: combine this into above write? */
> intel_panel_actually_set_backlight(connector, panel->backlight.level);
> +
> + /*
> + * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is
> + * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
> + * that has backlight.
> + */
> + if (IS_GEN2(dev))
> + I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
> }
>
> static void i965_enable_backlight(struct intel_connector *connector)
> --
> 2.1.4
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-06-29 11:30 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-26 10:54 [PATCH] drm/i915: fix backlight after resume on 855gm Jani Nikula
2015-06-26 10:54 ` Jani Nikula
2015-06-26 11:03 ` Chris Wilson
2015-06-26 11:03 ` Chris Wilson
2015-06-26 11:18 ` [PATCH v3] " Jani Nikula
2015-06-28 17:12 ` shuang.he
2015-06-29 11:32 ` Jani Nikula
2015-06-29 11:32 ` Jani Nikula
2015-06-28 12:08 ` [PATCH] " shuang.he
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.