stmmac still supporting spear600 ?

stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello,

I'm porting Linux to an old spear600 based platform, and therefore
trying to use the stmmac driver on this SoC. Unfortunately, it doesn't
work quite well and I'm wondering if the stmmac driver still properly
supports the old version of the IP that is used in this SoC. I'm
testing with v4.11-rc1.

First, the logs:

Linux version 4.11.0-rc1 (thomas@skate) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) ) #18 Thu Mar 9 09:18:01 CET 2017
[...]
libphy: Fixed MDIO Bus: probed
stmmaceth e0800000.ethernet: no reset control found
stmmac - user ID: 0x10, Synopsys ID: 0x32
stmmaceth e0800000.ethernet: Ring mode enabled
stmmaceth e0800000.ethernet: DMA HW capability register supported
stmmaceth e0800000.ethernet: Normal descriptors
libphy: stmmac: probed
stmmaceth e0800000.ethernet (unnamed net_device) (uninitialized): PHY ID 0007c0c4 at 31 IRQ POLL (stmmac-0:1f) active
[...]
# ifconfig eth0 192.168.1.89
stmmaceth e0800000.ethernet eth0: device MAC address 00:30:d3:21:22:60
Generic PHY stmmac-0:1f: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-0:1f, irq=-1)
stmmaceth e0800000.ethernet: Failed to reset the dma
stmmaceth e0800000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
stmmaceth e0800000.ethernet eth0: stmmac_open: Hw setup failed
ifconfig: SIOCSIFFLAGS: Device or resource busy

So the reason why it fails to reset the DMA is because
dwmac_dma_reset() sets bit DMA_BUS_MODE_SFT_RESET in register
DMA_BUS_MODE and waits for this bit to clear, but that never happens.

The reason why I'm not sure if this IP is still supported is because
dwmac1000_get_hw_feature() reads the DMA_HW_FEATURE register (offset
0x00001058), and my spear600 datasheet doesn't mention this register at
all.

It is worth mentioning that:

 - Ethernet is working fine under U-Boot (it's an old 2010.03 U-Boot
   version, with a good number of patches), so I'm sure the HW is
   working.

 - Setting bit 1 in the DMA_BUS_MODE register from U-Boot also leaves
   this bit set forever, it apparently never clears (unless my tests
   were wrong, which is very possible).

In terms of Device Tree, I'm simply using spear600.dtsi, and enabling
the gmac node, nothing else.

Has the stmmac driver been recently used/tested on spear600 ?

Thanks,

Thomas Petazzoni
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello,

I'm porting Linux to an old spear600 based platform, and therefore
trying to use the stmmac driver on this SoC. Unfortunately, it doesn't
work quite well and I'm wondering if the stmmac driver still properly
supports the old version of the IP that is used in this SoC. I'm
testing with v4.11-rc1.

First, the logs:

Linux version 4.11.0-rc1 (thomas at skate) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) ) #18 Thu Mar 9 09:18:01 CET 2017
[...]
libphy: Fixed MDIO Bus: probed
stmmaceth e0800000.ethernet: no reset control found
stmmac - user ID: 0x10, Synopsys ID: 0x32
stmmaceth e0800000.ethernet: Ring mode enabled
stmmaceth e0800000.ethernet: DMA HW capability register supported
stmmaceth e0800000.ethernet: Normal descriptors
libphy: stmmac: probed
stmmaceth e0800000.ethernet (unnamed net_device) (uninitialized): PHY ID 0007c0c4 at 31 IRQ POLL (stmmac-0:1f) active
[...]
# ifconfig eth0 192.168.1.89
stmmaceth e0800000.ethernet eth0: device MAC address 00:30:d3:21:22:60
Generic PHY stmmac-0:1f: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-0:1f, irq=-1)
stmmaceth e0800000.ethernet: Failed to reset the dma
stmmaceth e0800000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
stmmaceth e0800000.ethernet eth0: stmmac_open: Hw setup failed
ifconfig: SIOCSIFFLAGS: Device or resource busy

So the reason why it fails to reset the DMA is because
dwmac_dma_reset() sets bit DMA_BUS_MODE_SFT_RESET in register
DMA_BUS_MODE and waits for this bit to clear, but that never happens.

The reason why I'm not sure if this IP is still supported is because
dwmac1000_get_hw_feature() reads the DMA_HW_FEATURE register (offset
0x00001058), and my spear600 datasheet doesn't mention this register at
all.

It is worth mentioning that:

 - Ethernet is working fine under U-Boot (it's an old 2010.03 U-Boot
   version, with a good number of patches), so I'm sure the HW is
   working.

 - Setting bit 1 in the DMA_BUS_MODE register from U-Boot also leaves
   this bit set forever, it apparently never clears (unless my tests
   were wrong, which is very possible).

In terms of Device Tree, I'm simply using spear600.dtsi, and enabling
the gmac node, nothing else.

Has the stmmac driver been recently used/tested on spear600 ?

Thanks,

Thomas Petazzoni
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: stmmac still supporting spear600 ?

[Giuseppe CAVALLARO]

Hello

We do not test stmmac on this spear board since many years
and I guess you have to provide parameters from the platform.
In fact, stmmac is recently tested with DT.
IIRC, the mac on spear600 could not have the HW cap register
so it is mandatory to provide all the right parameters and
configurations for this HW.

Regards
Peppe

On 3/9/2017 9:34 AM, Thomas Petazzoni wrote:
> Hello,
>
> I'm porting Linux to an old spear600 based platform, and therefore
> trying to use the stmmac driver on this SoC. Unfortunately, it doesn't
> work quite well and I'm wondering if the stmmac driver still properly
> supports the old version of the IP that is used in this SoC. I'm
> testing with v4.11-rc1.
>
> First, the logs:
>
> Linux version 4.11.0-rc1 (thomas@skate) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) ) #18 Thu Mar 9 09:18:01 CET 2017
> [...]
> libphy: Fixed MDIO Bus: probed
> stmmaceth e0800000.ethernet: no reset control found
> stmmac - user ID: 0x10, Synopsys ID: 0x32
> stmmaceth e0800000.ethernet: Ring mode enabled
> stmmaceth e0800000.ethernet: DMA HW capability register supported
> stmmaceth e0800000.ethernet: Normal descriptors
> libphy: stmmac: probed
> stmmaceth e0800000.ethernet (unnamed net_device) (uninitialized): PHY ID 0007c0c4 at 31 IRQ POLL (stmmac-0:1f) active
> [...]
> # ifconfig eth0 192.168.1.89
> stmmaceth e0800000.ethernet eth0: device MAC address 00:30:d3:21:22:60
> Generic PHY stmmac-0:1f: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-0:1f, irq=-1)
> stmmaceth e0800000.ethernet: Failed to reset the dma
> stmmaceth e0800000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
> stmmaceth e0800000.ethernet eth0: stmmac_open: Hw setup failed
> ifconfig: SIOCSIFFLAGS: Device or resource busy
>
> So the reason why it fails to reset the DMA is because
> dwmac_dma_reset() sets bit DMA_BUS_MODE_SFT_RESET in register
> DMA_BUS_MODE and waits for this bit to clear, but that never happens.
>
> The reason why I'm not sure if this IP is still supported is because
> dwmac1000_get_hw_feature() reads the DMA_HW_FEATURE register (offset
> 0x00001058), and my spear600 datasheet doesn't mention this register at
> all.
>
> It is worth mentioning that:
>
>  - Ethernet is working fine under U-Boot (it's an old 2010.03 U-Boot
>    version, with a good number of patches), so I'm sure the HW is
>    working.
>
>  - Setting bit 1 in the DMA_BUS_MODE register from U-Boot also leaves
>    this bit set forever, it apparently never clears (unless my tests
>    were wrong, which is very possible).
>
> In terms of Device Tree, I'm simply using spear600.dtsi, and enabling
> the gmac node, nothing else.
>
> Has the stmmac driver been recently used/tested on spear600 ?
>
> Thanks,
>
> Thomas Petazzoni
>

stmmac still supporting spear600 ?

[Giuseppe CAVALLARO]

Hello

We do not test stmmac on this spear board since many years
and I guess you have to provide parameters from the platform.
In fact, stmmac is recently tested with DT.
IIRC, the mac on spear600 could not have the HW cap register
so it is mandatory to provide all the right parameters and
configurations for this HW.

Regards
Peppe

On 3/9/2017 9:34 AM, Thomas Petazzoni wrote:
> Hello,
>
> I'm porting Linux to an old spear600 based platform, and therefore
> trying to use the stmmac driver on this SoC. Unfortunately, it doesn't
> work quite well and I'm wondering if the stmmac driver still properly
> supports the old version of the IP that is used in this SoC. I'm
> testing with v4.11-rc1.
>
> First, the logs:
>
> Linux version 4.11.0-rc1 (thomas at skate) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) ) #18 Thu Mar 9 09:18:01 CET 2017
> [...]
> libphy: Fixed MDIO Bus: probed
> stmmaceth e0800000.ethernet: no reset control found
> stmmac - user ID: 0x10, Synopsys ID: 0x32
> stmmaceth e0800000.ethernet: Ring mode enabled
> stmmaceth e0800000.ethernet: DMA HW capability register supported
> stmmaceth e0800000.ethernet: Normal descriptors
> libphy: stmmac: probed
> stmmaceth e0800000.ethernet (unnamed net_device) (uninitialized): PHY ID 0007c0c4 at 31 IRQ POLL (stmmac-0:1f) active
> [...]
> # ifconfig eth0 192.168.1.89
> stmmaceth e0800000.ethernet eth0: device MAC address 00:30:d3:21:22:60
> Generic PHY stmmac-0:1f: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-0:1f, irq=-1)
> stmmaceth e0800000.ethernet: Failed to reset the dma
> stmmaceth e0800000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
> stmmaceth e0800000.ethernet eth0: stmmac_open: Hw setup failed
> ifconfig: SIOCSIFFLAGS: Device or resource busy
>
> So the reason why it fails to reset the DMA is because
> dwmac_dma_reset() sets bit DMA_BUS_MODE_SFT_RESET in register
> DMA_BUS_MODE and waits for this bit to clear, but that never happens.
>
> The reason why I'm not sure if this IP is still supported is because
> dwmac1000_get_hw_feature() reads the DMA_HW_FEATURE register (offset
> 0x00001058), and my spear600 datasheet doesn't mention this register at
> all.
>
> It is worth mentioning that:
>
>  - Ethernet is working fine under U-Boot (it's an old 2010.03 U-Boot
>    version, with a good number of patches), so I'm sure the HW is
>    working.
>
>  - Setting bit 1 in the DMA_BUS_MODE register from U-Boot also leaves
>    this bit set forever, it apparently never clears (unless my tests
>    were wrong, which is very possible).
>
> In terms of Device Tree, I'm simply using spear600.dtsi, and enabling
> the gmac node, nothing else.
>
> Has the stmmac driver been recently used/tested on spear600 ?
>
> Thanks,
>
> Thomas Petazzoni
>

Re: stmmac still supporting spear600 ?

[Viresh Kumar]

On 09-03-17, 10:09, Giuseppe CAVALLARO wrote:
> Hello
> 
> We do not test stmmac on this spear board since many years
> and I guess you have to provide parameters from the platform.
> In fact, stmmac is recently tested with DT.
> IIRC, the mac on spear600 could not have the HW cap register
> so it is mandatory to provide all the right parameters and
> configurations for this HW.

Same here, I haven't tested it since many years and trust whatever Giuseppe has
said.

-- 
viresh

stmmac still supporting spear600 ?

[Viresh Kumar]

On 09-03-17, 10:09, Giuseppe CAVALLARO wrote:
> Hello
> 
> We do not test stmmac on this spear board since many years
> and I guess you have to provide parameters from the platform.
> In fact, stmmac is recently tested with DT.
> IIRC, the mac on spear600 could not have the HW cap register
> so it is mandatory to provide all the right parameters and
> configurations for this HW.

Same here, I haven't tested it since many years and trust whatever Giuseppe has
said.

-- 
viresh

Re: stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello Giuseppe,

Thanks for your answer.

On Thu, 9 Mar 2017 10:09:02 +0100, Giuseppe CAVALLARO wrote:

> We do not test stmmac on this spear board since many years
> and I guess you have to provide parameters from the platform.

Ok, that's what I was afraid of :-/

> In fact, stmmac is recently tested with DT.

I'm also using the DT, so this is definitely not the problem.

> IIRC, the mac on spear600 could not have the HW cap register

Correct.

> so it is mandatory to provide all the right parameters and
> configurations for this HW.

OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
that never clears, contrary to what the datasheet says. Are there some
erratas?

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello Giuseppe,

Thanks for your answer.

On Thu, 9 Mar 2017 10:09:02 +0100, Giuseppe CAVALLARO wrote:

> We do not test stmmac on this spear board since many years
> and I guess you have to provide parameters from the platform.

Ok, that's what I was afraid of :-/

> In fact, stmmac is recently tested with DT.

I'm also using the DT, so this is definitely not the problem.

> IIRC, the mac on spear600 could not have the HW cap register

Correct.

> so it is mandatory to provide all the right parameters and
> configurations for this HW.

OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
that never clears, contrary to what the datasheet says. Are there some
erratas?

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: stmmac still supporting spear600 ?

[Giuseppe CAVALLARO]

Hello Thomas

On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:

> OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
> that never clears, contrary to what the datasheet says. Are there some
> erratas?

I suggest you to take a look at the tx/rx clocks from PHY.
You have to provide these otherwise you cannot reset the engine.

Best Regards
Peppe

>
> Best regards,
>
> Thomas
>

stmmac still supporting spear600 ?

[Giuseppe CAVALLARO]

Hello Thomas

On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:

> OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
> that never clears, contrary to what the datasheet says. Are there some
> erratas?

I suggest you to take a look at the tx/rx clocks from PHY.
You have to provide these otherwise you cannot reset the engine.

Best Regards
Peppe

>
> Best regards,
>
> Thomas
>

Re: stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello,

On Thu, 9 Mar 2017 15:56:31 +0100, Giuseppe CAVALLARO wrote:

> On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:
> 
> > OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
> > that never clears, contrary to what the datasheet says. Are there some
> > erratas?  
> 
> I suggest you to take a look at the tx/rx clocks from PHY.
> You have to provide these otherwise you cannot reset the engine.

Thanks for the hint.

Further research has revealed that everything is working fine on a
platform with a Gigabit PHY connected via GMII.

However, on a different platform (which I'm using) with a 10/100 PHY
connected via MII, DMA_RESET never clears, and networking doesn't work.
The SMSC PHY LAN8700 is also supposed to be providing the clock through
its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
mode, but still no luck so far.

Of course, if you have any suggestion or hint, I'm all ears :)

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello,

On Thu, 9 Mar 2017 15:56:31 +0100, Giuseppe CAVALLARO wrote:

> On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:
> 
> > OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
> > that never clears, contrary to what the datasheet says. Are there some
> > erratas?  
> 
> I suggest you to take a look at the tx/rx clocks from PHY.
> You have to provide these otherwise you cannot reset the engine.

Thanks for the hint.

Further research has revealed that everything is working fine on a
platform with a Gigabit PHY connected via GMII.

However, on a different platform (which I'm using) with a 10/100 PHY
connected via MII, DMA_RESET never clears, and networking doesn't work.
The SMSC PHY LAN8700 is also supposed to be providing the clock through
its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
mode, but still no luck so far.

Of course, if you have any suggestion or hint, I'm all ears :)

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: stmmac still supporting spear600 ?

[Giuseppe CAVALLARO]

Hello Thomas

On 3/21/2017 3:50 PM, Thomas Petazzoni wrote:
> Hello,
>
> On Thu, 9 Mar 2017 15:56:31 +0100, Giuseppe CAVALLARO wrote:
>
>> On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:
>>
>>> OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
>>> that never clears, contrary to what the datasheet says. Are there some
>>> erratas?
>> I suggest you to take a look at the tx/rx clocks from PHY.
>> You have to provide these otherwise you cannot reset the engine.
> Thanks for the hint.

you are welcome

> Further research has revealed that everything is working fine on a
> platform with a Gigabit PHY connected via GMII.
>
> However, on a different platform (which I'm using) with a 10/100 PHY
> connected via MII, DMA_RESET never clears, and networking doesn't work.
> The SMSC PHY LAN8700 is also supposed to be providing the clock through
> its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
> mode, but still no luck so far.
>
> Of course, if you have any suggestion or hint, I'm all ears :)

I can just you to keep the focus on clock configuration. I tested the 
SMSC PHY LAN8700
w/o any issues on several platform.  In MII both rx/tx_clk are provided 
by PHY and if you
have an external oscillator this should be safe enough, indeed.
Another check you can do is about the reset time! Maybe you need to 
change something
when reset the SMSC transceiver, try to increase the delay (if you use 
GPIO to reset it).

Regards
Peppe

>
> Thanks,
>
> Thomas

stmmac still supporting spear600 ?

[Giuseppe CAVALLARO]

Hello Thomas

On 3/21/2017 3:50 PM, Thomas Petazzoni wrote:
> Hello,
>
> On Thu, 9 Mar 2017 15:56:31 +0100, Giuseppe CAVALLARO wrote:
>
>> On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:
>>
>>> OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
>>> that never clears, contrary to what the datasheet says. Are there some
>>> erratas?
>> I suggest you to take a look at the tx/rx clocks from PHY.
>> You have to provide these otherwise you cannot reset the engine.
> Thanks for the hint.

you are welcome

> Further research has revealed that everything is working fine on a
> platform with a Gigabit PHY connected via GMII.
>
> However, on a different platform (which I'm using) with a 10/100 PHY
> connected via MII, DMA_RESET never clears, and networking doesn't work.
> The SMSC PHY LAN8700 is also supposed to be providing the clock through
> its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
> mode, but still no luck so far.
>
> Of course, if you have any suggestion or hint, I'm all ears :)

I can just you to keep the focus on clock configuration. I tested the 
SMSC PHY LAN8700
w/o any issues on several platform.  In MII both rx/tx_clk are provided 
by PHY and if you
have an external oscillator this should be safe enough, indeed.
Another check you can do is about the reset time! Maybe you need to 
change something
when reset the SMSC transceiver, try to increase the delay (if you use 
GPIO to reset it).

Regards
Peppe

>
> Thanks,
>
> Thomas

Re: stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello,

On Thu, 23 Mar 2017 11:33:23 +0100, Giuseppe CAVALLARO wrote:

> > Further research has revealed that everything is working fine on a
> > platform with a Gigabit PHY connected via GMII.
> >
> > However, on a different platform (which I'm using) with a 10/100 PHY
> > connected via MII, DMA_RESET never clears, and networking doesn't work.
> > The SMSC PHY LAN8700 is also supposed to be providing the clock through
> > its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
> > mode, but still no luck so far.
> >
> > Of course, if you have any suggestion or hint, I'm all ears :)  
> 
> I can just you to keep the focus on clock configuration. I tested the 
> SMSC PHY LAN8700
> w/o any issues on several platform.  In MII both rx/tx_clk are provided 
> by PHY and if you
> have an external oscillator this should be safe enough, indeed.
> Another check you can do is about the reset time! Maybe you need to 
> change something
> when reset the SMSC transceiver, try to increase the delay (if you use 
> GPIO to reset it).

On which platform did you test with the LAN8700 PHY ? Was it on a
SPEAr600 based platform ?

If you tested on SPEAr600, what is the GMAC clock configuration (i.e
the value of the GMAC_CFG_CTR and GMAC_CFG_SYNT registers) ?

Regarding the PHY reset time, our PHY reset pin is not connected to a
GPIO, but to the system reset logic, so Linux cannot reset the PHY with
a GPIO.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello,

On Thu, 23 Mar 2017 11:33:23 +0100, Giuseppe CAVALLARO wrote:

> > Further research has revealed that everything is working fine on a
> > platform with a Gigabit PHY connected via GMII.
> >
> > However, on a different platform (which I'm using) with a 10/100 PHY
> > connected via MII, DMA_RESET never clears, and networking doesn't work.
> > The SMSC PHY LAN8700 is also supposed to be providing the clock through
> > its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
> > mode, but still no luck so far.
> >
> > Of course, if you have any suggestion or hint, I'm all ears :)  
> 
> I can just you to keep the focus on clock configuration. I tested the 
> SMSC PHY LAN8700
> w/o any issues on several platform.  In MII both rx/tx_clk are provided 
> by PHY and if you
> have an external oscillator this should be safe enough, indeed.
> Another check you can do is about the reset time! Maybe you need to 
> change something
> when reset the SMSC transceiver, try to increase the delay (if you use 
> GPIO to reset it).

On which platform did you test with the LAN8700 PHY ? Was it on a
SPEAr600 based platform ?

If you tested on SPEAr600, what is the GMAC clock configuration (i.e
the value of the GMAC_CFG_CTR and GMAC_CFG_SYNT registers) ?

Regarding the PHY reset time, our PHY reset pin is not connected to a
GPIO, but to the system reset logic, so Linux cannot reset the PHY with
a GPIO.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: stmmac still supporting spear600 ?

[Giuseppe CAVALLARO]

Hi Thomas

I tested the SMSC on other platform (+ stmmac), not on SPEAr.

ok for reset, keep the radar on clock. Hmm, can you attach a piece of 
log file to see the failure?

Regards
Peppe

On 4/2/2017 11:30 PM, Thomas Petazzoni wrote:
> Hello,
>
> On Thu, 23 Mar 2017 11:33:23 +0100, Giuseppe CAVALLARO wrote:
>
>>> Further research has revealed that everything is working fine on a
>>> platform with a Gigabit PHY connected via GMII.
>>>
>>> However, on a different platform (which I'm using) with a 10/100 PHY
>>> connected via MII, DMA_RESET never clears, and networking doesn't work.
>>> The SMSC PHY LAN8700 is also supposed to be providing the clock through
>>> its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
>>> mode, but still no luck so far.
>>>
>>> Of course, if you have any suggestion or hint, I'm all ears :)
>> I can just you to keep the focus on clock configuration. I tested the
>> SMSC PHY LAN8700
>> w/o any issues on several platform.  In MII both rx/tx_clk are provided
>> by PHY and if you
>> have an external oscillator this should be safe enough, indeed.
>> Another check you can do is about the reset time! Maybe you need to
>> change something
>> when reset the SMSC transceiver, try to increase the delay (if you use
>> GPIO to reset it).
> On which platform did you test with the LAN8700 PHY ? Was it on a
> SPEAr600 based platform ?
>
> If you tested on SPEAr600, what is the GMAC clock configuration (i.e
> the value of the GMAC_CFG_CTR and GMAC_CFG_SYNT registers) ?
>
> Regarding the PHY reset time, our PHY reset pin is not connected to a
> GPIO, but to the system reset logic, so Linux cannot reset the PHY with
> a GPIO.
>
> Thanks!
>
> Thomas

stmmac still supporting spear600 ?

[Giuseppe CAVALLARO]

Hi Thomas

I tested the SMSC on other platform (+ stmmac), not on SPEAr.

ok for reset, keep the radar on clock. Hmm, can you attach a piece of 
log file to see the failure?

Regards
Peppe

On 4/2/2017 11:30 PM, Thomas Petazzoni wrote:
> Hello,
>
> On Thu, 23 Mar 2017 11:33:23 +0100, Giuseppe CAVALLARO wrote:
>
>>> Further research has revealed that everything is working fine on a
>>> platform with a Gigabit PHY connected via GMII.
>>>
>>> However, on a different platform (which I'm using) with a 10/100 PHY
>>> connected via MII, DMA_RESET never clears, and networking doesn't work.
>>> The SMSC PHY LAN8700 is also supposed to be providing the clock through
>>> its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
>>> mode, but still no luck so far.
>>>
>>> Of course, if you have any suggestion or hint, I'm all ears :)
>> I can just you to keep the focus on clock configuration. I tested the
>> SMSC PHY LAN8700
>> w/o any issues on several platform.  In MII both rx/tx_clk are provided
>> by PHY and if you
>> have an external oscillator this should be safe enough, indeed.
>> Another check you can do is about the reset time! Maybe you need to
>> change something
>> when reset the SMSC transceiver, try to increase the delay (if you use
>> GPIO to reset it).
> On which platform did you test with the LAN8700 PHY ? Was it on a
> SPEAr600 based platform ?
>
> If you tested on SPEAr600, what is the GMAC clock configuration (i.e
> the value of the GMAC_CFG_CTR and GMAC_CFG_SYNT registers) ?
>
> Regarding the PHY reset time, our PHY reset pin is not connected to a
> GPIO, but to the system reset logic, so Linux cannot reset the PHY with
> a GPIO.
>
> Thanks!
>
> Thomas

Re: stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello,

Thanks again for your answer, sorry for the delay, I was away from the
spear600 board for a while.

On Mon, 3 Apr 2017 08:16:50 +0200, Giuseppe CAVALLARO wrote:

> I tested the SMSC on other platform (+ stmmac), not on SPEAr.

OK. But I believe there might be a SPEAr specific issue here, which
might explain why you don't reproduce the problem.

> ok for reset, keep the radar on clock. Hmm, can you attach a piece of 
> log file to see the failure?

During the boot, nothing bad:

libphy: Fixed MDIO Bus: probed
stmmaceth e0800000.ethernet: no reset control found
stmmac - user ID: 0x10, Synopsys ID: 0x32
 Ring mode enabled
 DMA HW capability register supported Normal descriptors
libphy: stmmac: probed
eth0: PHY ID 0007c0c4 at 31 IRQ POLL (stmmac-0:1f) active

Then, when upping the interface:

# ifconfig eth0 up
eth0: device MAC address 00:30:d3:21:22:60
stmmaceth e0800000.ethernet: Failed to reset the dma
stmmac_hw_setup: DMA engine initialization failed
stmmac_open: Hw setup failed
SIOCSIFFLAGS: Device or resource busy

As I said earlier, the "Failed to reset the dma" is because
dwmac_dma_reset() returns -EBUSY because the DMA reset bit never
clears. Again, we see the same behavior in U-Boot (DMA reset bit never
clears), but Ethernet does work in U-Boot.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello,

Thanks again for your answer, sorry for the delay, I was away from the
spear600 board for a while.

On Mon, 3 Apr 2017 08:16:50 +0200, Giuseppe CAVALLARO wrote:

> I tested the SMSC on other platform (+ stmmac), not on SPEAr.

OK. But I believe there might be a SPEAr specific issue here, which
might explain why you don't reproduce the problem.

> ok for reset, keep the radar on clock. Hmm, can you attach a piece of 
> log file to see the failure?

During the boot, nothing bad:

libphy: Fixed MDIO Bus: probed
stmmaceth e0800000.ethernet: no reset control found
stmmac - user ID: 0x10, Synopsys ID: 0x32
 Ring mode enabled
 DMA HW capability register supported Normal descriptors
libphy: stmmac: probed
eth0: PHY ID 0007c0c4 at 31 IRQ POLL (stmmac-0:1f) active

Then, when upping the interface:

# ifconfig eth0 up
eth0: device MAC address 00:30:d3:21:22:60
stmmaceth e0800000.ethernet: Failed to reset the dma
stmmac_hw_setup: DMA engine initialization failed
stmmac_open: Hw setup failed
SIOCSIFFLAGS: Device or resource busy

As I said earlier, the "Failed to reset the dma" is because
dwmac_dma_reset() returns -EBUSY because the DMA reset bit never
clears. Again, we see the same behavior in U-Boot (DMA reset bit never
clears), but Ethernet does work in U-Boot.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: stmmac still supporting spear600 ?

[Thomas Petazzoni]

Viresh, Shiraz,

As the SPEAr600 platform maintainers, have you tested Ethernet in
recent times, especially with a MII PHY ? I'm still struggling to get
it working. Quick summary:

 - The same kernel works fine on another SPEAr600 platform that has a
   GMII PHY

 - The SPEAr600 platform with a MII PHY has Ethernet working fine under
   U-Boot (TFTP works), so the HW is known to be working.

 - I've compared the values of the MAC registers between U-Boot and
   Linux, and traced all the PHY registers read/write over the MDIO
   bus, and compared the traces between U-Boot and Linux. Found a few
   differences, but solving them didn't change the problem.

I'm suspecting the problem is not directly in the MAC/PHY
configuration. Would you have some hints like clock configuration, or
other system-level configuration that could affect this? Especially the
TXCLK from the PHY is not coming in through the same pin when in GMII
and MII mode it seems. Does this needs some special configuration?

Any hint/idea would definitely be welcome.

Thanks a lot!

Thomas

On Wed, 12 Apr 2017 15:05:58 +0200, Thomas Petazzoni wrote:
> Hello,
> 
> Thanks again for your answer, sorry for the delay, I was away from the
> spear600 board for a while.
> 
> On Mon, 3 Apr 2017 08:16:50 +0200, Giuseppe CAVALLARO wrote:
> 
> > I tested the SMSC on other platform (+ stmmac), not on SPEAr.  
> 
> OK. But I believe there might be a SPEAr specific issue here, which
> might explain why you don't reproduce the problem.
> 
> > ok for reset, keep the radar on clock. Hmm, can you attach a piece of 
> > log file to see the failure?  
> 
> During the boot, nothing bad:
> 
> libphy: Fixed MDIO Bus: probed
> stmmaceth e0800000.ethernet: no reset control found
> stmmac - user ID: 0x10, Synopsys ID: 0x32
>  Ring mode enabled
>  DMA HW capability register supported Normal descriptors
> libphy: stmmac: probed
> eth0: PHY ID 0007c0c4 at 31 IRQ POLL (stmmac-0:1f) active
> 
> Then, when upping the interface:
> 
> # ifconfig eth0 up
> eth0: device MAC address 00:30:d3:21:22:60
> stmmaceth e0800000.ethernet: Failed to reset the dma
> stmmac_hw_setup: DMA engine initialization failed
> stmmac_open: Hw setup failed
> SIOCSIFFLAGS: Device or resource busy
> 
> As I said earlier, the "Failed to reset the dma" is because
> dwmac_dma_reset() returns -EBUSY because the DMA reset bit never
> clears. Again, we see the same behavior in U-Boot (DMA reset bit never
> clears), but Ethernet does work in U-Boot.
> 
> Best regards,
> 
> Thomas



-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

stmmac still supporting spear600 ?

[Thomas Petazzoni]

Viresh, Shiraz,

As the SPEAr600 platform maintainers, have you tested Ethernet in
recent times, especially with a MII PHY ? I'm still struggling to get
it working. Quick summary:

 - The same kernel works fine on another SPEAr600 platform that has a
   GMII PHY

 - The SPEAr600 platform with a MII PHY has Ethernet working fine under
   U-Boot (TFTP works), so the HW is known to be working.

 - I've compared the values of the MAC registers between U-Boot and
   Linux, and traced all the PHY registers read/write over the MDIO
   bus, and compared the traces between U-Boot and Linux. Found a few
   differences, but solving them didn't change the problem.

I'm suspecting the problem is not directly in the MAC/PHY
configuration. Would you have some hints like clock configuration, or
other system-level configuration that could affect this? Especially the
TXCLK from the PHY is not coming in through the same pin when in GMII
and MII mode it seems. Does this needs some special configuration?

Any hint/idea would definitely be welcome.

Thanks a lot!

Thomas

On Wed, 12 Apr 2017 15:05:58 +0200, Thomas Petazzoni wrote:
> Hello,
> 
> Thanks again for your answer, sorry for the delay, I was away from the
> spear600 board for a while.
> 
> On Mon, 3 Apr 2017 08:16:50 +0200, Giuseppe CAVALLARO wrote:
> 
> > I tested the SMSC on other platform (+ stmmac), not on SPEAr.  
> 
> OK. But I believe there might be a SPEAr specific issue here, which
> might explain why you don't reproduce the problem.
> 
> > ok for reset, keep the radar on clock. Hmm, can you attach a piece of 
> > log file to see the failure?  
> 
> During the boot, nothing bad:
> 
> libphy: Fixed MDIO Bus: probed
> stmmaceth e0800000.ethernet: no reset control found
> stmmac - user ID: 0x10, Synopsys ID: 0x32
>  Ring mode enabled
>  DMA HW capability register supported Normal descriptors
> libphy: stmmac: probed
> eth0: PHY ID 0007c0c4 at 31 IRQ POLL (stmmac-0:1f) active
> 
> Then, when upping the interface:
> 
> # ifconfig eth0 up
> eth0: device MAC address 00:30:d3:21:22:60
> stmmaceth e0800000.ethernet: Failed to reset the dma
> stmmac_hw_setup: DMA engine initialization failed
> stmmac_open: Hw setup failed
> SIOCSIFFLAGS: Device or resource busy
> 
> As I said earlier, the "Failed to reset the dma" is because
> dwmac_dma_reset() returns -EBUSY because the DMA reset bit never
> clears. Again, we see the same behavior in U-Boot (DMA reset bit never
> clears), but Ethernet does work in U-Boot.
> 
> Best regards,
> 
> Thomas



-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello Giuseppe,

On Mon, 3 Apr 2017 08:16:50 +0200, Giuseppe CAVALLARO wrote:

> I tested the SMSC on other platform (+ stmmac), not on SPEAr.
> 
> ok for reset, keep the radar on clock. Hmm, can you attach a piece of 
> log file to see the failure?

We finally identified the issue: in a MII configuration, the PS bit
need to be set for the DMA reset procedure to work, but setting the DMA
reset bit clears the PS bit. So you have to set the PS bit after
asserting the DMA reset, and before polling for the DMA reset bit to
clear.

I have sent a fix that works for us (tested GMII and MII platforms),
but not sure if the implementation is the most appropriate. Let me know
if you have better suggestions.

See: http://marc.info/?l=linux-netdev&m=149328635210461&w=2

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

stmmac still supporting spear600 ?

[Thomas Petazzoni]

Hello Giuseppe,

On Mon, 3 Apr 2017 08:16:50 +0200, Giuseppe CAVALLARO wrote:

> I tested the SMSC on other platform (+ stmmac), not on SPEAr.
> 
> ok for reset, keep the radar on clock. Hmm, can you attach a piece of 
> log file to see the failure?

We finally identified the issue: in a MII configuration, the PS bit
need to be set for the DMA reset procedure to work, but setting the DMA
reset bit clears the PS bit. So you have to set the PS bit after
asserting the DMA reset, and before polling for the DMA reset bit to
clear.

I have sent a fix that works for us (tested GMII and MII platforms),
but not sure if the implementation is the most appropriate. Let me know
if you have better suggestions.

See: http://marc.info/?l=linux-netdev&m=149328635210461&w=2

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com