* [PATCH v3 0/5]
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add full LVTS support (MCU thermal domain + AP thermal domain) to MediaTek MT8192 SoC.
Also, add Suspend and Resume support to LVTS Driver (all SoCs),
and update the documentation that describes the Calibration Data Offsets.
Changelog:
v3 :
- Rebased :
base-commit: 6a3d37b4d885129561e1cef361216f00472f7d2e
- Fix issues in v2 pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>:
Use filtered mode to make sure threshold interrupts are triggered,
protocol documentation, cosmetics
- I (bero@baylibre.com) will be taking care of this patchset
from now on, since Balsam has left BayLibre. Thanks for
getting it almost ready, Balsam!
v2 :
- Based on top of thermal/linux-next :
base-commit: 7ac82227ee046f8234471de4c12a40b8c2d3ddcc
- Squash "add thermal zones and thermal nodes" and
"add temperature mitigation threshold" commits together to form
"arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones" commit.
- Add Suspend and Resume support to LVTS Driver.
- Update Calibration Data documentation.
- Fix calibration data offsets for mt8192
(Thanks to "Chen-Yu Tsai" and "Nícolas F. R. A. Prado").
https://lore.kernel.org/all/20230425133052.199767-1-bchihi@baylibre.com/
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
v1 :
- The initial series "Add LVTS support for mt8192" :
"https://lore.kernel.org/all/20230307163413.143334-1-bchihi@baylibre.com/".
Balsam CHIHI (5):
dt-bindings: thermal: mediatek: Add LVTS thermal controller definition
for mt8192
thermal/drivers/mediatek/lvts_thermal: Add suspend and resume
thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
thermal/drivers/mediatek/lvts_thermal: Update calibration data
documentation
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 ++++++++++++++++++
drivers/thermal/mediatek/lvts_thermal.c | 160 +++++-
.../thermal/mediatek,lvts-thermal.h | 19 +
3 files changed, 631 insertions(+), 2 deletions(-)
base-commit: 6a3d37b4d885129561e1cef361216f00472f7d2e
--
2.41.0.rc2
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add full LVTS support (MCU thermal domain + AP thermal domain) to MediaTek MT8192 SoC.
Also, add Suspend and Resume support to LVTS Driver (all SoCs),
and update the documentation that describes the Calibration Data Offsets.
Changelog:
v3 :
- Rebased :
base-commit: 6a3d37b4d885129561e1cef361216f00472f7d2e
- Fix issues in v2 pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>:
Use filtered mode to make sure threshold interrupts are triggered,
protocol documentation, cosmetics
- I (bero@baylibre.com) will be taking care of this patchset
from now on, since Balsam has left BayLibre. Thanks for
getting it almost ready, Balsam!
v2 :
- Based on top of thermal/linux-next :
base-commit: 7ac82227ee046f8234471de4c12a40b8c2d3ddcc
- Squash "add thermal zones and thermal nodes" and
"add temperature mitigation threshold" commits together to form
"arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones" commit.
- Add Suspend and Resume support to LVTS Driver.
- Update Calibration Data documentation.
- Fix calibration data offsets for mt8192
(Thanks to "Chen-Yu Tsai" and "Nícolas F. R. A. Prado").
https://lore.kernel.org/all/20230425133052.199767-1-bchihi@baylibre.com/
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
v1 :
- The initial series "Add LVTS support for mt8192" :
"https://lore.kernel.org/all/20230307163413.143334-1-bchihi@baylibre.com/".
Balsam CHIHI (5):
dt-bindings: thermal: mediatek: Add LVTS thermal controller definition
for mt8192
thermal/drivers/mediatek/lvts_thermal: Add suspend and resume
thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
thermal/drivers/mediatek/lvts_thermal: Update calibration data
documentation
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 ++++++++++++++++++
drivers/thermal/mediatek/lvts_thermal.c | 160 +++++-
.../thermal/mediatek,lvts-thermal.h | 19 +
3 files changed, 631 insertions(+), 2 deletions(-)
base-commit: 6a3d37b4d885129561e1cef361216f00472f7d2e
--
2.41.0.rc2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192
2023-05-29 15:35 ` Bernhard Rosenkränzer
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add LVTS thermal controller definition for MT8192.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
.../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
index 8fa5a46675c46..5e9eb62174268 100644
--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
@@ -26,4 +26,23 @@
#define MT8195_AP_CAM0 15
#define MT8195_AP_CAM1 16
+#define MT8192_MCU_BIG_CPU0 0
+#define MT8192_MCU_BIG_CPU1 1
+#define MT8192_MCU_BIG_CPU2 2
+#define MT8192_MCU_BIG_CPU3 3
+#define MT8192_MCU_LITTLE_CPU0 4
+#define MT8192_MCU_LITTLE_CPU1 5
+#define MT8192_MCU_LITTLE_CPU2 6
+#define MT8192_MCU_LITTLE_CPU3 7
+
+#define MT8192_AP_VPU0 8
+#define MT8192_AP_VPU1 9
+#define MT8192_AP_GPU0 10
+#define MT8192_AP_GPU1 11
+#define MT8192_AP_INFRA 12
+#define MT8192_AP_CAM 13
+#define MT8192_AP_MD0 14
+#define MT8192_AP_MD1 15
+#define MT8192_AP_MD2 16
+
#endif /* __MEDIATEK_LVTS_DT_H */
--
2.41.0.rc2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add LVTS thermal controller definition for MT8192.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
.../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
index 8fa5a46675c46..5e9eb62174268 100644
--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
@@ -26,4 +26,23 @@
#define MT8195_AP_CAM0 15
#define MT8195_AP_CAM1 16
+#define MT8192_MCU_BIG_CPU0 0
+#define MT8192_MCU_BIG_CPU1 1
+#define MT8192_MCU_BIG_CPU2 2
+#define MT8192_MCU_BIG_CPU3 3
+#define MT8192_MCU_LITTLE_CPU0 4
+#define MT8192_MCU_LITTLE_CPU1 5
+#define MT8192_MCU_LITTLE_CPU2 6
+#define MT8192_MCU_LITTLE_CPU3 7
+
+#define MT8192_AP_VPU0 8
+#define MT8192_AP_VPU1 9
+#define MT8192_AP_GPU0 10
+#define MT8192_AP_GPU1 11
+#define MT8192_AP_INFRA 12
+#define MT8192_AP_CAM 13
+#define MT8192_AP_MD0 14
+#define MT8192_AP_MD1 15
+#define MT8192_AP_MD2 16
+
#endif /* __MEDIATEK_LVTS_DT_H */
--
2.41.0.rc2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume
2023-05-29 15:35 ` Bernhard Rosenkränzer
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add suspend and resume support to LVTS driver.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 34 +++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index d0a3f95b7884b..5ea8a9d569ea6 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -1169,6 +1169,38 @@ static int lvts_remove(struct platform_device *pdev)
return 0;
}
+static int lvts_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct lvts_domain *lvts_td;
+ int i;
+
+ lvts_td = platform_get_drvdata(pdev);
+
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
+
+ clk_disable_unprepare(lvts_td->clk);
+
+ return 0;
+}
+
+static int lvts_resume(struct platform_device *pdev)
+{
+ struct lvts_domain *lvts_td;
+ int i, ret;
+
+ lvts_td = platform_get_drvdata(pdev);
+
+ ret = clk_prepare_enable(lvts_td->clk);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
+
+ return 0;
+}
+
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
{
.cal_offset = { 0x04, 0x07 },
@@ -1268,6 +1300,8 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
static struct platform_driver lvts_driver = {
.probe = lvts_probe,
.remove = lvts_remove,
+ .suspend = lvts_suspend,
+ .resume = lvts_resume,
.driver = {
.name = "mtk-lvts-thermal",
.of_match_table = lvts_of_match,
--
2.41.0.rc2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add suspend and resume support to LVTS driver.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 34 +++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index d0a3f95b7884b..5ea8a9d569ea6 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -1169,6 +1169,38 @@ static int lvts_remove(struct platform_device *pdev)
return 0;
}
+static int lvts_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct lvts_domain *lvts_td;
+ int i;
+
+ lvts_td = platform_get_drvdata(pdev);
+
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
+
+ clk_disable_unprepare(lvts_td->clk);
+
+ return 0;
+}
+
+static int lvts_resume(struct platform_device *pdev)
+{
+ struct lvts_domain *lvts_td;
+ int i, ret;
+
+ lvts_td = platform_get_drvdata(pdev);
+
+ ret = clk_prepare_enable(lvts_td->clk);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
+
+ return 0;
+}
+
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
{
.cal_offset = { 0x04, 0x07 },
@@ -1268,6 +1300,8 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
static struct platform_driver lvts_driver = {
.probe = lvts_probe,
.remove = lvts_remove,
+ .suspend = lvts_suspend,
+ .resume = lvts_resume,
.driver = {
.name = "mtk-lvts-thermal",
.of_match_table = lvts_of_match,
--
2.41.0.rc2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
2023-05-29 15:35 ` Bernhard Rosenkränzer
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add LVTS Driver support for MT8192.
Co-developed-by : Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 5ea8a9d569ea6..d5e5214784ece 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -80,6 +80,7 @@
#define LVTS_MSR_FILTERED_MODE 1
#define LVTS_HW_SHUTDOWN_MT8195 105000
+#define LVTS_HW_SHUTDOWN_MT8192 105000
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
static int coeff_b = LVTS_COEFF_B;
@@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
}
};
+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
+ {
+ .cal_offset = { 0x04, 0x08 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU0 },
+ { .dt_id = MT8192_MCU_BIG_CPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ },
+ {
+ .cal_offset = { 0x0c, 0x10 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU2 },
+ { .dt_id = MT8192_MCU_BIG_CPU3 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ },
+ {
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
+ },
+ .num_lvts_sensor = 4,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ }
+};
+
+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
+ {
+ .cal_offset = { 0x24, 0x28 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_VPU0 },
+ { .dt_id = MT8192_AP_VPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x2c, 0x30 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_GPU0 },
+ { .dt_id = MT8192_AP_GPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x34, 0x38 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_INFRA },
+ { .dt_id = MT8192_AP_CAM },
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x3c, 0x40, 0x44 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_MD0 },
+ { .dt_id = MT8192_AP_MD1 },
+ { .dt_id = MT8192_AP_MD2 }
+ },
+ .num_lvts_sensor = 3,
+ .offset = 0x300,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ }
+};
+
static const struct lvts_data mt8195_lvts_mcu_data = {
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
@@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
};
+static const struct lvts_data mt8192_lvts_mcu_data = {
+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
+};
+
+static const struct lvts_data mt8192_lvts_ap_data = {
+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
+};
+
static const struct of_device_id lvts_of_match[] = {
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
{},
};
MODULE_DEVICE_TABLE(of, lvts_of_match);
--
2.41.0.rc2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add LVTS Driver support for MT8192.
Co-developed-by : Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 5ea8a9d569ea6..d5e5214784ece 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -80,6 +80,7 @@
#define LVTS_MSR_FILTERED_MODE 1
#define LVTS_HW_SHUTDOWN_MT8195 105000
+#define LVTS_HW_SHUTDOWN_MT8192 105000
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
static int coeff_b = LVTS_COEFF_B;
@@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
}
};
+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
+ {
+ .cal_offset = { 0x04, 0x08 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU0 },
+ { .dt_id = MT8192_MCU_BIG_CPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ },
+ {
+ .cal_offset = { 0x0c, 0x10 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU2 },
+ { .dt_id = MT8192_MCU_BIG_CPU3 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ },
+ {
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
+ },
+ .num_lvts_sensor = 4,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ }
+};
+
+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
+ {
+ .cal_offset = { 0x24, 0x28 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_VPU0 },
+ { .dt_id = MT8192_AP_VPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x2c, 0x30 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_GPU0 },
+ { .dt_id = MT8192_AP_GPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x34, 0x38 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_INFRA },
+ { .dt_id = MT8192_AP_CAM },
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x3c, 0x40, 0x44 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_MD0 },
+ { .dt_id = MT8192_AP_MD1 },
+ { .dt_id = MT8192_AP_MD2 }
+ },
+ .num_lvts_sensor = 3,
+ .offset = 0x300,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ }
+};
+
static const struct lvts_data mt8195_lvts_mcu_data = {
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
@@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
};
+static const struct lvts_data mt8192_lvts_mcu_data = {
+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
+};
+
+static const struct lvts_data mt8192_lvts_ap_data = {
+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
+};
+
static const struct of_device_id lvts_of_match[] = {
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
{},
};
MODULE_DEVICE_TABLE(of, lvts_of_match);
--
2.41.0.rc2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
2023-05-29 15:35 ` Bernhard Rosenkränzer
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add thermal nodes and thermal zones for the mt8192.
The mt8192 SoC has several hotspots around the CPUs.
Specify the targeted temperature threshold to apply the mitigation
and define the associated cooling devices.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[bero@baylibre.com: cosmetic changes]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++
1 file changed, 454 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 5c30caf740265..330c5bb4ebc85 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -14,6 +14,8 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
#include <dt-bindings/reset/mt8192-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
/ {
compatible = "mediatek,mt8192";
@@ -71,6 +73,7 @@ cpu0: cpu@0 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu1: cpu@100 {
@@ -88,6 +91,7 @@ cpu1: cpu@100 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu2: cpu@200 {
@@ -105,6 +109,7 @@ cpu2: cpu@200 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu3: cpu@300 {
@@ -122,6 +127,7 @@ cpu3: cpu@300 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu4: cpu@400 {
@@ -139,6 +145,7 @@ cpu4: cpu@400 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu5: cpu@500 {
@@ -156,6 +163,7 @@ cpu5: cpu@500 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu6: cpu@600 {
@@ -173,6 +181,7 @@ cpu6: cpu@600 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu7: cpu@700 {
@@ -190,6 +199,7 @@ cpu7: cpu@700 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu-map {
@@ -771,6 +781,17 @@ spi0: spi@1100a000 {
status = "disabled";
};
+ lvts_ap: thermal-sensor@1100b000 {
+ compatible = "mediatek,mt8192-lvts-ap";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@@ -1097,6 +1118,17 @@ nor_flash: spi@11234000 {
status = "disabled";
};
+ lvts_mcu: thermal-sensor@11278000 {
+ compatible = "mediatek,mt8192-lvts-mcu";
+ reg = <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
efuse: efuse@11c10000 {
compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
@@ -1823,4 +1855,426 @@ larb2: larb@1f002000 {
power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
};
};
+
+ thermal_zones: thermal-zones {
+ cpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
+
+ trips {
+ cpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
+
+ trips {
+ cpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
+
+ trips {
+ cpu2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
+
+ trips {
+ cpu3_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
+
+ trips {
+ cpu4_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
+
+ trips {
+ cpu5_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
+
+ trips {
+ cpu6_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
+
+ trips {
+ cpu7_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ vpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_VPU0>;
+
+ trips {
+ vpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ vpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ vpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_VPU1>;
+
+ trips {
+ vpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ vpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
+
+ trips {
+ gpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_GPU1>;
+
+ trips {
+ gpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ infra-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_INFRA>;
+
+ trips {
+ infra_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ infra_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cam-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_CAM>;
+
+ trips {
+ cam_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cam_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD0>;
+
+ trips {
+ md0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD1>;
+
+ trips {
+ md1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD2>;
+
+ trips {
+ md2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
--
2.41.0.rc2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add thermal nodes and thermal zones for the mt8192.
The mt8192 SoC has several hotspots around the CPUs.
Specify the targeted temperature threshold to apply the mitigation
and define the associated cooling devices.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[bero@baylibre.com: cosmetic changes]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++
1 file changed, 454 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 5c30caf740265..330c5bb4ebc85 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -14,6 +14,8 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
#include <dt-bindings/reset/mt8192-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
/ {
compatible = "mediatek,mt8192";
@@ -71,6 +73,7 @@ cpu0: cpu@0 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu1: cpu@100 {
@@ -88,6 +91,7 @@ cpu1: cpu@100 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu2: cpu@200 {
@@ -105,6 +109,7 @@ cpu2: cpu@200 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu3: cpu@300 {
@@ -122,6 +127,7 @@ cpu3: cpu@300 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu4: cpu@400 {
@@ -139,6 +145,7 @@ cpu4: cpu@400 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu5: cpu@500 {
@@ -156,6 +163,7 @@ cpu5: cpu@500 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu6: cpu@600 {
@@ -173,6 +181,7 @@ cpu6: cpu@600 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu7: cpu@700 {
@@ -190,6 +199,7 @@ cpu7: cpu@700 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu-map {
@@ -771,6 +781,17 @@ spi0: spi@1100a000 {
status = "disabled";
};
+ lvts_ap: thermal-sensor@1100b000 {
+ compatible = "mediatek,mt8192-lvts-ap";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@@ -1097,6 +1118,17 @@ nor_flash: spi@11234000 {
status = "disabled";
};
+ lvts_mcu: thermal-sensor@11278000 {
+ compatible = "mediatek,mt8192-lvts-mcu";
+ reg = <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
efuse: efuse@11c10000 {
compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
@@ -1823,4 +1855,426 @@ larb2: larb@1f002000 {
power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
};
};
+
+ thermal_zones: thermal-zones {
+ cpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
+
+ trips {
+ cpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
+
+ trips {
+ cpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
+
+ trips {
+ cpu2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
+
+ trips {
+ cpu3_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
+
+ trips {
+ cpu4_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
+
+ trips {
+ cpu5_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
+
+ trips {
+ cpu6_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
+
+ trips {
+ cpu7_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ vpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_VPU0>;
+
+ trips {
+ vpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ vpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ vpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_VPU1>;
+
+ trips {
+ vpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ vpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
+
+ trips {
+ gpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_GPU1>;
+
+ trips {
+ gpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ infra-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_INFRA>;
+
+ trips {
+ infra_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ infra_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cam-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_CAM>;
+
+ trips {
+ cam_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cam_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD0>;
+
+ trips {
+ md0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD1>;
+
+ trips {
+ md1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD2>;
+
+ trips {
+ md2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
--
2.41.0.rc2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation
2023-05-29 15:35 ` Bernhard Rosenkränzer
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Update LVTS calibration data documentation for mt8192 and mt8195.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index d5e5214784ece..9185d02003633 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -531,7 +531,8 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* The efuse blob values follows the sensor enumeration per thermal
* controller. The decoding of the stream is as follow:
*
- * stream index map for MCU Domain :
+ * MT8195 :
+ * Stream index map for MCU Domain mt8195 :
*
* <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
@@ -542,7 +543,7 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
* 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
*
- * stream index map for AP Domain :
+ * Stream index map for AP Domain mt8195 :
*
* <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
@@ -556,6 +557,32 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
* 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
*
+ * MT8192 :
+ * Stream index map for MCU Domain mt8192 :
+ *
+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
+ *
+ * <-----sensor#2-----> <-----sensor#3----->
+ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
+ *
+ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
+ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
+ *
+ * Stream index map for AP Domain mt8192 :
+ *
+ * <-----sensor#0-----> <-----sensor#1----->
+ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
+ *
+ * <-----sensor#2-----> <-----sensor#3----->
+ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
+ *
+ * <-----sensor#4-----> <-----sensor#5----->
+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
+ *
+ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
+ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
+ *
* The data description gives the offset of the calibration data in
* this bytes stream for each sensor.
*/
--
2.41.0.rc2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation
@ 2023-05-29 15:35 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 37+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 15:35 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzystof.kozlowski+dt, rdunlap,
ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Update LVTS calibration data documentation for mt8192 and mt8195.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index d5e5214784ece..9185d02003633 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -531,7 +531,8 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* The efuse blob values follows the sensor enumeration per thermal
* controller. The decoding of the stream is as follow:
*
- * stream index map for MCU Domain :
+ * MT8195 :
+ * Stream index map for MCU Domain mt8195 :
*
* <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
@@ -542,7 +543,7 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
* 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
*
- * stream index map for AP Domain :
+ * Stream index map for AP Domain mt8195 :
*
* <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
@@ -556,6 +557,32 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
* 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
*
+ * MT8192 :
+ * Stream index map for MCU Domain mt8192 :
+ *
+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
+ *
+ * <-----sensor#2-----> <-----sensor#3----->
+ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
+ *
+ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
+ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
+ *
+ * Stream index map for AP Domain mt8192 :
+ *
+ * <-----sensor#0-----> <-----sensor#1----->
+ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
+ *
+ * <-----sensor#2-----> <-----sensor#3----->
+ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
+ *
+ * <-----sensor#4-----> <-----sensor#5----->
+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
+ *
+ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
+ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
+ *
* The data description gives the offset of the calibration data in
* this bytes stream for each sensor.
*/
--
2.41.0.rc2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
2023-05-29 15:35 ` Bernhard Rosenkränzer
@ 2023-05-29 16:30 ` Matthias Brugger
-1 siblings, 0 replies; 37+ messages in thread
From: Matthias Brugger @ 2023-05-29 16:30 UTC (permalink / raw)
To: Bernhard Rosenkränzer, daniel.lezcano,
angelogioacchino.delregno, rafael, amitk, rui.zhang, robh+dt,
krzystof.kozlowski+dt, rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
Hi Bernhard,
Please resend with a subject line for the cover letter.
Regards,
Matthias
On 29/05/2023 17:35, Bernhard Rosenkränzer wrote:
> From: Balsam CHIHI <bchihi@baylibre.com>
>
> Add full LVTS support (MCU thermal domain + AP thermal domain) to MediaTek MT8192 SoC.
> Also, add Suspend and Resume support to LVTS Driver (all SoCs),
> and update the documentation that describes the Calibration Data Offsets.
>
> Changelog:
> v3 :
> - Rebased :
> base-commit: 6a3d37b4d885129561e1cef361216f00472f7d2e
> - Fix issues in v2 pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>:
> Use filtered mode to make sure threshold interrupts are triggered,
> protocol documentation, cosmetics
> - I (bero@baylibre.com) will be taking care of this patchset
> from now on, since Balsam has left BayLibre. Thanks for
> getting it almost ready, Balsam!
>
> v2 :
> - Based on top of thermal/linux-next :
> base-commit: 7ac82227ee046f8234471de4c12a40b8c2d3ddcc
> - Squash "add thermal zones and thermal nodes" and
> "add temperature mitigation threshold" commits together to form
> "arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones" commit.
> - Add Suspend and Resume support to LVTS Driver.
> - Update Calibration Data documentation.
> - Fix calibration data offsets for mt8192
> (Thanks to "Chen-Yu Tsai" and "Nícolas F. R. A. Prado").
> https://lore.kernel.org/all/20230425133052.199767-1-bchihi@baylibre.com/
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
>
> v1 :
> - The initial series "Add LVTS support for mt8192" :
> "https://lore.kernel.org/all/20230307163413.143334-1-bchihi@baylibre.com/".
>
> Balsam CHIHI (5):
> dt-bindings: thermal: mediatek: Add LVTS thermal controller definition
> for mt8192
> thermal/drivers/mediatek/lvts_thermal: Add suspend and resume
> thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
> arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
> thermal/drivers/mediatek/lvts_thermal: Update calibration data
> documentation
>
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 ++++++++++++++++++
> drivers/thermal/mediatek/lvts_thermal.c | 160 +++++-
> .../thermal/mediatek,lvts-thermal.h | 19 +
> 3 files changed, 631 insertions(+), 2 deletions(-)
>
> base-commit: 6a3d37b4d885129561e1cef361216f00472f7d2e
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
@ 2023-05-29 16:30 ` Matthias Brugger
0 siblings, 0 replies; 37+ messages in thread
From: Matthias Brugger @ 2023-05-29 16:30 UTC (permalink / raw)
To: Bernhard Rosenkränzer, daniel.lezcano,
angelogioacchino.delregno, rafael, amitk, rui.zhang, robh+dt,
krzystof.kozlowski+dt, rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
Hi Bernhard,
Please resend with a subject line for the cover letter.
Regards,
Matthias
On 29/05/2023 17:35, Bernhard Rosenkränzer wrote:
> From: Balsam CHIHI <bchihi@baylibre.com>
>
> Add full LVTS support (MCU thermal domain + AP thermal domain) to MediaTek MT8192 SoC.
> Also, add Suspend and Resume support to LVTS Driver (all SoCs),
> and update the documentation that describes the Calibration Data Offsets.
>
> Changelog:
> v3 :
> - Rebased :
> base-commit: 6a3d37b4d885129561e1cef361216f00472f7d2e
> - Fix issues in v2 pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>:
> Use filtered mode to make sure threshold interrupts are triggered,
> protocol documentation, cosmetics
> - I (bero@baylibre.com) will be taking care of this patchset
> from now on, since Balsam has left BayLibre. Thanks for
> getting it almost ready, Balsam!
>
> v2 :
> - Based on top of thermal/linux-next :
> base-commit: 7ac82227ee046f8234471de4c12a40b8c2d3ddcc
> - Squash "add thermal zones and thermal nodes" and
> "add temperature mitigation threshold" commits together to form
> "arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones" commit.
> - Add Suspend and Resume support to LVTS Driver.
> - Update Calibration Data documentation.
> - Fix calibration data offsets for mt8192
> (Thanks to "Chen-Yu Tsai" and "Nícolas F. R. A. Prado").
> https://lore.kernel.org/all/20230425133052.199767-1-bchihi@baylibre.com/
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
>
> v1 :
> - The initial series "Add LVTS support for mt8192" :
> "https://lore.kernel.org/all/20230307163413.143334-1-bchihi@baylibre.com/".
>
> Balsam CHIHI (5):
> dt-bindings: thermal: mediatek: Add LVTS thermal controller definition
> for mt8192
> thermal/drivers/mediatek/lvts_thermal: Add suspend and resume
> thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
> arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
> thermal/drivers/mediatek/lvts_thermal: Update calibration data
> documentation
>
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 ++++++++++++++++++
> drivers/thermal/mediatek/lvts_thermal.c | 160 +++++-
> .../thermal/mediatek,lvts-thermal.h | 19 +
> 3 files changed, 631 insertions(+), 2 deletions(-)
>
> base-commit: 6a3d37b4d885129561e1cef361216f00472f7d2e
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2022-06-12 7:44 ` Teng Long
0 siblings, 0 replies; 37+ messages in thread
From: Teng Long @ 2022-06-12 7:44 UTC (permalink / raw)
To: dyroneteng; +Cc: avarab, derrickstolee, git, gitster, me, tenglong.tl
Sorry for the late reply (in emergency project).
I reread the replies in patch v2 and fixed/optimized
in patch v3 in respective, I hope I haven't missed
anything.
Thanks.
Teng Long (5):
pack-bitmap.c: continue looping when first MIDX bitmap is found
pack-bitmap.c: rename "idx_name" to "bitmap_name"
pack-bitmap.c: make warnings support i18N when opening bitmap
pack-bitmap.c: using error() instead of silently returning -1
bitmap: add trace2 outputs during open "bitmap" file
pack-bitmap.c | 58 +++++++++++++++++++++++++++++++------------------
repo-settings.c | 1 +
2 files changed, 38 insertions(+), 21 deletions(-)
Range-diff against v2:
1: 1bfd2fb6ab ! 1: 589e3f4075 pack-bitmap.c: continue looping when first MIDX bitmap is found
@@ Commit message
the first one has been found, then will break out by a "return"
directly.
- But actually, it's better to don't stop the loop until we have visited
+ But actually, it's better to continue the loop until we have visited
both the MIDX in our repository, as well as any alternates (along with
_their_ alternates, recursively).
+ The reason for this is, there may exist more than one MIDX file in
+ a repo. The "multi_pack_index" struct is actually designed as a singly
+ linked list, and if a MIDX file has been already opened successfully,
+ then the other MIDX files will be skipped and left with a warning
+ "ignoring extra bitmap file." to the output.
+
The discussion link of community:
https://public-inbox.org/git/YjzCTLLDCby+kJrZ@nand.local/
2: 1fff3b3ca7 ! 2: b6b30047fc pack-bitmap.c: rename "idx_name" to "bitmap_name"
@@ Commit message
There may bring some confusion in this "idx_name" naming, which
might lead us to think of ".idx "or" multi-pack-index" files, - although bitmap is essentially can be understood as a kind of index
- , let's define this name a little more accurate here.
+ although bitmap is essentially can be understood as a kind of index,
+ let's define this name a little more accurate here.
Signed-off-by: Teng Long <dyroneteng@gmail.com>
3: 5a8f5afccf ! 3: d8dfe53dd4 pack-bitmap.c: make warnings more detailed when opening bitmap
@@ Metadata
Author: Teng Long <dyroneteng@gmail.com>
## Commit message ##
- pack-bitmap.c: make warnings more detailed when opening bitmap
+ pack-bitmap.c: make warnings support i18N when opening bitmap
When calling the "open_midx_bitmap_1()" or "open_pack_bitmap_1()", there
will be a warning if a normal bitmap or MIDX bitmap already has been
- opened, then let's make the warning information more detailed. For
- example, it makes the error clearer in case of an accidental
- regression where we start looking for single-pack bitmaps after
- successfully opening a multi-pack one.
-
- At the same time, we made the previous and new warning texts support
- translation.
+ opened, then let's make the warning text supporting for translation.
Discussion in community:
@@ pack-bitmap.c: static int open_midx_bitmap_1(struct bitmap_index *bitmap_git,
get_midx_filename(&buf, midx->object_dir);
/* ignore extra bitmap file; we can only handle one */
- warning("ignoring extra bitmap file: %s", buf.buf);
-+ warning(_("a normal or midx bitmap already has been opened"));
+ warning(_("ignoring extra bitmap file: %s"), buf.buf);
close(fd);
strbuf_release(&buf);
@@ pack-bitmap.c: static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, st
if (bitmap_git->pack || bitmap_git->midx) {
/* ignore extra bitmap file; we can only handle one */
- warning("ignoring extra bitmap file: %s", packfile->pack_name);
-+ warning(_("a normal or midx bitmap already has been opened "));
+ warning(_("ignoring extra bitmap file: %s"), packfile->pack_name);
close(fd);
return -1;
}
-
- ## t/t5310-pack-bitmaps.sh ##
-@@ t/t5310-pack-bitmaps.sh: test_expect_success 'complains about multiple pack bitmaps' '
- test_line_count = 2 bitmaps &&
-
- git rev-list --use-bitmap-index HEAD 2>err &&
-+ grep "a bitmap has been opened" err &&
- grep "ignoring extra bitmap file" err
- )
- '
5: 1a169d7b5e ! 4: 72da3b5844 pack-bitmap.c: using error() instead of silently returning -1
@@ Commit message
## pack-bitmap.c ##
@@ pack-bitmap.c: static int open_midx_bitmap_1(struct bitmap_index *bitmap_git,
- trace2_data_string("midx", the_repository, "stat bitmap file",
- "failed");
+
+ if (fstat(fd, &st)) {
close(fd);
- return -1;
-+ return error("cannot stat bitmap file");
++ return error(_("cannot stat bitmap file"));
}
if (bitmap_git->pack || bitmap_git->midx) {
@@ pack-bitmap.c: static int open_midx_bitmap_1(struct bitmap_index *bitmap_git,
static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, struct packed_git *packfile)
@@ pack-bitmap.c: static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, struct packed_git
- trace2_data_string("bitmap", the_repository, "stat bitmap file",
- "failed");
+
+ if (fstat(fd, &st)) {
close(fd);
- return -1;
-+ return error("cannot stat bitmap file");
++ return error(_("cannot stat bitmap file"));
}
if (bitmap_git->pack || bitmap_git->midx) {
@@ pack-bitmap.c: static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, struct packed_git
+
if (!is_pack_valid(packfile)) {
- trace2_data_string("bitmap", the_repository, "packfile", "invalid");
close(fd);
- return -1;
-+ return error("packfile is invalid");
++ return error(_("packfile is invalid"));
}
bitmap_git->pack = packfile;
@@ pack-bitmap.c: static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, st
bitmap_git->map_pos = 0;
bitmap_git->pack = NULL;
- return -1;
-+ return error("bitmap header is invalid");
++ return error(_("bitmap header is invalid"));
}
return 0;
4: 2016ef2e34 ! 5: e118758d1d bitmap: add trace2 outputs during open "bitmap" file
@@ Metadata
## Commit message ##
bitmap: add trace2 outputs during open "bitmap" file
- It's supported for a Git repo to use bitmap in both normal bitmap way
- or a multi-pack-index bitmap.
-
- Sometimes the debug path is not obvious, for example, when executing:
+ It's supported for a repo to use bitmap in both "NORMAL" bitmap way
+ or a MIDX (multi-pack-index) bitmap. Either of two bitmap kinds can
+ exist in the repository, or both can be stored but let the config
+ controls which kind of bitmap is used (like "core.multipackIndex",
+ etc.). Because of this, sometimes the bitmap debug path is not
+ obvious enough, for example, when executing:
$git rev-list --test-bitmap HEAD
fatal: failed to load bitmap indexes
- If we see the output like this, we are not sure about what's happened,
- because the cause should be :
+ If we see the output like this, It's not sure for us to know
+ what's happened concretely, because the cause should be :
- 1. neither normal nor midx bitmap exists
- 2. only midx bitmap exists but core.multipackIndex="false"
- 3. core.multipackIndex="true" but midx bitmap file is currupt
- 4. core.multipackIndex="true" and no midx bitmap exists but
- normal bitmap file is currupt
+ 1. Neither normal nor MIDX bitmap exists.
+ 2. Only MIDX bitmap exists but core.multipackIndex="false".
+ 3. Config core.multipackIndex set to "true" but MIDX bitmap is
+ corrupted.
+ 4. Config core.multipackIndex set to "true" and no MIDX bitmap
+ exists but normal bitmap file is corrupted.
....
These are some of the scenarios I briefly tested, but maybe there are
- others (some scenarios is produced manually like "currupt bitmap file",
+ others (some scenarios is produced manually like "corrupted bitmap file",
but it's not represent it's an existed bug.).
Therefore, we added some TRACE2 code so that when we read the bitmap
we can be more clear about the decision path, such as whether it is
- working on midx bitmap or normal bitmap, or is it simply because the
- related configuration is disabled. This may help with logging, user
- troubleshooting, and development debugging.
-
- Here are some output examples when executing
- "$GIT_TRACE2_PERF=1 git rev-list --test-bitmap HEAD" under different
- situations:
-
- 1. _HAVE_ MIDX bitmap and NORMAL bitmap file, but the
- "core.multipackIndex" configures as "false":
-
- 19:38:43.007840 common-main.c:49 | d0 | main | version | | | | | 2.35.1.582.g8e9092487a
- 19:38:43.007874 common-main.c:50 | d0 | main | start | | 0.000305 | | | /opt/git/master/bin/git rev-list --test-bitmap HEAD
- 19:38:43.007950 compat/linux/procinfo.c:170 | d0 | main | cmd_ancestry | | | | | ancestry:[bash sshd sshd sshd systemd]
- 19:38:43.008091 git.c:460 | d0 | main | cmd_name | | | | | rev-list (rev-list)
- 19:38:43.008284 repo-settings.c:11 | d0 | main | data | r0 | 0.000720 | 0.000720 | config | feature.manyfiles:false
- 19:38:43.008297 repo-settings.c:11 | d0 | main | data | r0 | 0.000734 | 0.000734 | config | feature.experimental:false
- 19:38:43.008305 repo-settings.c:11 | d0 | main | data | r0 | 0.000742 | 0.000742 | config | core.commitgraph:true
- 19:38:43.008313 repo-settings.c:11 | d0 | main | data | r0 | 0.000749 | 0.000749 | config | commitgraph.readchangedpaths:true
- 19:38:43.008320 repo-settings.c:11 | d0 | main | data | r0 | 0.000756 | 0.000756 | config | gc.writecommitgraph:true
- 19:38:43.008327 repo-settings.c:11 | d0 | main | data | r0 | 0.000764 | 0.000764 | config | fetch.writecommitgraph:false
- 19:38:43.008334 repo-settings.c:11 | d0 | main | data | r0 | 0.000770 | 0.000770 | config | pack.usesparse:true
- 19:38:43.008341 repo-settings.c:11 | d0 | main | data | r0 | 0.000777 | 0.000777 | config | core.multipackindex:false
- 19:38:43.008348 repo-settings.c:11 | d0 | main | data | r0 | 0.000784 | 0.000784 | config | index.sparse:false
- 19:38:43.008724 pack-bitmap.c:536 | d0 | main | region_enter | r0 | 0.001160 | | pack-bitmap | label:open_bitmap
- 19:38:43.008738 pack-bitmap.c:390 | d0 | main | data | r0 | 0.001173 | 0.000013 | bitmap | ..try to open bitmap:/home/tenglong.tl/test/dyrone/.git/objects/pack/pack-2d1b3f749fb859b874710e33263d0847ef009e03.bitmap
- 19:38:43.008754 pack-bitmap.c:543 | d0 | main | region_leave | r0 | 0.001191 | 0.000031 | pack-bitmap | label:open_bitmap
- Bitmap v1 test (8 entries loaded)
- Found bitmap for 0a7df7ae92f8d8ed879c240f8ae9cdd33d18085e. 64 bits / 1801edc6 checksum
- 19:38:43.009099 progress.c:268 | d0 | main | region_enter | r0 | 0.001535 | | progress | label:Verifying bitmap entries
- Verifying bitmap entries: 100% (27/27), done.
- 19:38:43.009294 progress.c:339 | d0 | main | data | r0 | 0.001730 | 0.000195 | progress | ..total_objects:27
- 19:38:43.009302 progress.c:346 | d0 | main | region_leave | r0 | 0.001739 | 0.000204 | progress | label:Verifying bitmap entries
- OK!
- 19:38:43.009321 git.c:718 | d0 | main | exit | | 0.001757 | | | code:0
- 19:38:43.009329 trace2/tr2_tgt_perf.c:215 | d0 | main | atexit | | 0.001766 | | | code:0
-
- 2. _HAVE_ MIDX bitmap and NORMAL bitmap file, but the
- "core.multipackIndex" configures as "true":
-
- (omit duplicate outputs)
- ...
- 20:02:31.288797 repo-settings.c:11 | d0 | main | data | r0 | 0.000811 | 0.000811 | config | core.multipackindex:true
- 20:02:31.288806 repo-settings.c:11 | d0 | main | data | r0 | 0.000819 | 0.000819 | config | index.sparse:false
- 20:02:31.288836 midx.c:185 | d0 | main | data | r0 | 0.000849 | 0.000849 | midx | load/num_packs:1
- 20:02:31.288843 midx.c:186 | d0 | main | data | r0 | 0.000857 | 0.000857 | midx | load/num_objects:27
- 20:02:31.289217 pack-bitmap.c:536 | d0 | main | region_enter | r0 | 0.001229 | | pack-bitmap | label:open_bitmap
- 20:02:31.289230 pack-bitmap.c:318 | d0 | main | data | r0 | 0.001242 | 0.000013 | midx | ..try to open bitmap:/home/tenglong.tl/test/dyrone/.git/objects/pack/multi-pack-index-b6b04fbe053bd500d9ca13354466d3249dc275ac.bitmap
- 20:02:31.289252 pack-revindex.c:315 | d0 | main | data | r0 | 0.001265 | 0.000036 | load_midx_re | ..source:midx
- 20:02:31.289261 pack-bitmap.c:543 | d0 | main | region_leave | r0 | 0.001274 | 0.000045 | pack-bitmap | label:open_bitmap
- Bitmap v1 test (8 entries loaded)
- Found bitmap for 0a7df7ae92f8d8ed879c240f8ae9cdd33d18085e. 64 bits / 1801edc6 checksum
- 20:02:31.289594 progress.c:268 | d0 | main | region_enter | r0 | 0.001607 | | progress | label:Verifying bitmap entries
- Verifying bitmap entries: 100% (27/27), done.
- 20:02:31.289810 progress.c:339 | d0 | main | data | r0 | 0.001823 | 0.000216 | progress | ..total_objects:27
- 20:02:31.289824 progress.c:346 | d0 | main | region_leave | r0 | 0.001837 | 0.000230 | progress | label:Verifying bitmap entries
- OK!
- 20:02:31.289843 git.c:718 | d0 | main | exit | | 0.001856 | | | code:0
- 20:02:31.289860 trace2/tr2_tgt_perf.c:215 | d0 | main | atexit | | 0.001873 | | | code:0
-
- 3. _HAVE_ MIDX bitmap and a corrupt NORMAL bitmap file, but the
- "core.multipackIndex" configures as "false" :
-
- (omit duplicate outputs)
- ...
- 20:14:06.539305 repo-settings.c:11 | d0 | main | data | r0 | 0.000794 | 0.000794 | config | core.multipackindex:false
- 20:14:06.539310 repo-settings.c:11 | d0 | main | data | r0 | 0.000799 | 0.000799 | config | index.sparse:false
- 20:14:06.539658 pack-bitmap.c:536 | d0 | main | region_enter | r0 | 0.001146 | | pack-bitmap | label:open_bitmap
- 20:14:06.539671 pack-bitmap.c:390 | d0 | main | data | r0 | 0.001160 | 0.000014 | bitmap | ..try to open bitmap:/home/tenglong.tl/test/dyrone/.git/objects/pack/pack-2d1b3f749fb859b874710e33263d0847ef009e03.bitmap
- 20:14:06.539686 usage.c:79 | d0 | main | error | | | | | ..Corrupted bitmap index file (wrong header)
- error: Corrupted bitmap index file (wrong header)
- 20:14:06.539696 pack-bitmap.c:426 | d0 | main | data | r0 | 0.001185 | 0.000039 | bitmap | ..load bitmap header:failed
- 20:14:06.539709 usage.c:79 | d0 | main | error | | | | | ..bitmap header is invalid
- error: bitmap header is invalid
- 20:14:06.539719 pack-bitmap.c:543 | d0 | main | region_leave | r0 | 0.001208 | 0.000062 | pack-bitmap | label:open_bitmap
- 20:14:06.539726 usage.c:60 | d0 | main | error | | | | | failed to load bitmap indexes
- fatal: failed to load bitmap indexes
- 20:14:06.539735 usage.c:74 | d0 | main | exit | | 0.001224 | | | code:128
- 20:14:06.539744 trace2/tr2_tgt_perf.c:215 | d0 | main | atexit | | 0.001233 | | | code:128
+ working on MIDX or NORMAL bitmap at present, or the related config is
+ enabled or not. This may help with logging, user troubleshooting, and
+ development debugging.
+
+ Here are some brief output examples on different scenarios when
+ executing:
+
+ $GIT_TRACE2_PERF=1 git rev-list --test-bitmap HEAD
+
+ Scenario 1: core.multipackIndex [false], midx bitmap exists [Y],
+ normal bitmap exists [N]
+
+ 19:21:56.580349 repo-settings.c:11 | d0 | main | data | r1 | 0.000827 | 0.000827 | config | core.multipackindex:false
+ 19:21:56.580356 repo-settings.c:11 | d0 | main | data | r1 | 0.000834 | 0.000834 | config | index.sparse:false
+ 19:21:56.580706 pack-bitmap.c:525 | d0 | main | region_enter | r1 | 0.001183 | | pack-bitmap | label:open_bitmap
+ 19:21:56.580719 pack-bitmap.c:386 | d0 | main | data | r1 | 0.001196 | 0.000013 | bitmap | ..path:.git/objects/pack/pack-e9eb18e6a423057f4424a762069e13804a75d01e.bitmap
+ 19:21:56.580729 pack-bitmap.c:530 | d0 | main | region_leave | r1 | 0.001207 | 0.000024 | pack-bitmap | label:open_bitmap
+ 19:21:56.580737 usage.c:60 | d0 | main | error | | | | | failed to load bitmap indexes
+ fatal: failed to load bitmap indexes
+ 19:21:56.580746 usage.c:74 | d0 | main | exit | | 0.001224 | | | code:128
+ 19:21:56.580754 trace2/tr2_tgt_perf.c:215 | d0 | main | atexit | | 0.001232 | | | code:128
+
+ Scenario 2: core.multipackIndex [false], midx bitmap exists [Y],
+ normal bitmap exists [Y]
+
+ 19:23:44.692384 repo-settings.c:11 | d0 | main | data | r0 | 0.000765 | 0.000765 | config | core.multipackindex:false
+ 19:23:44.692755 pack-bitmap.c:525 | d0 | main | region_enter | r0 | 0.001135 | | pack-bitmap | label:open_bitmap
+ 19:23:44.692768 pack-bitmap.c:386 | d0 | main | data | r0 | 0.001149 | 0.000014 | bitmap | ..path:/home/tenglong.tl/test/dyrone_bitmap/.git/objects/pack/pack-e9eb18e6a423057f4424a762069e13804a75d01e.bitmap
+ 19:23:44.692790 pack-bitmap.c:530 | d0 | main | region_leave | r0 | 0.001171 | 0.000036 | pack-bitmap | label:open_bitmap
+ Bitmap v1 test (1 entries loaded)
+ Found bitmap for d864fefa87415d6cd289c72aa9ffd45b4a8ffd84. 64 bits / 11030517 checksum
+ 19:23:44.693119 progress.c:268 | d0 | main | region_enter | r0 | 0.001500 | | progress | label:Verifying bitmap entries
+ Verifying bitmap entries: 100% (3/3), done.
+ 19:23:44.693208 progress.c:339 | d0 | main | data | r0 | 0.001589 | 0.000089 | progress | ..total_objects:3
+ 19:23:44.693216 progress.c:346 | d0 | main | region_leave | r0 | 0.001597 | 0.000097 | progress | label:Verifying bitmap entries
+ OK!
+ 19:23:44.693234 git.c:718 | d0 | main | exit | | 0.001615 | | | code:0
+ 19:23:44.693244 trace2/tr2_tgt_perf.c:215 | d0 | main | atexit | | 0.001625 | | | code:0
+
+ Scenario 3: core.multipackIndex [true], midx bitmap exists [Y],
+ normal bitmap exists [Y]
+
+ 19:26:03.625055 repo-settings.c:11 | d0 | main | data | r0 | 0.000760 | 0.000760 | config | core.multipackindex:true
+ 19:26:03.625090 midx.c:185 | d0 | main | data | r0 | 0.000795 | 0.000795 | midx | load/num_packs:1
+ 19:26:03.625097 midx.c:186 | d0 | main | data | r0 | 0.000803 | 0.000803 | midx | load/num_objects:3
+ 19:26:03.625455 pack-bitmap.c:525 | d0 | main | region_enter | r0 | 0.001160 | | pack-bitmap | label:open_bitmap
+ 19:26:03.625470 pack-bitmap.c:318 | d0 | main | data | r0 | 0.001175 | 0.000015 | midx | ..path:/home/tenglong.tl/test/dyrone_bitmap/.git/objects/pack/multi-pack-index-fe8e96790bd34926423bdf3efd762dbbea9f3213.bitmap
+ 19:26:03.625489 pack-revindex.c:315 | d0 | main | data | r0 | 0.001194 | 0.000034 | load_midx_re | ..source:midx
+ 19:26:03.625496 pack-bitmap.c:530 | d0 | main | region_leave | r0 | 0.001202 | 0.000042 | pack-bitmap | label:open_bitmap
+ Bitmap v1 test (1 entries loaded)
+ Found bitmap for d864fefa87415d6cd289c72aa9ffd45b4a8ffd84. 64 bits / 11030517 checksum
+ 19:26:03.625818 progress.c:268 | d0 | main | region_enter | r0 | 0.001523 | | progress | label:Verifying bitmap entries
+ Verifying bitmap entries: 100% (3/3), done.
+ 19:26:03.625916 progress.c:339 | d0 | main | data | r0 | 0.001622 | 0.000099 | progress | ..total_objects:3
+ 19:26:03.625925 progress.c:346 | d0 | main | region_leave | r0 | 0.001630 | 0.000107 | progress | label:Verifying bitmap entries
+ OK!
+ 19:26:03.625943 git.c:718 | d0 | main | exit | | 0.001648 | | | code:0
+ 19:26:03.625952 trace2/tr2_tgt_perf.c:215 | d0 | main | atexit | | 0.001658 | | | code:0
+
+ Situation 4: core.multipackIndex [false], midx bitmap exists [N],
+ normal bitmap exists [Y].
+
+ 19:27:15.383037 repo-settings.c:11 | d0 | main | data | r0 | 0.000746 | 0.000746 | config | core.multipackindex:true
+ 19:27:15.383397 pack-bitmap.c:525 | d0 | main | region_enter | r0 | 0.001105 | | pack-bitmap | label:open_bitmap
+ 19:27:15.383408 pack-bitmap.c:386 | d0 | main | data | r0 | 0.001116 | 0.000011 | bitmap | ..path:/home/tenglong.tl/test/dyrone_bitmap/.git/objects/pack/pack-e9eb18e6a423057f4424a762069e13804a75d01e.bitmap
+ 19:27:15.383419 pack-bitmap.c:530 | d0 | main | region_leave | r0 | 0.001128 | 0.000023 | pack-bitmap | label:open_bitmap
+ Bitmap v1 test (1 entries loaded)
+ Found bitmap for d864fefa87415d6cd289c72aa9ffd45b4a8ffd84. 64 bits / 11030517 checksum
+ 19:27:15.383730 progress.c:268 | d0 | main | region_enter | r0 | 0.001439 | | progress | label:Verifying bitmap entries
+ Verifying bitmap entries: 100% (3/3), done.
+ 19:27:15.383822 progress.c:339 | d0 | main | data | r0 | 0.001531 | 0.000092 | progress | ..total_objects:3
+ 19:27:15.383830 progress.c:346 | d0 | main | region_leave | r0 | 0.001539 | 0.000100 | progress | label:Verifying bitmap entries
+ OK!
+ 19:27:15.383848 git.c:718 | d0 | main | exit | | 0.001557 | | | code:0
+ 19:27:15.383867 trace2/tr2_tgt_perf.c:215 | d0 | main | atexit | | 0.001576 | | | code:0
+
+ Scenario 5: core.multipackIndex [true], midx bitmap exists [Y] but corrupted,
+ normal bitmap exists [Y]
+
+ 19:29:25.888233 repo-settings.c:11 | d0 | main | data | r0 | 0.000794 | 0.000794 | config | core.multipackindex:true
+ 19:29:25.888591 pack-bitmap.c:525 | d0 | main | region_enter | r0 | 0.001152 | | pack-bitmap | label:open_bitmap
+ 19:29:25.888603 pack-bitmap.c:386 | d0 | main | data | r0 | 0.001163 | 0.000011 | bitmap | ..path:/home/tenglong.tl/test/dyrone_bitmap/.git/objects/pack/pack-e9eb18e6a423057f4424a762069e13804a75d01e.bitmap
+ 19:29:25.888622 usage.c:79 | d0 | main | error | | | | | ..Corrupted bitmap index file (wrong header)
+ error: Corrupted bitmap index file (wrong header)
+ 19:29:25.888638 usage.c:79 | d0 | main | error | | | | | ..bitmap header is invalid
+ error: bitmap header is invalid
+ 19:29:25.888650 pack-bitmap.c:530 | d0 | main | region_leave | r0 | 0.001211 | 0.000059 | pack-bitmap | label:open_bitmap
+ 19:29:25.888659 usage.c:60 | d0 | main | error | | | | | failed to load bitmap indexes
+ fatal: failed to load bitmap indexes
+ 19:29:25.888670 usage.c:74 | d0 | main | exit | | 0.001231 | | | code:128
+ 19:29:25.888680 trace2/tr2_tgt_perf.c:215 | d0 | main | atexit | | 0.001241 | | | code:128
Signed-off-by: Teng Long <dyroneteng@gmail.com>
@@ pack-bitmap.c: char *pack_bitmap_filename(struct packed_git *p)
struct stat st;
char *bitmap_name = midx_bitmap_filename(midx);
- int fd = git_open(bitmap_name);
-+ trace2_data_string("midx", the_repository, "try to open bitmap",
-+ bitmap_name);
++ trace2_data_string("midx", the_repository, "path", bitmap_name);
+ fd = git_open(bitmap_name);
free(bitmap_name);
-@@ pack-bitmap.c: static int open_midx_bitmap_1(struct bitmap_index *bitmap_git,
- return -1;
-
- if (fstat(fd, &st)) {
-+ trace2_data_string("midx", the_repository, "stat bitmap file",
-+ "failed");
- close(fd);
- return -1;
- }
@@ pack-bitmap.c: static int open_midx_bitmap_1(struct bitmap_index *bitmap_git,
MAP_PRIVATE, fd, 0);
close(fd);
@@ pack-bitmap.c: static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, st
return -1;
bitmap_name = pack_bitmap_filename(packfile);
-+ trace2_data_string("bitmap", the_repository, "try to open bitmap",
-+ bitmap_name);
++ trace2_data_string("bitmap", the_repository, "path", bitmap_name);
fd = git_open(bitmap_name);
free(bitmap_name);
-@@ pack-bitmap.c: static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, struct packed_git
- return -1;
-
- if (fstat(fd, &st)) {
-+ trace2_data_string("bitmap", the_repository, "stat bitmap file",
-+ "failed");
- close(fd);
- return -1;
- }
-@@ pack-bitmap.c: static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, struct packed_git
- }
-
- if (!is_pack_valid(packfile)) {
-+ trace2_data_string("bitmap", the_repository, "packfile", "invalid");
- close(fd);
- return -1;
- }
-@@ pack-bitmap.c: static int open_pack_bitmap_1(struct bitmap_index *bitmap_git, struct packed_git
- close(fd);
-
- if (load_bitmap_header(bitmap_git) < 0) {
-+ trace2_data_string("bitmap", the_repository,
-+ "load bitmap header", "failed");
- munmap(bitmap_git->map, bitmap_git->map_size);
- bitmap_git->map = NULL;
- bitmap_git->map_size = 0;
@@ pack-bitmap.c: static int open_midx_bitmap(struct repository *r,
static int open_bitmap(struct repository *r,
struct bitmap_index *bitmap_git)
{
- assert(!bitmap_git->map);
-+ int ret = -1;
++ int ret = 0;
-- if (!open_midx_bitmap(r, bitmap_git))
-- return 0;
-- return open_pack_bitmap(r, bitmap_git);
+ assert(!bitmap_git->map);
+ trace2_region_enter("pack-bitmap", "open_bitmap", r);
-+ if (!open_midx_bitmap(r, bitmap_git)) {
-+ ret = 0;
+ if (!open_midx_bitmap(r, bitmap_git))
+- return 0;
+- return open_pack_bitmap(r, bitmap_git);
+ goto done;
-+ }
+ ret = open_pack_bitmap(r, bitmap_git);
+done:
+ trace2_region_leave("pack-bitmap", "open_bitmap", r);
@@ repo-settings.c: static void repo_cfg_bool(struct repository *r, const char *key
}
void prepare_repo_settings(struct repository *r)
-
- ## t/t5310-pack-bitmaps.sh ##
-@@ t/t5310-pack-bitmaps.sh: test_expect_success 'complains about multiple pack bitmaps' '
- test_line_count = 2 bitmaps &&
-
- git rev-list --use-bitmap-index HEAD 2>err &&
-- grep "a bitmap has been opened" err &&
-- grep "ignoring extra bitmap file" err
-+ grep "warning: a normal or midx bitmap already has been opened" err &&
-+ grep "warning: ignoring extra bitmap file" err
- )
- '
-
--
2.35.1.582.g320e881567
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
2021-12-19 23:46 ` Florian Fainelli
@ 2021-12-20 8:59 ` Marc Zyngier
0 siblings, 0 replies; 37+ messages in thread
From: Marc Zyngier @ 2021-12-20 8:59 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-arm-kernel, Chris Healy, Will Deacon, Stefan Wahren,
vincent.weaver, Mark Rutland
Hi Florian,
On Sun, 19 Dec 2021 23:46:32 +0000,
Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> Hi Will, Marc,
+Mark
>
> On 5/21/2018 11:19 AM, Will Deacon wrote:
> > Hi Marc,
> >
> > Thanks for this.
> >
> > On Fri, May 18, 2018 at 03:39:08PM +0100, Marc Zyngier wrote:
> >> PMUv3 has been introduced with ARMv8 and, while it has only been used
> >> on 64bit systems so far, it would definitely be useful for 32bit
> >> guests running under KVM/arm64, for example.
> >>
> >> There is also the case of people natively running 32bit kernels on
> >> 64bit HW and trying to upstream unspeakable hacks, hoping that the
> >> stars will align and that they'll win the lottery (see [1]).
> >>
> >> So let's try again, and make the PMUv3 driver usable for everyone.
> >>
> >> This is done in three steps:
> >> (1) Move the driver from arch/arm64 to drivers/perf
> >> (2) Add a handful of system register accessors so that we can reuse
> >> the driver on 32bit
> >> (3) Provide the same accessors on 32bit, enable compilation, and
> >> make it the default selection for mach-virt.
> >>
> >> Tested on a Seattle box with 32bit guests.
> >
> > I think we should go ahead with something like this, but I don't think
> > we're quite there with these patches. If we're going to move the arch code
> > out into drivers, let's do that for the perf_event* files under arch/arm/
> > as well. Then we could have a structure along the lines of:
> >
> >
> > drivers/perf/arm_pmu.c - As it is today
> > drivers/perf/arm_cpu/xscale_pmu.c - Only builds for 32-bit
> > drivers/perf/arm_cpu/armv6_pmu.c - Only builds for 32-bit
> > drivers/perf/arm_cpu/arch_pmu.c - Works for v7/v8 on
> > both 32-bit and 64-bit
>
> There has been a recent renewed interest in this patch series from my
> side as well as other users, and I have picked up where Marc left and
> started moving the Xscale and ARMv6 PMU drivers as Will had asked the
> current result can be seen here:
>
> https://github.com/ffainelli/linux/commits/arm-pmuv3
Blast from the past!
>
> It is not entirely clear to me what you had in mind when you want to
> have a common driver for v7 and v8 under
> drivers/perf/arm_cpu/arch_pmu.c. How much sharing or consolidation
> would you expect to be done there?
The v7/v8 models are very similar (they share most of the registers,
and there is only a few bits and pieces that differ between PMUv3 and
its ancestors). It should be possible to build a single driver
However, the 32bit PMU code is bundled together with the
Krait/Scorpion code that isn't quite the same. Maybe this should be
spun as a different driver if this can be disentangled neatly enough?
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
2018-05-21 18:19 ` Will Deacon
(?)
@ 2021-12-19 23:46 ` Florian Fainelli
2021-12-20 8:59 ` Marc Zyngier
-1 siblings, 1 reply; 37+ messages in thread
From: Florian Fainelli @ 2021-12-19 23:46 UTC (permalink / raw)
To: linux-arm-kernel, Marc Zyngier, Chris Healy, Will Deacon,
Stefan Wahren, vincent.weaver
Hi Will, Marc,
On 5/21/2018 11:19 AM, Will Deacon wrote:
> Hi Marc,
>
> Thanks for this.
>
> On Fri, May 18, 2018 at 03:39:08PM +0100, Marc Zyngier wrote:
>> PMUv3 has been introduced with ARMv8 and, while it has only been used
>> on 64bit systems so far, it would definitely be useful for 32bit
>> guests running under KVM/arm64, for example.
>>
>> There is also the case of people natively running 32bit kernels on
>> 64bit HW and trying to upstream unspeakable hacks, hoping that the
>> stars will align and that they'll win the lottery (see [1]).
>>
>> So let's try again, and make the PMUv3 driver usable for everyone.
>>
>> This is done in three steps:
>> (1) Move the driver from arch/arm64 to drivers/perf
>> (2) Add a handful of system register accessors so that we can reuse
>> the driver on 32bit
>> (3) Provide the same accessors on 32bit, enable compilation, and
>> make it the default selection for mach-virt.
>>
>> Tested on a Seattle box with 32bit guests.
>
> I think we should go ahead with something like this, but I don't think
> we're quite there with these patches. If we're going to move the arch code
> out into drivers, let's do that for the perf_event* files under arch/arm/
> as well. Then we could have a structure along the lines of:
>
>
> drivers/perf/arm_pmu.c - As it is today
> drivers/perf/arm_cpu/xscale_pmu.c - Only builds for 32-bit
> drivers/perf/arm_cpu/armv6_pmu.c - Only builds for 32-bit
> drivers/perf/arm_cpu/arch_pmu.c - Works for v7/v8 on
> both 32-bit and 64-bit
There has been a recent renewed interest in this patch series from my
side as well as other users, and I have picked up where Marc left and
started moving the Xscale and ARMv6 PMU drivers as Will had asked the
current result can be seen here:
https://github.com/ffainelli/linux/commits/arm-pmuv3
It is not entirely clear to me what you had in mind when you want to
have a common driver for v7 and v8 under
drivers/perf/arm_cpu/arch_pmu.c. How much sharing or consolidation would
you expect to be done there?
Thanks!
--
Florian
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
2019-02-08 16:11 ` Federico Vaga
(?)
@ 2019-02-09 21:41 ` Andrew Lunn
-1 siblings, 0 replies; 37+ messages in thread
From: Andrew Lunn @ 2019-02-09 21:41 UTC (permalink / raw)
To: Federico Vaga; +Cc: Peter Korsgaard, linux-i2c, linux-kernel
On Fri, Feb 08, 2019 at 05:11:56PM +0100, Federico Vaga wrote:
> This patch set provides improvements to the i2c-ocore driver.
Hi Federico
Please could you fixup the SPDX patch, add my review/tested by tags,
and i think we are good to go.
Thanks
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2019-02-08 16:11 ` Federico Vaga
0 siblings, 0 replies; 37+ messages in thread
From: Federico Vaga @ 2019-02-08 16:11 UTC (permalink / raw)
To: Peter Korsgaard, Andrew Lunn; +Cc: linux-i2c, linux-kernel
This patch set provides improvements to the i2c-ocore driver.
[V2 -> V3]
- fix error condition on platform_get_irq(). Copied from
https://patchwork.ozlabs.org/patch/1038409/
[V1 -> V2]
- replaced usleep_range() with udelay() so that the polling version can be
used in atomic context.
- added dedicated patch for minor style issues
- fixed delay computation
- use spin_lock_irqsave(), instead of spin_trylock_irqsave(). IACK is always
necessary and a trylock would generate an extra interrupt for nothing
- make the driver ready for an eventual master_xfer_irqless()
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2019-02-08 16:11 ` Federico Vaga
0 siblings, 0 replies; 37+ messages in thread
From: Federico Vaga @ 2019-02-08 16:11 UTC (permalink / raw)
To: Peter Korsgaard, Andrew Lunn; +Cc: linux-i2c, linux-kernel
This patch set provides improvements to the i2c-ocore driver.
[V2 -> V3]
- fix error condition on platform_get_irq(). Copied from
https://patchwork.ozlabs.org/patch/1038409/
[V1 -> V2]
- replaced usleep_range() with udelay() so that the polling version can be
used in atomic context.
- added dedicated patch for minor style issues
- fixed delay computation
- use spin_lock_irqsave(), instead of spin_trylock_irqsave(). IACK is always
necessary and a trylock would generate an extra interrupt for nothing
- make the driver ready for an eventual master_xfer_irqless()
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
2018-05-18 14:39 ` Marc Zyngier
@ 2018-05-21 18:19 ` Will Deacon
-1 siblings, 0 replies; 37+ messages in thread
From: Will Deacon @ 2018-05-21 18:19 UTC (permalink / raw)
To: Marc Zyngier
Cc: linux-arm-kernel, linux-kernel, Mark Rutland, Russell King,
Vladimir Murzin, Vince Weaver, Peter Zijlstra, Stefan Wahren,
Eric Anholt, Florian Fainelli
Hi Marc,
Thanks for this.
On Fri, May 18, 2018 at 03:39:08PM +0100, Marc Zyngier wrote:
> PMUv3 has been introduced with ARMv8 and, while it has only been used
> on 64bit systems so far, it would definitely be useful for 32bit
> guests running under KVM/arm64, for example.
>
> There is also the case of people natively running 32bit kernels on
> 64bit HW and trying to upstream unspeakable hacks, hoping that the
> stars will align and that they'll win the lottery (see [1]).
>
> So let's try again, and make the PMUv3 driver usable for everyone.
>
> This is done in three steps:
> (1) Move the driver from arch/arm64 to drivers/perf
> (2) Add a handful of system register accessors so that we can reuse
> the driver on 32bit
> (3) Provide the same accessors on 32bit, enable compilation, and
> make it the default selection for mach-virt.
>
> Tested on a Seattle box with 32bit guests.
I think we should go ahead with something like this, but I don't think
we're quite there with these patches. If we're going to move the arch code
out into drivers, let's do that for the perf_event* files under arch/arm/
as well. Then we could have a structure along the lines of:
drivers/perf/arm_pmu.c - As it is today
drivers/perf/arm_cpu/xscale_pmu.c - Only builds for 32-bit
drivers/perf/arm_cpu/armv6_pmu.c - Only builds for 32-bit
drivers/perf/arm_cpu/arch_pmu.c - Works for v7/v8 on
both 32-bit and 64-bit
The latter can then pull in whatever accessors it needs from the arch
code headers.
I know it's more of an invasive change, but this way we always end up
running the same code on the two architectures and it will be much easier
to maintain.
Will
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2018-05-21 18:19 ` Will Deacon
0 siblings, 0 replies; 37+ messages in thread
From: Will Deacon @ 2018-05-21 18:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Marc,
Thanks for this.
On Fri, May 18, 2018 at 03:39:08PM +0100, Marc Zyngier wrote:
> PMUv3 has been introduced with ARMv8 and, while it has only been used
> on 64bit systems so far, it would definitely be useful for 32bit
> guests running under KVM/arm64, for example.
>
> There is also the case of people natively running 32bit kernels on
> 64bit HW and trying to upstream unspeakable hacks, hoping that the
> stars will align and that they'll win the lottery (see [1]).
>
> So let's try again, and make the PMUv3 driver usable for everyone.
>
> This is done in three steps:
> (1) Move the driver from arch/arm64 to drivers/perf
> (2) Add a handful of system register accessors so that we can reuse
> the driver on 32bit
> (3) Provide the same accessors on 32bit, enable compilation, and
> make it the default selection for mach-virt.
>
> Tested on a Seattle box with 32bit guests.
I think we should go ahead with something like this, but I don't think
we're quite there with these patches. If we're going to move the arch code
out into drivers, let's do that for the perf_event* files under arch/arm/
as well. Then we could have a structure along the lines of:
drivers/perf/arm_pmu.c - As it is today
drivers/perf/arm_cpu/xscale_pmu.c - Only builds for 32-bit
drivers/perf/arm_cpu/armv6_pmu.c - Only builds for 32-bit
drivers/perf/arm_cpu/arch_pmu.c - Works for v7/v8 on
both 32-bit and 64-bit
The latter can then pull in whatever accessors it needs from the arch
code headers.
I know it's more of an invasive change, but this way we always end up
running the same code on the two architectures and it will be much easier
to maintain.
Will
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
2018-05-18 16:41 ` Marc Zyngier
@ 2018-05-18 17:39 ` Stefan Wahren
-1 siblings, 0 replies; 37+ messages in thread
From: Stefan Wahren @ 2018-05-18 17:39 UTC (permalink / raw)
To: Marc Zyngier, Vince Weaver
Cc: Peter Zijlstra, Florian Fainelli, Vladimir Murzin, Eric Anholt,
Mark Rutland, Russell King, Will Deacon, linux-kernel,
linux-arm-kernel
> Marc Zyngier <marc.zyngier@arm.com> hat am 18. Mai 2018 um 18:41 geschrieben:
>
>
> [/me beats himself for not writing a subject line...]
>
> On 18/05/18 17:29, Vince Weaver wrote:
> > On Fri, 18 May 2018, Marc Zyngier wrote:
> >
> >> There is also the case of people natively running 32bit kernels on
> >> 64bit HW and trying to upstream unspeakable hacks, hoping that the
> >> stars will align and that they'll win the lottery (see [1]).
> >
> > I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream
> > (4.17-rc5-git) kernel and they work.
> >
> > [ 0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
> >
> > I only needed to add this to the devicetree
> >
> > arm-pmu {
> > compatible = "arm,cortex-a53-pmu";
> > interrupt-parent = <&local_intc>;
> > interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
> > };
>
> That's definitely the sensible thing to have on such hardware. Why isn't
> it in the upstream DT already, irrespective of the state of the kernel
> support?
I remember that Vince point out the absence. He asked about how to implement it and i wasn't sure about it. At this time we hadn't IRQ polarity support. So we wanted to get this puzzle piece before. In march i put it on my TODO list, but then RPI 3 B+ support had higher prio to get into 4.18.
In general we have the problem that most of the users take the downstream kernel and don't know about the differences. Luckily more distributions switch to the upstream kernel, which increases the feedback.
>
> > Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Thanks again
Stefan
>
> Thanks a lot for testing.
>
> M.
> --
> Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2018-05-18 17:39 ` Stefan Wahren
0 siblings, 0 replies; 37+ messages in thread
From: Stefan Wahren @ 2018-05-18 17:39 UTC (permalink / raw)
To: linux-arm-kernel
> Marc Zyngier <marc.zyngier@arm.com> hat am 18. Mai 2018 um 18:41 geschrieben:
>
>
> [/me beats himself for not writing a subject line...]
>
> On 18/05/18 17:29, Vince Weaver wrote:
> > On Fri, 18 May 2018, Marc Zyngier wrote:
> >
> >> There is also the case of people natively running 32bit kernels on
> >> 64bit HW and trying to upstream unspeakable hacks, hoping that the
> >> stars will align and that they'll win the lottery (see [1]).
> >
> > I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream
> > (4.17-rc5-git) kernel and they work.
> >
> > [ 0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
> >
> > I only needed to add this to the devicetree
> >
> > arm-pmu {
> > compatible = "arm,cortex-a53-pmu";
> > interrupt-parent = <&local_intc>;
> > interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
> > };
>
> That's definitely the sensible thing to have on such hardware. Why isn't
> it in the upstream DT already, irrespective of the state of the kernel
> support?
I remember that Vince point out the absence. He asked about how to implement it and i wasn't sure about it. At this time we hadn't IRQ polarity support. So we wanted to get this puzzle piece before. In march i put it on my TODO list, but then RPI 3 B+ support had higher prio to get into 4.18.
In general we have the problem that most of the users take the downstream kernel and don't know about the differences. Luckily more distributions switch to the upstream kernel, which increases the feedback.
>
> > Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Thanks again
Stefan
>
> Thanks a lot for testing.
>
> M.
> --
> Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
2018-05-18 16:29 ` Vince Weaver
@ 2018-05-18 16:41 ` Marc Zyngier
-1 siblings, 0 replies; 37+ messages in thread
From: Marc Zyngier @ 2018-05-18 16:41 UTC (permalink / raw)
To: Vince Weaver
Cc: linux-arm-kernel, linux-kernel, Will Deacon, Mark Rutland,
Russell King, Vladimir Murzin, Peter Zijlstra, Stefan Wahren,
Eric Anholt, Florian Fainelli
[/me beats himself for not writing a subject line...]
On 18/05/18 17:29, Vince Weaver wrote:
> On Fri, 18 May 2018, Marc Zyngier wrote:
>
>> There is also the case of people natively running 32bit kernels on
>> 64bit HW and trying to upstream unspeakable hacks, hoping that the
>> stars will align and that they'll win the lottery (see [1]).
>
> I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream
> (4.17-rc5-git) kernel and they work.
>
> [ 0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
>
> I only needed to add this to the devicetree
>
> arm-pmu {
> compatible = "arm,cortex-a53-pmu";
> interrupt-parent = <&local_intc>;
> interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
> };
That's definitely the sensible thing to have on such hardware. Why isn't
it in the upstream DT already, irrespective of the state of the kernel
support?
> Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Thanks a lot for testing.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2018-05-18 16:41 ` Marc Zyngier
0 siblings, 0 replies; 37+ messages in thread
From: Marc Zyngier @ 2018-05-18 16:41 UTC (permalink / raw)
To: linux-arm-kernel
[/me beats himself for not writing a subject line...]
On 18/05/18 17:29, Vince Weaver wrote:
> On Fri, 18 May 2018, Marc Zyngier wrote:
>
>> There is also the case of people natively running 32bit kernels on
>> 64bit HW and trying to upstream unspeakable hacks, hoping that the
>> stars will align and that they'll win the lottery (see [1]).
>
> I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream
> (4.17-rc5-git) kernel and they work.
>
> [ 0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
>
> I only needed to add this to the devicetree
>
> arm-pmu {
> compatible = "arm,cortex-a53-pmu";
> interrupt-parent = <&local_intc>;
> interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
> };
That's definitely the sensible thing to have on such hardware. Why isn't
it in the upstream DT already, irrespective of the state of the kernel
support?
> Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Thanks a lot for testing.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 0/5]
2018-05-18 14:39 ` Marc Zyngier
@ 2018-05-18 16:29 ` Vince Weaver
-1 siblings, 0 replies; 37+ messages in thread
From: Vince Weaver @ 2018-05-18 16:29 UTC (permalink / raw)
To: Marc Zyngier
Cc: linux-arm-kernel, linux-kernel, Will Deacon, Mark Rutland,
Russell King, Vladimir Murzin, Vince Weaver, Peter Zijlstra,
Stefan Wahren, Eric Anholt, Florian Fainelli
On Fri, 18 May 2018, Marc Zyngier wrote:
> There is also the case of people natively running 32bit kernels on
> 64bit HW and trying to upstream unspeakable hacks, hoping that the
> stars will align and that they'll win the lottery (see [1]).
I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream
(4.17-rc5-git) kernel and they work.
[ 0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
I only needed to add this to the devicetree
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&local_intc>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
};
Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Vince
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2018-05-18 16:29 ` Vince Weaver
0 siblings, 0 replies; 37+ messages in thread
From: Vince Weaver @ 2018-05-18 16:29 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 18 May 2018, Marc Zyngier wrote:
> There is also the case of people natively running 32bit kernels on
> 64bit HW and trying to upstream unspeakable hacks, hoping that the
> stars will align and that they'll win the lottery (see [1]).
I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream
(4.17-rc5-git) kernel and they work.
[ 0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
I only needed to add this to the devicetree
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&local_intc>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
};
Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Vince
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2018-05-18 14:39 ` Marc Zyngier
0 siblings, 0 replies; 37+ messages in thread
From: Marc Zyngier @ 2018-05-18 14:39 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: Will Deacon, Mark Rutland, Russell King, Vladimir Murzin,
Vince Weaver, Peter Zijlstra, Stefan Wahren, Eric Anholt,
Florian Fainelli
PMUv3 has been introduced with ARMv8 and, while it has only been used
on 64bit systems so far, it would definitely be useful for 32bit
guests running under KVM/arm64, for example.
There is also the case of people natively running 32bit kernels on
64bit HW and trying to upstream unspeakable hacks, hoping that the
stars will align and that they'll win the lottery (see [1]).
So let's try again, and make the PMUv3 driver usable for everyone.
This is done in three steps:
(1) Move the driver from arch/arm64 to drivers/perf
(2) Add a handful of system register accessors so that we can reuse
the driver on 32bit
(3) Provide the same accessors on 32bit, enable compilation, and
make it the default selection for mach-virt.
Tested on a Seattle box with 32bit guests.
* From v1:
- Fixed encodings for some CP15 accessors
- Added a terse note saying that CPU_V7 also covers ARMv8
- Rebased on v4.12-rc5
* From v2:
- SPDX tags on new and moved files. Yeah!
- Annual rebase on 4.17-rc5
[1] https://patchwork.kernel.org/patch/10406793/
Marc Zyngier (5):
arm64: perf: Move PMUv3 driver to drivers/perf
arm64: perf: Abstract system register accesses away
ARM: Make CONFIG_CPU_V7 valid for 32bit ARMv8 implementations
ARM: perf: Allow the use of the PMUv3 driver on 32bit ARM
ARM: mach-virt: Select PMUv3 driver by default
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arm_pmuv3.h | 125 +++++++++++++++++++++
arch/arm/mm/Kconfig | 2 +-
arch/arm64/include/asm/arm_pmuv3.h | 111 ++++++++++++++++++
arch/arm64/include/asm/perf_event.h | 55 ---------
arch/arm64/kernel/Makefile | 1 -
drivers/perf/Kconfig | 8 ++
drivers/perf/Makefile | 1 +
.../perf_event.c => drivers/perf/arm_pmuv3.c | 42 ++++---
include/kvm/arm_pmu.h | 2 +-
include/linux/perf/arm_pmuv3.h | 78 +++++++++++++
11 files changed, 346 insertions(+), 80 deletions(-)
create mode 100644 arch/arm/include/asm/arm_pmuv3.h
create mode 100644 arch/arm64/include/asm/arm_pmuv3.h
rename arch/arm64/kernel/perf_event.c => drivers/perf/arm_pmuv3.c (97%)
create mode 100644 include/linux/perf/arm_pmuv3.h
--
2.14.2
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2018-05-18 14:39 ` Marc Zyngier
0 siblings, 0 replies; 37+ messages in thread
From: Marc Zyngier @ 2018-05-18 14:39 UTC (permalink / raw)
To: linux-arm-kernel
PMUv3 has been introduced with ARMv8 and, while it has only been used
on 64bit systems so far, it would definitely be useful for 32bit
guests running under KVM/arm64, for example.
There is also the case of people natively running 32bit kernels on
64bit HW and trying to upstream unspeakable hacks, hoping that the
stars will align and that they'll win the lottery (see [1]).
So let's try again, and make the PMUv3 driver usable for everyone.
This is done in three steps:
(1) Move the driver from arch/arm64 to drivers/perf
(2) Add a handful of system register accessors so that we can reuse
the driver on 32bit
(3) Provide the same accessors on 32bit, enable compilation, and
make it the default selection for mach-virt.
Tested on a Seattle box with 32bit guests.
* From v1:
- Fixed encodings for some CP15 accessors
- Added a terse note saying that CPU_V7 also covers ARMv8
- Rebased on v4.12-rc5
* From v2:
- SPDX tags on new and moved files. Yeah!
- Annual rebase on 4.17-rc5
[1] https://patchwork.kernel.org/patch/10406793/
Marc Zyngier (5):
arm64: perf: Move PMUv3 driver to drivers/perf
arm64: perf: Abstract system register accesses away
ARM: Make CONFIG_CPU_V7 valid for 32bit ARMv8 implementations
ARM: perf: Allow the use of the PMUv3 driver on 32bit ARM
ARM: mach-virt: Select PMUv3 driver by default
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arm_pmuv3.h | 125 +++++++++++++++++++++
arch/arm/mm/Kconfig | 2 +-
arch/arm64/include/asm/arm_pmuv3.h | 111 ++++++++++++++++++
arch/arm64/include/asm/perf_event.h | 55 ---------
arch/arm64/kernel/Makefile | 1 -
drivers/perf/Kconfig | 8 ++
drivers/perf/Makefile | 1 +
.../perf_event.c => drivers/perf/arm_pmuv3.c | 42 ++++---
include/kvm/arm_pmu.h | 2 +-
include/linux/perf/arm_pmuv3.h | 78 +++++++++++++
11 files changed, 346 insertions(+), 80 deletions(-)
create mode 100644 arch/arm/include/asm/arm_pmuv3.h
create mode 100644 arch/arm64/include/asm/arm_pmuv3.h
rename arch/arm64/kernel/perf_event.c => drivers/perf/arm_pmuv3.c (97%)
create mode 100644 include/linux/perf/arm_pmuv3.h
--
2.14.2
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2015-07-12 5:10 Taeung Song
0 siblings, 0 replies; 37+ messages in thread
From: Taeung Song @ 2015-07-12 5:10 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: linux-kernel, jolsa, namhyung, Ingo Molnar, Taeung Song
Changes in v3:
- builtin-config.c: Add a config variable ’kmem.default’ with a default value into ‘struct default_configset’
which has default config variables and values.
- cmd_config(): Add a option ‘—global’ and ‘—local’ to enable config file location to be selected
Changes in v2:
- Renaming variables a more suitable name
1. ’—list-all' instead of '--all'
2. ’name' instead of 'subkey'
3. 'section, name, value' instead of 'given_section,subkey,value'
- Documentation/perf-config.txt: Correct small infelicities or typing errors in a perf-config documention.
- Documentation/perf-config.txt: Remove a part description of report.children because it was duplicated
in Documentation/callchain-overhead-calculation.txt
- builtin-config.c: Use a variable ’int actions’ instead of struct params which has ‘bool list_action’,
‘bool get_action’ and etc. , to simplify a branching statement for perf-config options
- builtin-config.c: Declaration a global variable ‘static struct default_configsets’ has config variables
with default values instead of using a 'util/PERFCONFIG-DEFAULT' file and remove functions merge()
and perse_key() to get perf config default values.
- normalize_value(): Add a function to normalize a value and check data type of it.
- cmd_config(): Simplify parsing arguments as arguments is just divided by '=' and then in front of '.' is a section,
between '.' and '=' is a name, and behind '=' is a value.
- show_all_config(): Print config variables ‘struct default_configsets’ haven't
- cmd_config(): Make a command ’perf config' without a option work as with a option ’—list’ instead of ‘—list-all’.
Taeung Song (5):
perf tools: Add 'perf-config' command
perf config: Add functions which can get or set perf config variables.
perf config: Add a option 'list-all' to perf-config.
perf config: Add a option 'remove' to perf-config.
perf config: Add ‘—system’ and ‘—global’ options to be able to select
which config file to be used.
tools/perf/Build | 1 +
tools/perf/Documentation/perf-config.txt | 401 ++++++++++++++++
tools/perf/Documentation/perfconfig.example | 70 ++-
tools/perf/builtin-config.c | 708 ++++++++++++++++++++++++++++
tools/perf/builtin.h | 1 +
tools/perf/command-list.txt | 1 +
tools/perf/perf.c | 1 +
tools/perf/util/cache.h | 20 +
tools/perf/util/config.c | 84 +++-
9 files changed, 1251 insertions(+), 36 deletions(-)
create mode 100644 tools/perf/Documentation/perf-config.txt
create mode 100644 tools/perf/builtin-config.c
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2014-12-08 9:46 ` Yunzhi Li
0 siblings, 0 replies; 37+ messages in thread
From: Yunzhi Li @ 2014-12-08 9:46 UTC (permalink / raw)
To: heiko, dianders, romain.perier
Cc: olof, huangtao, zyw, cf, linux-rockchip, Yunzhi Li, devicetree,
Paul Zimmerman, linux-usb, Kumar Gala, linux-kernel,
Grant Likely, Ian Campbell, Rob Herring, Pawel Moll,
Kishon Vijay Abraham I, Mark Rutland, Russell King,
linux-arm-kernel, Greg Kroah-Hartman
Patches to add support for Rockchip usb phys.Add a new Rockchip
usb phy driver and modify dwc2 controller driver to make dwc2
platform devices support a generic PHY framework driver. This
patch set has been tested on my rk3288-evb and power off the usb
phys would reduce about 60mW power budget in total during sustem
suspend.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement should
have braces.
- No need to test dwc2->phy for NULL before calling generic phy
APIs.
- Add more context about the changes in the long description.
Yunzhi Li (5):
phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Documentation: bindings: add doc for the Rockchip usb PHY
usb: dwc2: add generic PHY framework support for dwc2 usb
controler platform driver.
ARM: dts: add rk3288 usb PHY
ARM: dts: Enable usb PHY on rk3288-evb board
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 22 +++
arch/arm/boot/dts/rk3288-evb.dtsi | 4 +
arch/arm/boot/dts/rk3288.dtsi | 13 ++
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 179 +++++++++++++++++++++
drivers/usb/dwc2/gadget.c | 33 ++--
drivers/usb/dwc2/platform.c | 36 ++++-
8 files changed, 272 insertions(+), 23 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
create mode 100644 drivers/phy/phy-rockchip-usb.c
--
2.0.0
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2014-12-08 9:46 ` Yunzhi Li
0 siblings, 0 replies; 37+ messages in thread
From: Yunzhi Li @ 2014-12-08 9:46 UTC (permalink / raw)
To: linux-arm-kernel
Patches to add support for Rockchip usb phys.Add a new Rockchip
usb phy driver and modify dwc2 controller driver to make dwc2
platform devices support a generic PHY framework driver. This
patch set has been tested on my rk3288-evb and power off the usb
phys would reduce about 60mW power budget in total during sustem
suspend.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement should
have braces.
- No need to test dwc2->phy for NULL before calling generic phy
APIs.
- Add more context about the changes in the long description.
Yunzhi Li (5):
phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Documentation: bindings: add doc for the Rockchip usb PHY
usb: dwc2: add generic PHY framework support for dwc2 usb
controler platform driver.
ARM: dts: add rk3288 usb PHY
ARM: dts: Enable usb PHY on rk3288-evb board
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 22 +++
arch/arm/boot/dts/rk3288-evb.dtsi | 4 +
arch/arm/boot/dts/rk3288.dtsi | 13 ++
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 179 +++++++++++++++++++++
drivers/usb/dwc2/gadget.c | 33 ++--
drivers/usb/dwc2/platform.c | 36 ++++-
8 files changed, 272 insertions(+), 23 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
create mode 100644 drivers/phy/phy-rockchip-usb.c
--
2.0.0
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
2014-06-05 13:25 Maxime Ripard
@ 2014-06-09 13:56 ` Linus Walleij
0 siblings, 0 replies; 37+ messages in thread
From: Linus Walleij @ 2014-06-09 13:56 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 5, 2014 at 3:25 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> This is an attempt at making the external interrupts on the A31 and
> the A23 working.
I've applied these 5 patches to my devel branch, but you won't
see this on linux-next until after the merge window is closed.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2014-06-05 13:25 Maxime Ripard
2014-06-09 13:56 ` Linus Walleij
0 siblings, 1 reply; 37+ messages in thread
From: Maxime Ripard @ 2014-06-05 13:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi everyone,
This is an attempt at making the external interrupts on the A31 and
the A23 working.
The main difference with the previous code is that there's now several
banks and several parent interrupts, instead of a single bank with a
single parent interrupt in the older SoCs.
Most of the diffstat is to register the new irq pin functions. The
real code additions are those in the core pinctrl driver.
Maxime
Changes from v2:
- Fixed the bogus the irq_cfg_reg function that was not taking into
account the fact that we have several registers for this one.
- Remove the SUNXI_IRQ_NUMBER, since it was not really a good name
anymore, and replaced it for IRQ_PER_BANK.
- Removed meaningless and broken sunxi_irq_cfg_reg_from_bank function.
Changes from v1:
- Bail out of the interrupt handler in case of a spurious interrupt
- Fix the wrong register offset in sunxi_irq_*_reg functions.
Maxime Ripard (5):
pinctrl: sunxi: Remove irq_mask_ack and use irq_ack instead
pinctrl: sunxi: Add macro definition for pinctrl with more than one
interrupt
pinctrl: sunxi: Declare the number of interrupt banks in the
descriptor
pinctrl: sunxi: Declare the interrupt function for the A31
pinctrl: sunxi: Implement multiple interrupt banks support
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 1 +
drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c | 1 +
drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c | 1 +
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 1 +
drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 217 +++++++++++++++++++---------
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 1 +
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 81 +++++++----
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 44 ++++--
8 files changed, 238 insertions(+), 109 deletions(-)
--
2.0.0
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2009-11-10 22:36 ` Alex Chiang
0 siblings, 0 replies; 37+ messages in thread
From: Alex Chiang @ 2009-11-10 22:36 UTC (permalink / raw)
To: akpm; +Cc: linux-mm, linux-kernel, rientjes
This is v3 of the series.
I based it off of Linus's latest tree.
I did not include David Rientjes's "mm: slab allocate memory section nodemask
for large systems" patch in my series, since it's not necessarily related.
Please consider for inclusion for the next merge window (v2.6.33).
Thanks,
/ac
v2 -> v3:
- rebased to Linus's latest tree (799dd75b)
- Added David Rientjes's Acked-by: flags
- dropped S390 cc's, since they are unaffected by this series
v1 -> v2: http://thread.gmane.org/gmane.linux.kernel.mm/40084/
Address David Rientjes's comments
- check return value of sysfs_create_link in register_cpu_under_node
- do /not/ convert [un]register_cpu_under_node to return void, since
sparse starts whinging if you ignore sysfs_create_link()'s return
value and working around sparse makes the code ugly
- adjust documentation
Added S390 maintainers to cc: for patch [1/5] as per Kame-san's
suggestion. S390 may map a memory section to more than one node,
causing this series to break.
---
Alex Chiang (5):
mm: add numa node symlink for memory section in sysfs
mm: refactor register_cpu_under_node()
mm: refactor unregister_cpu_under_node()
mm: add numa node symlink for cpu devices in sysfs
Documentation: ABI: /sys/devices/system/cpu/cpu#/node
Documentation/ABI/testing/sysfs-devices-memory | 14 ++++-
Documentation/ABI/testing/sysfs-devices-system-cpu | 14 +++++
Documentation/memory-hotplug.txt | 11 ++--
drivers/base/node.c | 58 ++++++++++++++------
4 files changed, 76 insertions(+), 21 deletions(-)
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 0/5]
@ 2009-11-10 22:36 ` Alex Chiang
0 siblings, 0 replies; 37+ messages in thread
From: Alex Chiang @ 2009-11-10 22:36 UTC (permalink / raw)
To: akpm; +Cc: linux-mm, linux-kernel, rientjes
This is v3 of the series.
I based it off of Linus's latest tree.
I did not include David Rientjes's "mm: slab allocate memory section nodemask
for large systems" patch in my series, since it's not necessarily related.
Please consider for inclusion for the next merge window (v2.6.33).
Thanks,
/ac
v2 -> v3:
- rebased to Linus's latest tree (799dd75b)
- Added David Rientjes's Acked-by: flags
- dropped S390 cc's, since they are unaffected by this series
v1 -> v2: http://thread.gmane.org/gmane.linux.kernel.mm/40084/
Address David Rientjes's comments
- check return value of sysfs_create_link in register_cpu_under_node
- do /not/ convert [un]register_cpu_under_node to return void, since
sparse starts whinging if you ignore sysfs_create_link()'s return
value and working around sparse makes the code ugly
- adjust documentation
Added S390 maintainers to cc: for patch [1/5] as per Kame-san's
suggestion. S390 may map a memory section to more than one node,
causing this series to break.
---
Alex Chiang (5):
mm: add numa node symlink for memory section in sysfs
mm: refactor register_cpu_under_node()
mm: refactor unregister_cpu_under_node()
mm: add numa node symlink for cpu devices in sysfs
Documentation: ABI: /sys/devices/system/cpu/cpu#/node
Documentation/ABI/testing/sysfs-devices-memory | 14 ++++-
Documentation/ABI/testing/sysfs-devices-system-cpu | 14 +++++
Documentation/memory-hotplug.txt | 11 ++--
drivers/base/node.c | 58 ++++++++++++++------
4 files changed, 76 insertions(+), 21 deletions(-)
--
To unsubscribe, send a message with 'unsubscribe linux-mm' in
the body to majordomo@kvack.org. For more info on Linux MM,
see: http://www.linux-mm.org/ .
Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a>
^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2023-05-29 16:45 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-29 15:35 [PATCH v3 0/5] Bernhard Rosenkränzer
2023-05-29 15:35 ` Bernhard Rosenkränzer
2023-05-29 15:35 ` [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192 Bernhard Rosenkränzer
2023-05-29 15:35 ` Bernhard Rosenkränzer
2023-05-29 15:35 ` [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume Bernhard Rosenkränzer
2023-05-29 15:35 ` Bernhard Rosenkränzer
2023-05-29 15:35 ` [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Bernhard Rosenkränzer
2023-05-29 15:35 ` Bernhard Rosenkränzer
2023-05-29 15:35 ` [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones Bernhard Rosenkränzer
2023-05-29 15:35 ` Bernhard Rosenkränzer
2023-05-29 15:35 ` [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation Bernhard Rosenkränzer
2023-05-29 15:35 ` Bernhard Rosenkränzer
2023-05-29 16:30 ` [PATCH v3 0/5] Matthias Brugger
2023-05-29 16:30 ` Matthias Brugger
-- strict thread matches above, loose matches on Subject: below --
2022-04-21 13:26 [PATCH v2 0/5] trace2 output for bitmap decision path Teng Long
2022-06-12 7:44 ` [PATCH v3 0/5] Teng Long
2022-06-12 7:44 ` Teng Long
2019-02-08 16:11 Federico Vaga
2019-02-08 16:11 ` Federico Vaga
2019-02-09 21:41 ` Andrew Lunn
2018-05-18 14:39 Marc Zyngier
2018-05-18 14:39 ` Marc Zyngier
2018-05-18 16:29 ` Vince Weaver
2018-05-18 16:29 ` Vince Weaver
2018-05-18 16:41 ` Marc Zyngier
2018-05-18 16:41 ` Marc Zyngier
2018-05-18 17:39 ` Stefan Wahren
2018-05-18 17:39 ` Stefan Wahren
2018-05-21 18:19 ` Will Deacon
2018-05-21 18:19 ` Will Deacon
2021-12-19 23:46 ` Florian Fainelli
2021-12-20 8:59 ` Marc Zyngier
2015-07-12 5:10 Taeung Song
2014-12-08 9:46 Yunzhi Li
2014-12-08 9:46 ` Yunzhi Li
2014-06-05 13:25 Maxime Ripard
2014-06-09 13:56 ` Linus Walleij
2009-11-10 22:36 Alex Chiang
2009-11-10 22:36 ` Alex Chiang
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.