From: abhinavk@codeaurora.org To: Marijn Suijten <marijn.suijten@somainline.org> Cc: phone-devel@vger.kernel.org, freedreno@lists.freedesktop.org, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>, David Airlie <airlied@linux.ie>, linux-arm-msm@vger.kernel.org, Konrad Dybcio <konrad.dybcio@somainline.org>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Clark <robdclark@gmail.com>, Martin Botka <martin.botka@somainline.org>, ~postmarketos/upstreaming@lists.sr.ht, Daniel Vetter <daniel@ffwll.ch>, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>, Sean Paul <sean@poorly.run> Subject: Re: [Freedreno] [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal Date: Wed, 07 Apr 2021 11:19:53 -0700 [thread overview] Message-ID: <6413863d04df9743e2d7e81beff5c3e8@codeaurora.org> (raw) In-Reply-To: <20210406214726.131534-2-marijn.suijten@somainline.org> Hi Marijn On 2021-04-06 14:47, Marijn Suijten wrote: > Leaving this at a close-to-maximum register value 0xFFF0 means it takes > very long for the MDSS to generate a software vsync interrupt when the > hardware TE interrupt doesn't arrive. Configuring this to double the > vtotal (like some downstream kernels) leads to a frame to take at most > twice before the vsync signal, until hardware TE comes up. > > In this case the hardware interrupt responsible for providing this > signal - "disp-te" gpio - is not hooked up to the mdp5 vsync/pp logic > at > all. This solves severe panel update issues observed on at least the > Xperia Loire and Tone series, until said gpio is properly hooked up to > an irq. The reason the CONFIG_HEIGHT was at such a high value is to make sure that we always get the TE only from the panel vsync and not false positives coming from the tear check logic itself. When you say that disp-te gpio is not hooked up, is it something incorrect with the schematic OR panel is not generating the TE correctly? > > Suggested-by: AngeloGioacchino Del Regno > <angelogioacchino.delregno@somainline.org> > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > Reviewed-by: AngeloGioacchino Del Regno > <angelogioacchino.delregno@somainline.org> > --- > drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c > index ff2c1d583c79..2d5ac03dbc17 100644 > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c > @@ -51,7 +51,7 @@ static int pingpong_tearcheck_setup(struct > drm_encoder *encoder, > > mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); > mdp5_write(mdp5_kms, > - REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), 0xfff0); > + REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), (2 * mode->vtotal)); > mdp5_write(mdp5_kms, > REG_MDP5_PP_VSYNC_INIT_VAL(pp_id), mode->vdisplay); > mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + > 1);
WARNING: multiple messages have this Message-ID (diff)
From: abhinavk@codeaurora.org To: Marijn Suijten <marijn.suijten@somainline.org> Cc: Sean Paul <sean@poorly.run>, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>, David Airlie <airlied@linux.ie>, linux-arm-msm@vger.kernel.org, Konrad Dybcio <konrad.dybcio@somainline.org>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Martin Botka <martin.botka@somainline.org>, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>, phone-devel@vger.kernel.org, freedreno@lists.freedesktop.org Subject: Re: [Freedreno] [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal Date: Wed, 07 Apr 2021 11:19:53 -0700 [thread overview] Message-ID: <6413863d04df9743e2d7e81beff5c3e8@codeaurora.org> (raw) In-Reply-To: <20210406214726.131534-2-marijn.suijten@somainline.org> Hi Marijn On 2021-04-06 14:47, Marijn Suijten wrote: > Leaving this at a close-to-maximum register value 0xFFF0 means it takes > very long for the MDSS to generate a software vsync interrupt when the > hardware TE interrupt doesn't arrive. Configuring this to double the > vtotal (like some downstream kernels) leads to a frame to take at most > twice before the vsync signal, until hardware TE comes up. > > In this case the hardware interrupt responsible for providing this > signal - "disp-te" gpio - is not hooked up to the mdp5 vsync/pp logic > at > all. This solves severe panel update issues observed on at least the > Xperia Loire and Tone series, until said gpio is properly hooked up to > an irq. The reason the CONFIG_HEIGHT was at such a high value is to make sure that we always get the TE only from the panel vsync and not false positives coming from the tear check logic itself. When you say that disp-te gpio is not hooked up, is it something incorrect with the schematic OR panel is not generating the TE correctly? > > Suggested-by: AngeloGioacchino Del Regno > <angelogioacchino.delregno@somainline.org> > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > Reviewed-by: AngeloGioacchino Del Regno > <angelogioacchino.delregno@somainline.org> > --- > drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c > index ff2c1d583c79..2d5ac03dbc17 100644 > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c > @@ -51,7 +51,7 @@ static int pingpong_tearcheck_setup(struct > drm_encoder *encoder, > > mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); > mdp5_write(mdp5_kms, > - REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), 0xfff0); > + REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), (2 * mode->vtotal)); > mdp5_write(mdp5_kms, > REG_MDP5_PP_VSYNC_INIT_VAL(pp_id), mode->vdisplay); > mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + > 1); _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2021-04-07 18:20 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-06 21:47 [PATCH 0/3] drm/msm/mdp5: Emit vsync signal often enough Marijn Suijten 2021-04-06 21:47 ` Marijn Suijten 2021-04-06 21:47 ` [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal Marijn Suijten 2021-04-06 21:47 ` Marijn Suijten 2021-04-07 18:19 ` abhinavk [this message] 2021-04-07 18:19 ` [Freedreno] " abhinavk 2021-04-07 19:11 ` AngeloGioacchino Del Regno 2021-04-07 19:11 ` AngeloGioacchino Del Regno 2021-04-08 19:05 ` Rob Clark 2021-04-08 19:05 ` Rob Clark 2021-04-08 23:16 ` AngeloGioacchino Del Regno 2021-04-09 0:08 ` Rob Clark 2021-04-09 0:08 ` Rob Clark 2021-04-09 8:22 ` Marijn Suijten 2021-04-09 8:22 ` Marijn Suijten 2021-04-06 21:47 ` [PATCH 2/3] drm/msm/mdp5: Do not multiply vclk line count by 100 Marijn Suijten 2021-04-06 21:47 ` Marijn Suijten 2021-04-06 21:47 ` [PATCH 3/3] drm/msm/mdp5: Disable pingpong autorefresh at tearcheck init Marijn Suijten 2021-04-06 21:47 ` Marijn Suijten
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