* ARM DMA Zones (coherent memory pool)
[not found] <1706190290.100315.1358858042869.JavaMail.root@elliptictech.com>
@ 2013-01-22 12:36 ` Tom St Denis
0 siblings, 0 replies; 2+ messages in thread
From: Tom St Denis @ 2013-01-22 12:36 UTC (permalink / raw)
To: linux-kernel; +Cc: linux-arm-kernel
Hi all,
I was wondering if there was a proper way of instructing the init code (atomic_pool_init) for the DMA coherent subsystem to point to a fixed location instead of using alloc_pages()?
I ask because on our system (Zynq702/706 boards) DDR has a high latency (~25-30 cycles) whereas FPGA memory can be much quicker. What I'd like to do is create a 256Kbyte memory in FPGA BRAMs and then have the CPU point at it for the DMA zone.
Is that at all possible through a simple kernel cmdline or patch?
Tom
^ permalink raw reply [flat|nested] 2+ messages in thread
* ARM DMA Zones (coherent memory pool)
@ 2013-01-22 12:36 ` Tom St Denis
0 siblings, 0 replies; 2+ messages in thread
From: Tom St Denis @ 2013-01-22 12:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
I was wondering if there was a proper way of instructing the init code (atomic_pool_init) for the DMA coherent subsystem to point to a fixed location instead of using alloc_pages()?
I ask because on our system (Zynq702/706 boards) DDR has a high latency (~25-30 cycles) whereas FPGA memory can be much quicker. What I'd like to do is create a 256Kbyte memory in FPGA BRAMs and then have the CPU point at it for the DMA zone.
Is that at all possible through a simple kernel cmdline or patch?
Tom
^ permalink raw reply [flat|nested] 2+ messages in thread
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2013-01-22 12:36 ` ARM DMA Zones (coherent memory pool) Tom St Denis
2013-01-22 12:36 ` Tom St Denis
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