[PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[Jerome Brunet]

The patchset is the 2nd round of update to the meson gxbb clock controller
to add initial audio support. The patchset is based on clk-next.

There is not much out of the ordinary here (adding new clocks and exposing
them) except maybe for 2 patches:
Patch #2: Adds a safety check while registering clocks to protect against
          holes in clk_hw_onecell_data, if it ever happens. Same thing is
	  done for the meson8b clock controller. 
Patch #3: Adds a new clock divider driver to implement the necessary
          policy for the i2s master clock (see patch changelog)

This patchset has been test on the gxbb p200 and gxl p230.

Jerome Brunet (8):
  dt-bindings: clock: gxbb: expose spdif clock gates
  clk: meson: gxbb: protect against holes in the onecell_data array
  clk: meson: add audio clock divider support
  clk: meson: gxbb: add cts_amclk
  clk: meson: gxbb: add cts_mclk_i958
  clk: meson: gxbb: add cts_i958 clock
  dt-bindings: clock: gxbb: expose i2s master clock
  dt-bindings: clock: gxbb: expose spdif master clock

 drivers/clk/meson/Makefile            |   2 +-
 drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
 drivers/clk/meson/clkc.h              |  10 +++
 drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h              |  13 ++-
 include/dt-bindings/clock/gxbb-clkc.h |   5 ++
 6 files changed, 319 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/meson/clk-audio-divider.c

-- 
2.9.3

[PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[Jerome Brunet]

The patchset is the 2nd round of update to the meson gxbb clock controller
to add initial audio support. The patchset is based on clk-next.

There is not much out of the ordinary here (adding new clocks and exposing
them) except maybe for 2 patches:
Patch #2: Adds a safety check while registering clocks to protect against
          holes in clk_hw_onecell_data, if it ever happens. Same thing is
	  done for the meson8b clock controller. 
Patch #3: Adds a new clock divider driver to implement the necessary
          policy for the i2s master clock (see patch changelog)

This patchset has been test on the gxbb p200 and gxl p230.

Jerome Brunet (8):
  dt-bindings: clock: gxbb: expose spdif clock gates
  clk: meson: gxbb: protect against holes in the onecell_data array
  clk: meson: add audio clock divider support
  clk: meson: gxbb: add cts_amclk
  clk: meson: gxbb: add cts_mclk_i958
  clk: meson: gxbb: add cts_i958 clock
  dt-bindings: clock: gxbb: expose i2s master clock
  dt-bindings: clock: gxbb: expose spdif master clock

 drivers/clk/meson/Makefile            |   2 +-
 drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
 drivers/clk/meson/clkc.h              |  10 +++
 drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h              |  13 ++-
 include/dt-bindings/clock/gxbb-clkc.h |   5 ++
 6 files changed, 319 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/meson/clk-audio-divider.c

-- 
2.9.3

[PATCH v1 1/8] dt-bindings: clock: gxbb: expose spdif clock gates

[Jerome Brunet]

Expose the clock gates required for the spdif output

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.h              | 4 ++--
 include/dt-bindings/clock/gxbb-clkc.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 9d949244b104..0d535f7e7aed 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -209,7 +209,7 @@
 /* CLKID_ETH */
 #define CLKID_DEMUX		  37
 /* CLKID_AIU_GLUE */
-#define CLKID_IEC958		  39
+/* CLKID_IEC958 */
 /* CLKID_I2S_OUT */
 #define CLKID_AMCLK		  41
 #define CLKID_AIFIFO2		  42
@@ -251,7 +251,7 @@
 #define CLKID_GCLK_VENCI_INT	  78
 #define CLKID_DAC_CLK		  79
 /* CLKID_AOCLK_GATE */
-#define CLKID_IEC958_GATE	  81
+/* CLKID_IEC958_GATE */
 #define CLKID_ENC480P		  82
 #define CLKID_RNG1		  83
 #define CLKID_GCLK_VENCI_INT1	  84
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index cce6cb5418f1..1d4614bc8154 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -18,6 +18,7 @@
 #define CLKID_SAR_ADC		23
 #define CLKID_ETH		36
 #define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
 #define CLKID_I2S_OUT		40
 #define CLKID_MIXER_IFACE	44
 #define CLKID_AIU		47
@@ -30,6 +31,7 @@
 #define CLKID_SANA		69
 #define CLKID_GCLK_VENCI_INT0	77
 #define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
 #define CLKID_AO_I2C		93
 #define CLKID_SD_EMMC_A		94
 #define CLKID_SD_EMMC_B		95
-- 
2.9.3

[PATCH v1 1/8] dt-bindings: clock: gxbb: expose spdif clock gates

[Jerome Brunet]

Expose the clock gates required for the spdif output

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.h              | 4 ++--
 include/dt-bindings/clock/gxbb-clkc.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 9d949244b104..0d535f7e7aed 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -209,7 +209,7 @@
 /* CLKID_ETH */
 #define CLKID_DEMUX		  37
 /* CLKID_AIU_GLUE */
-#define CLKID_IEC958		  39
+/* CLKID_IEC958 */
 /* CLKID_I2S_OUT */
 #define CLKID_AMCLK		  41
 #define CLKID_AIFIFO2		  42
@@ -251,7 +251,7 @@
 #define CLKID_GCLK_VENCI_INT	  78
 #define CLKID_DAC_CLK		  79
 /* CLKID_AOCLK_GATE */
-#define CLKID_IEC958_GATE	  81
+/* CLKID_IEC958_GATE */
 #define CLKID_ENC480P		  82
 #define CLKID_RNG1		  83
 #define CLKID_GCLK_VENCI_INT1	  84
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index cce6cb5418f1..1d4614bc8154 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -18,6 +18,7 @@
 #define CLKID_SAR_ADC		23
 #define CLKID_ETH		36
 #define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
 #define CLKID_I2S_OUT		40
 #define CLKID_MIXER_IFACE	44
 #define CLKID_AIU		47
@@ -30,6 +31,7 @@
 #define CLKID_SANA		69
 #define CLKID_GCLK_VENCI_INT0	77
 #define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
 #define CLKID_AO_I2C		93
 #define CLKID_SD_EMMC_A		94
 #define CLKID_SD_EMMC_B		95
-- 
2.9.3

[PATCH v1 2/8] clk: meson: gxbb: protect against holes in the onecell_data array

[Jerome Brunet]

The clock controller is getting more complex and it might be possible, in
the future, to have holes in the clk_hw_onecell_data array. Just make sure
we skip those holes if it ever happens.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 75197664a7ee..28812ea41a60 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1388,6 +1388,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
 	 * register all clks
 	 */
 	for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
+		/* array might be sparse */
+		if (!clkc_data->hw_onecell_data->hws[clkid])
+			continue;
+
 		ret = devm_clk_hw_register(dev,
 					clkc_data->hw_onecell_data->hws[clkid]);
 		if (ret)
-- 
2.9.3

[PATCH v1 2/8] clk: meson: gxbb: protect against holes in the onecell_data array

[Jerome Brunet]

The clock controller is getting more complex and it might be possible, in
the future, to have holes in the clk_hw_onecell_data array. Just make sure
we skip those holes if it ever happens.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 75197664a7ee..28812ea41a60 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1388,6 +1388,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
 	 * register all clks
 	 */
 	for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
+		/* array might be sparse */
+		if (!clkc_data->hw_onecell_data->hws[clkid])
+			continue;
+
 		ret = devm_clk_hw_register(dev,
 					clkc_data->hw_onecell_data->hws[clkid]);
 		if (ret)
-- 
2.9.3

[PATCH v1 3/8] clk: meson: add audio clock divider support

[Jerome Brunet]

The audio divider needs a specific clock divider driver.
With am mpll parent clock, which is able to provide a fairly precise rate,
the generic divider tends to select low value of the divider. In such case
the quality of the clock is very poor. For the same final rate, maximizing
the audio clock divider value and selecting the corresponding mpll rate
gives better results. This is what this driver aims to acheive. So far, so
good.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/Makefile            |   2 +-
 drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
 drivers/clk/meson/clkc.h              |  10 +++
 3 files changed, 160 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/clk-audio-divider.c

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 349583405b7c..83b6d9d65aa1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,6 +2,6 @@
 # Makefile for Meson specific clk
 #
 
-obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
new file mode 100644
index 000000000000..ac713b9ea84a
--- /dev/null
+++ b/drivers/clk/meson/clk-audio-divider.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2017 AmLogic, Inc.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * i2s master clock divider: The algorithm of the generic clk-divider used with
+ * a very precise clock parent such as the mpll tends to select a low divider
+ * factor. This gives very results with this particular divider, especially with
+ * high frequencies (> 100 MHz)
+ *
+ * This driver try to select the maximum possible divider with the rate the
+ * upstream clock can provide.
+ */
+
+#include <linux/clk-provider.h>
+#include "clkc.h"
+
+#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
+				struct meson_clk_audio_divider, hw)
+
+static int _div_round(unsigned long parent_rate, unsigned long rate,
+		      unsigned long flags)
+{
+	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
+		return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
+
+	return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+}
+
+static int _get_val(unsigned long parent_rate, unsigned long rate)
+{
+	return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
+}
+
+static int _valid_divider(struct clk_hw *hw, int divider)
+{
+	struct meson_clk_audio_divider *adiv =
+		to_meson_clk_audio_divider(hw);
+	int max_divider;
+	u8 width;
+
+	width = adiv->div.width;
+	max_divider = 1 << width;
+
+	if (divider < 1)
+		return 1;
+	else if (divider > max_divider)
+		return max_divider;
+
+	return divider;
+}
+
+static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
+					       unsigned long parent_rate)
+{
+	struct meson_clk_audio_divider *adiv =
+		to_meson_clk_audio_divider(hw);
+	struct parm *p;
+	unsigned long reg, divider;
+
+	p = &adiv->div;
+	reg = readl(adiv->base + p->reg_off);
+	divider = PARM_GET(p->width, p->shift, reg) + 1;
+
+	return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
+}
+
+static long audio_divider_round_rate(struct clk_hw *hw,
+				     unsigned long rate,
+				     unsigned long *parent_rate)
+{
+	struct meson_clk_audio_divider *adiv =
+		to_meson_clk_audio_divider(hw);
+	unsigned long max_prate;
+	int divider;
+
+	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+		divider = _div_round(*parent_rate, rate, adiv->flags);
+		divider = _valid_divider(hw, divider);
+		return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
+	}
+
+	/* Get the maximum parent rate */
+	max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
+
+	/* Get the corresponding rounded down divider */
+	divider = max_prate / rate;
+	divider = _valid_divider(hw, divider);
+
+	/* Get actual rate of the parent */
+	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+					 divider * rate);
+
+	return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
+}
+
+static int audio_divider_set_rate(struct clk_hw *hw,
+				  unsigned long rate,
+				  unsigned long parent_rate)
+{
+	struct meson_clk_audio_divider *adiv =
+		to_meson_clk_audio_divider(hw);
+	struct parm *p;
+	unsigned long reg, flags = 0;
+	int val;
+
+	val = _get_val(parent_rate, rate);
+
+	if (adiv->lock)
+		spin_lock_irqsave(adiv->lock, flags);
+	else
+		__acquire(adiv->lock);
+
+	p = &adiv->div;
+	reg = readl(adiv->base + p->reg_off);
+	reg = PARM_SET(p->width, p->shift, reg, val);
+	writel(reg, adiv->base + p->reg_off);
+
+	if (adiv->lock)
+		spin_unlock_irqrestore(adiv->lock, flags);
+	else
+		__release(adiv->lock);
+
+	return 0;
+}
+
+const struct clk_ops meson_clk_audio_divider_ro_ops = {
+	.recalc_rate	= audio_divider_recalc_rate,
+	.round_rate	= audio_divider_round_rate,
+};
+
+const struct clk_ops meson_clk_audio_divider_ops = {
+	.recalc_rate	= audio_divider_recalc_rate,
+	.round_rate	= audio_divider_round_rate,
+	.set_rate	= audio_divider_set_rate,
+};
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index b0c9999d03de..d6feafe8bd6c 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -121,6 +121,14 @@ struct meson_clk_mpll {
 	spinlock_t *lock;
 };
 
+struct meson_clk_audio_divider {
+	struct clk_hw hw;
+	void __iomem *base;
+	struct parm div;
+	u8 flags;
+	spinlock_t *lock;
+};
+
 #define MESON_GATE(_name, _reg, _bit)					\
 struct clk_gate _name = { 						\
 	.reg = (void __iomem *) _reg, 					\
@@ -141,5 +149,7 @@ extern const struct clk_ops meson_clk_pll_ops;
 extern const struct clk_ops meson_clk_cpu_ops;
 extern const struct clk_ops meson_clk_mpll_ro_ops;
 extern const struct clk_ops meson_clk_mpll_ops;
+extern const struct clk_ops meson_clk_audio_divider_ro_ops;
+extern const struct clk_ops meson_clk_audio_divider_ops;
 
 #endif /* __CLKC_H */
-- 
2.9.3

[PATCH v1 3/8] clk: meson: add audio clock divider support

[Jerome Brunet]

The audio divider needs a specific clock divider driver.
With am mpll parent clock, which is able to provide a fairly precise rate,
the generic divider tends to select low value of the divider. In such case
the quality of the clock is very poor. For the same final rate, maximizing
the audio clock divider value and selecting the corresponding mpll rate
gives better results. This is what this driver aims to acheive. So far, so
good.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/Makefile            |   2 +-
 drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
 drivers/clk/meson/clkc.h              |  10 +++
 3 files changed, 160 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/clk-audio-divider.c

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 349583405b7c..83b6d9d65aa1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,6 +2,6 @@
 # Makefile for Meson specific clk
 #
 
-obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
new file mode 100644
index 000000000000..ac713b9ea84a
--- /dev/null
+++ b/drivers/clk/meson/clk-audio-divider.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2017 AmLogic, Inc.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * i2s master clock divider: The algorithm of the generic clk-divider used with
+ * a very precise clock parent such as the mpll tends to select a low divider
+ * factor. This gives very results with this particular divider, especially with
+ * high frequencies (> 100 MHz)
+ *
+ * This driver try to select the maximum possible divider with the rate the
+ * upstream clock can provide.
+ */
+
+#include <linux/clk-provider.h>
+#include "clkc.h"
+
+#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
+				struct meson_clk_audio_divider, hw)
+
+static int _div_round(unsigned long parent_rate, unsigned long rate,
+		      unsigned long flags)
+{
+	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
+		return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
+
+	return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+}
+
+static int _get_val(unsigned long parent_rate, unsigned long rate)
+{
+	return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
+}
+
+static int _valid_divider(struct clk_hw *hw, int divider)
+{
+	struct meson_clk_audio_divider *adiv =
+		to_meson_clk_audio_divider(hw);
+	int max_divider;
+	u8 width;
+
+	width = adiv->div.width;
+	max_divider = 1 << width;
+
+	if (divider < 1)
+		return 1;
+	else if (divider > max_divider)
+		return max_divider;
+
+	return divider;
+}
+
+static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
+					       unsigned long parent_rate)
+{
+	struct meson_clk_audio_divider *adiv =
+		to_meson_clk_audio_divider(hw);
+	struct parm *p;
+	unsigned long reg, divider;
+
+	p = &adiv->div;
+	reg = readl(adiv->base + p->reg_off);
+	divider = PARM_GET(p->width, p->shift, reg) + 1;
+
+	return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
+}
+
+static long audio_divider_round_rate(struct clk_hw *hw,
+				     unsigned long rate,
+				     unsigned long *parent_rate)
+{
+	struct meson_clk_audio_divider *adiv =
+		to_meson_clk_audio_divider(hw);
+	unsigned long max_prate;
+	int divider;
+
+	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+		divider = _div_round(*parent_rate, rate, adiv->flags);
+		divider = _valid_divider(hw, divider);
+		return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
+	}
+
+	/* Get the maximum parent rate */
+	max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
+
+	/* Get the corresponding rounded down divider */
+	divider = max_prate / rate;
+	divider = _valid_divider(hw, divider);
+
+	/* Get actual rate of the parent */
+	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+					 divider * rate);
+
+	return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
+}
+
+static int audio_divider_set_rate(struct clk_hw *hw,
+				  unsigned long rate,
+				  unsigned long parent_rate)
+{
+	struct meson_clk_audio_divider *adiv =
+		to_meson_clk_audio_divider(hw);
+	struct parm *p;
+	unsigned long reg, flags = 0;
+	int val;
+
+	val = _get_val(parent_rate, rate);
+
+	if (adiv->lock)
+		spin_lock_irqsave(adiv->lock, flags);
+	else
+		__acquire(adiv->lock);
+
+	p = &adiv->div;
+	reg = readl(adiv->base + p->reg_off);
+	reg = PARM_SET(p->width, p->shift, reg, val);
+	writel(reg, adiv->base + p->reg_off);
+
+	if (adiv->lock)
+		spin_unlock_irqrestore(adiv->lock, flags);
+	else
+		__release(adiv->lock);
+
+	return 0;
+}
+
+const struct clk_ops meson_clk_audio_divider_ro_ops = {
+	.recalc_rate	= audio_divider_recalc_rate,
+	.round_rate	= audio_divider_round_rate,
+};
+
+const struct clk_ops meson_clk_audio_divider_ops = {
+	.recalc_rate	= audio_divider_recalc_rate,
+	.round_rate	= audio_divider_round_rate,
+	.set_rate	= audio_divider_set_rate,
+};
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index b0c9999d03de..d6feafe8bd6c 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -121,6 +121,14 @@ struct meson_clk_mpll {
 	spinlock_t *lock;
 };
 
+struct meson_clk_audio_divider {
+	struct clk_hw hw;
+	void __iomem *base;
+	struct parm div;
+	u8 flags;
+	spinlock_t *lock;
+};
+
 #define MESON_GATE(_name, _reg, _bit)					\
 struct clk_gate _name = { 						\
 	.reg = (void __iomem *) _reg, 					\
@@ -141,5 +149,7 @@ extern const struct clk_ops meson_clk_pll_ops;
 extern const struct clk_ops meson_clk_cpu_ops;
 extern const struct clk_ops meson_clk_mpll_ro_ops;
 extern const struct clk_ops meson_clk_mpll_ops;
+extern const struct clk_ops meson_clk_audio_divider_ro_ops;
+extern const struct clk_ops meson_clk_audio_divider_ops;
 
 #endif /* __CLKC_H */
-- 
2.9.3

Re: [PATCH v1 3/8] clk: meson: add audio clock divider support

[Hendrik v. Raven]

On Tue, Mar 28, 2017 at 04:46:00PM +0200, Jerome Brunet wrote:
> The audio divider needs a specific clock divider driver.
> With am mpll parent clock, which is able to provide a fairly precise rate,
> the generic divider tends to select low value of the divider. In such case
> the quality of the clock is very poor. For the same final rate, maximizing
> the audio clock divider value and selecting the corresponding mpll rate
> gives better results. This is what this driver aims to acheive. So far, so
> good.
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/Makefile            |   2 +-
>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/clkc.h              |  10 +++
>  3 files changed, 160 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
> 
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 349583405b7c..83b6d9d65aa1 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -2,6 +2,6 @@
>  # Makefile for Meson specific clk
>  #
>  
> -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
> +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o
> diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
> new file mode 100644
> index 000000000000..ac713b9ea84a
> --- /dev/null
> +++ b/drivers/clk/meson/clk-audio-divider.c
> @@ -0,0 +1,149 @@
> +/*
> + * Copyright (c) 2017 AmLogic, Inc.
> + * Author: Jerome Brunet <jbrunet@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/*
> + * i2s master clock divider: The algorithm of the generic clk-divider used with
> + * a very precise clock parent such as the mpll tends to select a low divider
> + * factor. This gives very results with this particular divider, especially with
a "poor" appears to be missing here

> + * high frequencies (> 100 MHz)
> + *
> + * This driver try to select the maximum possible divider with the rate the
> + * upstream clock can provide.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include "clkc.h"
> +
> +#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
> +				struct meson_clk_audio_divider, hw)
> +
> +static int _div_round(unsigned long parent_rate, unsigned long rate,
> +		      unsigned long flags)
> +{
> +	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
> +		return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
> +
> +	return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
> +}
> +
> +static int _get_val(unsigned long parent_rate, unsigned long rate)
> +{
> +	return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
> +}
> +
> +static int _valid_divider(struct clk_hw *hw, int divider)
> +{
> +	struct meson_clk_audio_divider *adiv =
> +		to_meson_clk_audio_divider(hw);
> +	int max_divider;
> +	u8 width;
> +
> +	width = adiv->div.width;
> +	max_divider = 1 << width;
> +
> +	if (divider < 1)
> +		return 1;
> +	else if (divider > max_divider)
> +		return max_divider;
> +
> +	return divider;
This can be replaced by 
return clamp(divider, 1, max_divider);

> +}
> +
> +static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
> +					       unsigned long parent_rate)
> +{
> +	struct meson_clk_audio_divider *adiv =
> +		to_meson_clk_audio_divider(hw);
> +	struct parm *p;
> +	unsigned long reg, divider;
> +
> +	p = &adiv->div;
> +	reg = readl(adiv->base + p->reg_off);
> +	divider = PARM_GET(p->width, p->shift, reg) + 1;
> +
> +	return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
> +}
> +
> +static long audio_divider_round_rate(struct clk_hw *hw,
> +				     unsigned long rate,
> +				     unsigned long *parent_rate)
> +{
> +	struct meson_clk_audio_divider *adiv =
> +		to_meson_clk_audio_divider(hw);
> +	unsigned long max_prate;
> +	int divider;
> +
> +	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
> +		divider = _div_round(*parent_rate, rate, adiv->flags);
> +		divider = _valid_divider(hw, divider);
> +		return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
> +	}
> +
> +	/* Get the maximum parent rate */
> +	max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
> +
> +	/* Get the corresponding rounded down divider */
> +	divider = max_prate / rate;
> +	divider = _valid_divider(hw, divider);
> +
> +	/* Get actual rate of the parent */
> +	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
> +					 divider * rate);
> +
> +	return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
> +}
> +
> +static int audio_divider_set_rate(struct clk_hw *hw,
> +				  unsigned long rate,
> +				  unsigned long parent_rate)
> +{
> +	struct meson_clk_audio_divider *adiv =
> +		to_meson_clk_audio_divider(hw);
> +	struct parm *p;
> +	unsigned long reg, flags = 0;
> +	int val;
> +
> +	val = _get_val(parent_rate, rate);
> +
> +	if (adiv->lock)
> +		spin_lock_irqsave(adiv->lock, flags);
> +	else
> +		__acquire(adiv->lock);
> +
> +	p = &adiv->div;
> +	reg = readl(adiv->base + p->reg_off);
> +	reg = PARM_SET(p->width, p->shift, reg, val);
> +	writel(reg, adiv->base + p->reg_off);
> +
> +	if (adiv->lock)
> +		spin_unlock_irqrestore(adiv->lock, flags);
> +	else
> +		__release(adiv->lock);
> +
> +	return 0;
> +}
> +
> +const struct clk_ops meson_clk_audio_divider_ro_ops = {
> +	.recalc_rate	= audio_divider_recalc_rate,
> +	.round_rate	= audio_divider_round_rate,
> +};
> +
> +const struct clk_ops meson_clk_audio_divider_ops = {
> +	.recalc_rate	= audio_divider_recalc_rate,
> +	.round_rate	= audio_divider_round_rate,
> +	.set_rate	= audio_divider_set_rate,
> +};
> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> index b0c9999d03de..d6feafe8bd6c 100644
> --- a/drivers/clk/meson/clkc.h
> +++ b/drivers/clk/meson/clkc.h
> @@ -121,6 +121,14 @@ struct meson_clk_mpll {
>  	spinlock_t *lock;
>  };
>  
> +struct meson_clk_audio_divider {
> +	struct clk_hw hw;
> +	void __iomem *base;
> +	struct parm div;
> +	u8 flags;
> +	spinlock_t *lock;
> +};
> +
>  #define MESON_GATE(_name, _reg, _bit)					\
>  struct clk_gate _name = { 						\
>  	.reg = (void __iomem *) _reg, 					\
> @@ -141,5 +149,7 @@ extern const struct clk_ops meson_clk_pll_ops;
>  extern const struct clk_ops meson_clk_cpu_ops;
>  extern const struct clk_ops meson_clk_mpll_ro_ops;
>  extern const struct clk_ops meson_clk_mpll_ops;
> +extern const struct clk_ops meson_clk_audio_divider_ro_ops;
> +extern const struct clk_ops meson_clk_audio_divider_ops;
>  
>  #endif /* __CLKC_H */
> -- 
> 2.9.3
> 
> 
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH v1 3/8] clk: meson: add audio clock divider support

[Hendrik v. Raven]

On Tue, Mar 28, 2017 at 04:46:00PM +0200, Jerome Brunet wrote:
> The audio divider needs a specific clock divider driver.
> With am mpll parent clock, which is able to provide a fairly precise rate,
> the generic divider tends to select low value of the divider. In such case
> the quality of the clock is very poor. For the same final rate, maximizing
> the audio clock divider value and selecting the corresponding mpll rate
> gives better results. This is what this driver aims to acheive. So far, so
> good.
> 
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/clk/meson/Makefile            |   2 +-
>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/clkc.h              |  10 +++
>  3 files changed, 160 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
> 
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 349583405b7c..83b6d9d65aa1 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -2,6 +2,6 @@
>  # Makefile for Meson specific clk
>  #
>  
> -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
> +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o
> diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
> new file mode 100644
> index 000000000000..ac713b9ea84a
> --- /dev/null
> +++ b/drivers/clk/meson/clk-audio-divider.c
> @@ -0,0 +1,149 @@
> +/*
> + * Copyright (c) 2017 AmLogic, Inc.
> + * Author: Jerome Brunet <jbrunet@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/*
> + * i2s master clock divider: The algorithm of the generic clk-divider used with
> + * a very precise clock parent such as the mpll tends to select a low divider
> + * factor. This gives very results with this particular divider, especially with
a "poor" appears to be missing here

> + * high frequencies (> 100 MHz)
> + *
> + * This driver try to select the maximum possible divider with the rate the
> + * upstream clock can provide.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include "clkc.h"
> +
> +#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
> +				struct meson_clk_audio_divider, hw)
> +
> +static int _div_round(unsigned long parent_rate, unsigned long rate,
> +		      unsigned long flags)
> +{
> +	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
> +		return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
> +
> +	return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
> +}
> +
> +static int _get_val(unsigned long parent_rate, unsigned long rate)
> +{
> +	return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
> +}
> +
> +static int _valid_divider(struct clk_hw *hw, int divider)
> +{
> +	struct meson_clk_audio_divider *adiv =
> +		to_meson_clk_audio_divider(hw);
> +	int max_divider;
> +	u8 width;
> +
> +	width = adiv->div.width;
> +	max_divider = 1 << width;
> +
> +	if (divider < 1)
> +		return 1;
> +	else if (divider > max_divider)
> +		return max_divider;
> +
> +	return divider;
This can be replaced by 
return clamp(divider, 1, max_divider);

> +}
> +
> +static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
> +					       unsigned long parent_rate)
> +{
> +	struct meson_clk_audio_divider *adiv =
> +		to_meson_clk_audio_divider(hw);
> +	struct parm *p;
> +	unsigned long reg, divider;
> +
> +	p = &adiv->div;
> +	reg = readl(adiv->base + p->reg_off);
> +	divider = PARM_GET(p->width, p->shift, reg) + 1;
> +
> +	return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
> +}
> +
> +static long audio_divider_round_rate(struct clk_hw *hw,
> +				     unsigned long rate,
> +				     unsigned long *parent_rate)
> +{
> +	struct meson_clk_audio_divider *adiv =
> +		to_meson_clk_audio_divider(hw);
> +	unsigned long max_prate;
> +	int divider;
> +
> +	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
> +		divider = _div_round(*parent_rate, rate, adiv->flags);
> +		divider = _valid_divider(hw, divider);
> +		return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
> +	}
> +
> +	/* Get the maximum parent rate */
> +	max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
> +
> +	/* Get the corresponding rounded down divider */
> +	divider = max_prate / rate;
> +	divider = _valid_divider(hw, divider);
> +
> +	/* Get actual rate of the parent */
> +	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
> +					 divider * rate);
> +
> +	return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
> +}
> +
> +static int audio_divider_set_rate(struct clk_hw *hw,
> +				  unsigned long rate,
> +				  unsigned long parent_rate)
> +{
> +	struct meson_clk_audio_divider *adiv =
> +		to_meson_clk_audio_divider(hw);
> +	struct parm *p;
> +	unsigned long reg, flags = 0;
> +	int val;
> +
> +	val = _get_val(parent_rate, rate);
> +
> +	if (adiv->lock)
> +		spin_lock_irqsave(adiv->lock, flags);
> +	else
> +		__acquire(adiv->lock);
> +
> +	p = &adiv->div;
> +	reg = readl(adiv->base + p->reg_off);
> +	reg = PARM_SET(p->width, p->shift, reg, val);
> +	writel(reg, adiv->base + p->reg_off);
> +
> +	if (adiv->lock)
> +		spin_unlock_irqrestore(adiv->lock, flags);
> +	else
> +		__release(adiv->lock);
> +
> +	return 0;
> +}
> +
> +const struct clk_ops meson_clk_audio_divider_ro_ops = {
> +	.recalc_rate	= audio_divider_recalc_rate,
> +	.round_rate	= audio_divider_round_rate,
> +};
> +
> +const struct clk_ops meson_clk_audio_divider_ops = {
> +	.recalc_rate	= audio_divider_recalc_rate,
> +	.round_rate	= audio_divider_round_rate,
> +	.set_rate	= audio_divider_set_rate,
> +};
> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> index b0c9999d03de..d6feafe8bd6c 100644
> --- a/drivers/clk/meson/clkc.h
> +++ b/drivers/clk/meson/clkc.h
> @@ -121,6 +121,14 @@ struct meson_clk_mpll {
>  	spinlock_t *lock;
>  };
>  
> +struct meson_clk_audio_divider {
> +	struct clk_hw hw;
> +	void __iomem *base;
> +	struct parm div;
> +	u8 flags;
> +	spinlock_t *lock;
> +};
> +
>  #define MESON_GATE(_name, _reg, _bit)					\
>  struct clk_gate _name = { 						\
>  	.reg = (void __iomem *) _reg, 					\
> @@ -141,5 +149,7 @@ extern const struct clk_ops meson_clk_pll_ops;
>  extern const struct clk_ops meson_clk_cpu_ops;
>  extern const struct clk_ops meson_clk_mpll_ro_ops;
>  extern const struct clk_ops meson_clk_mpll_ops;
> +extern const struct clk_ops meson_clk_audio_divider_ro_ops;
> +extern const struct clk_ops meson_clk_audio_divider_ops;
>  
>  #endif /* __CLKC_H */
> -- 
> 2.9.3
> 
> 
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH v1 3/8] clk: meson: add audio clock divider support

[Jerome Brunet]

On Tue, 2017-03-28 at 16:58 +0200, Hendrik v. Raven wrote:
> On Tue, Mar 28, 2017 at 04:46:00PM +0200, Jerome Brunet wrote:
> > The audio divider needs a specific clock divider driver.
> > With am mpll parent clock, which is able to provide a fairly precise rate,
> > the generic divider tends to select low value of the divider. In such case
> > the quality of the clock is very poor. For the same final rate, maximizing
> > the audio clock divider value and selecting the corresponding mpll rate
> > gives better results. This is what this driver aims to acheive. So far, so
> > good.
> > 
> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > ---
> >  drivers/clk/meson/Makefile            |   2 +-
> >  drivers/clk/meson/clk-audio-divider.c | 149
> > ++++++++++++++++++++++++++++++++++
> >  drivers/clk/meson/clkc.h              |  10 +++
> >  3 files changed, 160 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/meson/clk-audio-divider.c
> > 
> > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> > index 349583405b7c..83b6d9d65aa1 100644
> > --- a/drivers/clk/meson/Makefile
> > +++ b/drivers/clk/meson/Makefile
> > @@ -2,6 +2,6 @@
> >  # Makefile for Meson specific clk
> >  #
> >  
> > -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
> > +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-
> > audio-divider.o
> >  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> >  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o
> > diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-
> > audio-divider.c
> > new file mode 100644
> > index 000000000000..ac713b9ea84a
> > --- /dev/null
> > +++ b/drivers/clk/meson/clk-audio-divider.c
> > @@ -0,0 +1,149 @@
> > +/*
> > + * Copyright (c) 2017 AmLogic, Inc.
> > + * Author: Jerome Brunet <jbrunet@baylibre.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> > for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along
> > with
> > + * this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +/*
> > + * i2s master clock divider: The algorithm of the generic clk-divider used
> > with
> > + * a very precise clock parent such as the mpll tends to select a low
> > divider
> > + * factor. This gives very results with this particular divider, especially
> > with
> 
> a "poor" appears to be missing here
Indeed, thanks for spotting this 

> 
> > + * high frequencies (> 100 MHz)
> > + *
> > + * This driver try to select the maximum possible divider with the rate the
> > + * upstream clock can provide.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include "clkc.h"
> > +
> > +#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
> > +				struct meson_clk_audio_divider, hw)
> > +
> > +static int _div_round(unsigned long parent_rate, unsigned long rate,
> > +		      unsigned long flags)
> > +{
> > +	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
> > +		return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
> > +
> > +	return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
> > +}
> > +
> > +static int _get_val(unsigned long parent_rate, unsigned long rate)
> > +{
> > +	return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
> > +}
> > +
> > +static int _valid_divider(struct clk_hw *hw, int divider)
> > +{
> > +	struct meson_clk_audio_divider *adiv =
> > +		to_meson_clk_audio_divider(hw);
> > +	int max_divider;
> > +	u8 width;
> > +
> > +	width = adiv->div.width;
> > +	max_divider = 1 << width;
> > +
> > +	if (divider < 1)
> > +		return 1;
> > +	else if (divider > max_divider)
> > +		return max_divider;
> > +
> > +	return divider;
> 
> This can be replaced by 
> return clamp(divider, 1, max_divider);
Will be replaced in v2. Thx

> 
> > +}
> > +
> > +static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
> > +					       unsigned long parent_rate)
> > +{
> > +	struct meson_clk_audio_divider *adiv =
> > +		to_meson_clk_audio_divider(hw);
> > +	struct parm *p;
> > +	unsigned long reg, divider;
> > +
> > +	p = &adiv->div;
> > +	reg = readl(adiv->base + p->reg_off);
> > +	divider = PARM_GET(p->width, p->shift, reg) + 1;
> > +
> > +	return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
> > +}
> > +
> > +static long audio_divider_round_rate(struct clk_hw *hw,
> > +				     unsigned long rate,
> > +				     unsigned long *parent_rate)
> > +{
> > +	struct meson_clk_audio_divider *adiv =
> > +		to_meson_clk_audio_divider(hw);
> > +	unsigned long max_prate;
> > +	int divider;
> > +
> > +	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
> > +		divider = _div_round(*parent_rate, rate, adiv->flags);
> > +		divider = _valid_divider(hw, divider);
> > +		return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
> > +	}
> > +
> > +	/* Get the maximum parent rate */
> > +	max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
> > +
> > +	/* Get the corresponding rounded down divider */
> > +	divider = max_prate / rate;
> > +	divider = _valid_divider(hw, divider);
> > +
> > +	/* Get actual rate of the parent */
> > +	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
> > +					 divider * rate);
> > +
> > +	return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
> > +}
> > +
> > +static int audio_divider_set_rate(struct clk_hw *hw,
> > +				  unsigned long rate,
> > +				  unsigned long parent_rate)
> > +{
> > +	struct meson_clk_audio_divider *adiv =
> > +		to_meson_clk_audio_divider(hw);
> > +	struct parm *p;
> > +	unsigned long reg, flags = 0;
> > +	int val;
> > +
> > +	val = _get_val(parent_rate, rate);
> > +
> > +	if (adiv->lock)
> > +		spin_lock_irqsave(adiv->lock, flags);
> > +	else
> > +		__acquire(adiv->lock);
> > +
> > +	p = &adiv->div;
> > +	reg = readl(adiv->base + p->reg_off);
> > +	reg = PARM_SET(p->width, p->shift, reg, val);
> > +	writel(reg, adiv->base + p->reg_off);
> > +
> > +	if (adiv->lock)
> > +		spin_unlock_irqrestore(adiv->lock, flags);
> > +	else
> > +		__release(adiv->lock);
> > +
> > +	return 0;
> > +}
> > +
> > +const struct clk_ops meson_clk_audio_divider_ro_ops = {
> > +	.recalc_rate	= audio_divider_recalc_rate,
> > +	.round_rate	= audio_divider_round_rate,
> > +};
> > +
> > +const struct clk_ops meson_clk_audio_divider_ops = {
> > +	.recalc_rate	= audio_divider_recalc_rate,
> > +	.round_rate	= audio_divider_round_rate,
> > +	.set_rate	= audio_divider_set_rate,
> > +};
> > diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> > index b0c9999d03de..d6feafe8bd6c 100644
> > --- a/drivers/clk/meson/clkc.h
> > +++ b/drivers/clk/meson/clkc.h
> > @@ -121,6 +121,14 @@ struct meson_clk_mpll {
> >  	spinlock_t *lock;
> >  };
> >  
> > +struct meson_clk_audio_divider {
> > +	struct clk_hw hw;
> > +	void __iomem *base;
> > +	struct parm div;
> > +	u8 flags;
> > +	spinlock_t *lock;
> > +};
> > +
> >  #define MESON_GATE(_name, _reg, _bit)					
> > \
> >  struct clk_gate _name = { 						\
> >  	.reg = (void __iomem *) _reg, 					
> > \
> > @@ -141,5 +149,7 @@ extern const struct clk_ops meson_clk_pll_ops;
> >  extern const struct clk_ops meson_clk_cpu_ops;
> >  extern const struct clk_ops meson_clk_mpll_ro_ops;
> >  extern const struct clk_ops meson_clk_mpll_ops;
> > +extern const struct clk_ops meson_clk_audio_divider_ro_ops;
> > +extern const struct clk_ops meson_clk_audio_divider_ops;
> >  
> >  #endif /* __CLKC_H */
> > -- 
> > 2.9.3
> > 
> > 
> > _______________________________________________
> > linux-amlogic mailing list
> > linux-amlogic@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH v1 3/8] clk: meson: add audio clock divider support

[Jerome Brunet]

On Tue, 2017-03-28 at 16:58 +0200, Hendrik v. Raven wrote:
> On Tue, Mar 28, 2017 at 04:46:00PM +0200, Jerome Brunet wrote:
> > The audio divider needs a specific clock divider driver.
> > With am mpll parent clock, which is able to provide a fairly precise rate,
> > the generic divider tends to select low value of the divider. In such case
> > the quality of the clock is very poor. For the same final rate, maximizing
> > the audio clock divider value and selecting the corresponding mpll rate
> > gives better results. This is what this driver aims to acheive. So far, so
> > good.
> > 
> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > ---
> > ?drivers/clk/meson/Makefile????????????|???2 +-
> > ?drivers/clk/meson/clk-audio-divider.c | 149
> > ++++++++++++++++++++++++++++++++++
> > ?drivers/clk/meson/clkc.h??????????????|??10 +++
> > ?3 files changed, 160 insertions(+), 1 deletion(-)
> > ?create mode 100644 drivers/clk/meson/clk-audio-divider.c
> > 
> > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> > index 349583405b7c..83b6d9d65aa1 100644
> > --- a/drivers/clk/meson/Makefile
> > +++ b/drivers/clk/meson/Makefile
> > @@ -2,6 +2,6 @@
> > ?# Makefile for Meson specific clk
> > ?#
> > ?
> > -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
> > +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-
> > audio-divider.o
> > ?obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> > ?obj-$(CONFIG_COMMON_CLK_GXBB)	?+= gxbb.o gxbb-aoclk.o
> > diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-
> > audio-divider.c
> > new file mode 100644
> > index 000000000000..ac713b9ea84a
> > --- /dev/null
> > +++ b/drivers/clk/meson/clk-audio-divider.c
> > @@ -0,0 +1,149 @@
> > +/*
> > + * Copyright (c) 2017 AmLogic, Inc.
> > + * Author: Jerome Brunet <jbrunet@baylibre.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE.??See the GNU General Public License
> > for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along
> > with
> > + * this program.??If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +/*
> > + * i2s master clock divider: The algorithm of the generic clk-divider used
> > with
> > + * a very precise clock parent such as the mpll tends to select a low
> > divider
> > + * factor. This gives very results with this particular divider, especially
> > with
> 
> a "poor" appears to be missing here
Indeed, thanks for spotting this 

> 
> > + * high frequencies (> 100 MHz)
> > + *
> > + * This driver try to select the maximum possible divider with the rate the
> > + * upstream clock can provide.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include "clkc.h"
> > +
> > +#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
> > +				struct meson_clk_audio_divider, hw)
> > +
> > +static int _div_round(unsigned long parent_rate, unsigned long rate,
> > +		??????unsigned long flags)
> > +{
> > +	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
> > +		return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
> > +
> > +	return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
> > +}
> > +
> > +static int _get_val(unsigned long parent_rate, unsigned long rate)
> > +{
> > +	return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
> > +}
> > +
> > +static int _valid_divider(struct clk_hw *hw, int divider)
> > +{
> > +	struct meson_clk_audio_divider *adiv =
> > +		to_meson_clk_audio_divider(hw);
> > +	int max_divider;
> > +	u8 width;
> > +
> > +	width = adiv->div.width;
> > +	max_divider = 1 << width;
> > +
> > +	if (divider < 1)
> > +		return 1;
> > +	else if (divider > max_divider)
> > +		return max_divider;
> > +
> > +	return divider;
> 
> This can be replaced by?
> return clamp(divider, 1, max_divider);
Will be replaced in v2. Thx

> 
> > +}
> > +
> > +static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
> > +					???????unsigned long parent_rate)
> > +{
> > +	struct meson_clk_audio_divider *adiv =
> > +		to_meson_clk_audio_divider(hw);
> > +	struct parm *p;
> > +	unsigned long reg, divider;
> > +
> > +	p = &adiv->div;
> > +	reg = readl(adiv->base + p->reg_off);
> > +	divider = PARM_GET(p->width, p->shift, reg) + 1;
> > +
> > +	return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
> > +}
> > +
> > +static long audio_divider_round_rate(struct clk_hw *hw,
> > +				?????unsigned long rate,
> > +				?????unsigned long *parent_rate)
> > +{
> > +	struct meson_clk_audio_divider *adiv =
> > +		to_meson_clk_audio_divider(hw);
> > +	unsigned long max_prate;
> > +	int divider;
> > +
> > +	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
> > +		divider = _div_round(*parent_rate, rate, adiv->flags);
> > +		divider = _valid_divider(hw, divider);
> > +		return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
> > +	}
> > +
> > +	/* Get the maximum parent rate */
> > +	max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
> > +
> > +	/* Get the corresponding rounded down divider */
> > +	divider = max_prate / rate;
> > +	divider = _valid_divider(hw, divider);
> > +
> > +	/* Get actual rate of the parent */
> > +	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
> > +					?divider * rate);
> > +
> > +	return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
> > +}
> > +
> > +static int audio_divider_set_rate(struct clk_hw *hw,
> > +				??unsigned long rate,
> > +				??unsigned long parent_rate)
> > +{
> > +	struct meson_clk_audio_divider *adiv =
> > +		to_meson_clk_audio_divider(hw);
> > +	struct parm *p;
> > +	unsigned long reg, flags = 0;
> > +	int val;
> > +
> > +	val = _get_val(parent_rate, rate);
> > +
> > +	if (adiv->lock)
> > +		spin_lock_irqsave(adiv->lock, flags);
> > +	else
> > +		__acquire(adiv->lock);
> > +
> > +	p = &adiv->div;
> > +	reg = readl(adiv->base + p->reg_off);
> > +	reg = PARM_SET(p->width, p->shift, reg, val);
> > +	writel(reg, adiv->base + p->reg_off);
> > +
> > +	if (adiv->lock)
> > +		spin_unlock_irqrestore(adiv->lock, flags);
> > +	else
> > +		__release(adiv->lock);
> > +
> > +	return 0;
> > +}
> > +
> > +const struct clk_ops meson_clk_audio_divider_ro_ops = {
> > +	.recalc_rate	= audio_divider_recalc_rate,
> > +	.round_rate	= audio_divider_round_rate,
> > +};
> > +
> > +const struct clk_ops meson_clk_audio_divider_ops = {
> > +	.recalc_rate	= audio_divider_recalc_rate,
> > +	.round_rate	= audio_divider_round_rate,
> > +	.set_rate	= audio_divider_set_rate,
> > +};
> > diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> > index b0c9999d03de..d6feafe8bd6c 100644
> > --- a/drivers/clk/meson/clkc.h
> > +++ b/drivers/clk/meson/clkc.h
> > @@ -121,6 +121,14 @@ struct meson_clk_mpll {
> > ?	spinlock_t *lock;
> > ?};
> > ?
> > +struct meson_clk_audio_divider {
> > +	struct clk_hw hw;
> > +	void __iomem *base;
> > +	struct parm div;
> > +	u8 flags;
> > +	spinlock_t *lock;
> > +};
> > +
> > ?#define MESON_GATE(_name, _reg, _bit)					
> > \
> > ?struct clk_gate _name = {?						\
> > ?	.reg = (void __iomem *) _reg,?					
> > \
> > @@ -141,5 +149,7 @@ extern const struct clk_ops meson_clk_pll_ops;
> > ?extern const struct clk_ops meson_clk_cpu_ops;
> > ?extern const struct clk_ops meson_clk_mpll_ro_ops;
> > ?extern const struct clk_ops meson_clk_mpll_ops;
> > +extern const struct clk_ops meson_clk_audio_divider_ro_ops;
> > +extern const struct clk_ops meson_clk_audio_divider_ops;
> > ?
> > ?#endif /* __CLKC_H */
> > --?
> > 2.9.3
> > 
> > 
> > _______________________________________________
> > linux-amlogic mailing list
> > linux-amlogic at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH v1 4/8] clk: meson: gxbb: add cts_amclk

[Jerome Brunet]

Add the i2s master clock also referred as cts_amclk

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h |  5 +++-
 2 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 28812ea41a60..1c20edbfc812 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -845,6 +845,51 @@ static struct clk_mux gxbb_mali = {
 	},
 };
 
+static struct clk_mux gxbb_cts_amclk_sel = {
+	.reg = (void *) HHI_AUD_CLK_CNTL,
+	.mask = 0x3,
+	.shift = 9,
+	/* Default parent unknown (register reset value: 0) */
+	.table = (u32[]){ 1, 2, 3 },
+	.lock = &clk_lock,
+		.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk_sel",
+		.ops = &clk_mux_ops,
+		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
+		.num_parents = 3,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
+	.div = {
+		.reg_off = HHI_AUD_CLK_CNTL,
+		.shift   = 0,
+		.width   = 8,
+	},
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk_div",
+		.ops = &meson_clk_audio_divider_ops,
+		.parent_names = (const char *[]){ "cts_amclk_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
+	},
+};
+
+static struct clk_gate gxbb_cts_amclk = {
+	.reg = (void *) HHI_AUD_CLK_CNTL,
+	.bit_idx = 8,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk",
+		.ops = &clk_gate_ops,
+		.parent_names = (const char *[]){ "cts_amclk_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1045,6 +1090,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 		[CLKID_MALI_1_DIV]	    = &gxbb_mali_1_div.hw,
 		[CLKID_MALI_1]		    = &gxbb_mali_1.hw,
 		[CLKID_MALI]		    = &gxbb_mali.hw,
+		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
+		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
+		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1158,6 +1206,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
 		[CLKID_MALI_1_DIV]	    = &gxbb_mali_1_div.hw,
 		[CLKID_MALI_1]		    = &gxbb_mali_1.hw,
 		[CLKID_MALI]		    = &gxbb_mali.hw,
+		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
+		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
+		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1270,6 +1321,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
 	&gxbb_sar_adc_clk,
 	&gxbb_mali_0,
 	&gxbb_mali_1,
+	&gxbb_cts_amclk,
 };
 
 static struct clk_mux *const gxbb_clk_muxes[] = {
@@ -1278,6 +1330,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
 	&gxbb_mali_0_sel,
 	&gxbb_mali_1_sel,
 	&gxbb_mali,
+	&gxbb_cts_amclk_sel,
 };
 
 static struct clk_divider *const gxbb_clk_dividers[] = {
@@ -1287,6 +1340,10 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
 	&gxbb_mali_1_div,
 };
 
+static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
+	&gxbb_cts_amclk_div,
+};
+
 struct clkc_data {
 	struct clk_gate *const *clk_gates;
 	unsigned int clk_gates_count;
@@ -1298,6 +1355,8 @@ struct clkc_data {
 	unsigned int clk_muxes_count;
 	struct clk_divider *const *clk_dividers;
 	unsigned int clk_dividers_count;
+	struct meson_clk_audio_divider *const *clk_audio_dividers;
+	unsigned int clk_audio_dividers_count;
 	struct meson_clk_cpu *cpu_clk;
 	struct clk_hw_onecell_data *hw_onecell_data;
 };
@@ -1313,6 +1372,8 @@ static const struct clkc_data gxbb_clkc_data = {
 	.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
 	.clk_dividers = gxbb_clk_dividers,
 	.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
+	.clk_audio_dividers = gxbb_audio_dividers,
+	.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
 	.cpu_clk = &gxbb_cpu_clk,
 	.hw_onecell_data = &gxbb_hw_onecell_data,
 };
@@ -1328,6 +1389,8 @@ static const struct clkc_data gxl_clkc_data = {
 	.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
 	.clk_dividers = gxbb_clk_dividers,
 	.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
+	.clk_audio_dividers = gxbb_audio_dividers,
+	.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
 	.cpu_clk = &gxbb_cpu_clk,
 	.hw_onecell_data = &gxl_hw_onecell_data,
 };
@@ -1384,6 +1447,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
 		clkc_data->clk_dividers[i]->reg = clk_base +
 			(u64)clkc_data->clk_dividers[i]->reg;
 
+	/* Populate base address for the audio dividers */
+	for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
+		clkc_data->clk_audio_dividers[i]->base = clk_base;
+
 	/*
 	 * register all clks
 	 */
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0d535f7e7aed..c8e9fb99af92 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -277,8 +277,11 @@
 #define CLKID_MALI_1_DIV	 104
 /* CLKID_MALI_1	*/
 /* CLKID_MALI	*/
+#define CLKID_CTS_AMCLK		  107
+#define CLKID_CTS_AMCLK_SEL	  108
+#define CLKID_CTS_AMCLK_DIV	  109
 
-#define NR_CLKS			  107
+#define NR_CLKS			  110
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
-- 
2.9.3

[PATCH v1 4/8] clk: meson: gxbb: add cts_amclk

[Jerome Brunet]

Add the i2s master clock also referred as cts_amclk

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h |  5 +++-
 2 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 28812ea41a60..1c20edbfc812 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -845,6 +845,51 @@ static struct clk_mux gxbb_mali = {
 	},
 };
 
+static struct clk_mux gxbb_cts_amclk_sel = {
+	.reg = (void *) HHI_AUD_CLK_CNTL,
+	.mask = 0x3,
+	.shift = 9,
+	/* Default parent unknown (register reset value: 0) */
+	.table = (u32[]){ 1, 2, 3 },
+	.lock = &clk_lock,
+		.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk_sel",
+		.ops = &clk_mux_ops,
+		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
+		.num_parents = 3,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
+	.div = {
+		.reg_off = HHI_AUD_CLK_CNTL,
+		.shift   = 0,
+		.width   = 8,
+	},
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk_div",
+		.ops = &meson_clk_audio_divider_ops,
+		.parent_names = (const char *[]){ "cts_amclk_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
+	},
+};
+
+static struct clk_gate gxbb_cts_amclk = {
+	.reg = (void *) HHI_AUD_CLK_CNTL,
+	.bit_idx = 8,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk",
+		.ops = &clk_gate_ops,
+		.parent_names = (const char *[]){ "cts_amclk_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1045,6 +1090,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 		[CLKID_MALI_1_DIV]	    = &gxbb_mali_1_div.hw,
 		[CLKID_MALI_1]		    = &gxbb_mali_1.hw,
 		[CLKID_MALI]		    = &gxbb_mali.hw,
+		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
+		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
+		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1158,6 +1206,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
 		[CLKID_MALI_1_DIV]	    = &gxbb_mali_1_div.hw,
 		[CLKID_MALI_1]		    = &gxbb_mali_1.hw,
 		[CLKID_MALI]		    = &gxbb_mali.hw,
+		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
+		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
+		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1270,6 +1321,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
 	&gxbb_sar_adc_clk,
 	&gxbb_mali_0,
 	&gxbb_mali_1,
+	&gxbb_cts_amclk,
 };
 
 static struct clk_mux *const gxbb_clk_muxes[] = {
@@ -1278,6 +1330,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
 	&gxbb_mali_0_sel,
 	&gxbb_mali_1_sel,
 	&gxbb_mali,
+	&gxbb_cts_amclk_sel,
 };
 
 static struct clk_divider *const gxbb_clk_dividers[] = {
@@ -1287,6 +1340,10 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
 	&gxbb_mali_1_div,
 };
 
+static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
+	&gxbb_cts_amclk_div,
+};
+
 struct clkc_data {
 	struct clk_gate *const *clk_gates;
 	unsigned int clk_gates_count;
@@ -1298,6 +1355,8 @@ struct clkc_data {
 	unsigned int clk_muxes_count;
 	struct clk_divider *const *clk_dividers;
 	unsigned int clk_dividers_count;
+	struct meson_clk_audio_divider *const *clk_audio_dividers;
+	unsigned int clk_audio_dividers_count;
 	struct meson_clk_cpu *cpu_clk;
 	struct clk_hw_onecell_data *hw_onecell_data;
 };
@@ -1313,6 +1372,8 @@ static const struct clkc_data gxbb_clkc_data = {
 	.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
 	.clk_dividers = gxbb_clk_dividers,
 	.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
+	.clk_audio_dividers = gxbb_audio_dividers,
+	.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
 	.cpu_clk = &gxbb_cpu_clk,
 	.hw_onecell_data = &gxbb_hw_onecell_data,
 };
@@ -1328,6 +1389,8 @@ static const struct clkc_data gxl_clkc_data = {
 	.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
 	.clk_dividers = gxbb_clk_dividers,
 	.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
+	.clk_audio_dividers = gxbb_audio_dividers,
+	.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
 	.cpu_clk = &gxbb_cpu_clk,
 	.hw_onecell_data = &gxl_hw_onecell_data,
 };
@@ -1384,6 +1447,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
 		clkc_data->clk_dividers[i]->reg = clk_base +
 			(u64)clkc_data->clk_dividers[i]->reg;
 
+	/* Populate base address for the audio dividers */
+	for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
+		clkc_data->clk_audio_dividers[i]->base = clk_base;
+
 	/*
 	 * register all clks
 	 */
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0d535f7e7aed..c8e9fb99af92 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -277,8 +277,11 @@
 #define CLKID_MALI_1_DIV	 104
 /* CLKID_MALI_1	*/
 /* CLKID_MALI	*/
+#define CLKID_CTS_AMCLK		  107
+#define CLKID_CTS_AMCLK_SEL	  108
+#define CLKID_CTS_AMCLK_DIV	  109
 
-#define NR_CLKS			  107
+#define NR_CLKS			  110
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
-- 
2.9.3

[PATCH v1 5/8] clk: meson: gxbb: add cts_mclk_i958

[Jerome Brunet]

Add the spdif master clock also referred as cts_mclk_i958

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h |  5 ++++-
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 1c20edbfc812..72492cc63915 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -890,6 +890,49 @@ static struct clk_gate gxbb_cts_amclk = {
 	},
 };
 
+static struct clk_mux gxbb_cts_mclk_i958_sel = {
+	.reg = (void *)HHI_AUD_CLK_CNTL2,
+	.mask = 0x3,
+	.shift = 25,
+	/* Default parent unknown (register reset value: 0) */
+	.table = (u32[]){ 1, 2, 3 },
+	.lock = &clk_lock,
+		.hw.init = &(struct clk_init_data){
+		.name = "cts_mclk_i958_sel",
+		.ops = &clk_mux_ops,
+		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
+		.num_parents = 3,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_divider gxbb_cts_mclk_i958_div = {
+	.reg = (void *)HHI_AUD_CLK_CNTL2,
+	.shift = 16,
+	.width = 8,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_mclk_i958_div",
+		.ops = &clk_divider_ops,
+		.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
+	},
+};
+
+static struct clk_gate gxbb_cts_mclk_i958 = {
+	.reg = (void *)HHI_AUD_CLK_CNTL2,
+	.bit_idx = 24,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_mclk_i958",
+		.ops = &clk_gate_ops,
+		.parent_names = (const char *[]){ "cts_mclk_i958_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1093,6 +1136,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
 		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
 		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
+		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
+		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
+		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1209,6 +1255,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
 		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
 		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
 		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
+		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
+		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
+		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1322,6 +1371,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
 	&gxbb_mali_0,
 	&gxbb_mali_1,
 	&gxbb_cts_amclk,
+	&gxbb_cts_mclk_i958,
 };
 
 static struct clk_mux *const gxbb_clk_muxes[] = {
@@ -1331,6 +1381,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
 	&gxbb_mali_1_sel,
 	&gxbb_mali,
 	&gxbb_cts_amclk_sel,
+	&gxbb_cts_mclk_i958_sel,
 };
 
 static struct clk_divider *const gxbb_clk_dividers[] = {
@@ -1338,6 +1389,7 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
 	&gxbb_sar_adc_clk_div,
 	&gxbb_mali_0_div,
 	&gxbb_mali_1_div,
+	&gxbb_cts_mclk_i958_div,
 };
 
 static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index c8e9fb99af92..efa90dad3478 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -280,8 +280,11 @@
 #define CLKID_CTS_AMCLK		  107
 #define CLKID_CTS_AMCLK_SEL	  108
 #define CLKID_CTS_AMCLK_DIV	  109
+#define CLKID_CTS_MCLK_I958	  110
+#define CLKID_CTS_MCLK_I958_SEL	  111
+#define CLKID_CTS_MCLK_I958_DIV	  112
 
-#define NR_CLKS			  110
+#define NR_CLKS			  113
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
-- 
2.9.3

[PATCH v1 5/8] clk: meson: gxbb: add cts_mclk_i958

[Jerome Brunet]

Add the spdif master clock also referred as cts_mclk_i958

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h |  5 ++++-
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 1c20edbfc812..72492cc63915 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -890,6 +890,49 @@ static struct clk_gate gxbb_cts_amclk = {
 	},
 };
 
+static struct clk_mux gxbb_cts_mclk_i958_sel = {
+	.reg = (void *)HHI_AUD_CLK_CNTL2,
+	.mask = 0x3,
+	.shift = 25,
+	/* Default parent unknown (register reset value: 0) */
+	.table = (u32[]){ 1, 2, 3 },
+	.lock = &clk_lock,
+		.hw.init = &(struct clk_init_data){
+		.name = "cts_mclk_i958_sel",
+		.ops = &clk_mux_ops,
+		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
+		.num_parents = 3,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_divider gxbb_cts_mclk_i958_div = {
+	.reg = (void *)HHI_AUD_CLK_CNTL2,
+	.shift = 16,
+	.width = 8,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_mclk_i958_div",
+		.ops = &clk_divider_ops,
+		.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
+	},
+};
+
+static struct clk_gate gxbb_cts_mclk_i958 = {
+	.reg = (void *)HHI_AUD_CLK_CNTL2,
+	.bit_idx = 24,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_mclk_i958",
+		.ops = &clk_gate_ops,
+		.parent_names = (const char *[]){ "cts_mclk_i958_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1093,6 +1136,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
 		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
 		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
+		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
+		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
+		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1209,6 +1255,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
 		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
 		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
 		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
+		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
+		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
+		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1322,6 +1371,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
 	&gxbb_mali_0,
 	&gxbb_mali_1,
 	&gxbb_cts_amclk,
+	&gxbb_cts_mclk_i958,
 };
 
 static struct clk_mux *const gxbb_clk_muxes[] = {
@@ -1331,6 +1381,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
 	&gxbb_mali_1_sel,
 	&gxbb_mali,
 	&gxbb_cts_amclk_sel,
+	&gxbb_cts_mclk_i958_sel,
 };
 
 static struct clk_divider *const gxbb_clk_dividers[] = {
@@ -1338,6 +1389,7 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
 	&gxbb_sar_adc_clk_div,
 	&gxbb_mali_0_div,
 	&gxbb_mali_1_div,
+	&gxbb_cts_mclk_i958_div,
 };
 
 static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index c8e9fb99af92..efa90dad3478 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -280,8 +280,11 @@
 #define CLKID_CTS_AMCLK		  107
 #define CLKID_CTS_AMCLK_SEL	  108
 #define CLKID_CTS_AMCLK_DIV	  109
+#define CLKID_CTS_MCLK_I958	  110
+#define CLKID_CTS_MCLK_I958_SEL	  111
+#define CLKID_CTS_MCLK_I958_DIV	  112
 
-#define NR_CLKS			  110
+#define NR_CLKS			  113
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
-- 
2.9.3

[PATCH v1 6/8] clk: meson: gxbb: add cts_i958 clock

[Jerome Brunet]

This adds the cts_i958 clock to control the clock source of the spdif
output block. This mux is not explicitly mentionned in the documentation
but it is critical to the spdif dai. It is used to select whether the clock
source of the spdif output is cts_amclk (when data are taken from i2s
buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer)

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 21 +++++++++++++++++++++
 drivers/clk/meson/gxbb.h |  3 ++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 72492cc63915..ad5f027af1a2 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -933,6 +933,24 @@ static struct clk_gate gxbb_cts_mclk_i958 = {
 	},
 };
 
+static struct clk_mux gxbb_cts_i958 = {
+	.reg = (void *)HHI_AUD_CLK_CNTL2,
+	.mask = 0x1,
+	.shift = 27,
+	.lock = &clk_lock,
+		.hw.init = &(struct clk_init_data){
+		.name = "cts_i958",
+		.ops = &clk_mux_ops,
+		.parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
+		.num_parents = 2,
+		/*
+		 *The parent is specific to origin of the audio data. Let the
+		 * consumer choose the appropriate parent
+		 */
+		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1139,6 +1157,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
 		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
 		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
+		[CLKID_CTS_I958]	    = &gxbb_cts_i958.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1258,6 +1277,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
 		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
 		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
 		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
+		[CLKID_CTS_I958]	    = &gxbb_cts_i958.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1382,6 +1402,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
 	&gxbb_mali,
 	&gxbb_cts_amclk_sel,
 	&gxbb_cts_mclk_i958_sel,
+	&gxbb_cts_i958,
 };
 
 static struct clk_divider *const gxbb_clk_dividers[] = {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index efa90dad3478..3b0665099a1e 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -283,8 +283,9 @@
 #define CLKID_CTS_MCLK_I958	  110
 #define CLKID_CTS_MCLK_I958_SEL	  111
 #define CLKID_CTS_MCLK_I958_DIV	  112
+#define CLKID_CTS_I958		  113
 
-#define NR_CLKS			  113
+#define NR_CLKS			  114
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
-- 
2.9.3

[PATCH v1 6/8] clk: meson: gxbb: add cts_i958 clock

[Jerome Brunet]

This adds the cts_i958 clock to control the clock source of the spdif
output block. This mux is not explicitly mentionned in the documentation
but it is critical to the spdif dai. It is used to select whether the clock
source of the spdif output is cts_amclk (when data are taken from i2s
buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer)

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 21 +++++++++++++++++++++
 drivers/clk/meson/gxbb.h |  3 ++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 72492cc63915..ad5f027af1a2 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -933,6 +933,24 @@ static struct clk_gate gxbb_cts_mclk_i958 = {
 	},
 };
 
+static struct clk_mux gxbb_cts_i958 = {
+	.reg = (void *)HHI_AUD_CLK_CNTL2,
+	.mask = 0x1,
+	.shift = 27,
+	.lock = &clk_lock,
+		.hw.init = &(struct clk_init_data){
+		.name = "cts_i958",
+		.ops = &clk_mux_ops,
+		.parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
+		.num_parents = 2,
+		/*
+		 *The parent is specific to origin of the audio data. Let the
+		 * consumer choose the appropriate parent
+		 */
+		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1139,6 +1157,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
 		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
 		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
+		[CLKID_CTS_I958]	    = &gxbb_cts_i958.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1258,6 +1277,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
 		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
 		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
 		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
+		[CLKID_CTS_I958]	    = &gxbb_cts_i958.hw,
 	},
 	.num = NR_CLKS,
 };
@@ -1382,6 +1402,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
 	&gxbb_mali,
 	&gxbb_cts_amclk_sel,
 	&gxbb_cts_mclk_i958_sel,
+	&gxbb_cts_i958,
 };
 
 static struct clk_divider *const gxbb_clk_dividers[] = {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index efa90dad3478..3b0665099a1e 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -283,8 +283,9 @@
 #define CLKID_CTS_MCLK_I958	  110
 #define CLKID_CTS_MCLK_I958_SEL	  111
 #define CLKID_CTS_MCLK_I958_DIV	  112
+#define CLKID_CTS_I958		  113
 
-#define NR_CLKS			  113
+#define NR_CLKS			  114
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
-- 
2.9.3

[PATCH v1 7/8] dt-bindings: clock: gxbb: expose i2s master clock

[Jerome Brunet]

Expose cts_amclk in the device tree bindings

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.h              | 2 +-
 include/dt-bindings/clock/gxbb-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 3b0665099a1e..742bc3b42565 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -277,7 +277,7 @@
 #define CLKID_MALI_1_DIV	 104
 /* CLKID_MALI_1	*/
 /* CLKID_MALI	*/
-#define CLKID_CTS_AMCLK		  107
+/* CLKID_CTS_AMCLK */
 #define CLKID_CTS_AMCLK_SEL	  108
 #define CLKID_CTS_AMCLK_DIV	  109
 #define CLKID_CTS_MCLK_I958	  110
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 1d4614bc8154..0d231bef92e0 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -43,5 +43,6 @@
 #define CLKID_MALI_1_SEL	103
 #define CLKID_MALI_1		105
 #define CLKID_MALI		106
+#define CLKID_CTS_AMCLK		107
 
 #endif /* __GXBB_CLKC_H */
-- 
2.9.3

[PATCH v1 7/8] dt-bindings: clock: gxbb: expose i2s master clock

[Jerome Brunet]

Expose cts_amclk in the device tree bindings

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.h              | 2 +-
 include/dt-bindings/clock/gxbb-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 3b0665099a1e..742bc3b42565 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -277,7 +277,7 @@
 #define CLKID_MALI_1_DIV	 104
 /* CLKID_MALI_1	*/
 /* CLKID_MALI	*/
-#define CLKID_CTS_AMCLK		  107
+/* CLKID_CTS_AMCLK */
 #define CLKID_CTS_AMCLK_SEL	  108
 #define CLKID_CTS_AMCLK_DIV	  109
 #define CLKID_CTS_MCLK_I958	  110
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 1d4614bc8154..0d231bef92e0 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -43,5 +43,6 @@
 #define CLKID_MALI_1_SEL	103
 #define CLKID_MALI_1		105
 #define CLKID_MALI		106
+#define CLKID_CTS_AMCLK		107
 
 #endif /* __GXBB_CLKC_H */
-- 
2.9.3

[PATCH v1 8/8] dt-bindings: clock: gxbb: expose spdif master clock

[Jerome Brunet]

Expose the spdif master clock and the mux to select the appropriate spdif
clock parent depending on the data source.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.h              | 4 ++--
 include/dt-bindings/clock/gxbb-clkc.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 742bc3b42565..17c6aef033ff 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -280,10 +280,10 @@
 /* CLKID_CTS_AMCLK */
 #define CLKID_CTS_AMCLK_SEL	  108
 #define CLKID_CTS_AMCLK_DIV	  109
-#define CLKID_CTS_MCLK_I958	  110
+/* CLKID_CTS_MCLK_I958 */
 #define CLKID_CTS_MCLK_I958_SEL	  111
 #define CLKID_CTS_MCLK_I958_DIV	  112
-#define CLKID_CTS_I958		  113
+/* CLKID_CTS_I958 */
 
 #define NR_CLKS			  114
 
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 0d231bef92e0..4516bc4253b5 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -44,5 +44,7 @@
 #define CLKID_MALI_1		105
 #define CLKID_MALI		106
 #define CLKID_CTS_AMCLK		107
+#define CLKID_CTS_MCLK_I958	110
+#define CLKID_CTS_I958		113
 
 #endif /* __GXBB_CLKC_H */
-- 
2.9.3

[PATCH v1 8/8] dt-bindings: clock: gxbb: expose spdif master clock

[Jerome Brunet]

Expose the spdif master clock and the mux to select the appropriate spdif
clock parent depending on the data source.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.h              | 4 ++--
 include/dt-bindings/clock/gxbb-clkc.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 742bc3b42565..17c6aef033ff 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -280,10 +280,10 @@
 /* CLKID_CTS_AMCLK */
 #define CLKID_CTS_AMCLK_SEL	  108
 #define CLKID_CTS_AMCLK_DIV	  109
-#define CLKID_CTS_MCLK_I958	  110
+/* CLKID_CTS_MCLK_I958 */
 #define CLKID_CTS_MCLK_I958_SEL	  111
 #define CLKID_CTS_MCLK_I958_DIV	  112
-#define CLKID_CTS_I958		  113
+/* CLKID_CTS_I958 */
 
 #define NR_CLKS			  114
 
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 0d231bef92e0..4516bc4253b5 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -44,5 +44,7 @@
 #define CLKID_MALI_1		105
 #define CLKID_MALI		106
 #define CLKID_CTS_AMCLK		107
+#define CLKID_CTS_MCLK_I958	110
+#define CLKID_CTS_I958		113
 
 #endif /* __GXBB_CLKC_H */
-- 
2.9.3

Re: [PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[Michael Turquette]

Hi Jerome,

Adding Neil Armstong to Cc.

Quoting Jerome Brunet (2017-03-28 07:45:57)
> The patchset is the 2nd round of update to the meson gxbb clock controller
> to add initial audio support. The patchset is based on clk-next.
> 
> There is not much out of the ordinary here (adding new clocks and exposing
> them) except maybe for 2 patches:
> Patch #2: Adds a safety check while registering clocks to protect against
>           holes in clk_hw_onecell_data, if it ever happens. Same thing is
>           done for the meson8b clock controller. 
> Patch #3: Adds a new clock divider driver to implement the necessary
>           policy for the i2s master clock (see patch changelog)
> 
> This patchset has been test on the gxbb p200 and gxl p230.

First off, this series looks fine to me. Please add,

Acked-by: Michael Turquette <mturquette@baylibre.com>

Secondly, it seems the AmLogic clock drivers have mostly calmed down and
things are in the "add new clocks when we need them" phase, which is
nice. Since you and Neil are doing a lot of this work, might I suggest
that you both start collecting patches for the AmLogic/meson clock
drivers begin submitting pull requests to Stephen and myself?

As usual the rules are the same as always: all patches in the PR must
first be posted for review on the list. PRs should correspond to signed
tags. Stephen and I might ignore PRs sent after -rc4, and will
definitely ignore PRs sent after -rc6 since we want some stabilization
time before the merge window. Base your branch on -rc1, not on clk-next.

Also feel free to submit a patch to MAINTAINERS with either one or both
of you maintaining the meson clk stuff, assuming that you're OK to
review all of those patches and collect them into a PR.

Thoughts?

If it sounds good to you then I suggest grabbing the clk-meson branch
from the clk tree and using that as a baseline for your first PR. In the
future you'll just Linus' -rc1, but I have already created a branch for
this cycle. You can apply these 8 patches with my Ack and send a PR by
-rc6 (possibly with other stuff collected from Martin, etc).

Thanks,
Mike

> 
> Jerome Brunet (8):
>   dt-bindings: clock: gxbb: expose spdif clock gates
>   clk: meson: gxbb: protect against holes in the onecell_data array
>   clk: meson: add audio clock divider support
>   clk: meson: gxbb: add cts_amclk
>   clk: meson: gxbb: add cts_mclk_i958
>   clk: meson: gxbb: add cts_i958 clock
>   dt-bindings: clock: gxbb: expose i2s master clock
>   dt-bindings: clock: gxbb: expose spdif master clock
> 
>  drivers/clk/meson/Makefile            |   2 +-
>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/clkc.h              |  10 +++
>  drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++++++
>  drivers/clk/meson/gxbb.h              |  13 ++-
>  include/dt-bindings/clock/gxbb-clkc.h |   5 ++
>  6 files changed, 319 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
> 
> -- 
> 2.9.3
> 

[PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[Michael Turquette]

Hi Jerome,

Adding Neil Armstong to Cc.

Quoting Jerome Brunet (2017-03-28 07:45:57)
> The patchset is the 2nd round of update to the meson gxbb clock controller
> to add initial audio support. The patchset is based on clk-next.
> 
> There is not much out of the ordinary here (adding new clocks and exposing
> them) except maybe for 2 patches:
> Patch #2: Adds a safety check while registering clocks to protect against
>           holes in clk_hw_onecell_data, if it ever happens. Same thing is
>           done for the meson8b clock controller. 
> Patch #3: Adds a new clock divider driver to implement the necessary
>           policy for the i2s master clock (see patch changelog)
> 
> This patchset has been test on the gxbb p200 and gxl p230.

First off, this series looks fine to me. Please add,

Acked-by: Michael Turquette <mturquette@baylibre.com>

Secondly, it seems the AmLogic clock drivers have mostly calmed down and
things are in the "add new clocks when we need them" phase, which is
nice. Since you and Neil are doing a lot of this work, might I suggest
that you both start collecting patches for the AmLogic/meson clock
drivers begin submitting pull requests to Stephen and myself?

As usual the rules are the same as always: all patches in the PR must
first be posted for review on the list. PRs should correspond to signed
tags. Stephen and I might ignore PRs sent after -rc4, and will
definitely ignore PRs sent after -rc6 since we want some stabilization
time before the merge window. Base your branch on -rc1, not on clk-next.

Also feel free to submit a patch to MAINTAINERS with either one or both
of you maintaining the meson clk stuff, assuming that you're OK to
review all of those patches and collect them into a PR.

Thoughts?

If it sounds good to you then I suggest grabbing the clk-meson branch
from the clk tree and using that as a baseline for your first PR. In the
future you'll just Linus' -rc1, but I have already created a branch for
this cycle. You can apply these 8 patches with my Ack and send a PR by
-rc6 (possibly with other stuff collected from Martin, etc).

Thanks,
Mike

> 
> Jerome Brunet (8):
>   dt-bindings: clock: gxbb: expose spdif clock gates
>   clk: meson: gxbb: protect against holes in the onecell_data array
>   clk: meson: add audio clock divider support
>   clk: meson: gxbb: add cts_amclk
>   clk: meson: gxbb: add cts_mclk_i958
>   clk: meson: gxbb: add cts_i958 clock
>   dt-bindings: clock: gxbb: expose i2s master clock
>   dt-bindings: clock: gxbb: expose spdif master clock
> 
>  drivers/clk/meson/Makefile            |   2 +-
>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/clkc.h              |  10 +++
>  drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++++++
>  drivers/clk/meson/gxbb.h              |  13 ++-
>  include/dt-bindings/clock/gxbb-clkc.h |   5 ++
>  6 files changed, 319 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
> 
> -- 
> 2.9.3
> 

Re: [PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[Michael Turquette]

Hi Jerome,

Adding Neil Armstong to Cc.

Quoting Jerome Brunet (2017-03-28 07:45:57)
> The patchset is the 2nd round of update to the meson gxbb clock controller
> to add initial audio support. The patchset is based on clk-next.
> =

> There is not much out of the ordinary here (adding new clocks and exposing
> them) except maybe for 2 patches:
> Patch #2: Adds a safety check while registering clocks to protect against
>           holes in clk_hw_onecell_data, if it ever happens. Same thing is
>           done for the meson8b clock controller. =

> Patch #3: Adds a new clock divider driver to implement the necessary
>           policy for the i2s master clock (see patch changelog)
> =

> This patchset has been test on the gxbb p200 and gxl p230.

First off, this series looks fine to me. Please add,

Acked-by: Michael Turquette <mturquette@baylibre.com>

Secondly, it seems the AmLogic clock drivers have mostly calmed down and
things are in the "add new clocks when we need them" phase, which is
nice. Since you and Neil are doing a lot of this work, might I suggest
that you both start collecting patches for the AmLogic/meson clock
drivers begin submitting pull requests to Stephen and myself?

As usual the rules are the same as always: all patches in the PR must
first be posted for review on the list. PRs should correspond to signed
tags. Stephen and I might ignore PRs sent after -rc4, and will
definitely ignore PRs sent after -rc6 since we want some stabilization
time before the merge window. Base your branch on -rc1, not on clk-next.

Also feel free to submit a patch to MAINTAINERS with either one or both
of you maintaining the meson clk stuff, assuming that you're OK to
review all of those patches and collect them into a PR.

Thoughts?

If it sounds good to you then I suggest grabbing the clk-meson branch
from the clk tree and using that as a baseline for your first PR. In the
future you'll just Linus' -rc1, but I have already created a branch for
this cycle. You can apply these 8 patches with my Ack and send a PR by
-rc6 (possibly with other stuff collected from Martin, etc).

Thanks,
Mike

> =

> Jerome Brunet (8):
>   dt-bindings: clock: gxbb: expose spdif clock gates
>   clk: meson: gxbb: protect against holes in the onecell_data array
>   clk: meson: add audio clock divider support
>   clk: meson: gxbb: add cts_amclk
>   clk: meson: gxbb: add cts_mclk_i958
>   clk: meson: gxbb: add cts_i958 clock
>   dt-bindings: clock: gxbb: expose i2s master clock
>   dt-bindings: clock: gxbb: expose spdif master clock
> =

>  drivers/clk/meson/Makefile            |   2 +-
>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++=
++++++
>  drivers/clk/meson/clkc.h              |  10 +++
>  drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++=
++++
>  drivers/clk/meson/gxbb.h              |  13 ++-
>  include/dt-bindings/clock/gxbb-clkc.h |   5 ++
>  6 files changed, 319 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
> =

> -- =

> 2.9.3
>=20

Re: [PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[Michael Turquette]

Hi Jerome,

Adding Neil Armstong to Cc.

Quoting Jerome Brunet (2017-03-28 07:45:57)
> The patchset is the 2nd round of update to the meson gxbb clock controller
> to add initial audio support. The patchset is based on clk-next.
> 
> There is not much out of the ordinary here (adding new clocks and exposing
> them) except maybe for 2 patches:
> Patch #2: Adds a safety check while registering clocks to protect against
>           holes in clk_hw_onecell_data, if it ever happens. Same thing is
>           done for the meson8b clock controller. 
> Patch #3: Adds a new clock divider driver to implement the necessary
>           policy for the i2s master clock (see patch changelog)
> 
> This patchset has been test on the gxbb p200 and gxl p230.

First off, this series looks fine to me. Please add,

Acked-by: Michael Turquette <mturquette@baylibre.com>

Secondly, it seems the AmLogic clock drivers have mostly calmed down and
things are in the "add new clocks when we need them" phase, which is
nice. Since you and Neil are doing a lot of this work, might I suggest
that you both start collecting patches for the AmLogic/meson clock
drivers begin submitting pull requests to Stephen and myself?

As usual the rules are the same as always: all patches in the PR must
first be posted for review on the list. PRs should correspond to signed
tags. Stephen and I might ignore PRs sent after -rc4, and will
definitely ignore PRs sent after -rc6 since we want some stabilization
time before the merge window. Base your branch on -rc1, not on clk-next.

Also feel free to submit a patch to MAINTAINERS with either one or both
of you maintaining the meson clk stuff, assuming that you're OK to
review all of those patches and collect them into a PR.

Thoughts?

If it sounds good to you then I suggest grabbing the clk-meson branch
from the clk tree and using that as a baseline for your first PR. In the
future you'll just Linus' -rc1, but I have already created a branch for
this cycle. You can apply these 8 patches with my Ack and send a PR by
-rc6 (possibly with other stuff collected from Martin, etc).

Thanks,
Mike

> 
> Jerome Brunet (8):
>   dt-bindings: clock: gxbb: expose spdif clock gates
>   clk: meson: gxbb: protect against holes in the onecell_data array
>   clk: meson: add audio clock divider support
>   clk: meson: gxbb: add cts_amclk
>   clk: meson: gxbb: add cts_mclk_i958
>   clk: meson: gxbb: add cts_i958 clock
>   dt-bindings: clock: gxbb: expose i2s master clock
>   dt-bindings: clock: gxbb: expose spdif master clock
> 
>  drivers/clk/meson/Makefile            |   2 +-
>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/clkc.h              |  10 +++
>  drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++++++
>  drivers/clk/meson/gxbb.h              |  13 ++-
>  include/dt-bindings/clock/gxbb-clkc.h |   5 ++
>  6 files changed, 319 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
> 
> -- 
> 2.9.3
> 

Re: [PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[Neil Armstrong]

On 03/29/2017 10:42 PM, Michael Turquette wrote:
> Hi Jerome,
> 
> Adding Neil Armstong to Cc.
> 
> Quoting Jerome Brunet (2017-03-28 07:45:57)
>> The patchset is the 2nd round of update to the meson gxbb clock controller
>> to add initial audio support. The patchset is based on clk-next.
>>
>> There is not much out of the ordinary here (adding new clocks and exposing
>> them) except maybe for 2 patches:
>> Patch #2: Adds a safety check while registering clocks to protect against
>>           holes in clk_hw_onecell_data, if it ever happens. Same thing is
>>           done for the meson8b clock controller. 
>> Patch #3: Adds a new clock divider driver to implement the necessary
>>           policy for the i2s master clock (see patch changelog)
>>
>> This patchset has been test on the gxbb p200 and gxl p230.
> 
> First off, this series looks fine to me. Please add,
> 
> Acked-by: Michael Turquette <mturquette@baylibre.com>
> 
> Secondly, it seems the AmLogic clock drivers have mostly calmed down and
> things are in the "add new clocks when we need them" phase, which is
> nice. Since you and Neil are doing a lot of this work, might I suggest
> that you both start collecting patches for the AmLogic/meson clock
> drivers begin submitting pull requests to Stephen and myself?
> 
> As usual the rules are the same as always: all patches in the PR must
> first be posted for review on the list. PRs should correspond to signed
> tags. Stephen and I might ignore PRs sent after -rc4, and will
> definitely ignore PRs sent after -rc6 since we want some stabilization
> time before the merge window. Base your branch on -rc1, not on clk-next.
> 
> Also feel free to submit a patch to MAINTAINERS with either one or both
> of you maintaining the meson clk stuff, assuming that you're OK to
> review all of those patches and collect them into a PR.
> 
> Thoughts?

Thanks Mike, I'll be glad to co-maintain this with jerome !

Neil

> 
> If it sounds good to you then I suggest grabbing the clk-meson branch
> from the clk tree and using that as a baseline for your first PR. In the
> future you'll just Linus' -rc1, but I have already created a branch for
> this cycle. You can apply these 8 patches with my Ack and send a PR by
> -rc6 (possibly with other stuff collected from Martin, etc).

Acked !

> 
> Thanks,
> Mike
> 
>>
>> Jerome Brunet (8):
>>   dt-bindings: clock: gxbb: expose spdif clock gates
>>   clk: meson: gxbb: protect against holes in the onecell_data array
>>   clk: meson: add audio clock divider support
>>   clk: meson: gxbb: add cts_amclk
>>   clk: meson: gxbb: add cts_mclk_i958
>>   clk: meson: gxbb: add cts_i958 clock
>>   dt-bindings: clock: gxbb: expose i2s master clock
>>   dt-bindings: clock: gxbb: expose spdif master clock
>>
>>  drivers/clk/meson/Makefile            |   2 +-
>>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/clkc.h              |  10 +++
>>  drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/gxbb.h              |  13 ++-
>>  include/dt-bindings/clock/gxbb-clkc.h |   5 ++
>>  6 files changed, 319 insertions(+), 4 deletions(-)
>>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
>>
>> -- 
>> 2.9.3
>>

[PATCH v1 0/8] clk: meson: gxbb: more clock controller update for audio support

[Neil Armstrong]

On 03/29/2017 10:42 PM, Michael Turquette wrote:
> Hi Jerome,
> 
> Adding Neil Armstong to Cc.
> 
> Quoting Jerome Brunet (2017-03-28 07:45:57)
>> The patchset is the 2nd round of update to the meson gxbb clock controller
>> to add initial audio support. The patchset is based on clk-next.
>>
>> There is not much out of the ordinary here (adding new clocks and exposing
>> them) except maybe for 2 patches:
>> Patch #2: Adds a safety check while registering clocks to protect against
>>           holes in clk_hw_onecell_data, if it ever happens. Same thing is
>>           done for the meson8b clock controller. 
>> Patch #3: Adds a new clock divider driver to implement the necessary
>>           policy for the i2s master clock (see patch changelog)
>>
>> This patchset has been test on the gxbb p200 and gxl p230.
> 
> First off, this series looks fine to me. Please add,
> 
> Acked-by: Michael Turquette <mturquette@baylibre.com>
> 
> Secondly, it seems the AmLogic clock drivers have mostly calmed down and
> things are in the "add new clocks when we need them" phase, which is
> nice. Since you and Neil are doing a lot of this work, might I suggest
> that you both start collecting patches for the AmLogic/meson clock
> drivers begin submitting pull requests to Stephen and myself?
> 
> As usual the rules are the same as always: all patches in the PR must
> first be posted for review on the list. PRs should correspond to signed
> tags. Stephen and I might ignore PRs sent after -rc4, and will
> definitely ignore PRs sent after -rc6 since we want some stabilization
> time before the merge window. Base your branch on -rc1, not on clk-next.
> 
> Also feel free to submit a patch to MAINTAINERS with either one or both
> of you maintaining the meson clk stuff, assuming that you're OK to
> review all of those patches and collect them into a PR.
> 
> Thoughts?

Thanks Mike, I'll be glad to co-maintain this with jerome !

Neil

> 
> If it sounds good to you then I suggest grabbing the clk-meson branch
> from the clk tree and using that as a baseline for your first PR. In the
> future you'll just Linus' -rc1, but I have already created a branch for
> this cycle. You can apply these 8 patches with my Ack and send a PR by
> -rc6 (possibly with other stuff collected from Martin, etc).

Acked !

> 
> Thanks,
> Mike
> 
>>
>> Jerome Brunet (8):
>>   dt-bindings: clock: gxbb: expose spdif clock gates
>>   clk: meson: gxbb: protect against holes in the onecell_data array
>>   clk: meson: add audio clock divider support
>>   clk: meson: gxbb: add cts_amclk
>>   clk: meson: gxbb: add cts_mclk_i958
>>   clk: meson: gxbb: add cts_i958 clock
>>   dt-bindings: clock: gxbb: expose i2s master clock
>>   dt-bindings: clock: gxbb: expose spdif master clock
>>
>>  drivers/clk/meson/Makefile            |   2 +-
>>  drivers/clk/meson/clk-audio-divider.c | 149 ++++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/clkc.h              |  10 +++
>>  drivers/clk/meson/gxbb.c              | 144 ++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/gxbb.h              |  13 ++-
>>  include/dt-bindings/clock/gxbb-clkc.h |   5 ++
>>  6 files changed, 319 insertions(+), 4 deletions(-)
>>  create mode 100644 drivers/clk/meson/clk-audio-divider.c
>>
>> -- 
>> 2.9.3
>>