[PATCH 1/2] eal/x86: use cpuid builtin

[PATCH 1/2] eal/x86: use cpuid builtin

[Sergio Gonzalez Monroy]

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c | 41 +++++----------------------
 1 file changed, 7 insertions(+), 34 deletions(-)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 0138257..6760e33 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -36,6 +36,7 @@
 #include <stdio.h>
 #include <errno.h>
 #include <stdint.h>
+#include <cpuid.h>
 
 enum cpu_register_t {
 	RTE_REG_EAX = 0,
@@ -156,38 +157,12 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
 };
 
-/*
- * Execute CPUID instruction and get contents of a specific register
- *
- * This function, when compiled with GCC, will generate architecture-neutral
- * code, as per GCC manual.
- */
-static void
-rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
-{
-#if defined(__i386__) && defined(__PIC__)
-	/* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
-	asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
-		 : "=r" (out[RTE_REG_EBX]),
-		   "=a" (out[RTE_REG_EAX]),
-		   "=c" (out[RTE_REG_ECX]),
-		   "=d" (out[RTE_REG_EDX])
-		 : "a" (leaf), "c" (subleaf));
-#else
-	asm volatile("cpuid"
-		 : "=a" (out[RTE_REG_EAX]),
-		   "=b" (out[RTE_REG_EBX]),
-		   "=c" (out[RTE_REG_ECX]),
-		   "=d" (out[RTE_REG_EDX])
-		 : "a" (leaf), "c" (subleaf));
-#endif
-}
-
 int
 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
 {
 	const struct feature_entry *feat;
 	cpuid_registers_t regs;
+	int ret;
 
 	if (feature >= RTE_CPUFLAG_NUMFLAGS)
 		/* Flag does not match anything in the feature tables */
@@ -199,13 +174,11 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
 		/* This entry in the table wasn't filled out! */
 		return -EFAULT;
 
-	rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
-	if (((regs[RTE_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
-	      regs[RTE_REG_EAX] < feat->leaf)
-		return 0;
-
-	/* get the cpuid leaf containing the desired feature */
-	rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
+	ret = __get_cpuid_count(feat->leaf, feat->subleaf,
+			&regs[RTE_REG_EAX], &regs[RTE_REG_EBX],
+			&regs[RTE_REG_ECX], &regs[RTE_REG_EDX]);
+	if (!ret)
+		return ret;
 
 	/* check if the feature is enabled */
 	return (regs[feat->reg] >> feat->bit) & 1;
-- 
2.9.5

[PATCH 2/2] eal/x86: implement x86 specific tsc hz

[Sergio Gonzalez Monroy]

First, try to use CPUID Time Stamp Counter and Nominal Core Crystal
Clock Information Leaf to determine the tsc hz on platforms that
supports it (does not require priviledge user).

If the CPUID leaf is not available, then try to determine the tsc hz by
reading the MSR 0xCE (requires priviledge user).

Default to the DPDK tsc hz estimation if both methods fail.

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cycles.c        | 138 +++++++++++++++++++++
 .../common/include/arch/x86/rte_cycles.h           |   7 +-
 lib/librte_eal/linuxapp/eal/Makefile               |   1 +
 3 files changed, 141 insertions(+), 5 deletions(-)
 create mode 100644 lib/librte_eal/common/arch/x86/rte_cycles.c

diff --git a/lib/librte_eal/common/arch/x86/rte_cycles.c b/lib/librte_eal/common/arch/x86/rte_cycles.c
new file mode 100644
index 0000000..8e24d4b
--- /dev/null
+++ b/lib/librte_eal/common/arch/x86/rte_cycles.c
@@ -0,0 +1,138 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of Intel Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <fcntl.h>
+#include <unistd.h>
+#include <cpuid.h>
+#include <rte_cycles.h>
+
+static unsigned int
+rte_cpu_get_model(uint32_t fam_mod_step)
+{
+	uint32_t family, model, ext_model;
+
+	family = (fam_mod_step >> 8) & 0xf;
+	model = (fam_mod_step >> 4) & 0xf;
+
+	if (family == 6 || family == 15) {
+		ext_model = (fam_mod_step >> 16) & 0xf;
+		model += (ext_model << 4);
+	}
+
+	return model;
+}
+
+static int32_t
+rdmsr(int msr, uint64_t *val)
+{
+	int fd;
+	int ret = 0;
+
+	fd = open("/dev/cpu/0/msr", O_RDONLY);
+	if (fd < 0)
+		return fd;
+
+	ret = pread(fd, val, sizeof(uint64_t), msr);
+
+	close(fd);
+
+	return ret;
+}
+
+static uint32_t
+check_model_wsm_nhm(uint8_t model)
+{
+	switch (model) {
+	/* Westmere */
+	case 0x25:
+	case 0x2C:
+	case 0x2F:
+	/* Nehalem */
+	case 0x1E:
+	case 0x1F:
+	case 0x1A:
+	case 0x2E:
+		return 1;
+	}
+
+	return 0;
+}
+
+static uint32_t
+check_model_gdm_dnv(uint8_t model)
+{
+	switch (model) {
+	/* Goldmont */
+	case 0x5C:
+	/* Denverton */
+	case 0x5F:
+		return 1;
+	}
+
+	return 0;
+}
+
+uint64_t
+rte_rdtsc_arch_hz(void)
+{
+	uint64_t tsc_hz = 0;
+	uint32_t a, b, c, d;
+	int32_t ret;
+	uint8_t mult, model;
+
+	/*
+	 * Time Stamp Counter and Nominal Core Crystal Clock
+	 * Information Leaf
+	 */
+	ret = __get_cpuid(0x15, &a, &b, &c, &d);
+	if (ret)
+		/* EBX : TSC/Crystal ratio, ECX : Crystal Hz */
+		if (b && c)
+			return c * (b / a);
+
+	__cpuid(0x1, a, b, c, d);
+	model = rte_cpu_get_model(a);
+
+	if (check_model_wsm_nhm(model))
+		mult = 133;
+	else if ((c & bit_AVX) || check_model_gdm_dnv(model))
+		mult = 100;
+	else
+		return 0;
+
+	ret = rdmsr(0xCE, &tsc_hz);
+	if (!(ret < 0))
+		return ((tsc_hz >> 8) & 0xff) * mult * 1E6;
+
+	return 0;
+}
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cycles.h b/lib/librte_eal/common/include/arch/x86/rte_cycles.h
index e2661e2..0db89dc 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cycles.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cycles.h
@@ -84,11 +84,8 @@ rte_rdtsc(void)
  *   The number of rdtsc cycles in one second. Return zero if the architecture
  *   support is not available.
  */
-static inline uint64_t
-rte_rdtsc_arch_hz(void)
-{
-	return 0;
-}
+uint64_t
+rte_rdtsc_arch_hz(void);
 
 static inline uint64_t
 rte_rdtsc_precise(void)
diff --git a/lib/librte_eal/linuxapp/eal/Makefile b/lib/librte_eal/linuxapp/eal/Makefile
index 90bca4d..9d44828 100644
--- a/lib/librte_eal/linuxapp/eal/Makefile
+++ b/lib/librte_eal/linuxapp/eal/Makefile
@@ -104,6 +104,7 @@ SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += rte_service.c
 # from arch dir
 SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += rte_cpuflags.c
 SRCS-$(CONFIG_RTE_ARCH_X86) += rte_spinlock.c
+SRCS-$(CONFIG_RTE_ARCH_X86) += rte_cycles.c
 
 CFLAGS_eal_common_cpuflags.o := $(CPUFLAGS_LIST)
 
-- 
2.9.5

Re: [PATCH 2/2] eal/x86: implement x86 specific tsc hz

[Bruce Richardson]

On Wed, Aug 23, 2017 at 01:42:41PM +0100, Sergio Gonzalez Monroy wrote:
> First, try to use CPUID Time Stamp Counter and Nominal Core Crystal
> Clock Information Leaf to determine the tsc hz on platforms that
> supports it (does not require priviledge user).
> 
> If the CPUID leaf is not available, then try to determine the tsc hz by
> reading the MSR 0xCE (requires priviledge user).
> 
> Default to the DPDK tsc hz estimation if both methods fail.
> 
> Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
> ---
This patch depends on Jerin's previous set for getting the exact TSC
frequency on different platforms, right?

Re: [PATCH 2/2] eal/x86: implement x86 specific tsc hz

[Sergio Gonzalez Monroy]

On 23/08/2017 14:17, Bruce Richardson wrote:
> On Wed, Aug 23, 2017 at 01:42:41PM +0100, Sergio Gonzalez Monroy wrote:
>> First, try to use CPUID Time Stamp Counter and Nominal Core Crystal
>> Clock Information Leaf to determine the tsc hz on platforms that
>> supports it (does not require priviledge user).
>>
>> If the CPUID leaf is not available, then try to determine the tsc hz by
>> reading the MSR 0xCE (requires priviledge user).
>>
>> Default to the DPDK tsc hz estimation if both methods fail.
>>
>> Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
>> ---
> This patch depends on Jerin's previous set for getting the exact TSC
> frequency on different platforms, right?

It does, I forgot to mention it.

I'll send them apart as these patches are not really dependent.

Thanks,
Sergio

Re: [PATCH 2/2] eal/x86: implement x86 specific tsc hz

[Bruce Richardson]

On Wed, Aug 23, 2017 at 02:57:30PM +0100, Sergio Gonzalez Monroy wrote:
> On 23/08/2017 14:17, Bruce Richardson wrote:
> > On Wed, Aug 23, 2017 at 01:42:41PM +0100, Sergio Gonzalez Monroy wrote:
> > > First, try to use CPUID Time Stamp Counter and Nominal Core Crystal
> > > Clock Information Leaf to determine the tsc hz on platforms that
> > > supports it (does not require priviledge user).
> > > 
> > > If the CPUID leaf is not available, then try to determine the tsc hz by
> > > reading the MSR 0xCE (requires priviledge user).
> > > 
> > > Default to the DPDK tsc hz estimation if both methods fail.
> > > 
> > > Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
> > > ---
> > This patch depends on Jerin's previous set for getting the exact TSC
> > frequency on different platforms, right?
> 
> It does, I forgot to mention it.
> 
> I'll send them apart as these patches are not really dependent.
>
Ok, the patches look good to me otherwise, so include my ack if
re-sending.

Series-Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Re: [PATCH 1/2] eal/x86: use cpuid builtin

[Thomas Monjalon]

Please could you explain why the asm code was used?
Are you sure this builtin is implemented everywhere?

Re: [PATCH 1/2] eal/x86: use cpuid builtin

[Sergio Gonzalez Monroy]

On 23/08/2017 21:49, Thomas Monjalon wrote:
> Please could you explain why the asm code was used?

I guess we were not aware that there was a builtin for it.

> Are you sure this builtin is implemented everywhere?
>

Actually the builtin used in this patch is not supported in most CLANG 
version (just recently merged upstream),
so I have reworked the patch to use builtin supported in both GCC and 
CLANG 3.4+.

Thanks,
Sergio