* [Qemu-devel] [RFC for-2.13 01/12] target/ppc: Standardize instance_init and realize function names
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-27 7:12 ` Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 02/12] target/ppc: Simplify cpu valid check in ppc_cpu_realize David Gibson
` (10 subsequent siblings)
11 siblings, 1 reply; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
Because of the various hooks called some variant on "init" - and the rather
greater number that used to exist, I'm always wondering when a function
called simply "*_init" or "*_initfn" will be called.
To make it easier on myself, and maybe others, rename the instance_init
hooks for ppc cpus to *_instance_init(). While we're at it rename the
realize time hooks to *_realize() (from *_realizefn()) which seems to be
the more common current convention.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate_init.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 391b94b97d..56b80a204a 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9726,7 +9726,7 @@ static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
#endif
}
-static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
+static void ppc_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
PowerPCCPU *cpu = POWERPC_CPU(dev);
@@ -9952,7 +9952,7 @@ unrealize:
cpu_exec_unrealizefn(cs);
}
-static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
+static void ppc_cpu_unrealize(DeviceState *dev, Error **errp)
{
PowerPCCPU *cpu = POWERPC_CPU(dev);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
@@ -10438,7 +10438,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
}
#endif
-static void ppc_cpu_initfn(Object *obj)
+static void ppc_cpu_instance_init(Object *obj)
{
CPUState *cs = CPU(obj);
PowerPCCPU *cpu = POWERPC_CPU(obj);
@@ -10561,9 +10561,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
- device_class_set_parent_realize(dc, ppc_cpu_realizefn,
+ device_class_set_parent_realize(dc, ppc_cpu_realize,
&pcc->parent_realize);
- device_class_set_parent_unrealize(dc, ppc_cpu_unrealizefn,
+ device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
&pcc->parent_unrealize);
pcc->pvr_match = ppc_pvr_match_default;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
@@ -10623,7 +10623,7 @@ static const TypeInfo ppc_cpu_type_info = {
.name = TYPE_POWERPC_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(PowerPCCPU),
- .instance_init = ppc_cpu_initfn,
+ .instance_init = ppc_cpu_instance_init,
.abstract = true,
.class_size = sizeof(PowerPCCPUClass),
.class_init = ppc_cpu_class_init,
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 01/12] target/ppc: Standardize instance_init and realize function names
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 01/12] target/ppc: Standardize instance_init and realize function names David Gibson
@ 2018-03-27 7:12 ` Greg Kurz
0 siblings, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-27 7:12 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:30 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> Because of the various hooks called some variant on "init" - and the rather
> greater number that used to exist, I'm always wondering when a function
> called simply "*_init" or "*_initfn" will be called.
>
> To make it easier on myself, and maybe others, rename the instance_init
> hooks for ppc cpus to *_instance_init(). While we're at it rename the
> realize time hooks to *_realize() (from *_realizefn()) which seems to be
> the more common current convention.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> target/ppc/translate_init.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 391b94b97d..56b80a204a 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -9726,7 +9726,7 @@ static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
> #endif
> }
>
> -static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
> +static void ppc_cpu_realize(DeviceState *dev, Error **errp)
> {
> CPUState *cs = CPU(dev);
> PowerPCCPU *cpu = POWERPC_CPU(dev);
> @@ -9952,7 +9952,7 @@ unrealize:
> cpu_exec_unrealizefn(cs);
> }
>
> -static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
> +static void ppc_cpu_unrealize(DeviceState *dev, Error **errp)
> {
> PowerPCCPU *cpu = POWERPC_CPU(dev);
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> @@ -10438,7 +10438,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
> }
> #endif
>
> -static void ppc_cpu_initfn(Object *obj)
> +static void ppc_cpu_instance_init(Object *obj)
> {
> CPUState *cs = CPU(obj);
> PowerPCCPU *cpu = POWERPC_CPU(obj);
> @@ -10561,9 +10561,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
> CPUClass *cc = CPU_CLASS(oc);
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> - device_class_set_parent_realize(dc, ppc_cpu_realizefn,
> + device_class_set_parent_realize(dc, ppc_cpu_realize,
> &pcc->parent_realize);
> - device_class_set_parent_unrealize(dc, ppc_cpu_unrealizefn,
> + device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
> &pcc->parent_unrealize);
> pcc->pvr_match = ppc_pvr_match_default;
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
> @@ -10623,7 +10623,7 @@ static const TypeInfo ppc_cpu_type_info = {
> .name = TYPE_POWERPC_CPU,
> .parent = TYPE_CPU,
> .instance_size = sizeof(PowerPCCPU),
> - .instance_init = ppc_cpu_initfn,
> + .instance_init = ppc_cpu_instance_init,
> .abstract = true,
> .class_size = sizeof(PowerPCCPUClass),
> .class_init = ppc_cpu_class_init,
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 02/12] target/ppc: Simplify cpu valid check in ppc_cpu_realize
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 01/12] target/ppc: Standardize instance_init and realize function names David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-27 6:36 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
2018-03-27 7:13 ` [Qemu-devel] " Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 03/12] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() David Gibson
` (9 subsequent siblings)
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
The #if isn't necessary, because there's a suitable one inside
ppc_cpu_is_valid(). We've already filtered for suitable cpu models in the
functions that search and register them. So by the time we get to realize
having an invalid one indicates a code error, not a user error, so an
assert() is more appropriate than error_setg().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate_init.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 56b80a204a..2ae718242a 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9749,14 +9749,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
}
}
-#if defined(TARGET_PPCEMB)
- if (!ppc_cpu_is_valid(pcc)) {
- error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
- "Please use qemu-system-ppc or qemu-system-ppc64 instead "
- "or choose another CPU model.");
- goto unrealize;
- }
-#endif
+ assert(ppc_cpu_is_valid(pcc));
create_ppc_opcodes(cpu, &local_err);
if (local_err != NULL) {
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [RFC for-2.13 02/12] target/ppc: Simplify cpu valid check in ppc_cpu_realize
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 02/12] target/ppc: Simplify cpu valid check in ppc_cpu_realize David Gibson
@ 2018-03-27 6:36 ` Thomas Huth
2018-03-27 7:13 ` [Qemu-devel] " Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Thomas Huth @ 2018-03-27 6:36 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: qemu-devel, clg, bharata
On 27.03.2018 06:37, David Gibson wrote:
> The #if isn't necessary, because there's a suitable one inside
> ppc_cpu_is_valid(). We've already filtered for suitable cpu models in the
> functions that search and register them. So by the time we get to realize
> having an invalid one indicates a code error, not a user error, so an
> assert() is more appropriate than error_setg().
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/translate_init.c | 9 +--------
> 1 file changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 56b80a204a..2ae718242a 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -9749,14 +9749,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
> }
> }
>
> -#if defined(TARGET_PPCEMB)
> - if (!ppc_cpu_is_valid(pcc)) {
> - error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
> - "Please use qemu-system-ppc or qemu-system-ppc64 instead "
> - "or choose another CPU model.");
> - goto unrealize;
> - }
> -#endif
> + assert(ppc_cpu_is_valid(pcc));
>
> create_ppc_opcodes(cpu, &local_err);
> if (local_err != NULL) {
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 02/12] target/ppc: Simplify cpu valid check in ppc_cpu_realize
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 02/12] target/ppc: Simplify cpu valid check in ppc_cpu_realize David Gibson
2018-03-27 6:36 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
@ 2018-03-27 7:13 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-27 7:13 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:31 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> The #if isn't necessary, because there's a suitable one inside
> ppc_cpu_is_valid(). We've already filtered for suitable cpu models in the
> functions that search and register them. So by the time we get to realize
> having an invalid one indicates a code error, not a user error, so an
> assert() is more appropriate than error_setg().
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> target/ppc/translate_init.c | 9 +--------
> 1 file changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 56b80a204a..2ae718242a 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -9749,14 +9749,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
> }
> }
>
> -#if defined(TARGET_PPCEMB)
> - if (!ppc_cpu_is_valid(pcc)) {
> - error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
> - "Please use qemu-system-ppc or qemu-system-ppc64 instead "
> - "or choose another CPU model.");
> - goto unrealize;
> - }
> -#endif
> + assert(ppc_cpu_is_valid(pcc));
>
> create_ppc_opcodes(cpu, &local_err);
> if (local_err != NULL) {
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 03/12] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 01/12] target/ppc: Standardize instance_init and realize function names David Gibson
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 02/12] target/ppc: Simplify cpu valid check in ppc_cpu_realize David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-27 7:15 ` Greg Kurz
2018-03-27 8:41 ` Cédric Le Goater
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 04/12] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions David Gibson
` (8 subsequent siblings)
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this
change will make some things simpler later on.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/fdt.c | 5 +++--
hw/ppc/pnv.c | 4 ++--
hw/ppc/spapr.c | 4 ++--
include/hw/ppc/fdt.h | 2 +-
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
index 2ffc5866e4..2721603ffa 100644
--- a/hw/ppc/fdt.c
+++ b/hw/ppc/fdt.c
@@ -13,9 +13,10 @@
#include "hw/ppc/fdt.h"
#if defined(TARGET_PPC64)
-size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
- size_t maxsize)
+size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
+ size_t maxsize)
{
+ CPUPPCState *env = &cpu->env;
size_t maxcells = maxsize / sizeof(uint32_t);
int i, j, count;
uint32_t *p = prop;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 98ee3c607a..5a79b24828 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -209,8 +209,8 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
_FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
}
- page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
- sizeof(page_sizes_prop));
+ page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
+ sizeof(page_sizes_prop));
if (page_sizes_prop_size) {
_FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
page_sizes_prop, page_sizes_prop_size)));
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2c0be8c898..a35bffd524 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -581,8 +581,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
_FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
}
- page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
- sizeof(page_sizes_prop));
+ page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
+ sizeof(page_sizes_prop));
if (page_sizes_prop_size) {
_FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
page_sizes_prop, page_sizes_prop_size)));
diff --git a/include/hw/ppc/fdt.h b/include/hw/ppc/fdt.h
index bd5b0a8c3d..a8cd85069f 100644
--- a/include/hw/ppc/fdt.h
+++ b/include/hw/ppc/fdt.h
@@ -23,7 +23,7 @@
} \
} while (0)
-size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
+size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
size_t maxsize);
#endif /* PPC_FDT_H */
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 03/12] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 03/12] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() David Gibson
@ 2018-03-27 7:15 ` Greg Kurz
2018-03-27 8:41 ` Cédric Le Goater
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-27 7:15 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:32 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this
> change will make some things simpler later on.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> hw/ppc/fdt.c | 5 +++--
> hw/ppc/pnv.c | 4 ++--
> hw/ppc/spapr.c | 4 ++--
> include/hw/ppc/fdt.h | 2 +-
> 4 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
> index 2ffc5866e4..2721603ffa 100644
> --- a/hw/ppc/fdt.c
> +++ b/hw/ppc/fdt.c
> @@ -13,9 +13,10 @@
> #include "hw/ppc/fdt.h"
>
> #if defined(TARGET_PPC64)
> -size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
> - size_t maxsize)
> +size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
> + size_t maxsize)
> {
> + CPUPPCState *env = &cpu->env;
> size_t maxcells = maxsize / sizeof(uint32_t);
> int i, j, count;
> uint32_t *p = prop;
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 98ee3c607a..5a79b24828 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -209,8 +209,8 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
> _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
> }
>
> - page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
> - sizeof(page_sizes_prop));
> + page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
> + sizeof(page_sizes_prop));
> if (page_sizes_prop_size) {
> _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
> page_sizes_prop, page_sizes_prop_size)));
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 2c0be8c898..a35bffd524 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -581,8 +581,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
> _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
> }
>
> - page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
> - sizeof(page_sizes_prop));
> + page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
> + sizeof(page_sizes_prop));
> if (page_sizes_prop_size) {
> _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
> page_sizes_prop, page_sizes_prop_size)));
> diff --git a/include/hw/ppc/fdt.h b/include/hw/ppc/fdt.h
> index bd5b0a8c3d..a8cd85069f 100644
> --- a/include/hw/ppc/fdt.h
> +++ b/include/hw/ppc/fdt.h
> @@ -23,7 +23,7 @@
> } \
> } while (0)
>
> -size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
> +size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
> size_t maxsize);
>
> #endif /* PPC_FDT_H */
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 03/12] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 03/12] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() David Gibson
2018-03-27 7:15 ` Greg Kurz
@ 2018-03-27 8:41 ` Cédric Le Goater
1 sibling, 0 replies; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-27 8:41 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug
Cc: agraf, qemu-devel, benh, bharata, Cédric Le Goater
On 03/27/2018 06:37 AM, David Gibson wrote:
> As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this
> change will make some things simpler later on.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/fdt.c | 5 +++--
> hw/ppc/pnv.c | 4 ++--
> hw/ppc/spapr.c | 4 ++--
> include/hw/ppc/fdt.h | 2 +-
> 4 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
> index 2ffc5866e4..2721603ffa 100644
> --- a/hw/ppc/fdt.c
> +++ b/hw/ppc/fdt.c
> @@ -13,9 +13,10 @@
> #include "hw/ppc/fdt.h"
>
> #if defined(TARGET_PPC64)
> -size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
> - size_t maxsize)
> +size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
> + size_t maxsize)
> {
> + CPUPPCState *env = &cpu->env;
> size_t maxcells = maxsize / sizeof(uint32_t);
> int i, j, count;
> uint32_t *p = prop;
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 98ee3c607a..5a79b24828 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -209,8 +209,8 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
> _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
> }
>
> - page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
> - sizeof(page_sizes_prop));
> + page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
> + sizeof(page_sizes_prop));
> if (page_sizes_prop_size) {
> _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
> page_sizes_prop, page_sizes_prop_size)));
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 2c0be8c898..a35bffd524 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -581,8 +581,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
> _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
> }
>
> - page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
> - sizeof(page_sizes_prop));
> + page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
> + sizeof(page_sizes_prop));
> if (page_sizes_prop_size) {
> _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
> page_sizes_prop, page_sizes_prop_size)));
> diff --git a/include/hw/ppc/fdt.h b/include/hw/ppc/fdt.h
> index bd5b0a8c3d..a8cd85069f 100644
> --- a/include/hw/ppc/fdt.h
> +++ b/include/hw/ppc/fdt.h
> @@ -23,7 +23,7 @@
> } \
> } while (0)
>
> -size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
> +size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
> size_t maxsize);
>
> #endif /* PPC_FDT_H */
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 04/12] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (2 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 03/12] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-27 8:17 ` Greg Kurz
2018-03-27 8:45 ` Cédric Le Goater
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information David Gibson
` (7 subsequent siblings)
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
In most cases we prefer to pass a PowerPCCPU rather than the (embedded)
CPUPPCState.
For ppc_hash64_update_{rmls,vrma}() change to take "cpu" instead of "env".
For ppc_hash64_set_{dsi,isi}() remove the redundant "env" parameter.
In theory this makes more work for the functions, but since "cs", "cpu"
and "env" are related by at most constant offsets, the compiler should be
able to optimize out the difference at effectively zero cost.
helper_*() functions are left alone - since they're more closely tied to
the TCG generated code, passing "env" is still the standard there.
While we're there, fix an incorrect indentation.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/mmu-hash64.c | 35 +++++++++++++++++++----------------
target/ppc/mmu-hash64.h | 4 ++--
target/ppc/translate_init.c | 4 ++--
3 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index c9b72b7429..a87fa7c83f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -633,9 +633,9 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
return 0;
}
-static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
- uint64_t error_code)
+static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
{
+ CPUPPCState *env = &POWERPC_CPU(cs)->env;
bool vpm;
if (msr_ir) {
@@ -659,9 +659,9 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
env->error_code = error_code;
}
-static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
- uint64_t dsisr)
+static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr)
{
+ CPUPPCState *env = &POWERPC_CPU(cs)->env;
bool vpm;
if (msr_dr) {
@@ -741,13 +741,13 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
} else {
/* The access failed, generate the approriate interrupt */
if (rwx == 2) {
- ppc_hash64_set_isi(cs, env, SRR1_PROTFAULT);
+ ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
} else {
int dsisr = DSISR_PROTFAULT;
if (rwx == 1) {
dsisr |= DSISR_ISSTORE;
}
- ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
+ ppc_hash64_set_dsi(cs, eaddr, dsisr);
}
return 1;
}
@@ -783,7 +783,7 @@ skip_slb_search:
/* 3. Check for segment level no-execute violation */
if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
- ppc_hash64_set_isi(cs, env, SRR1_NOEXEC_GUARD);
+ ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
return 1;
}
@@ -791,13 +791,13 @@ skip_slb_search:
ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
if (ptex == -1) {
if (rwx == 2) {
- ppc_hash64_set_isi(cs, env, SRR1_NOPTE);
+ ppc_hash64_set_isi(cs, SRR1_NOPTE);
} else {
int dsisr = DSISR_NOPTE;
if (rwx == 1) {
dsisr |= DSISR_ISSTORE;
}
- ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
+ ppc_hash64_set_dsi(cs, eaddr, dsisr);
}
return 1;
}
@@ -824,7 +824,7 @@ skip_slb_search:
if (PAGE_EXEC & ~amr_prot) {
srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
}
- ppc_hash64_set_isi(cs, env, srr1);
+ ppc_hash64_set_isi(cs, srr1);
} else {
int dsisr = 0;
if (need_prot[rwx] & ~pp_prot) {
@@ -836,7 +836,7 @@ skip_slb_search:
if (need_prot[rwx] & ~amr_prot) {
dsisr |= DSISR_AMR;
}
- ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
+ ppc_hash64_set_dsi(cs, eaddr, dsisr);
}
return 1;
}
@@ -942,8 +942,9 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
}
-void ppc_hash64_update_rmls(CPUPPCState *env)
+void ppc_hash64_update_rmls(PowerPCCPU *cpu)
{
+ CPUPPCState *env = &cpu->env;
uint64_t lpcr = env->spr[SPR_LPCR];
/*
@@ -976,8 +977,9 @@ void ppc_hash64_update_rmls(CPUPPCState *env)
}
}
-void ppc_hash64_update_vrma(CPUPPCState *env)
+void ppc_hash64_update_vrma(PowerPCCPU *cpu)
{
+ CPUPPCState *env = &cpu->env;
const struct ppc_one_seg_page_size *sps = NULL;
target_ulong esid, vsid, lpcr;
ppc_slb_t *slb = &env->vrma_slb;
@@ -1002,7 +1004,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env)
vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
esid = SLB_ESID_V;
- for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
if (!sps1->page_shift) {
@@ -1028,6 +1030,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env)
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
uint64_t lpcr = 0;
/* Filter out bits */
@@ -1089,6 +1092,6 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
;
}
env->spr[SPR_LPCR] = lpcr;
- ppc_hash64_update_rmls(env);
- ppc_hash64_update_vrma(env);
+ ppc_hash64_update_rmls(cpu);
+ ppc_hash64_update_vrma(cpu);
}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index d297b97d37..95a8c330d6 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -17,8 +17,8 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
target_ulong pte0, target_ulong pte1);
unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
uint64_t pte0, uint64_t pte1);
-void ppc_hash64_update_vrma(CPUPPCState *env);
-void ppc_hash64_update_rmls(CPUPPCState *env);
+void ppc_hash64_update_vrma(PowerPCCPU *cpu);
+void ppc_hash64_update_rmls(PowerPCCPU *cpu);
#endif
/*
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 2ae718242a..29bd6f3654 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8975,8 +8975,8 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
/* Update some env bits based on new LPCR value */
- ppc_hash64_update_rmls(env);
- ppc_hash64_update_vrma(env);
+ ppc_hash64_update_rmls(cpu);
+ ppc_hash64_update_vrma(cpu);
/* Tell KVM that we're in PAPR mode */
if (kvm_enabled()) {
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 04/12] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 04/12] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions David Gibson
@ 2018-03-27 8:17 ` Greg Kurz
2018-03-27 8:45 ` Cédric Le Goater
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-27 8:17 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:33 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> In most cases we prefer to pass a PowerPCCPU rather than the (embedded)
> CPUPPCState.
>
> For ppc_hash64_update_{rmls,vrma}() change to take "cpu" instead of "env".
> For ppc_hash64_set_{dsi,isi}() remove the redundant "env" parameter.
>
> In theory this makes more work for the functions, but since "cs", "cpu"
> and "env" are related by at most constant offsets, the compiler should be
> able to optimize out the difference at effectively zero cost.
>
> helper_*() functions are left alone - since they're more closely tied to
> the TCG generated code, passing "env" is still the standard there.
>
> While we're there, fix an incorrect indentation.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> target/ppc/mmu-hash64.c | 35 +++++++++++++++++++----------------
> target/ppc/mmu-hash64.h | 4 ++--
> target/ppc/translate_init.c | 4 ++--
> 3 files changed, 23 insertions(+), 20 deletions(-)
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index c9b72b7429..a87fa7c83f 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -633,9 +633,9 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> return 0;
> }
>
> -static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
> - uint64_t error_code)
> +static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
> {
> + CPUPPCState *env = &POWERPC_CPU(cs)->env;
> bool vpm;
>
> if (msr_ir) {
> @@ -659,9 +659,9 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
> env->error_code = error_code;
> }
>
> -static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
> - uint64_t dsisr)
> +static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr)
> {
> + CPUPPCState *env = &POWERPC_CPU(cs)->env;
> bool vpm;
>
> if (msr_dr) {
> @@ -741,13 +741,13 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
> } else {
> /* The access failed, generate the approriate interrupt */
> if (rwx == 2) {
> - ppc_hash64_set_isi(cs, env, SRR1_PROTFAULT);
> + ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
> } else {
> int dsisr = DSISR_PROTFAULT;
> if (rwx == 1) {
> dsisr |= DSISR_ISSTORE;
> }
> - ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
> + ppc_hash64_set_dsi(cs, eaddr, dsisr);
> }
> return 1;
> }
> @@ -783,7 +783,7 @@ skip_slb_search:
>
> /* 3. Check for segment level no-execute violation */
> if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
> - ppc_hash64_set_isi(cs, env, SRR1_NOEXEC_GUARD);
> + ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
> return 1;
> }
>
> @@ -791,13 +791,13 @@ skip_slb_search:
> ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
> if (ptex == -1) {
> if (rwx == 2) {
> - ppc_hash64_set_isi(cs, env, SRR1_NOPTE);
> + ppc_hash64_set_isi(cs, SRR1_NOPTE);
> } else {
> int dsisr = DSISR_NOPTE;
> if (rwx == 1) {
> dsisr |= DSISR_ISSTORE;
> }
> - ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
> + ppc_hash64_set_dsi(cs, eaddr, dsisr);
> }
> return 1;
> }
> @@ -824,7 +824,7 @@ skip_slb_search:
> if (PAGE_EXEC & ~amr_prot) {
> srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
> }
> - ppc_hash64_set_isi(cs, env, srr1);
> + ppc_hash64_set_isi(cs, srr1);
> } else {
> int dsisr = 0;
> if (need_prot[rwx] & ~pp_prot) {
> @@ -836,7 +836,7 @@ skip_slb_search:
> if (need_prot[rwx] & ~amr_prot) {
> dsisr |= DSISR_AMR;
> }
> - ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
> + ppc_hash64_set_dsi(cs, eaddr, dsisr);
> }
> return 1;
> }
> @@ -942,8 +942,9 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
> cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
> }
>
> -void ppc_hash64_update_rmls(CPUPPCState *env)
> +void ppc_hash64_update_rmls(PowerPCCPU *cpu)
> {
> + CPUPPCState *env = &cpu->env;
> uint64_t lpcr = env->spr[SPR_LPCR];
>
> /*
> @@ -976,8 +977,9 @@ void ppc_hash64_update_rmls(CPUPPCState *env)
> }
> }
>
> -void ppc_hash64_update_vrma(CPUPPCState *env)
> +void ppc_hash64_update_vrma(PowerPCCPU *cpu)
> {
> + CPUPPCState *env = &cpu->env;
> const struct ppc_one_seg_page_size *sps = NULL;
> target_ulong esid, vsid, lpcr;
> ppc_slb_t *slb = &env->vrma_slb;
> @@ -1002,7 +1004,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env)
> vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
> esid = SLB_ESID_V;
>
> - for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> + for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
>
> if (!sps1->page_shift) {
> @@ -1028,6 +1030,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env)
>
> void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint64_t lpcr = 0;
>
> /* Filter out bits */
> @@ -1089,6 +1092,6 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> ;
> }
> env->spr[SPR_LPCR] = lpcr;
> - ppc_hash64_update_rmls(env);
> - ppc_hash64_update_vrma(env);
> + ppc_hash64_update_rmls(cpu);
> + ppc_hash64_update_vrma(cpu);
> }
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index d297b97d37..95a8c330d6 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -17,8 +17,8 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
> target_ulong pte0, target_ulong pte1);
> unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> uint64_t pte0, uint64_t pte1);
> -void ppc_hash64_update_vrma(CPUPPCState *env);
> -void ppc_hash64_update_rmls(CPUPPCState *env);
> +void ppc_hash64_update_vrma(PowerPCCPU *cpu);
> +void ppc_hash64_update_rmls(PowerPCCPU *cpu);
> #endif
>
> /*
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 2ae718242a..29bd6f3654 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8975,8 +8975,8 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
> env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
>
> /* Update some env bits based on new LPCR value */
> - ppc_hash64_update_rmls(env);
> - ppc_hash64_update_vrma(env);
> + ppc_hash64_update_rmls(cpu);
> + ppc_hash64_update_vrma(cpu);
>
> /* Tell KVM that we're in PAPR mode */
> if (kvm_enabled()) {
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 04/12] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 04/12] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions David Gibson
2018-03-27 8:17 ` Greg Kurz
@ 2018-03-27 8:45 ` Cédric Le Goater
1 sibling, 0 replies; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-27 8:45 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> In most cases we prefer to pass a PowerPCCPU rather than the (embedded)
> CPUPPCState.
>
> For ppc_hash64_update_{rmls,vrma}() change to take "cpu" instead of "env".
> For ppc_hash64_set_{dsi,isi}() remove the redundant "env" parameter.
>
> In theory this makes more work for the functions, but since "cs", "cpu"
> and "env" are related by at most constant offsets, the compiler should be
> able to optimize out the difference at effectively zero cost.
>
> helper_*() functions are left alone - since they're more closely tied to
> the TCG generated code, passing "env" is still the standard there.
>
> While we're there, fix an incorrect indentation.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/mmu-hash64.c | 35 +++++++++++++++++++----------------
> target/ppc/mmu-hash64.h | 4 ++--
> target/ppc/translate_init.c | 4 ++--
> 3 files changed, 23 insertions(+), 20 deletions(-)
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index c9b72b7429..a87fa7c83f 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -633,9 +633,9 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> return 0;
> }
>
> -static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
> - uint64_t error_code)
> +static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
> {
> + CPUPPCState *env = &POWERPC_CPU(cs)->env;
> bool vpm;
>
> if (msr_ir) {
> @@ -659,9 +659,9 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
> env->error_code = error_code;
> }
>
> -static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
> - uint64_t dsisr)
> +static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr)
> {
> + CPUPPCState *env = &POWERPC_CPU(cs)->env;
> bool vpm;
>
> if (msr_dr) {
> @@ -741,13 +741,13 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
> } else {
> /* The access failed, generate the approriate interrupt */
> if (rwx == 2) {
> - ppc_hash64_set_isi(cs, env, SRR1_PROTFAULT);
> + ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
> } else {
> int dsisr = DSISR_PROTFAULT;
> if (rwx == 1) {
> dsisr |= DSISR_ISSTORE;
> }
> - ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
> + ppc_hash64_set_dsi(cs, eaddr, dsisr);
> }
> return 1;
> }
> @@ -783,7 +783,7 @@ skip_slb_search:
>
> /* 3. Check for segment level no-execute violation */
> if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
> - ppc_hash64_set_isi(cs, env, SRR1_NOEXEC_GUARD);
> + ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
> return 1;
> }
>
> @@ -791,13 +791,13 @@ skip_slb_search:
> ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
> if (ptex == -1) {
> if (rwx == 2) {
> - ppc_hash64_set_isi(cs, env, SRR1_NOPTE);
> + ppc_hash64_set_isi(cs, SRR1_NOPTE);
> } else {
> int dsisr = DSISR_NOPTE;
> if (rwx == 1) {
> dsisr |= DSISR_ISSTORE;
> }
> - ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
> + ppc_hash64_set_dsi(cs, eaddr, dsisr);
> }
> return 1;
> }
> @@ -824,7 +824,7 @@ skip_slb_search:
> if (PAGE_EXEC & ~amr_prot) {
> srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
> }
> - ppc_hash64_set_isi(cs, env, srr1);
> + ppc_hash64_set_isi(cs, srr1);
> } else {
> int dsisr = 0;
> if (need_prot[rwx] & ~pp_prot) {
> @@ -836,7 +836,7 @@ skip_slb_search:
> if (need_prot[rwx] & ~amr_prot) {
> dsisr |= DSISR_AMR;
> }
> - ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
> + ppc_hash64_set_dsi(cs, eaddr, dsisr);
> }
> return 1;
> }
> @@ -942,8 +942,9 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
> cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
> }
>
> -void ppc_hash64_update_rmls(CPUPPCState *env)
> +void ppc_hash64_update_rmls(PowerPCCPU *cpu)
> {
> + CPUPPCState *env = &cpu->env;
> uint64_t lpcr = env->spr[SPR_LPCR];
>
> /*
> @@ -976,8 +977,9 @@ void ppc_hash64_update_rmls(CPUPPCState *env)
> }
> }
>
> -void ppc_hash64_update_vrma(CPUPPCState *env)
> +void ppc_hash64_update_vrma(PowerPCCPU *cpu)
> {
> + CPUPPCState *env = &cpu->env;
> const struct ppc_one_seg_page_size *sps = NULL;
> target_ulong esid, vsid, lpcr;
> ppc_slb_t *slb = &env->vrma_slb;
> @@ -1002,7 +1004,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env)
> vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
> esid = SLB_ESID_V;
>
> - for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> + for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
>
> if (!sps1->page_shift) {
> @@ -1028,6 +1030,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env)
>
> void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint64_t lpcr = 0;
>
> /* Filter out bits */
> @@ -1089,6 +1092,6 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> ;
> }
> env->spr[SPR_LPCR] = lpcr;
> - ppc_hash64_update_rmls(env);
> - ppc_hash64_update_vrma(env);
> + ppc_hash64_update_rmls(cpu);
> + ppc_hash64_update_vrma(cpu);
> }
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index d297b97d37..95a8c330d6 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -17,8 +17,8 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
> target_ulong pte0, target_ulong pte1);
> unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> uint64_t pte0, uint64_t pte1);
> -void ppc_hash64_update_vrma(CPUPPCState *env);
> -void ppc_hash64_update_rmls(CPUPPCState *env);
> +void ppc_hash64_update_vrma(PowerPCCPU *cpu);
> +void ppc_hash64_update_rmls(PowerPCCPU *cpu);
> #endif
>
> /*
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 2ae718242a..29bd6f3654 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8975,8 +8975,8 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
> env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
>
> /* Update some env bits based on new LPCR value */
> - ppc_hash64_update_rmls(env);
> - ppc_hash64_update_vrma(env);
> + ppc_hash64_update_rmls(cpu);
> + ppc_hash64_update_vrma(cpu);
>
> /* Tell KVM that we're in PAPR mode */
> if (kvm_enabled()) {
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (3 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 04/12] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-27 8:54 ` Cédric Le Goater
2018-03-27 13:54 ` Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 06/12] target/ppc: Move page size setup to helper function David Gibson
` (6 subsequent siblings)
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
CPU definitions for cpus with the 64-bit hash MMU can include a table of
available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
However, it turns out all the cpus which support 64K pages already include
an explicit table of page sizes, so there's no point to the fallback table
including 64k pages.
That removes the only place which tests POWERPC_MMU_64K, so we can remove
it. Which in turn allows some logic to be removed from
kvm_fixup_page_sizes().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-qom.h | 4 ----
target/ppc/kvm.c | 7 -------
target/ppc/translate_init.c | 20 ++------------------
3 files changed, 2 insertions(+), 29 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index deaa46a14b..9bbb05cf62 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -70,7 +70,6 @@ enum powerpc_mmu_t {
#define POWERPC_MMU_64 0x00010000
#define POWERPC_MMU_1TSEG 0x00020000
#define POWERPC_MMU_AMR 0x00040000
-#define POWERPC_MMU_64K 0x00080000
#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
@@ -78,15 +77,12 @@ enum powerpc_mmu_t {
POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_64K
| POWERPC_MMU_AMR | 0x00000003,
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_64K
| POWERPC_MMU_AMR | 0x00000004,
/* Architecture 3.00 variant */
POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_64K
| POWERPC_MMU_AMR | POWERPC_MMU_V3
| 0x00000005,
};
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 79a436a384..6160356a4a 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -425,7 +425,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
static bool has_smmu_info;
CPUPPCState *env = &cpu->env;
int iq, ik, jq, jk;
- bool has_64k_pages = false;
/* We only handle page sizes for 64-bit server guests for now */
if (!(env->mmu_model & POWERPC_MMU_64)) {
@@ -471,9 +470,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
ksps->enc[jk].page_shift)) {
continue;
}
- if (ksps->enc[jk].page_shift == 16) {
- has_64k_pages = true;
- }
qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;
qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;
if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {
@@ -488,9 +484,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
env->mmu_model &= ~POWERPC_MMU_1TSEG;
}
- if (!has_64k_pages) {
- env->mmu_model &= ~POWERPC_MMU_64K;
- }
}
bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 29bd6f3654..99be6fcd68 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10469,7 +10469,7 @@ static void ppc_cpu_instance_init(Object *obj)
env->sps = *pcc->sps;
} else if (env->mmu_model & POWERPC_MMU_64) {
/* Use default sets of page sizes. We don't support MPSS */
- static const struct ppc_segment_page_sizes defsps_4k = {
+ static const struct ppc_segment_page_sizes defsps = {
.sps = {
{ .page_shift = 12, /* 4K */
.slb_enc = 0,
@@ -10481,23 +10481,7 @@ static void ppc_cpu_instance_init(Object *obj)
},
},
};
- static const struct ppc_segment_page_sizes defsps_64k = {
- .sps = {
- { .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 } }
- },
- { .page_shift = 16, /* 64K */
- .slb_enc = 0x110,
- .enc = { { .page_shift = 16, .pte_enc = 1 } }
- },
- { .page_shift = 24, /* 16M */
- .slb_enc = 0x100,
- .enc = { { .page_shift = 24, .pte_enc = 0 } }
- },
- },
- };
- env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
+ env->sps = defsps;
}
#endif /* defined(TARGET_PPC64) */
}
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information David Gibson
@ 2018-03-27 8:54 ` Cédric Le Goater
2018-03-27 13:54 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-27 8:54 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> CPU definitions for cpus with the 64-bit hash MMU can include a table of
> available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
> fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
>
> However, it turns out all the cpus which support 64K pages already include
> an explicit table of page sizes, so there's no point to the fallback table
> including 64k pages.
>
> That removes the only place which tests POWERPC_MMU_64K, so we can remove
> it. Which in turn allows some logic to be removed from
> kvm_fixup_page_sizes().
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/cpu-qom.h | 4 ----
> target/ppc/kvm.c | 7 -------
> target/ppc/translate_init.c | 20 ++------------------
> 3 files changed, 2 insertions(+), 29 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index deaa46a14b..9bbb05cf62 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -70,7 +70,6 @@ enum powerpc_mmu_t {
> #define POWERPC_MMU_64 0x00010000
> #define POWERPC_MMU_1TSEG 0x00020000
> #define POWERPC_MMU_AMR 0x00040000
> -#define POWERPC_MMU_64K 0x00080000
> #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> /* 64 bits PowerPC MMU */
> POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> @@ -78,15 +77,12 @@ enum powerpc_mmu_t {
> POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
> /* Architecture 2.06 variant */
> POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_64K
> | POWERPC_MMU_AMR | 0x00000003,
> /* Architecture 2.07 variant */
> POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_64K
> | POWERPC_MMU_AMR | 0x00000004,
> /* Architecture 3.00 variant */
> POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_64K
> | POWERPC_MMU_AMR | POWERPC_MMU_V3
> | 0x00000005,
> };
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 79a436a384..6160356a4a 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -425,7 +425,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> static bool has_smmu_info;
> CPUPPCState *env = &cpu->env;
> int iq, ik, jq, jk;
> - bool has_64k_pages = false;
>
> /* We only handle page sizes for 64-bit server guests for now */
> if (!(env->mmu_model & POWERPC_MMU_64)) {
> @@ -471,9 +470,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> ksps->enc[jk].page_shift)) {
> continue;
> }
> - if (ksps->enc[jk].page_shift == 16) {
> - has_64k_pages = true;
> - }
> qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;
> qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;
> if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {
> @@ -488,9 +484,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
> env->mmu_model &= ~POWERPC_MMU_1TSEG;
> }
> - if (!has_64k_pages) {
> - env->mmu_model &= ~POWERPC_MMU_64K;
> - }
> }
>
> bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 29bd6f3654..99be6fcd68 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -10469,7 +10469,7 @@ static void ppc_cpu_instance_init(Object *obj)
> env->sps = *pcc->sps;
> } else if (env->mmu_model & POWERPC_MMU_64) {
> /* Use default sets of page sizes. We don't support MPSS */
> - static const struct ppc_segment_page_sizes defsps_4k = {
> + static const struct ppc_segment_page_sizes defsps = {
> .sps = {
> { .page_shift = 12, /* 4K */
> .slb_enc = 0,
> @@ -10481,23 +10481,7 @@ static void ppc_cpu_instance_init(Object *obj)
> },
> },
> };
> - static const struct ppc_segment_page_sizes defsps_64k = {
> - .sps = {
> - { .page_shift = 12, /* 4K */
> - .slb_enc = 0,
> - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> - },
> - { .page_shift = 16, /* 64K */
> - .slb_enc = 0x110,
> - .enc = { { .page_shift = 16, .pte_enc = 1 } }
> - },
> - { .page_shift = 24, /* 16M */
> - .slb_enc = 0x100,
> - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> - },
> - },
> - };
> - env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
> + env->sps = defsps;
> }
> #endif /* defined(TARGET_PPC64) */
> }
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information David Gibson
2018-03-27 8:54 ` Cédric Le Goater
@ 2018-03-27 13:54 ` Greg Kurz
2018-03-28 0:32 ` David Gibson
1 sibling, 1 reply; 45+ messages in thread
From: Greg Kurz @ 2018-03-27 13:54 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:34 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> CPU definitions for cpus with the 64-bit hash MMU can include a table of
> available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
> fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
>
> However, it turns out all the cpus which support 64K pages already include
> an explicit table of page sizes, so there's no point to the fallback table
> including 64k pages.
>
I was thinking that 64k pages came with POWER5+. At least, this is mentioned
in several places:
https://www.ibm.com/support/knowledgecenter/ssw_aix_72/com.ibm.aix.performance/supported_page_sizes_processor_type.htm
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a4a0f2524acc2c602cadd8e743be19d86f3a746b
And we do support POWER5+ with TCG and KVM PR. Shouldn't we include an explicit
table of pages sizes there as well ?
> That removes the only place which tests POWERPC_MMU_64K, so we can remove
> it. Which in turn allows some logic to be removed from
> kvm_fixup_page_sizes().
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/cpu-qom.h | 4 ----
> target/ppc/kvm.c | 7 -------
> target/ppc/translate_init.c | 20 ++------------------
> 3 files changed, 2 insertions(+), 29 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index deaa46a14b..9bbb05cf62 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -70,7 +70,6 @@ enum powerpc_mmu_t {
> #define POWERPC_MMU_64 0x00010000
> #define POWERPC_MMU_1TSEG 0x00020000
> #define POWERPC_MMU_AMR 0x00040000
> -#define POWERPC_MMU_64K 0x00080000
> #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> /* 64 bits PowerPC MMU */
> POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> @@ -78,15 +77,12 @@ enum powerpc_mmu_t {
> POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
> /* Architecture 2.06 variant */
> POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_64K
> | POWERPC_MMU_AMR | 0x00000003,
> /* Architecture 2.07 variant */
> POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_64K
> | POWERPC_MMU_AMR | 0x00000004,
> /* Architecture 3.00 variant */
> POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_64K
> | POWERPC_MMU_AMR | POWERPC_MMU_V3
> | 0x00000005,
> };
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 79a436a384..6160356a4a 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -425,7 +425,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> static bool has_smmu_info;
> CPUPPCState *env = &cpu->env;
> int iq, ik, jq, jk;
> - bool has_64k_pages = false;
>
> /* We only handle page sizes for 64-bit server guests for now */
> if (!(env->mmu_model & POWERPC_MMU_64)) {
> @@ -471,9 +470,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> ksps->enc[jk].page_shift)) {
> continue;
> }
> - if (ksps->enc[jk].page_shift == 16) {
> - has_64k_pages = true;
> - }
> qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;
> qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;
> if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {
> @@ -488,9 +484,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
> env->mmu_model &= ~POWERPC_MMU_1TSEG;
> }
> - if (!has_64k_pages) {
> - env->mmu_model &= ~POWERPC_MMU_64K;
> - }
> }
>
> bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 29bd6f3654..99be6fcd68 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -10469,7 +10469,7 @@ static void ppc_cpu_instance_init(Object *obj)
> env->sps = *pcc->sps;
> } else if (env->mmu_model & POWERPC_MMU_64) {
> /* Use default sets of page sizes. We don't support MPSS */
> - static const struct ppc_segment_page_sizes defsps_4k = {
> + static const struct ppc_segment_page_sizes defsps = {
> .sps = {
> { .page_shift = 12, /* 4K */
> .slb_enc = 0,
> @@ -10481,23 +10481,7 @@ static void ppc_cpu_instance_init(Object *obj)
> },
> },
> };
> - static const struct ppc_segment_page_sizes defsps_64k = {
> - .sps = {
> - { .page_shift = 12, /* 4K */
> - .slb_enc = 0,
> - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> - },
> - { .page_shift = 16, /* 64K */
> - .slb_enc = 0x110,
> - .enc = { { .page_shift = 16, .pte_enc = 1 } }
> - },
> - { .page_shift = 24, /* 16M */
> - .slb_enc = 0x100,
> - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> - },
> - },
> - };
> - env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
> + env->sps = defsps;
> }
> #endif /* defined(TARGET_PPC64) */
> }
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information
2018-03-27 13:54 ` Greg Kurz
@ 2018-03-28 0:32 ` David Gibson
2018-03-28 8:01 ` Greg Kurz
0 siblings, 1 reply; 45+ messages in thread
From: David Gibson @ 2018-03-28 0:32 UTC (permalink / raw)
To: Greg Kurz; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
[-- Attachment #1: Type: text/plain, Size: 6751 bytes --]
On Tue, Mar 27, 2018 at 03:54:55PM +0200, Greg Kurz wrote:
> On Tue, 27 Mar 2018 15:37:34 +1100
> David Gibson <david@gibson.dropbear.id.au> wrote:
>
> > CPU definitions for cpus with the 64-bit hash MMU can include a table of
> > available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
> > fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
> >
> > However, it turns out all the cpus which support 64K pages already include
> > an explicit table of page sizes, so there's no point to the fallback table
> > including 64k pages.
> >
>
> I was thinking that 64k pages came with POWER5+. At least, this is mentioned
> in several places:
>
> https://www.ibm.com/support/knowledgecenter/ssw_aix_72/com.ibm.aix.performance/supported_page_sizes_processor_type.htm
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a4a0f2524acc2c602cadd8e743be19d86f3a746b
Ok, I didn't know that. However, that was already wrong - we weren't
setting the MMU_64K bit for POWER5+.
> And we do support POWER5+ with TCG and KVM PR.
Well, theoretically. I doubt it's been tested in years, and I
strongly suspect it won't actually work.
> Shouldn't we include an explicit
> table of pages sizes there as well ?
Yeah, but I think it makes more sense to fix that later. Or, more
likely, not, since no-one actually cares about POWER5.
>
> > That removes the only place which tests POWERPC_MMU_64K, so we can remove
> > it. Which in turn allows some logic to be removed from
> > kvm_fixup_page_sizes().
> >
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> > target/ppc/cpu-qom.h | 4 ----
> > target/ppc/kvm.c | 7 -------
> > target/ppc/translate_init.c | 20 ++------------------
> > 3 files changed, 2 insertions(+), 29 deletions(-)
> >
> > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> > index deaa46a14b..9bbb05cf62 100644
> > --- a/target/ppc/cpu-qom.h
> > +++ b/target/ppc/cpu-qom.h
> > @@ -70,7 +70,6 @@ enum powerpc_mmu_t {
> > #define POWERPC_MMU_64 0x00010000
> > #define POWERPC_MMU_1TSEG 0x00020000
> > #define POWERPC_MMU_AMR 0x00040000
> > -#define POWERPC_MMU_64K 0x00080000
> > #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> > /* 64 bits PowerPC MMU */
> > POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> > @@ -78,15 +77,12 @@ enum powerpc_mmu_t {
> > POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
> > /* Architecture 2.06 variant */
> > POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > - | POWERPC_MMU_64K
> > | POWERPC_MMU_AMR | 0x00000003,
> > /* Architecture 2.07 variant */
> > POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > - | POWERPC_MMU_64K
> > | POWERPC_MMU_AMR | 0x00000004,
> > /* Architecture 3.00 variant */
> > POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > - | POWERPC_MMU_64K
> > | POWERPC_MMU_AMR | POWERPC_MMU_V3
> > | 0x00000005,
> > };
> > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> > index 79a436a384..6160356a4a 100644
> > --- a/target/ppc/kvm.c
> > +++ b/target/ppc/kvm.c
> > @@ -425,7 +425,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > static bool has_smmu_info;
> > CPUPPCState *env = &cpu->env;
> > int iq, ik, jq, jk;
> > - bool has_64k_pages = false;
> >
> > /* We only handle page sizes for 64-bit server guests for now */
> > if (!(env->mmu_model & POWERPC_MMU_64)) {
> > @@ -471,9 +470,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > ksps->enc[jk].page_shift)) {
> > continue;
> > }
> > - if (ksps->enc[jk].page_shift == 16) {
> > - has_64k_pages = true;
> > - }
> > qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;
> > qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;
> > if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {
> > @@ -488,9 +484,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
> > env->mmu_model &= ~POWERPC_MMU_1TSEG;
> > }
> > - if (!has_64k_pages) {
> > - env->mmu_model &= ~POWERPC_MMU_64K;
> > - }
> > }
> >
> > bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
> > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> > index 29bd6f3654..99be6fcd68 100644
> > --- a/target/ppc/translate_init.c
> > +++ b/target/ppc/translate_init.c
> > @@ -10469,7 +10469,7 @@ static void ppc_cpu_instance_init(Object *obj)
> > env->sps = *pcc->sps;
> > } else if (env->mmu_model & POWERPC_MMU_64) {
> > /* Use default sets of page sizes. We don't support MPSS */
> > - static const struct ppc_segment_page_sizes defsps_4k = {
> > + static const struct ppc_segment_page_sizes defsps = {
> > .sps = {
> > { .page_shift = 12, /* 4K */
> > .slb_enc = 0,
> > @@ -10481,23 +10481,7 @@ static void ppc_cpu_instance_init(Object *obj)
> > },
> > },
> > };
> > - static const struct ppc_segment_page_sizes defsps_64k = {
> > - .sps = {
> > - { .page_shift = 12, /* 4K */
> > - .slb_enc = 0,
> > - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> > - },
> > - { .page_shift = 16, /* 64K */
> > - .slb_enc = 0x110,
> > - .enc = { { .page_shift = 16, .pte_enc = 1 } }
> > - },
> > - { .page_shift = 24, /* 16M */
> > - .slb_enc = 0x100,
> > - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> > - },
> > - },
> > - };
> > - env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
> > + env->sps = defsps;
> > }
> > #endif /* defined(TARGET_PPC64) */
> > }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information
2018-03-28 0:32 ` David Gibson
@ 2018-03-28 8:01 ` Greg Kurz
2018-03-28 8:54 ` David Gibson
0 siblings, 1 reply; 45+ messages in thread
From: Greg Kurz @ 2018-03-28 8:01 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Wed, 28 Mar 2018 11:32:04 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> On Tue, Mar 27, 2018 at 03:54:55PM +0200, Greg Kurz wrote:
> > On Tue, 27 Mar 2018 15:37:34 +1100
> > David Gibson <david@gibson.dropbear.id.au> wrote:
> >
> > > CPU definitions for cpus with the 64-bit hash MMU can include a table of
> > > available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
> > > fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
> > >
> > > However, it turns out all the cpus which support 64K pages already include
> > > an explicit table of page sizes, so there's no point to the fallback table
> > > including 64k pages.
> > >
> >
> > I was thinking that 64k pages came with POWER5+. At least, this is mentioned
> > in several places:
> >
> > https://www.ibm.com/support/knowledgecenter/ssw_aix_72/com.ibm.aix.performance/supported_page_sizes_processor_type.htm
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a4a0f2524acc2c602cadd8e743be19d86f3a746b
>
> Ok, I didn't know that. However, that was already wrong - we weren't
> setting the MMU_64K bit for POWER5+.
>
Yes, I just happened to realize that while reviewing this patch. Hence the
remark :)
> > And we do support POWER5+ with TCG and KVM PR.
>
> Well, theoretically. I doubt it's been tested in years, and I
> strongly suspect it won't actually work.
>
For the records, I could successfully boot a rhel67 guest on a POWER8 host
with:
-machine accel=kvm,kvm-type=PR,vsmt=1 -cpu power5+
but it fails with TCG. The guest kernel oopses at some point because
of an illegal instruction and panics later on.
> > Shouldn't we include an explicit
> > table of pages sizes there as well ?
>
> Yeah, but I think it makes more sense to fix that later. Or, more
> likely, not, since no-one actually cares about POWER5.
>
You're probably right.
Anyway, this patch is the way to go, so:
Reviewed-by: Greg Kurz <groug@kaod.org>
> >
> > > That removes the only place which tests POWERPC_MMU_64K, so we can remove
> > > it. Which in turn allows some logic to be removed from
> > > kvm_fixup_page_sizes().
> > >
> > > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > > ---
> > > target/ppc/cpu-qom.h | 4 ----
> > > target/ppc/kvm.c | 7 -------
> > > target/ppc/translate_init.c | 20 ++------------------
> > > 3 files changed, 2 insertions(+), 29 deletions(-)
> > >
> > > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> > > index deaa46a14b..9bbb05cf62 100644
> > > --- a/target/ppc/cpu-qom.h
> > > +++ b/target/ppc/cpu-qom.h
> > > @@ -70,7 +70,6 @@ enum powerpc_mmu_t {
> > > #define POWERPC_MMU_64 0x00010000
> > > #define POWERPC_MMU_1TSEG 0x00020000
> > > #define POWERPC_MMU_AMR 0x00040000
> > > -#define POWERPC_MMU_64K 0x00080000
> > > #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> > > /* 64 bits PowerPC MMU */
> > > POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> > > @@ -78,15 +77,12 @@ enum powerpc_mmu_t {
> > > POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
> > > /* Architecture 2.06 variant */
> > > POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > > - | POWERPC_MMU_64K
> > > | POWERPC_MMU_AMR | 0x00000003,
> > > /* Architecture 2.07 variant */
> > > POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > > - | POWERPC_MMU_64K
> > > | POWERPC_MMU_AMR | 0x00000004,
> > > /* Architecture 3.00 variant */
> > > POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > > - | POWERPC_MMU_64K
> > > | POWERPC_MMU_AMR | POWERPC_MMU_V3
> > > | 0x00000005,
> > > };
> > > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> > > index 79a436a384..6160356a4a 100644
> > > --- a/target/ppc/kvm.c
> > > +++ b/target/ppc/kvm.c
> > > @@ -425,7 +425,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > > static bool has_smmu_info;
> > > CPUPPCState *env = &cpu->env;
> > > int iq, ik, jq, jk;
> > > - bool has_64k_pages = false;
> > >
> > > /* We only handle page sizes for 64-bit server guests for now */
> > > if (!(env->mmu_model & POWERPC_MMU_64)) {
> > > @@ -471,9 +470,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > > ksps->enc[jk].page_shift)) {
> > > continue;
> > > }
> > > - if (ksps->enc[jk].page_shift == 16) {
> > > - has_64k_pages = true;
> > > - }
> > > qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;
> > > qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;
> > > if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {
> > > @@ -488,9 +484,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > > if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
> > > env->mmu_model &= ~POWERPC_MMU_1TSEG;
> > > }
> > > - if (!has_64k_pages) {
> > > - env->mmu_model &= ~POWERPC_MMU_64K;
> > > - }
> > > }
> > >
> > > bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
> > > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> > > index 29bd6f3654..99be6fcd68 100644
> > > --- a/target/ppc/translate_init.c
> > > +++ b/target/ppc/translate_init.c
> > > @@ -10469,7 +10469,7 @@ static void ppc_cpu_instance_init(Object *obj)
> > > env->sps = *pcc->sps;
> > > } else if (env->mmu_model & POWERPC_MMU_64) {
> > > /* Use default sets of page sizes. We don't support MPSS */
> > > - static const struct ppc_segment_page_sizes defsps_4k = {
> > > + static const struct ppc_segment_page_sizes defsps = {
> > > .sps = {
> > > { .page_shift = 12, /* 4K */
> > > .slb_enc = 0,
> > > @@ -10481,23 +10481,7 @@ static void ppc_cpu_instance_init(Object *obj)
> > > },
> > > },
> > > };
> > > - static const struct ppc_segment_page_sizes defsps_64k = {
> > > - .sps = {
> > > - { .page_shift = 12, /* 4K */
> > > - .slb_enc = 0,
> > > - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> > > - },
> > > - { .page_shift = 16, /* 64K */
> > > - .slb_enc = 0x110,
> > > - .enc = { { .page_shift = 16, .pte_enc = 1 } }
> > > - },
> > > - { .page_shift = 24, /* 16M */
> > > - .slb_enc = 0x100,
> > > - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> > > - },
> > > - },
> > > - };
> > > - env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
> > > + env->sps = defsps;
> > > }
> > > #endif /* defined(TARGET_PPC64) */
> > > }
> >
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information
2018-03-28 8:01 ` Greg Kurz
@ 2018-03-28 8:54 ` David Gibson
0 siblings, 0 replies; 45+ messages in thread
From: David Gibson @ 2018-03-28 8:54 UTC (permalink / raw)
To: Greg Kurz; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
[-- Attachment #1: Type: text/plain, Size: 8299 bytes --]
On Wed, Mar 28, 2018 at 10:01:38AM +0200, Greg Kurz wrote:
> On Wed, 28 Mar 2018 11:32:04 +1100
> David Gibson <david@gibson.dropbear.id.au> wrote:
>
> > On Tue, Mar 27, 2018 at 03:54:55PM +0200, Greg Kurz wrote:
> > > On Tue, 27 Mar 2018 15:37:34 +1100
> > > David Gibson <david@gibson.dropbear.id.au> wrote:
> > >
> > > > CPU definitions for cpus with the 64-bit hash MMU can include a table of
> > > > available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
> > > > fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
> > > >
> > > > However, it turns out all the cpus which support 64K pages already include
> > > > an explicit table of page sizes, so there's no point to the fallback table
> > > > including 64k pages.
> > > >
> > >
> > > I was thinking that 64k pages came with POWER5+. At least, this is mentioned
> > > in several places:
> > >
> > > https://www.ibm.com/support/knowledgecenter/ssw_aix_72/com.ibm.aix.performance/supported_page_sizes_processor_type.htm
> > >
> > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a4a0f2524acc2c602cadd8e743be19d86f3a746b
> >
> > Ok, I didn't know that. However, that was already wrong - we weren't
> > setting the MMU_64K bit for POWER5+.
> >
>
> Yes, I just happened to realize that while reviewing this patch. Hence the
> remark :)
>
> > > And we do support POWER5+ with TCG and KVM PR.
> >
> > Well, theoretically. I doubt it's been tested in years, and I
> > strongly suspect it won't actually work.
> >
>
> For the records, I could successfully boot a rhel67 guest on a POWER8 host
> with:
>
> -machine accel=kvm,kvm-type=PR,vsmt=1 -cpu power5+
Yeah, under KVM (at least HV) I'm pretty sure it will effectively act
like the host CPU, even if you try to specify something else.
> but it fails with TCG. The guest kernel oopses at some point because
> of an illegal instruction and panics later on.
Right I'm pretty sure any guest distro that's even remotely modern
will be compiler to use instructions that weren't available on
power5+.
> > > Shouldn't we include an explicit
> > > table of pages sizes there as well ?
> >
> > Yeah, but I think it makes more sense to fix that later. Or, more
> > likely, not, since no-one actually cares about POWER5.
> >
>
> You're probably right.
>
> Anyway, this patch is the way to go, so:
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
>
> > >
> > > > That removes the only place which tests POWERPC_MMU_64K, so we can remove
> > > > it. Which in turn allows some logic to be removed from
> > > > kvm_fixup_page_sizes().
> > > >
> > > > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > > > ---
> > > > target/ppc/cpu-qom.h | 4 ----
> > > > target/ppc/kvm.c | 7 -------
> > > > target/ppc/translate_init.c | 20 ++------------------
> > > > 3 files changed, 2 insertions(+), 29 deletions(-)
> > > >
> > > > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> > > > index deaa46a14b..9bbb05cf62 100644
> > > > --- a/target/ppc/cpu-qom.h
> > > > +++ b/target/ppc/cpu-qom.h
> > > > @@ -70,7 +70,6 @@ enum powerpc_mmu_t {
> > > > #define POWERPC_MMU_64 0x00010000
> > > > #define POWERPC_MMU_1TSEG 0x00020000
> > > > #define POWERPC_MMU_AMR 0x00040000
> > > > -#define POWERPC_MMU_64K 0x00080000
> > > > #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> > > > /* 64 bits PowerPC MMU */
> > > > POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> > > > @@ -78,15 +77,12 @@ enum powerpc_mmu_t {
> > > > POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
> > > > /* Architecture 2.06 variant */
> > > > POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > > > - | POWERPC_MMU_64K
> > > > | POWERPC_MMU_AMR | 0x00000003,
> > > > /* Architecture 2.07 variant */
> > > > POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > > > - | POWERPC_MMU_64K
> > > > | POWERPC_MMU_AMR | 0x00000004,
> > > > /* Architecture 3.00 variant */
> > > > POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > > > - | POWERPC_MMU_64K
> > > > | POWERPC_MMU_AMR | POWERPC_MMU_V3
> > > > | 0x00000005,
> > > > };
> > > > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> > > > index 79a436a384..6160356a4a 100644
> > > > --- a/target/ppc/kvm.c
> > > > +++ b/target/ppc/kvm.c
> > > > @@ -425,7 +425,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > > > static bool has_smmu_info;
> > > > CPUPPCState *env = &cpu->env;
> > > > int iq, ik, jq, jk;
> > > > - bool has_64k_pages = false;
> > > >
> > > > /* We only handle page sizes for 64-bit server guests for now */
> > > > if (!(env->mmu_model & POWERPC_MMU_64)) {
> > > > @@ -471,9 +470,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > > > ksps->enc[jk].page_shift)) {
> > > > continue;
> > > > }
> > > > - if (ksps->enc[jk].page_shift == 16) {
> > > > - has_64k_pages = true;
> > > > - }
> > > > qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;
> > > > qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;
> > > > if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {
> > > > @@ -488,9 +484,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > > > if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
> > > > env->mmu_model &= ~POWERPC_MMU_1TSEG;
> > > > }
> > > > - if (!has_64k_pages) {
> > > > - env->mmu_model &= ~POWERPC_MMU_64K;
> > > > - }
> > > > }
> > > >
> > > > bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
> > > > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> > > > index 29bd6f3654..99be6fcd68 100644
> > > > --- a/target/ppc/translate_init.c
> > > > +++ b/target/ppc/translate_init.c
> > > > @@ -10469,7 +10469,7 @@ static void ppc_cpu_instance_init(Object *obj)
> > > > env->sps = *pcc->sps;
> > > > } else if (env->mmu_model & POWERPC_MMU_64) {
> > > > /* Use default sets of page sizes. We don't support MPSS */
> > > > - static const struct ppc_segment_page_sizes defsps_4k = {
> > > > + static const struct ppc_segment_page_sizes defsps = {
> > > > .sps = {
> > > > { .page_shift = 12, /* 4K */
> > > > .slb_enc = 0,
> > > > @@ -10481,23 +10481,7 @@ static void ppc_cpu_instance_init(Object *obj)
> > > > },
> > > > },
> > > > };
> > > > - static const struct ppc_segment_page_sizes defsps_64k = {
> > > > - .sps = {
> > > > - { .page_shift = 12, /* 4K */
> > > > - .slb_enc = 0,
> > > > - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> > > > - },
> > > > - { .page_shift = 16, /* 64K */
> > > > - .slb_enc = 0x110,
> > > > - .enc = { { .page_shift = 16, .pte_enc = 1 } }
> > > > - },
> > > > - { .page_shift = 24, /* 16M */
> > > > - .slb_enc = 0x100,
> > > > - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> > > > - },
> > > > - },
> > > > - };
> > > > - env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
> > > > + env->sps = defsps;
> > > > }
> > > > #endif /* defined(TARGET_PPC64) */
> > > > }
> > >
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 06/12] target/ppc: Move page size setup to helper function
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (4 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 05/12] target/ppc: Remove fallback 64k pagesize information David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-27 8:56 ` Cédric Le Goater
2018-03-27 13:58 ` Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 07/12] target/ppc: Split page size information into a separate allocation David Gibson
` (5 subsequent siblings)
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
Initialization of the env->sps structure at the end of instance_init is
specific to the 64-bit hash MMU, so move the code into a helper function
in mmu-hash64.c.
We also create a corresponding function to be called at finalize time -
it's empty for now, but we'll need it shortly.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/mmu-hash64.c | 29 +++++++++++++++++++++++++++++
target/ppc/mmu-hash64.h | 11 +++++++++++
target/ppc/translate_init.c | 29 +++++++++--------------------
3 files changed, 49 insertions(+), 20 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a87fa7c83f..4cb7d1cf07 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1095,3 +1095,32 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
ppc_hash64_update_rmls(cpu);
ppc_hash64_update_vrma(cpu);
}
+
+void ppc_hash64_init(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+ if (pcc->sps) {
+ env->sps = *pcc->sps;
+ } else if (env->mmu_model & POWERPC_MMU_64) {
+ /* Use default sets of page sizes. We don't support MPSS */
+ static const struct ppc_segment_page_sizes defsps = {
+ .sps = {
+ { .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 } }
+ },
+ { .page_shift = 24, /* 16M */
+ .slb_enc = 0x100,
+ .enc = { { .page_shift = 24, .pte_enc = 0 } }
+ },
+ },
+ };
+ env->sps = defsps;
+ }
+}
+
+void ppc_hash64_finalize(PowerPCCPU *cpu)
+{
+}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 95a8c330d6..074ded4c27 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -19,6 +19,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
uint64_t pte0, uint64_t pte1);
void ppc_hash64_update_vrma(PowerPCCPU *cpu);
void ppc_hash64_update_rmls(PowerPCCPU *cpu);
+void ppc_hash64_init(PowerPCCPU *cpu);
+void ppc_hash64_finalize(PowerPCCPU *cpu);
#endif
/*
@@ -136,4 +138,13 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
#endif /* CONFIG_USER_ONLY */
+#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
+static inline void ppc_hash64_init(PowerPCCPU *cpu)
+{
+}
+static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
+{
+}
+#endif
+
#endif /* MMU_HASH64_H */
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 99be6fcd68..aa63a5dcb3 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10464,26 +10464,14 @@ static void ppc_cpu_instance_init(Object *obj)
env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
#endif
-#if defined(TARGET_PPC64)
- if (pcc->sps) {
- env->sps = *pcc->sps;
- } else if (env->mmu_model & POWERPC_MMU_64) {
- /* Use default sets of page sizes. We don't support MPSS */
- static const struct ppc_segment_page_sizes defsps = {
- .sps = {
- { .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 } }
- },
- { .page_shift = 24, /* 16M */
- .slb_enc = 0x100,
- .enc = { { .page_shift = 24, .pte_enc = 0 } }
- },
- },
- };
- env->sps = defsps;
- }
-#endif /* defined(TARGET_PPC64) */
+ ppc_hash64_init(cpu);
+}
+
+static void ppc_cpu_instance_finalize(Object *obj)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(obj);
+
+ ppc_hash64_finalize(cpu);
}
static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -10601,6 +10589,7 @@ static const TypeInfo ppc_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(PowerPCCPU),
.instance_init = ppc_cpu_instance_init,
+ .instance_finalize = ppc_cpu_instance_finalize,
.abstract = true,
.class_size = sizeof(PowerPCCPUClass),
.class_init = ppc_cpu_class_init,
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 06/12] target/ppc: Move page size setup to helper function
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 06/12] target/ppc: Move page size setup to helper function David Gibson
@ 2018-03-27 8:56 ` Cédric Le Goater
2018-03-27 13:58 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-27 8:56 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> Initialization of the env->sps structure at the end of instance_init is
> specific to the 64-bit hash MMU, so move the code into a helper function
> in mmu-hash64.c.
>
> We also create a corresponding function to be called at finalize time -
> it's empty for now, but we'll need it shortly.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/mmu-hash64.c | 29 +++++++++++++++++++++++++++++
> target/ppc/mmu-hash64.h | 11 +++++++++++
> target/ppc/translate_init.c | 29 +++++++++--------------------
> 3 files changed, 49 insertions(+), 20 deletions(-)
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index a87fa7c83f..4cb7d1cf07 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1095,3 +1095,32 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> ppc_hash64_update_rmls(cpu);
> ppc_hash64_update_vrma(cpu);
> }
> +
> +void ppc_hash64_init(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> +
> + if (pcc->sps) {
> + env->sps = *pcc->sps;
> + } else if (env->mmu_model & POWERPC_MMU_64) {
> + /* Use default sets of page sizes. We don't support MPSS */
> + static const struct ppc_segment_page_sizes defsps = {
> + .sps = {
> + { .page_shift = 12, /* 4K */
> + .slb_enc = 0,
> + .enc = { { .page_shift = 12, .pte_enc = 0 } }
> + },
> + { .page_shift = 24, /* 16M */
> + .slb_enc = 0x100,
> + .enc = { { .page_shift = 24, .pte_enc = 0 } }
> + },
> + },
> + };
> + env->sps = defsps;
> + }
> +}
> +
> +void ppc_hash64_finalize(PowerPCCPU *cpu)
> +{
> +}
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 95a8c330d6..074ded4c27 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -19,6 +19,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> uint64_t pte0, uint64_t pte1);
> void ppc_hash64_update_vrma(PowerPCCPU *cpu);
> void ppc_hash64_update_rmls(PowerPCCPU *cpu);
> +void ppc_hash64_init(PowerPCCPU *cpu);
> +void ppc_hash64_finalize(PowerPCCPU *cpu);
> #endif
>
> /*
> @@ -136,4 +138,13 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
>
> #endif /* CONFIG_USER_ONLY */
>
> +#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
> +static inline void ppc_hash64_init(PowerPCCPU *cpu)
> +{
> +}
> +static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
> +{
> +}
> +#endif
> +
> #endif /* MMU_HASH64_H */
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 99be6fcd68..aa63a5dcb3 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -10464,26 +10464,14 @@ static void ppc_cpu_instance_init(Object *obj)
> env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
> #endif
>
> -#if defined(TARGET_PPC64)
> - if (pcc->sps) {
> - env->sps = *pcc->sps;
> - } else if (env->mmu_model & POWERPC_MMU_64) {
> - /* Use default sets of page sizes. We don't support MPSS */
> - static const struct ppc_segment_page_sizes defsps = {
> - .sps = {
> - { .page_shift = 12, /* 4K */
> - .slb_enc = 0,
> - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> - },
> - { .page_shift = 24, /* 16M */
> - .slb_enc = 0x100,
> - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> - },
> - },
> - };
> - env->sps = defsps;
> - }
> -#endif /* defined(TARGET_PPC64) */
> + ppc_hash64_init(cpu);
> +}
> +
> +static void ppc_cpu_instance_finalize(Object *obj)
> +{
> + PowerPCCPU *cpu = POWERPC_CPU(obj);
> +
> + ppc_hash64_finalize(cpu);
> }
>
> static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
> @@ -10601,6 +10589,7 @@ static const TypeInfo ppc_cpu_type_info = {
> .parent = TYPE_CPU,
> .instance_size = sizeof(PowerPCCPU),
> .instance_init = ppc_cpu_instance_init,
> + .instance_finalize = ppc_cpu_instance_finalize,
> .abstract = true,
> .class_size = sizeof(PowerPCCPUClass),
> .class_init = ppc_cpu_class_init,
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 06/12] target/ppc: Move page size setup to helper function
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 06/12] target/ppc: Move page size setup to helper function David Gibson
2018-03-27 8:56 ` Cédric Le Goater
@ 2018-03-27 13:58 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-27 13:58 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:35 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> Initialization of the env->sps structure at the end of instance_init is
> specific to the 64-bit hash MMU, so move the code into a helper function
> in mmu-hash64.c.
>
> We also create a corresponding function to be called at finalize time -
> it's empty for now, but we'll need it shortly.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> target/ppc/mmu-hash64.c | 29 +++++++++++++++++++++++++++++
> target/ppc/mmu-hash64.h | 11 +++++++++++
> target/ppc/translate_init.c | 29 +++++++++--------------------
> 3 files changed, 49 insertions(+), 20 deletions(-)
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index a87fa7c83f..4cb7d1cf07 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1095,3 +1095,32 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> ppc_hash64_update_rmls(cpu);
> ppc_hash64_update_vrma(cpu);
> }
> +
> +void ppc_hash64_init(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> +
> + if (pcc->sps) {
> + env->sps = *pcc->sps;
> + } else if (env->mmu_model & POWERPC_MMU_64) {
> + /* Use default sets of page sizes. We don't support MPSS */
> + static const struct ppc_segment_page_sizes defsps = {
> + .sps = {
> + { .page_shift = 12, /* 4K */
> + .slb_enc = 0,
> + .enc = { { .page_shift = 12, .pte_enc = 0 } }
> + },
> + { .page_shift = 24, /* 16M */
> + .slb_enc = 0x100,
> + .enc = { { .page_shift = 24, .pte_enc = 0 } }
> + },
> + },
> + };
> + env->sps = defsps;
> + }
> +}
> +
> +void ppc_hash64_finalize(PowerPCCPU *cpu)
> +{
> +}
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 95a8c330d6..074ded4c27 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -19,6 +19,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> uint64_t pte0, uint64_t pte1);
> void ppc_hash64_update_vrma(PowerPCCPU *cpu);
> void ppc_hash64_update_rmls(PowerPCCPU *cpu);
> +void ppc_hash64_init(PowerPCCPU *cpu);
> +void ppc_hash64_finalize(PowerPCCPU *cpu);
> #endif
>
> /*
> @@ -136,4 +138,13 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
>
> #endif /* CONFIG_USER_ONLY */
>
> +#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
> +static inline void ppc_hash64_init(PowerPCCPU *cpu)
> +{
> +}
> +static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
> +{
> +}
> +#endif
> +
> #endif /* MMU_HASH64_H */
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 99be6fcd68..aa63a5dcb3 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -10464,26 +10464,14 @@ static void ppc_cpu_instance_init(Object *obj)
> env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
> #endif
>
> -#if defined(TARGET_PPC64)
> - if (pcc->sps) {
> - env->sps = *pcc->sps;
> - } else if (env->mmu_model & POWERPC_MMU_64) {
> - /* Use default sets of page sizes. We don't support MPSS */
> - static const struct ppc_segment_page_sizes defsps = {
> - .sps = {
> - { .page_shift = 12, /* 4K */
> - .slb_enc = 0,
> - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> - },
> - { .page_shift = 24, /* 16M */
> - .slb_enc = 0x100,
> - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> - },
> - },
> - };
> - env->sps = defsps;
> - }
> -#endif /* defined(TARGET_PPC64) */
> + ppc_hash64_init(cpu);
> +}
> +
> +static void ppc_cpu_instance_finalize(Object *obj)
> +{
> + PowerPCCPU *cpu = POWERPC_CPU(obj);
> +
> + ppc_hash64_finalize(cpu);
> }
>
> static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
> @@ -10601,6 +10589,7 @@ static const TypeInfo ppc_cpu_type_info = {
> .parent = TYPE_CPU,
> .instance_size = sizeof(PowerPCCPU),
> .instance_init = ppc_cpu_instance_init,
> + .instance_finalize = ppc_cpu_instance_finalize,
> .abstract = true,
> .class_size = sizeof(PowerPCCPUClass),
> .class_init = ppc_cpu_class_init,
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 07/12] target/ppc: Split page size information into a separate allocation
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (5 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 06/12] target/ppc: Move page size setup to helper function David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-28 7:28 ` Cédric Le Goater
2018-03-28 8:15 ` Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 08/12] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs David Gibson
` (4 subsequent siblings)
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
env->sps contains page size encoding information as an embedded structure.
Since this information is specific to 64-bit hash MMUs, split it out into
a separately allocated structure, to reduce the basic env size for other
cpus. Along the way we make a few other cleanups:
* Rename to PPCHash64Options which is more in line with qemu name
conventions, and reflects that we're going to merge some more hash64
mmu specific details in there in future
* Move structure definitions to the mmu-hash64.[ch] files.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/fdt.c | 4 ++--
target/ppc/cpu-qom.h | 4 ++--
target/ppc/cpu.h | 22 +--------------------
target/ppc/kvm.c | 4 ++--
target/ppc/mmu-hash64.c | 47 ++++++++++++++++++++++++++++++++++++---------
target/ppc/mmu-hash64.h | 21 ++++++++++++++++++++
target/ppc/translate_init.c | 36 +++-------------------------------
7 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
index 2721603ffa..c4ba16f6b4 100644
--- a/hw/ppc/fdt.c
+++ b/hw/ppc/fdt.c
@@ -9,6 +9,7 @@
#include "qemu/osdep.h"
#include "target/ppc/cpu.h"
+#include "target/ppc/mmu-hash64.h"
#include "hw/ppc/fdt.h"
@@ -16,13 +17,12 @@
size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
size_t maxsize)
{
- CPUPPCState *env = &cpu->env;
size_t maxcells = maxsize / sizeof(uint32_t);
int i, j, count;
uint32_t *p = prop;
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
+ struct ppc_one_seg_page_size *sps = &cpu->hash64_opts->sps[i];
if (!sps->page_shift) {
break;
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 9bbb05cf62..3e5ef7375f 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -160,7 +160,7 @@ enum powerpc_input_t {
PPC_FLAGS_INPUT_RCPU,
};
-struct ppc_segment_page_sizes;
+typedef struct PPCHash64Options PPCHash64Options;
/**
* PowerPCCPUClass:
@@ -194,7 +194,7 @@ typedef struct PowerPCCPUClass {
uint32_t flags;
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
- const struct ppc_segment_page_sizes *sps;
+ const PPCHash64Options *hash64_opts;
struct ppc_radix_page_info *radix_page_info;
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c621a6bd5e..fb6c578eb5 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -948,28 +948,8 @@ enum {
#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
-/*****************************************************************************/
-/* Segment page size information, used by recent hash MMUs
- * The format of this structure mirrors kvm_ppc_smmu_info
- */
-
#define PPC_PAGE_SIZES_MAX_SZ 8
-struct ppc_one_page_size {
- uint32_t page_shift; /* Page shift (or 0) */
- uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
-};
-
-struct ppc_one_seg_page_size {
- uint32_t page_shift; /* Base page shift of segment (or 0) */
- uint32_t slb_enc; /* SLB encoding for BookS */
- struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
-};
-
-struct ppc_segment_page_sizes {
- struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
-};
-
struct ppc_radix_page_info {
uint32_t count;
uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
@@ -1106,7 +1086,6 @@ struct CPUPPCState {
uint64_t insns_flags;
uint64_t insns_flags2;
#if defined(TARGET_PPC64)
- struct ppc_segment_page_sizes sps;
ppc_slb_t vrma_slb;
target_ulong rmls;
bool ci_large_pages;
@@ -1227,6 +1206,7 @@ struct PowerPCCPU {
PPCVirtualHypervisor *vhyp;
Object *intc;
int32_t node_id; /* NUMA node this CPU belongs to */
+ PPCHash64Options *hash64_opts;
/* Fields related to migration compatibility hacks */
bool pre_2_8_migration;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 6160356a4a..01947169c9 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -442,7 +442,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
}
/* Convert to QEMU form */
- memset(&env->sps, 0, sizeof(env->sps));
+ memset(cpu->hash64_opts, 0, sizeof(*cpu->hash64_opts));
/* If we have HV KVM, we need to forbid CI large pages if our
* host page size is smaller than 64K.
@@ -456,7 +456,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
* the selected CPU has with the capabilities that KVM supports.
*/
for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {
- struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];
+ struct ppc_one_seg_page_size *qsps = &cpu->hash64_opts->sps[iq];
struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];
if (!kvm_valid_page_size(smmu_info.flags, max_cpu_page_size,
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 4cb7d1cf07..d7a0e5615f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -165,7 +165,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
}
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
+ const struct ppc_one_seg_page_size *sps1 = &cpu->hash64_opts->sps[i];
if (!sps1->page_shift) {
break;
@@ -552,7 +552,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
/* If ISL is set in LPCR we need to clamp the page size to 4K */
if (env->spr[SPR_LPCR] & LPCR_ISL) {
/* We assume that when using TCG, 4k is first entry of SPS */
- sps = &env->sps.sps[0];
+ sps = &cpu->hash64_opts->sps[0];
assert(sps->page_shift == 12);
}
@@ -605,7 +605,6 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
uint64_t pte0, uint64_t pte1)
{
- CPUPPCState *env = &cpu->env;
int i;
if (!(pte0 & HPTE64_V_LARGE)) {
@@ -617,7 +616,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
* this gives an unambiguous result.
*/
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
+ const struct ppc_one_seg_page_size *sps = &cpu->hash64_opts->sps[i];
unsigned shift;
if (!sps->page_shift) {
@@ -1005,7 +1004,7 @@ void ppc_hash64_update_vrma(PowerPCCPU *cpu)
esid = SLB_ESID_V;
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
+ const struct ppc_one_seg_page_size *sps1 = &cpu->hash64_opts->sps[i];
if (!sps1->page_shift) {
break;
@@ -1101,11 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- if (pcc->sps) {
- env->sps = *pcc->sps;
+ if (pcc->hash64_opts) {
+ cpu->hash64_opts = g_memdup(pcc->hash64_opts,
+ sizeof(*cpu->hash64_opts));
} else if (env->mmu_model & POWERPC_MMU_64) {
/* Use default sets of page sizes. We don't support MPSS */
- static const struct ppc_segment_page_sizes defsps = {
+ static const PPCHash64Options defopts = {
.sps = {
{ .page_shift = 12, /* 4K */
.slb_enc = 0,
@@ -1117,10 +1117,39 @@ void ppc_hash64_init(PowerPCCPU *cpu)
},
},
};
- env->sps = defsps;
+ cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
}
}
void ppc_hash64_finalize(PowerPCCPU *cpu)
{
+ g_free(cpu->hash64_opts);
}
+
+const PPCHash64Options ppc_hash64_opts_POWER7 = {
+ .sps = {
+ {
+ .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 },
+ { .page_shift = 16, .pte_enc = 0x7 },
+ { .page_shift = 24, .pte_enc = 0x38 }, },
+ },
+ {
+ .page_shift = 16, /* 64K */
+ .slb_enc = SLB_VSID_64K,
+ .enc = { { .page_shift = 16, .pte_enc = 0x1 },
+ { .page_shift = 24, .pte_enc = 0x8 }, },
+ },
+ {
+ .page_shift = 24, /* 16M */
+ .slb_enc = SLB_VSID_16M,
+ .enc = { { .page_shift = 24, .pte_enc = 0 }, },
+ },
+ {
+ .page_shift = 34, /* 16G */
+ .slb_enc = SLB_VSID_16G,
+ .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
+ },
+ }
+};
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 074ded4c27..d42cbc2762 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -136,6 +136,27 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
return ldq_p(&(hptes[i].pte1));
}
+/*
+ * MMU Options
+ */
+
+struct ppc_one_page_size {
+ uint32_t page_shift; /* Page shift (or 0) */
+ uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
+};
+
+struct ppc_one_seg_page_size {
+ uint32_t page_shift; /* Base page shift of segment (or 0) */
+ uint32_t slb_enc; /* SLB encoding for BookS */
+ struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
+};
+
+struct PPCHash64Options {
+ struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
+};
+
+extern const PPCHash64Options ppc_hash64_opts_POWER7;
+
#endif /* CONFIG_USER_ONLY */
#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index aa63a5dcb3..040d6fbac3 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8368,36 +8368,6 @@ static Property powerpc_servercpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
-#ifdef CONFIG_SOFTMMU
-static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
- .sps = {
- {
- .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 },
- { .page_shift = 16, .pte_enc = 0x7 },
- { .page_shift = 24, .pte_enc = 0x38 }, },
- },
- {
- .page_shift = 16, /* 64K */
- .slb_enc = SLB_VSID_64K,
- .enc = { { .page_shift = 16, .pte_enc = 0x1 },
- { .page_shift = 24, .pte_enc = 0x8 }, },
- },
- {
- .page_shift = 24, /* 16M */
- .slb_enc = SLB_VSID_16M,
- .enc = { { .page_shift = 24, .pte_enc = 0 }, },
- },
- {
- .page_shift = 34, /* 16G */
- .slb_enc = SLB_VSID_16G,
- .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
- },
- }
-};
-#endif /* CONFIG_SOFTMMU */
-
static void init_proc_POWER7(CPUPPCState *env)
{
/* Common Registers */
@@ -8526,7 +8496,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
- pcc->sps = &POWER7_POWER8_sps;
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
@@ -8698,7 +8668,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_07;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
- pcc->sps = &POWER7_POWER8_sps;
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
#endif
pcc->excp_model = POWERPC_EXCP_POWER8;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
@@ -8893,7 +8863,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
/* segment page size remain the same */
- pcc->sps = &POWER7_POWER8_sps;
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
pcc->radix_page_info = &POWER9_radix_page_info;
#endif
pcc->excp_model = POWERPC_EXCP_POWER8;
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 07/12] target/ppc: Split page size information into a separate allocation
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 07/12] target/ppc: Split page size information into a separate allocation David Gibson
@ 2018-03-28 7:28 ` Cédric Le Goater
2018-03-29 4:46 ` David Gibson
2018-03-28 8:15 ` Greg Kurz
1 sibling, 1 reply; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-28 7:28 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> env->sps contains page size encoding information as an embedded structure.
> Since this information is specific to 64-bit hash MMUs, split it out into
> a separately allocated structure, to reduce the basic env size for other
> cpus. Along the way we make a few other cleanups:
>
> * Rename to PPCHash64Options which is more in line with qemu name
> conventions, and reflects that we're going to merge some more hash64
> mmu specific details in there in future
>
> * Move structure definitions to the mmu-hash64.[ch] files.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
While you are at changing things, maybe you could CamelCase
struct ppc_one_seg_page_size
struct ppc_one_page_size
No big deal.
Thanks,
C.
> ---
> hw/ppc/fdt.c | 4 ++--
> target/ppc/cpu-qom.h | 4 ++--
> target/ppc/cpu.h | 22 +--------------------
> target/ppc/kvm.c | 4 ++--
> target/ppc/mmu-hash64.c | 47 ++++++++++++++++++++++++++++++++++++---------
> target/ppc/mmu-hash64.h | 21 ++++++++++++++++++++
> target/ppc/translate_init.c | 36 +++-------------------------------
> 7 files changed, 69 insertions(+), 69 deletions(-)
>
> diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
> index 2721603ffa..c4ba16f6b4 100644
> --- a/hw/ppc/fdt.c
> +++ b/hw/ppc/fdt.c
> @@ -9,6 +9,7 @@
>
> #include "qemu/osdep.h"
> #include "target/ppc/cpu.h"
> +#include "target/ppc/mmu-hash64.h"
>
> #include "hw/ppc/fdt.h"
>
> @@ -16,13 +17,12 @@
> size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
> size_t maxsize)
> {
> - CPUPPCState *env = &cpu->env;
> size_t maxcells = maxsize / sizeof(uint32_t);
> int i, j, count;
> uint32_t *p = prop;
>
> for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> - struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
> + struct ppc_one_seg_page_size *sps = &cpu->hash64_opts->sps[i];
>
> if (!sps->page_shift) {
> break;
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index 9bbb05cf62..3e5ef7375f 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -160,7 +160,7 @@ enum powerpc_input_t {
> PPC_FLAGS_INPUT_RCPU,
> };
>
> -struct ppc_segment_page_sizes;
> +typedef struct PPCHash64Options PPCHash64Options;
>
> /**
> * PowerPCCPUClass:
> @@ -194,7 +194,7 @@ typedef struct PowerPCCPUClass {
> uint32_t flags;
> int bfd_mach;
> uint32_t l1_dcache_size, l1_icache_size;
> - const struct ppc_segment_page_sizes *sps;
> + const PPCHash64Options *hash64_opts;
> struct ppc_radix_page_info *radix_page_info;
> void (*init_proc)(CPUPPCState *env);
> int (*check_pow)(CPUPPCState *env);
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index c621a6bd5e..fb6c578eb5 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -948,28 +948,8 @@ enum {
>
> #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
>
> -/*****************************************************************************/
> -/* Segment page size information, used by recent hash MMUs
> - * The format of this structure mirrors kvm_ppc_smmu_info
> - */
> -
> #define PPC_PAGE_SIZES_MAX_SZ 8
>
> -struct ppc_one_page_size {
> - uint32_t page_shift; /* Page shift (or 0) */
> - uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
> -};
> -
> -struct ppc_one_seg_page_size {
> - uint32_t page_shift; /* Base page shift of segment (or 0) */
> - uint32_t slb_enc; /* SLB encoding for BookS */
> - struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
> -};
> -
> -struct ppc_segment_page_sizes {
> - struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> -};
> -
> struct ppc_radix_page_info {
> uint32_t count;
> uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
> @@ -1106,7 +1086,6 @@ struct CPUPPCState {
> uint64_t insns_flags;
> uint64_t insns_flags2;
> #if defined(TARGET_PPC64)
> - struct ppc_segment_page_sizes sps;
> ppc_slb_t vrma_slb;
> target_ulong rmls;
> bool ci_large_pages;
> @@ -1227,6 +1206,7 @@ struct PowerPCCPU {
> PPCVirtualHypervisor *vhyp;
> Object *intc;
> int32_t node_id; /* NUMA node this CPU belongs to */
> + PPCHash64Options *hash64_opts;
>
> /* Fields related to migration compatibility hacks */
> bool pre_2_8_migration;
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 6160356a4a..01947169c9 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -442,7 +442,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> }
>
> /* Convert to QEMU form */
> - memset(&env->sps, 0, sizeof(env->sps));
> + memset(cpu->hash64_opts, 0, sizeof(*cpu->hash64_opts));
>
> /* If we have HV KVM, we need to forbid CI large pages if our
> * host page size is smaller than 64K.
> @@ -456,7 +456,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> * the selected CPU has with the capabilities that KVM supports.
> */
> for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {
> - struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];
> + struct ppc_one_seg_page_size *qsps = &cpu->hash64_opts->sps[iq];
> struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];
>
> if (!kvm_valid_page_size(smmu_info.flags, max_cpu_page_size,
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 4cb7d1cf07..d7a0e5615f 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -165,7 +165,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
> }
>
> for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> - const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
> + const struct ppc_one_seg_page_size *sps1 = &cpu->hash64_opts->sps[i];
>
> if (!sps1->page_shift) {
> break;
> @@ -552,7 +552,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
> /* If ISL is set in LPCR we need to clamp the page size to 4K */
> if (env->spr[SPR_LPCR] & LPCR_ISL) {
> /* We assume that when using TCG, 4k is first entry of SPS */
> - sps = &env->sps.sps[0];
> + sps = &cpu->hash64_opts->sps[0];
> assert(sps->page_shift == 12);
> }
>
> @@ -605,7 +605,6 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
> unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> uint64_t pte0, uint64_t pte1)
> {
> - CPUPPCState *env = &cpu->env;
> int i;
>
> if (!(pte0 & HPTE64_V_LARGE)) {
> @@ -617,7 +616,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> * this gives an unambiguous result.
> */
> for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> - const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
> + const struct ppc_one_seg_page_size *sps = &cpu->hash64_opts->sps[i];
> unsigned shift;
>
> if (!sps->page_shift) {
> @@ -1005,7 +1004,7 @@ void ppc_hash64_update_vrma(PowerPCCPU *cpu)
> esid = SLB_ESID_V;
>
> for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> - const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
> + const struct ppc_one_seg_page_size *sps1 = &cpu->hash64_opts->sps[i];
>
> if (!sps1->page_shift) {
> break;
> @@ -1101,11 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
> CPUPPCState *env = &cpu->env;
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>
> - if (pcc->sps) {
> - env->sps = *pcc->sps;
> + if (pcc->hash64_opts) {
> + cpu->hash64_opts = g_memdup(pcc->hash64_opts,
> + sizeof(*cpu->hash64_opts));
> } else if (env->mmu_model & POWERPC_MMU_64) {
> /* Use default sets of page sizes. We don't support MPSS */
> - static const struct ppc_segment_page_sizes defsps = {
> + static const PPCHash64Options defopts = {
> .sps = {
> { .page_shift = 12, /* 4K */
> .slb_enc = 0,
> @@ -1117,10 +1117,39 @@ void ppc_hash64_init(PowerPCCPU *cpu)
> },
> },
> };
> - env->sps = defsps;
> + cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
> }
> }
>
> void ppc_hash64_finalize(PowerPCCPU *cpu)
> {
> + g_free(cpu->hash64_opts);
> }
> +
> +const PPCHash64Options ppc_hash64_opts_POWER7 = {
> + .sps = {
> + {
> + .page_shift = 12, /* 4K */
> + .slb_enc = 0,
> + .enc = { { .page_shift = 12, .pte_enc = 0 },
> + { .page_shift = 16, .pte_enc = 0x7 },
> + { .page_shift = 24, .pte_enc = 0x38 }, },
> + },
> + {
> + .page_shift = 16, /* 64K */
> + .slb_enc = SLB_VSID_64K,
> + .enc = { { .page_shift = 16, .pte_enc = 0x1 },
> + { .page_shift = 24, .pte_enc = 0x8 }, },
> + },
> + {
> + .page_shift = 24, /* 16M */
> + .slb_enc = SLB_VSID_16M,
> + .enc = { { .page_shift = 24, .pte_enc = 0 }, },
> + },
> + {
> + .page_shift = 34, /* 16G */
> + .slb_enc = SLB_VSID_16G,
> + .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
> + },
> + }
> +};
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 074ded4c27..d42cbc2762 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -136,6 +136,27 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
> return ldq_p(&(hptes[i].pte1));
> }
>
> +/*
> + * MMU Options
> + */
> +
> +struct ppc_one_page_size {
> + uint32_t page_shift; /* Page shift (or 0) */
> + uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
> +};
> +
> +struct ppc_one_seg_page_size {
> + uint32_t page_shift; /* Base page shift of segment (or 0) */
> + uint32_t slb_enc; /* SLB encoding for BookS */
> + struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
> +};
> +
> +struct PPCHash64Options {
> + struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> +};
> +
> +extern const PPCHash64Options ppc_hash64_opts_POWER7;
> +
> #endif /* CONFIG_USER_ONLY */
>
> #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index aa63a5dcb3..040d6fbac3 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8368,36 +8368,6 @@ static Property powerpc_servercpu_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -#ifdef CONFIG_SOFTMMU
> -static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
> - .sps = {
> - {
> - .page_shift = 12, /* 4K */
> - .slb_enc = 0,
> - .enc = { { .page_shift = 12, .pte_enc = 0 },
> - { .page_shift = 16, .pte_enc = 0x7 },
> - { .page_shift = 24, .pte_enc = 0x38 }, },
> - },
> - {
> - .page_shift = 16, /* 64K */
> - .slb_enc = SLB_VSID_64K,
> - .enc = { { .page_shift = 16, .pte_enc = 0x1 },
> - { .page_shift = 24, .pte_enc = 0x8 }, },
> - },
> - {
> - .page_shift = 24, /* 16M */
> - .slb_enc = SLB_VSID_16M,
> - .enc = { { .page_shift = 24, .pte_enc = 0 }, },
> - },
> - {
> - .page_shift = 34, /* 16G */
> - .slb_enc = SLB_VSID_16G,
> - .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
> - },
> - }
> -};
> -#endif /* CONFIG_SOFTMMU */
> -
> static void init_proc_POWER7(CPUPPCState *env)
> {
> /* Common Registers */
> @@ -8526,7 +8496,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> pcc->mmu_model = POWERPC_MMU_2_06;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> - pcc->sps = &POWER7_POWER8_sps;
> + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> #endif
> pcc->excp_model = POWERPC_EXCP_POWER7;
> pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> @@ -8698,7 +8668,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> pcc->mmu_model = POWERPC_MMU_2_07;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> - pcc->sps = &POWER7_POWER8_sps;
> + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> #endif
> pcc->excp_model = POWERPC_EXCP_POWER8;
> pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> @@ -8893,7 +8863,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
> /* segment page size remain the same */
> - pcc->sps = &POWER7_POWER8_sps;
> + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> pcc->radix_page_info = &POWER9_radix_page_info;
> #endif
> pcc->excp_model = POWERPC_EXCP_POWER8;
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 07/12] target/ppc: Split page size information into a separate allocation
2018-03-28 7:28 ` Cédric Le Goater
@ 2018-03-29 4:46 ` David Gibson
0 siblings, 0 replies; 45+ messages in thread
From: David Gibson @ 2018-03-29 4:46 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, groug, agraf, qemu-devel, benh, bharata
[-- Attachment #1: Type: text/plain, Size: 14562 bytes --]
On Wed, Mar 28, 2018 at 09:28:41AM +0200, Cédric Le Goater wrote:
> On 03/27/2018 06:37 AM, David Gibson wrote:
> > env->sps contains page size encoding information as an embedded structure.
> > Since this information is specific to 64-bit hash MMUs, split it out into
> > a separately allocated structure, to reduce the basic env size for other
> > cpus. Along the way we make a few other cleanups:
> >
> > * Rename to PPCHash64Options which is more in line with qemu name
> > conventions, and reflects that we're going to merge some more hash64
> > mmu specific details in there in future
> >
> > * Move structure definitions to the mmu-hash64.[ch] files.
> >
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>
> While you are at changing things, maybe you could CamelCase
>
> struct ppc_one_seg_page_size
> struct ppc_one_page_size
Good idea, I'll include that in the next spin.
>
> No big deal.
>
> Thanks,
>
> C.
>
> > ---
> > hw/ppc/fdt.c | 4 ++--
> > target/ppc/cpu-qom.h | 4 ++--
> > target/ppc/cpu.h | 22 +--------------------
> > target/ppc/kvm.c | 4 ++--
> > target/ppc/mmu-hash64.c | 47 ++++++++++++++++++++++++++++++++++++---------
> > target/ppc/mmu-hash64.h | 21 ++++++++++++++++++++
> > target/ppc/translate_init.c | 36 +++-------------------------------
> > 7 files changed, 69 insertions(+), 69 deletions(-)
> >
> > diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
> > index 2721603ffa..c4ba16f6b4 100644
> > --- a/hw/ppc/fdt.c
> > +++ b/hw/ppc/fdt.c
> > @@ -9,6 +9,7 @@
> >
> > #include "qemu/osdep.h"
> > #include "target/ppc/cpu.h"
> > +#include "target/ppc/mmu-hash64.h"
> >
> > #include "hw/ppc/fdt.h"
> >
> > @@ -16,13 +17,12 @@
> > size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
> > size_t maxsize)
> > {
> > - CPUPPCState *env = &cpu->env;
> > size_t maxcells = maxsize / sizeof(uint32_t);
> > int i, j, count;
> > uint32_t *p = prop;
> >
> > for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> > - struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
> > + struct ppc_one_seg_page_size *sps = &cpu->hash64_opts->sps[i];
> >
> > if (!sps->page_shift) {
> > break;
> > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> > index 9bbb05cf62..3e5ef7375f 100644
> > --- a/target/ppc/cpu-qom.h
> > +++ b/target/ppc/cpu-qom.h
> > @@ -160,7 +160,7 @@ enum powerpc_input_t {
> > PPC_FLAGS_INPUT_RCPU,
> > };
> >
> > -struct ppc_segment_page_sizes;
> > +typedef struct PPCHash64Options PPCHash64Options;
> >
> > /**
> > * PowerPCCPUClass:
> > @@ -194,7 +194,7 @@ typedef struct PowerPCCPUClass {
> > uint32_t flags;
> > int bfd_mach;
> > uint32_t l1_dcache_size, l1_icache_size;
> > - const struct ppc_segment_page_sizes *sps;
> > + const PPCHash64Options *hash64_opts;
> > struct ppc_radix_page_info *radix_page_info;
> > void (*init_proc)(CPUPPCState *env);
> > int (*check_pow)(CPUPPCState *env);
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index c621a6bd5e..fb6c578eb5 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -948,28 +948,8 @@ enum {
> >
> > #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
> >
> > -/*****************************************************************************/
> > -/* Segment page size information, used by recent hash MMUs
> > - * The format of this structure mirrors kvm_ppc_smmu_info
> > - */
> > -
> > #define PPC_PAGE_SIZES_MAX_SZ 8
> >
> > -struct ppc_one_page_size {
> > - uint32_t page_shift; /* Page shift (or 0) */
> > - uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
> > -};
> > -
> > -struct ppc_one_seg_page_size {
> > - uint32_t page_shift; /* Base page shift of segment (or 0) */
> > - uint32_t slb_enc; /* SLB encoding for BookS */
> > - struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
> > -};
> > -
> > -struct ppc_segment_page_sizes {
> > - struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> > -};
> > -
> > struct ppc_radix_page_info {
> > uint32_t count;
> > uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
> > @@ -1106,7 +1086,6 @@ struct CPUPPCState {
> > uint64_t insns_flags;
> > uint64_t insns_flags2;
> > #if defined(TARGET_PPC64)
> > - struct ppc_segment_page_sizes sps;
> > ppc_slb_t vrma_slb;
> > target_ulong rmls;
> > bool ci_large_pages;
> > @@ -1227,6 +1206,7 @@ struct PowerPCCPU {
> > PPCVirtualHypervisor *vhyp;
> > Object *intc;
> > int32_t node_id; /* NUMA node this CPU belongs to */
> > + PPCHash64Options *hash64_opts;
> >
> > /* Fields related to migration compatibility hacks */
> > bool pre_2_8_migration;
> > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> > index 6160356a4a..01947169c9 100644
> > --- a/target/ppc/kvm.c
> > +++ b/target/ppc/kvm.c
> > @@ -442,7 +442,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > }
> >
> > /* Convert to QEMU form */
> > - memset(&env->sps, 0, sizeof(env->sps));
> > + memset(cpu->hash64_opts, 0, sizeof(*cpu->hash64_opts));
> >
> > /* If we have HV KVM, we need to forbid CI large pages if our
> > * host page size is smaller than 64K.
> > @@ -456,7 +456,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > * the selected CPU has with the capabilities that KVM supports.
> > */
> > for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {
> > - struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];
> > + struct ppc_one_seg_page_size *qsps = &cpu->hash64_opts->sps[iq];
> > struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];
> >
> > if (!kvm_valid_page_size(smmu_info.flags, max_cpu_page_size,
> > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> > index 4cb7d1cf07..d7a0e5615f 100644
> > --- a/target/ppc/mmu-hash64.c
> > +++ b/target/ppc/mmu-hash64.c
> > @@ -165,7 +165,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
> > }
> >
> > for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> > - const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
> > + const struct ppc_one_seg_page_size *sps1 = &cpu->hash64_opts->sps[i];
> >
> > if (!sps1->page_shift) {
> > break;
> > @@ -552,7 +552,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
> > /* If ISL is set in LPCR we need to clamp the page size to 4K */
> > if (env->spr[SPR_LPCR] & LPCR_ISL) {
> > /* We assume that when using TCG, 4k is first entry of SPS */
> > - sps = &env->sps.sps[0];
> > + sps = &cpu->hash64_opts->sps[0];
> > assert(sps->page_shift == 12);
> > }
> >
> > @@ -605,7 +605,6 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
> > unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> > uint64_t pte0, uint64_t pte1)
> > {
> > - CPUPPCState *env = &cpu->env;
> > int i;
> >
> > if (!(pte0 & HPTE64_V_LARGE)) {
> > @@ -617,7 +616,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> > * this gives an unambiguous result.
> > */
> > for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> > - const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
> > + const struct ppc_one_seg_page_size *sps = &cpu->hash64_opts->sps[i];
> > unsigned shift;
> >
> > if (!sps->page_shift) {
> > @@ -1005,7 +1004,7 @@ void ppc_hash64_update_vrma(PowerPCCPU *cpu)
> > esid = SLB_ESID_V;
> >
> > for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> > - const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
> > + const struct ppc_one_seg_page_size *sps1 = &cpu->hash64_opts->sps[i];
> >
> > if (!sps1->page_shift) {
> > break;
> > @@ -1101,11 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
> > CPUPPCState *env = &cpu->env;
> > PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> >
> > - if (pcc->sps) {
> > - env->sps = *pcc->sps;
> > + if (pcc->hash64_opts) {
> > + cpu->hash64_opts = g_memdup(pcc->hash64_opts,
> > + sizeof(*cpu->hash64_opts));
> > } else if (env->mmu_model & POWERPC_MMU_64) {
> > /* Use default sets of page sizes. We don't support MPSS */
> > - static const struct ppc_segment_page_sizes defsps = {
> > + static const PPCHash64Options defopts = {
> > .sps = {
> > { .page_shift = 12, /* 4K */
> > .slb_enc = 0,
> > @@ -1117,10 +1117,39 @@ void ppc_hash64_init(PowerPCCPU *cpu)
> > },
> > },
> > };
> > - env->sps = defsps;
> > + cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
> > }
> > }
> >
> > void ppc_hash64_finalize(PowerPCCPU *cpu)
> > {
> > + g_free(cpu->hash64_opts);
> > }
> > +
> > +const PPCHash64Options ppc_hash64_opts_POWER7 = {
> > + .sps = {
> > + {
> > + .page_shift = 12, /* 4K */
> > + .slb_enc = 0,
> > + .enc = { { .page_shift = 12, .pte_enc = 0 },
> > + { .page_shift = 16, .pte_enc = 0x7 },
> > + { .page_shift = 24, .pte_enc = 0x38 }, },
> > + },
> > + {
> > + .page_shift = 16, /* 64K */
> > + .slb_enc = SLB_VSID_64K,
> > + .enc = { { .page_shift = 16, .pte_enc = 0x1 },
> > + { .page_shift = 24, .pte_enc = 0x8 }, },
> > + },
> > + {
> > + .page_shift = 24, /* 16M */
> > + .slb_enc = SLB_VSID_16M,
> > + .enc = { { .page_shift = 24, .pte_enc = 0 }, },
> > + },
> > + {
> > + .page_shift = 34, /* 16G */
> > + .slb_enc = SLB_VSID_16G,
> > + .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
> > + },
> > + }
> > +};
> > diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> > index 074ded4c27..d42cbc2762 100644
> > --- a/target/ppc/mmu-hash64.h
> > +++ b/target/ppc/mmu-hash64.h
> > @@ -136,6 +136,27 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
> > return ldq_p(&(hptes[i].pte1));
> > }
> >
> > +/*
> > + * MMU Options
> > + */
> > +
> > +struct ppc_one_page_size {
> > + uint32_t page_shift; /* Page shift (or 0) */
> > + uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
> > +};
> > +
> > +struct ppc_one_seg_page_size {
> > + uint32_t page_shift; /* Base page shift of segment (or 0) */
> > + uint32_t slb_enc; /* SLB encoding for BookS */
> > + struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
> > +};
> > +
> > +struct PPCHash64Options {
> > + struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> > +};
> > +
> > +extern const PPCHash64Options ppc_hash64_opts_POWER7;
> > +
> > #endif /* CONFIG_USER_ONLY */
> >
> > #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
> > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> > index aa63a5dcb3..040d6fbac3 100644
> > --- a/target/ppc/translate_init.c
> > +++ b/target/ppc/translate_init.c
> > @@ -8368,36 +8368,6 @@ static Property powerpc_servercpu_properties[] = {
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > -#ifdef CONFIG_SOFTMMU
> > -static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
> > - .sps = {
> > - {
> > - .page_shift = 12, /* 4K */
> > - .slb_enc = 0,
> > - .enc = { { .page_shift = 12, .pte_enc = 0 },
> > - { .page_shift = 16, .pte_enc = 0x7 },
> > - { .page_shift = 24, .pte_enc = 0x38 }, },
> > - },
> > - {
> > - .page_shift = 16, /* 64K */
> > - .slb_enc = SLB_VSID_64K,
> > - .enc = { { .page_shift = 16, .pte_enc = 0x1 },
> > - { .page_shift = 24, .pte_enc = 0x8 }, },
> > - },
> > - {
> > - .page_shift = 24, /* 16M */
> > - .slb_enc = SLB_VSID_16M,
> > - .enc = { { .page_shift = 24, .pte_enc = 0 }, },
> > - },
> > - {
> > - .page_shift = 34, /* 16G */
> > - .slb_enc = SLB_VSID_16G,
> > - .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
> > - },
> > - }
> > -};
> > -#endif /* CONFIG_SOFTMMU */
> > -
> > static void init_proc_POWER7(CPUPPCState *env)
> > {
> > /* Common Registers */
> > @@ -8526,7 +8496,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> > pcc->mmu_model = POWERPC_MMU_2_06;
> > #if defined(CONFIG_SOFTMMU)
> > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> > - pcc->sps = &POWER7_POWER8_sps;
> > + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> > #endif
> > pcc->excp_model = POWERPC_EXCP_POWER7;
> > pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> > @@ -8698,7 +8668,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> > pcc->mmu_model = POWERPC_MMU_2_07;
> > #if defined(CONFIG_SOFTMMU)
> > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> > - pcc->sps = &POWER7_POWER8_sps;
> > + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> > #endif
> > pcc->excp_model = POWERPC_EXCP_POWER8;
> > pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> > @@ -8893,7 +8863,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> > #if defined(CONFIG_SOFTMMU)
> > pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
> > /* segment page size remain the same */
> > - pcc->sps = &POWER7_POWER8_sps;
> > + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> > pcc->radix_page_info = &POWER9_radix_page_info;
> > #endif
> > pcc->excp_model = POWERPC_EXCP_POWER8;
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Qemu-devel] [RFC for-2.13 07/12] target/ppc: Split page size information into a separate allocation
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 07/12] target/ppc: Split page size information into a separate allocation David Gibson
2018-03-28 7:28 ` Cédric Le Goater
@ 2018-03-28 8:15 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-28 8:15 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:36 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> env->sps contains page size encoding information as an embedded structure.
> Since this information is specific to 64-bit hash MMUs, split it out into
> a separately allocated structure, to reduce the basic env size for other
> cpus. Along the way we make a few other cleanups:
>
> * Rename to PPCHash64Options which is more in line with qemu name
> conventions, and reflects that we're going to merge some more hash64
> mmu specific details in there in future
>
> * Move structure definitions to the mmu-hash64.[ch] files.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> hw/ppc/fdt.c | 4 ++--
> target/ppc/cpu-qom.h | 4 ++--
> target/ppc/cpu.h | 22 +--------------------
> target/ppc/kvm.c | 4 ++--
> target/ppc/mmu-hash64.c | 47 ++++++++++++++++++++++++++++++++++++---------
> target/ppc/mmu-hash64.h | 21 ++++++++++++++++++++
> target/ppc/translate_init.c | 36 +++-------------------------------
> 7 files changed, 69 insertions(+), 69 deletions(-)
>
> diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
> index 2721603ffa..c4ba16f6b4 100644
> --- a/hw/ppc/fdt.c
> +++ b/hw/ppc/fdt.c
> @@ -9,6 +9,7 @@
>
> #include "qemu/osdep.h"
> #include "target/ppc/cpu.h"
> +#include "target/ppc/mmu-hash64.h"
>
> #include "hw/ppc/fdt.h"
>
> @@ -16,13 +17,12 @@
> size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
> size_t maxsize)
> {
> - CPUPPCState *env = &cpu->env;
> size_t maxcells = maxsize / sizeof(uint32_t);
> int i, j, count;
> uint32_t *p = prop;
>
> for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> - struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
> + struct ppc_one_seg_page_size *sps = &cpu->hash64_opts->sps[i];
>
> if (!sps->page_shift) {
> break;
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index 9bbb05cf62..3e5ef7375f 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -160,7 +160,7 @@ enum powerpc_input_t {
> PPC_FLAGS_INPUT_RCPU,
> };
>
> -struct ppc_segment_page_sizes;
> +typedef struct PPCHash64Options PPCHash64Options;
>
> /**
> * PowerPCCPUClass:
> @@ -194,7 +194,7 @@ typedef struct PowerPCCPUClass {
> uint32_t flags;
> int bfd_mach;
> uint32_t l1_dcache_size, l1_icache_size;
> - const struct ppc_segment_page_sizes *sps;
> + const PPCHash64Options *hash64_opts;
> struct ppc_radix_page_info *radix_page_info;
> void (*init_proc)(CPUPPCState *env);
> int (*check_pow)(CPUPPCState *env);
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index c621a6bd5e..fb6c578eb5 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -948,28 +948,8 @@ enum {
>
> #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
>
> -/*****************************************************************************/
> -/* Segment page size information, used by recent hash MMUs
> - * The format of this structure mirrors kvm_ppc_smmu_info
> - */
> -
> #define PPC_PAGE_SIZES_MAX_SZ 8
>
> -struct ppc_one_page_size {
> - uint32_t page_shift; /* Page shift (or 0) */
> - uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
> -};
> -
> -struct ppc_one_seg_page_size {
> - uint32_t page_shift; /* Base page shift of segment (or 0) */
> - uint32_t slb_enc; /* SLB encoding for BookS */
> - struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
> -};
> -
> -struct ppc_segment_page_sizes {
> - struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> -};
> -
> struct ppc_radix_page_info {
> uint32_t count;
> uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
> @@ -1106,7 +1086,6 @@ struct CPUPPCState {
> uint64_t insns_flags;
> uint64_t insns_flags2;
> #if defined(TARGET_PPC64)
> - struct ppc_segment_page_sizes sps;
> ppc_slb_t vrma_slb;
> target_ulong rmls;
> bool ci_large_pages;
> @@ -1227,6 +1206,7 @@ struct PowerPCCPU {
> PPCVirtualHypervisor *vhyp;
> Object *intc;
> int32_t node_id; /* NUMA node this CPU belongs to */
> + PPCHash64Options *hash64_opts;
>
> /* Fields related to migration compatibility hacks */
> bool pre_2_8_migration;
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 6160356a4a..01947169c9 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -442,7 +442,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> }
>
> /* Convert to QEMU form */
> - memset(&env->sps, 0, sizeof(env->sps));
> + memset(cpu->hash64_opts, 0, sizeof(*cpu->hash64_opts));
>
> /* If we have HV KVM, we need to forbid CI large pages if our
> * host page size is smaller than 64K.
> @@ -456,7 +456,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> * the selected CPU has with the capabilities that KVM supports.
> */
> for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {
> - struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];
> + struct ppc_one_seg_page_size *qsps = &cpu->hash64_opts->sps[iq];
> struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];
>
> if (!kvm_valid_page_size(smmu_info.flags, max_cpu_page_size,
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 4cb7d1cf07..d7a0e5615f 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -165,7 +165,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
> }
>
> for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> - const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
> + const struct ppc_one_seg_page_size *sps1 = &cpu->hash64_opts->sps[i];
>
> if (!sps1->page_shift) {
> break;
> @@ -552,7 +552,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
> /* If ISL is set in LPCR we need to clamp the page size to 4K */
> if (env->spr[SPR_LPCR] & LPCR_ISL) {
> /* We assume that when using TCG, 4k is first entry of SPS */
> - sps = &env->sps.sps[0];
> + sps = &cpu->hash64_opts->sps[0];
> assert(sps->page_shift == 12);
> }
>
> @@ -605,7 +605,6 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
> unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> uint64_t pte0, uint64_t pte1)
> {
> - CPUPPCState *env = &cpu->env;
> int i;
>
> if (!(pte0 & HPTE64_V_LARGE)) {
> @@ -617,7 +616,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> * this gives an unambiguous result.
> */
> for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> - const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
> + const struct ppc_one_seg_page_size *sps = &cpu->hash64_opts->sps[i];
> unsigned shift;
>
> if (!sps->page_shift) {
> @@ -1005,7 +1004,7 @@ void ppc_hash64_update_vrma(PowerPCCPU *cpu)
> esid = SLB_ESID_V;
>
> for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
> - const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
> + const struct ppc_one_seg_page_size *sps1 = &cpu->hash64_opts->sps[i];
>
> if (!sps1->page_shift) {
> break;
> @@ -1101,11 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
> CPUPPCState *env = &cpu->env;
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>
> - if (pcc->sps) {
> - env->sps = *pcc->sps;
> + if (pcc->hash64_opts) {
> + cpu->hash64_opts = g_memdup(pcc->hash64_opts,
> + sizeof(*cpu->hash64_opts));
> } else if (env->mmu_model & POWERPC_MMU_64) {
> /* Use default sets of page sizes. We don't support MPSS */
> - static const struct ppc_segment_page_sizes defsps = {
> + static const PPCHash64Options defopts = {
> .sps = {
> { .page_shift = 12, /* 4K */
> .slb_enc = 0,
> @@ -1117,10 +1117,39 @@ void ppc_hash64_init(PowerPCCPU *cpu)
> },
> },
> };
> - env->sps = defsps;
> + cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
> }
> }
>
> void ppc_hash64_finalize(PowerPCCPU *cpu)
> {
> + g_free(cpu->hash64_opts);
> }
> +
> +const PPCHash64Options ppc_hash64_opts_POWER7 = {
> + .sps = {
> + {
> + .page_shift = 12, /* 4K */
> + .slb_enc = 0,
> + .enc = { { .page_shift = 12, .pte_enc = 0 },
> + { .page_shift = 16, .pte_enc = 0x7 },
> + { .page_shift = 24, .pte_enc = 0x38 }, },
> + },
> + {
> + .page_shift = 16, /* 64K */
> + .slb_enc = SLB_VSID_64K,
> + .enc = { { .page_shift = 16, .pte_enc = 0x1 },
> + { .page_shift = 24, .pte_enc = 0x8 }, },
> + },
> + {
> + .page_shift = 24, /* 16M */
> + .slb_enc = SLB_VSID_16M,
> + .enc = { { .page_shift = 24, .pte_enc = 0 }, },
> + },
> + {
> + .page_shift = 34, /* 16G */
> + .slb_enc = SLB_VSID_16G,
> + .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
> + },
> + }
> +};
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 074ded4c27..d42cbc2762 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -136,6 +136,27 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
> return ldq_p(&(hptes[i].pte1));
> }
>
> +/*
> + * MMU Options
> + */
> +
> +struct ppc_one_page_size {
> + uint32_t page_shift; /* Page shift (or 0) */
> + uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
> +};
> +
> +struct ppc_one_seg_page_size {
> + uint32_t page_shift; /* Base page shift of segment (or 0) */
> + uint32_t slb_enc; /* SLB encoding for BookS */
> + struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
> +};
> +
> +struct PPCHash64Options {
> + struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> +};
> +
> +extern const PPCHash64Options ppc_hash64_opts_POWER7;
> +
> #endif /* CONFIG_USER_ONLY */
>
> #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index aa63a5dcb3..040d6fbac3 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8368,36 +8368,6 @@ static Property powerpc_servercpu_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -#ifdef CONFIG_SOFTMMU
> -static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
> - .sps = {
> - {
> - .page_shift = 12, /* 4K */
> - .slb_enc = 0,
> - .enc = { { .page_shift = 12, .pte_enc = 0 },
> - { .page_shift = 16, .pte_enc = 0x7 },
> - { .page_shift = 24, .pte_enc = 0x38 }, },
> - },
> - {
> - .page_shift = 16, /* 64K */
> - .slb_enc = SLB_VSID_64K,
> - .enc = { { .page_shift = 16, .pte_enc = 0x1 },
> - { .page_shift = 24, .pte_enc = 0x8 }, },
> - },
> - {
> - .page_shift = 24, /* 16M */
> - .slb_enc = SLB_VSID_16M,
> - .enc = { { .page_shift = 24, .pte_enc = 0 }, },
> - },
> - {
> - .page_shift = 34, /* 16G */
> - .slb_enc = SLB_VSID_16G,
> - .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
> - },
> - }
> -};
> -#endif /* CONFIG_SOFTMMU */
> -
> static void init_proc_POWER7(CPUPPCState *env)
> {
> /* Common Registers */
> @@ -8526,7 +8496,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> pcc->mmu_model = POWERPC_MMU_2_06;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> - pcc->sps = &POWER7_POWER8_sps;
> + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> #endif
> pcc->excp_model = POWERPC_EXCP_POWER7;
> pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> @@ -8698,7 +8668,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> pcc->mmu_model = POWERPC_MMU_2_07;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> - pcc->sps = &POWER7_POWER8_sps;
> + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> #endif
> pcc->excp_model = POWERPC_EXCP_POWER8;
> pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> @@ -8893,7 +8863,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
> /* segment page size remain the same */
> - pcc->sps = &POWER7_POWER8_sps;
> + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> pcc->radix_page_info = &POWER9_radix_page_info;
> #endif
> pcc->excp_model = POWERPC_EXCP_POWER8;
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 08/12] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (6 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 07/12] target/ppc: Split page size information into a separate allocation David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-28 7:31 ` Cédric Le Goater
2018-03-28 8:33 ` Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 09/12] target/ppc: Move 1T segment and AMR options to PPCHash64Options David Gibson
` (3 subsequent siblings)
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
Currently some cpus set the hash64_opts field in the class structure, with
specific details of their variant of the 64-bit hash mmu. For the
remaining cpus with that mmu, ppc_hash64_realize() fills in defaults.
But there are only a couple of cpus that use those fallbacks, so just have
them to set the has64_opts field instead, simplifying the logic.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/mmu-hash64.c | 36 ++++++++++++++++++------------------
target/ppc/mmu-hash64.h | 1 +
target/ppc/translate_init.c | 2 ++
3 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index d7a0e5615f..d369b1bf86 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1100,25 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- if (pcc->hash64_opts) {
- cpu->hash64_opts = g_memdup(pcc->hash64_opts,
- sizeof(*cpu->hash64_opts));
- } else if (env->mmu_model & POWERPC_MMU_64) {
- /* Use default sets of page sizes. We don't support MPSS */
- static const PPCHash64Options defopts = {
- .sps = {
- { .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 } }
- },
- { .page_shift = 24, /* 16M */
- .slb_enc = 0x100,
- .enc = { { .page_shift = 24, .pte_enc = 0 } }
- },
- },
- };
- cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
+ if (!pcc->hash64_opts) {
+ assert(!(env->mmu_model & POWERPC_MMU_64));
+ return;
}
+
+ cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts));
}
void ppc_hash64_finalize(PowerPCCPU *cpu)
@@ -1126,6 +1113,19 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
g_free(cpu->hash64_opts);
}
+const PPCHash64Options ppc_hash64_opts_basic = {
+ .sps = {
+ { .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 } }
+ },
+ { .page_shift = 24, /* 16M */
+ .slb_enc = 0x100,
+ .enc = { { .page_shift = 24, .pte_enc = 0 } }
+ },
+ },
+};
+
const PPCHash64Options ppc_hash64_opts_POWER7 = {
.sps = {
{
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index d42cbc2762..ff0c48af55 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -155,6 +155,7 @@ struct PPCHash64Options {
struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
};
+extern const PPCHash64Options ppc_hash64_opts_basic;
extern const PPCHash64Options ppc_hash64_opts_POWER7;
#endif /* CONFIG_USER_ONLY */
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 040d6fbac3..ae005b2a54 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8242,6 +8242,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_64B;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->hash64_opts = &ppc_hash64_opts_basic;
#endif
pcc->excp_model = POWERPC_EXCP_970;
pcc->bus_model = PPC_FLAGS_INPUT_970;
@@ -8319,6 +8320,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_03;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->hash64_opts = &ppc_hash64_opts_basic;
#endif
pcc->excp_model = POWERPC_EXCP_970;
pcc->bus_model = PPC_FLAGS_INPUT_970;
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 08/12] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 08/12] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs David Gibson
@ 2018-03-28 7:31 ` Cédric Le Goater
2018-03-28 8:33 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-28 7:31 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> Currently some cpus set the hash64_opts field in the class structure, with
> specific details of their variant of the 64-bit hash mmu. For the
> remaining cpus with that mmu, ppc_hash64_realize() fills in defaults.
>
> But there are only a couple of cpus that use those fallbacks, so just have
> them to set the has64_opts field instead, simplifying the logic.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/mmu-hash64.c | 36 ++++++++++++++++++------------------
> target/ppc/mmu-hash64.h | 1 +
> target/ppc/translate_init.c | 2 ++
> 3 files changed, 21 insertions(+), 18 deletions(-)
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index d7a0e5615f..d369b1bf86 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1100,25 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
> CPUPPCState *env = &cpu->env;
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>
> - if (pcc->hash64_opts) {
> - cpu->hash64_opts = g_memdup(pcc->hash64_opts,
> - sizeof(*cpu->hash64_opts));
> - } else if (env->mmu_model & POWERPC_MMU_64) {
> - /* Use default sets of page sizes. We don't support MPSS */
> - static const PPCHash64Options defopts = {
> - .sps = {
> - { .page_shift = 12, /* 4K */
> - .slb_enc = 0,
> - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> - },
> - { .page_shift = 24, /* 16M */
> - .slb_enc = 0x100,
> - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> - },
> - },
> - };
> - cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
> + if (!pcc->hash64_opts) {
> + assert(!(env->mmu_model & POWERPC_MMU_64));
> + return;
> }
> +
> + cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts));
> }
>
> void ppc_hash64_finalize(PowerPCCPU *cpu)
> @@ -1126,6 +1113,19 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
> g_free(cpu->hash64_opts);
> }
>
> +const PPCHash64Options ppc_hash64_opts_basic = {
> + .sps = {
> + { .page_shift = 12, /* 4K */
> + .slb_enc = 0,
> + .enc = { { .page_shift = 12, .pte_enc = 0 } }
> + },
> + { .page_shift = 24, /* 16M */
> + .slb_enc = 0x100,
> + .enc = { { .page_shift = 24, .pte_enc = 0 } }
> + },
> + },
> +};
> +
> const PPCHash64Options ppc_hash64_opts_POWER7 = {
> .sps = {
> {
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index d42cbc2762..ff0c48af55 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -155,6 +155,7 @@ struct PPCHash64Options {
> struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> };
>
> +extern const PPCHash64Options ppc_hash64_opts_basic;
> extern const PPCHash64Options ppc_hash64_opts_POWER7;
>
> #endif /* CONFIG_USER_ONLY */
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 040d6fbac3..ae005b2a54 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8242,6 +8242,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
> pcc->mmu_model = POWERPC_MMU_64B;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> + pcc->hash64_opts = &ppc_hash64_opts_basic;
> #endif
> pcc->excp_model = POWERPC_EXCP_970;
> pcc->bus_model = PPC_FLAGS_INPUT_970;
> @@ -8319,6 +8320,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> pcc->mmu_model = POWERPC_MMU_2_03;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> + pcc->hash64_opts = &ppc_hash64_opts_basic;
> #endif
> pcc->excp_model = POWERPC_EXCP_970;
> pcc->bus_model = PPC_FLAGS_INPUT_970;
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 08/12] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 08/12] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs David Gibson
2018-03-28 7:31 ` Cédric Le Goater
@ 2018-03-28 8:33 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-28 8:33 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:37 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> Currently some cpus set the hash64_opts field in the class structure, with
> specific details of their variant of the 64-bit hash mmu. For the
> remaining cpus with that mmu, ppc_hash64_realize() fills in defaults.
>
> But there are only a couple of cpus that use those fallbacks, so just have
> them to set the has64_opts field instead, simplifying the logic.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> target/ppc/mmu-hash64.c | 36 ++++++++++++++++++------------------
> target/ppc/mmu-hash64.h | 1 +
> target/ppc/translate_init.c | 2 ++
> 3 files changed, 21 insertions(+), 18 deletions(-)
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index d7a0e5615f..d369b1bf86 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1100,25 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
> CPUPPCState *env = &cpu->env;
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>
> - if (pcc->hash64_opts) {
> - cpu->hash64_opts = g_memdup(pcc->hash64_opts,
> - sizeof(*cpu->hash64_opts));
> - } else if (env->mmu_model & POWERPC_MMU_64) {
> - /* Use default sets of page sizes. We don't support MPSS */
> - static const PPCHash64Options defopts = {
> - .sps = {
> - { .page_shift = 12, /* 4K */
> - .slb_enc = 0,
> - .enc = { { .page_shift = 12, .pte_enc = 0 } }
> - },
> - { .page_shift = 24, /* 16M */
> - .slb_enc = 0x100,
> - .enc = { { .page_shift = 24, .pte_enc = 0 } }
> - },
> - },
> - };
> - cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
> + if (!pcc->hash64_opts) {
> + assert(!(env->mmu_model & POWERPC_MMU_64));
> + return;
> }
> +
> + cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts));
> }
>
> void ppc_hash64_finalize(PowerPCCPU *cpu)
> @@ -1126,6 +1113,19 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
> g_free(cpu->hash64_opts);
> }
>
> +const PPCHash64Options ppc_hash64_opts_basic = {
> + .sps = {
> + { .page_shift = 12, /* 4K */
> + .slb_enc = 0,
> + .enc = { { .page_shift = 12, .pte_enc = 0 } }
> + },
> + { .page_shift = 24, /* 16M */
> + .slb_enc = 0x100,
> + .enc = { { .page_shift = 24, .pte_enc = 0 } }
> + },
> + },
> +};
> +
> const PPCHash64Options ppc_hash64_opts_POWER7 = {
> .sps = {
> {
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index d42cbc2762..ff0c48af55 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -155,6 +155,7 @@ struct PPCHash64Options {
> struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> };
>
> +extern const PPCHash64Options ppc_hash64_opts_basic;
> extern const PPCHash64Options ppc_hash64_opts_POWER7;
>
> #endif /* CONFIG_USER_ONLY */
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 040d6fbac3..ae005b2a54 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8242,6 +8242,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
> pcc->mmu_model = POWERPC_MMU_64B;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> + pcc->hash64_opts = &ppc_hash64_opts_basic;
> #endif
> pcc->excp_model = POWERPC_EXCP_970;
> pcc->bus_model = PPC_FLAGS_INPUT_970;
> @@ -8319,6 +8320,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> pcc->mmu_model = POWERPC_MMU_2_03;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> + pcc->hash64_opts = &ppc_hash64_opts_basic;
> #endif
> pcc->excp_model = POWERPC_EXCP_970;
> pcc->bus_model = PPC_FLAGS_INPUT_970;
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 09/12] target/ppc: Move 1T segment and AMR options to PPCHash64Options
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (7 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 08/12] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-28 7:40 ` Cédric Le Goater
2018-03-28 8:48 ` Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 10/12] target/ppc: Fold ci_large_pages flag into PPCHash64Options David Gibson
` (2 subsequent siblings)
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
MMU types, with various flag bits as well. This makes which bits of the
field should be compared pretty confusing.
Make a start on cleaning that up by moving two of the flags bits -
POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit
hash MMU into a new flags field in PPCHash64Options structure.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 3 ++-
hw/ppc/spapr.c | 2 +-
target/ppc/cpu-qom.h | 11 +++--------
target/ppc/kvm.c | 4 ++--
target/ppc/mmu-hash64.c | 6 ++++--
target/ppc/mmu-hash64.h | 3 +++
6 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5a79b24828..0aa878b771 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -36,6 +36,7 @@
#include "monitor/monitor.h"
#include "hw/intc/intc.h"
#include "hw/ipmi/ipmi.h"
+#include "target/ppc/mmu-hash64.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/pnv_xscom.h"
@@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
_FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
}
- if (env->mmu_model & POWERPC_MMU_1TSEG) {
+ if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
_FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
segs, sizeof(segs))));
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a35bffd524..436ed39f7f 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
_FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
}
- if (env->mmu_model & POWERPC_MMU_1TSEG) {
+ if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
_FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
segs, sizeof(segs))));
}
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 3e5ef7375f..2bd58b2a84 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -68,22 +68,17 @@ enum powerpc_mmu_t {
/* PowerPC 601 MMU model (specific BATs format) */
POWERPC_MMU_601 = 0x0000000A,
#define POWERPC_MMU_64 0x00010000
-#define POWERPC_MMU_1TSEG 0x00020000
-#define POWERPC_MMU_AMR 0x00040000
#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
- POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_AMR | 0x00000003,
+ POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
/* Architecture 2.07 variant */
- POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_AMR | 0x00000004,
+ POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
/* Architecture 3.00 variant */
- POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_AMR | POWERPC_MMU_V3
+ POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
| 0x00000005,
};
#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 01947169c9..3424917381 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
/* HV KVM has backing store size restrictions */
info->flags = KVM_PPC_PAGE_SIZES_REAL;
- if (env->mmu_model & POWERPC_MMU_1TSEG) {
+ if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
info->flags |= KVM_PPC_1T_SEGMENTS;
}
@@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
}
env->slb_nr = smmu_info.slb_size;
if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
- env->mmu_model &= ~POWERPC_MMU_1TSEG;
+ cpu->hash64_opts->flags &= ~PPC_HASH64_1TSEG;
}
}
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index d369b1bf86..1d785f50d7 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
return -1; /* Bad segment size */
}
- if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
+ if ((vsid & SLB_VSID_B) && !(cpu->hash64_opts->flags & PPC_HASH64_1TSEG)) {
return -1; /* 1T segment on MMU that doesn't support it */
}
@@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
/* Only recent MMUs implement Virtual Page Class Key Protection */
- if (!(env->mmu_model & POWERPC_MMU_AMR)) {
+ if (!(cpu->hash64_opts->flags & PPC_HASH64_AMR)) {
return prot;
}
@@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
}
const PPCHash64Options ppc_hash64_opts_basic = {
+ .flags = 0,
.sps = {
{ .page_shift = 12, /* 4K */
.slb_enc = 0,
@@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
};
const PPCHash64Options ppc_hash64_opts_POWER7 = {
+ .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
.sps = {
{
.page_shift = 12, /* 4K */
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index ff0c48af55..6cfca97a60 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -152,6 +152,9 @@ struct ppc_one_seg_page_size {
};
struct PPCHash64Options {
+#define PPC_HASH64_1TSEG 0x00001
+#define PPC_HASH64_AMR 0x00002
+ unsigned flags;
struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
};
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 09/12] target/ppc: Move 1T segment and AMR options to PPCHash64Options
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 09/12] target/ppc: Move 1T segment and AMR options to PPCHash64Options David Gibson
@ 2018-03-28 7:40 ` Cédric Le Goater
2018-03-29 4:57 ` David Gibson
2018-03-28 8:48 ` Greg Kurz
1 sibling, 1 reply; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-28 7:40 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
> MMU types, with various flag bits as well. This makes which bits of the
> field should be compared pretty confusing.
>
> Make a start on cleaning that up by moving two of the flags bits -
> POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit
> hash MMU into a new flags field in PPCHash64Options structure.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Maybe introduce a small helper :
#define ppc_hash64_has(cpu, opt) ((cpu)->hash64_opts->flags & (opt))
Thanks,
C.
> ---
> hw/ppc/pnv.c | 3 ++-
> hw/ppc/spapr.c | 2 +-
> target/ppc/cpu-qom.h | 11 +++--------
> target/ppc/kvm.c | 4 ++--
> target/ppc/mmu-hash64.c | 6 ++++--
> target/ppc/mmu-hash64.h | 3 +++
> 6 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 5a79b24828..0aa878b771 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -36,6 +36,7 @@
> #include "monitor/monitor.h"
> #include "hw/intc/intc.h"
> #include "hw/ipmi/ipmi.h"
> +#include "target/ppc/mmu-hash64.h"
>
> #include "hw/ppc/xics.h"
> #include "hw/ppc/pnv_xscom.h"
> @@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
> _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
> }
>
> - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
> segs, sizeof(segs))));
> }
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index a35bffd524..436ed39f7f 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
> _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
> }
>
> - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
> segs, sizeof(segs))));
> }
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index 3e5ef7375f..2bd58b2a84 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -68,22 +68,17 @@ enum powerpc_mmu_t {
> /* PowerPC 601 MMU model (specific BATs format) */
> POWERPC_MMU_601 = 0x0000000A,
> #define POWERPC_MMU_64 0x00010000
> -#define POWERPC_MMU_1TSEG 0x00020000
> -#define POWERPC_MMU_AMR 0x00040000
> #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> /* 64 bits PowerPC MMU */
> POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> /* Architecture 2.03 and later (has LPCR) */
> POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
> /* Architecture 2.06 variant */
> - POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_AMR | 0x00000003,
> + POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
> /* Architecture 2.07 variant */
> - POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_AMR | 0x00000004,
> + POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
> /* Architecture 3.00 variant */
> - POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_AMR | POWERPC_MMU_V3
> + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
> | 0x00000005,
> };
> #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 01947169c9..3424917381 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
> /* HV KVM has backing store size restrictions */
> info->flags = KVM_PPC_PAGE_SIZES_REAL;
>
> - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> info->flags |= KVM_PPC_1T_SEGMENTS;
> }
>
> @@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> }
> env->slb_nr = smmu_info.slb_size;
> if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
> - env->mmu_model &= ~POWERPC_MMU_1TSEG;
> + cpu->hash64_opts->flags &= ~PPC_HASH64_1TSEG;
> }
> }
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index d369b1bf86..1d785f50d7 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
> if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
> return -1; /* Bad segment size */
> }
> - if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
> + if ((vsid & SLB_VSID_B) && !(cpu->hash64_opts->flags & PPC_HASH64_1TSEG)) {
> return -1; /* 1T segment on MMU that doesn't support it */
> }
>
> @@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
> int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>
> /* Only recent MMUs implement Virtual Page Class Key Protection */
> - if (!(env->mmu_model & POWERPC_MMU_AMR)) {
> + if (!(cpu->hash64_opts->flags & PPC_HASH64_AMR)) {
> return prot;
> }
>
> @@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
> }
>
> const PPCHash64Options ppc_hash64_opts_basic = {
> + .flags = 0,
> .sps = {
> { .page_shift = 12, /* 4K */
> .slb_enc = 0,
> @@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
> };
>
> const PPCHash64Options ppc_hash64_opts_POWER7 = {
> + .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
> .sps = {
> {
> .page_shift = 12, /* 4K */
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index ff0c48af55..6cfca97a60 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -152,6 +152,9 @@ struct ppc_one_seg_page_size {
> };
>
> struct PPCHash64Options {
> +#define PPC_HASH64_1TSEG 0x00001
> +#define PPC_HASH64_AMR 0x00002
> + unsigned flags;
> struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> };
>
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 09/12] target/ppc: Move 1T segment and AMR options to PPCHash64Options
2018-03-28 7:40 ` Cédric Le Goater
@ 2018-03-29 4:57 ` David Gibson
0 siblings, 0 replies; 45+ messages in thread
From: David Gibson @ 2018-03-29 4:57 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, groug, agraf, qemu-devel, benh, bharata
[-- Attachment #1: Type: text/plain, Size: 7483 bytes --]
On Wed, Mar 28, 2018 at 09:40:13AM +0200, Cédric Le Goater wrote:
> On 03/27/2018 06:37 AM, David Gibson wrote:
> > Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
> > MMU types, with various flag bits as well. This makes which bits of the
> > field should be compared pretty confusing.
> >
> > Make a start on cleaning that up by moving two of the flags bits -
> > POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit
> > hash MMU into a new flags field in PPCHash64Options structure.
> >
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>
> Maybe introduce a small helper :
>
> #define ppc_hash64_has(cpu, opt) ((cpu)->hash64_opts->flags &
> (opt))
Good idea, that makes things rather nicer. I'll include it in the
next spin.
>
> Thanks,
>
> C.
>
> > ---
> > hw/ppc/pnv.c | 3 ++-
> > hw/ppc/spapr.c | 2 +-
> > target/ppc/cpu-qom.h | 11 +++--------
> > target/ppc/kvm.c | 4 ++--
> > target/ppc/mmu-hash64.c | 6 ++++--
> > target/ppc/mmu-hash64.h | 3 +++
> > 6 files changed, 15 insertions(+), 14 deletions(-)
> >
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index 5a79b24828..0aa878b771 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -36,6 +36,7 @@
> > #include "monitor/monitor.h"
> > #include "hw/intc/intc.h"
> > #include "hw/ipmi/ipmi.h"
> > +#include "target/ppc/mmu-hash64.h"
> >
> > #include "hw/ppc/xics.h"
> > #include "hw/ppc/pnv_xscom.h"
> > @@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
> > _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
> > }
> >
> > - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> > + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> > _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
> > segs, sizeof(segs))));
> > }
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index a35bffd524..436ed39f7f 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
> > _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
> > }
> >
> > - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> > + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> > _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
> > segs, sizeof(segs))));
> > }
> > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> > index 3e5ef7375f..2bd58b2a84 100644
> > --- a/target/ppc/cpu-qom.h
> > +++ b/target/ppc/cpu-qom.h
> > @@ -68,22 +68,17 @@ enum powerpc_mmu_t {
> > /* PowerPC 601 MMU model (specific BATs format) */
> > POWERPC_MMU_601 = 0x0000000A,
> > #define POWERPC_MMU_64 0x00010000
> > -#define POWERPC_MMU_1TSEG 0x00020000
> > -#define POWERPC_MMU_AMR 0x00040000
> > #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> > /* 64 bits PowerPC MMU */
> > POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> > /* Architecture 2.03 and later (has LPCR) */
> > POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
> > /* Architecture 2.06 variant */
> > - POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > - | POWERPC_MMU_AMR | 0x00000003,
> > + POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
> > /* Architecture 2.07 variant */
> > - POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > - | POWERPC_MMU_AMR | 0x00000004,
> > + POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
> > /* Architecture 3.00 variant */
> > - POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > - | POWERPC_MMU_AMR | POWERPC_MMU_V3
> > + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
> > | 0x00000005,
> > };
> > #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
> > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> > index 01947169c9..3424917381 100644
> > --- a/target/ppc/kvm.c
> > +++ b/target/ppc/kvm.c
> > @@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
> > /* HV KVM has backing store size restrictions */
> > info->flags = KVM_PPC_PAGE_SIZES_REAL;
> >
> > - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> > + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> > info->flags |= KVM_PPC_1T_SEGMENTS;
> > }
> >
> > @@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> > }
> > env->slb_nr = smmu_info.slb_size;
> > if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
> > - env->mmu_model &= ~POWERPC_MMU_1TSEG;
> > + cpu->hash64_opts->flags &= ~PPC_HASH64_1TSEG;
> > }
> > }
> >
> > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> > index d369b1bf86..1d785f50d7 100644
> > --- a/target/ppc/mmu-hash64.c
> > +++ b/target/ppc/mmu-hash64.c
> > @@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
> > if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
> > return -1; /* Bad segment size */
> > }
> > - if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
> > + if ((vsid & SLB_VSID_B) && !(cpu->hash64_opts->flags & PPC_HASH64_1TSEG)) {
> > return -1; /* 1T segment on MMU that doesn't support it */
> > }
> >
> > @@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
> > int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> >
> > /* Only recent MMUs implement Virtual Page Class Key Protection */
> > - if (!(env->mmu_model & POWERPC_MMU_AMR)) {
> > + if (!(cpu->hash64_opts->flags & PPC_HASH64_AMR)) {
> > return prot;
> > }
> >
> > @@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
> > }
> >
> > const PPCHash64Options ppc_hash64_opts_basic = {
> > + .flags = 0,
> > .sps = {
> > { .page_shift = 12, /* 4K */
> > .slb_enc = 0,
> > @@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
> > };
> >
> > const PPCHash64Options ppc_hash64_opts_POWER7 = {
> > + .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
> > .sps = {
> > {
> > .page_shift = 12, /* 4K */
> > diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> > index ff0c48af55..6cfca97a60 100644
> > --- a/target/ppc/mmu-hash64.h
> > +++ b/target/ppc/mmu-hash64.h
> > @@ -152,6 +152,9 @@ struct ppc_one_seg_page_size {
> > };
> >
> > struct PPCHash64Options {
> > +#define PPC_HASH64_1TSEG 0x00001
> > +#define PPC_HASH64_AMR 0x00002
> > + unsigned flags;
> > struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> > };
> >
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Qemu-devel] [RFC for-2.13 09/12] target/ppc: Move 1T segment and AMR options to PPCHash64Options
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 09/12] target/ppc: Move 1T segment and AMR options to PPCHash64Options David Gibson
2018-03-28 7:40 ` Cédric Le Goater
@ 2018-03-28 8:48 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-28 8:48 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:38 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
> MMU types, with various flag bits as well. This makes which bits of the
> field should be compared pretty confusing.
>
> Make a start on cleaning that up by moving two of the flags bits -
> POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit
> hash MMU into a new flags field in PPCHash64Options structure.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> hw/ppc/pnv.c | 3 ++-
> hw/ppc/spapr.c | 2 +-
> target/ppc/cpu-qom.h | 11 +++--------
> target/ppc/kvm.c | 4 ++--
> target/ppc/mmu-hash64.c | 6 ++++--
> target/ppc/mmu-hash64.h | 3 +++
> 6 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 5a79b24828..0aa878b771 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -36,6 +36,7 @@
> #include "monitor/monitor.h"
> #include "hw/intc/intc.h"
> #include "hw/ipmi/ipmi.h"
> +#include "target/ppc/mmu-hash64.h"
>
> #include "hw/ppc/xics.h"
> #include "hw/ppc/pnv_xscom.h"
> @@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
> _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
> }
>
> - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
> segs, sizeof(segs))));
> }
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index a35bffd524..436ed39f7f 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
> _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
> }
>
> - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
> segs, sizeof(segs))));
> }
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index 3e5ef7375f..2bd58b2a84 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -68,22 +68,17 @@ enum powerpc_mmu_t {
> /* PowerPC 601 MMU model (specific BATs format) */
> POWERPC_MMU_601 = 0x0000000A,
> #define POWERPC_MMU_64 0x00010000
> -#define POWERPC_MMU_1TSEG 0x00020000
> -#define POWERPC_MMU_AMR 0x00040000
> #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> /* 64 bits PowerPC MMU */
> POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> /* Architecture 2.03 and later (has LPCR) */
> POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
> /* Architecture 2.06 variant */
> - POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_AMR | 0x00000003,
> + POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
> /* Architecture 2.07 variant */
> - POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_AMR | 0x00000004,
> + POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
> /* Architecture 3.00 variant */
> - POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> - | POWERPC_MMU_AMR | POWERPC_MMU_V3
> + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
> | 0x00000005,
> };
> #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 01947169c9..3424917381 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
> /* HV KVM has backing store size restrictions */
> info->flags = KVM_PPC_PAGE_SIZES_REAL;
>
> - if (env->mmu_model & POWERPC_MMU_1TSEG) {
> + if (cpu->hash64_opts->flags & PPC_HASH64_1TSEG) {
> info->flags |= KVM_PPC_1T_SEGMENTS;
> }
>
> @@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> }
> env->slb_nr = smmu_info.slb_size;
> if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
> - env->mmu_model &= ~POWERPC_MMU_1TSEG;
> + cpu->hash64_opts->flags &= ~PPC_HASH64_1TSEG;
> }
> }
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index d369b1bf86..1d785f50d7 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
> if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
> return -1; /* Bad segment size */
> }
> - if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
> + if ((vsid & SLB_VSID_B) && !(cpu->hash64_opts->flags & PPC_HASH64_1TSEG)) {
> return -1; /* 1T segment on MMU that doesn't support it */
> }
>
> @@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
> int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>
> /* Only recent MMUs implement Virtual Page Class Key Protection */
> - if (!(env->mmu_model & POWERPC_MMU_AMR)) {
> + if (!(cpu->hash64_opts->flags & PPC_HASH64_AMR)) {
> return prot;
> }
>
> @@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
> }
>
> const PPCHash64Options ppc_hash64_opts_basic = {
> + .flags = 0,
> .sps = {
> { .page_shift = 12, /* 4K */
> .slb_enc = 0,
> @@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
> };
>
> const PPCHash64Options ppc_hash64_opts_POWER7 = {
> + .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
> .sps = {
> {
> .page_shift = 12, /* 4K */
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index ff0c48af55..6cfca97a60 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -152,6 +152,9 @@ struct ppc_one_seg_page_size {
> };
>
> struct PPCHash64Options {
> +#define PPC_HASH64_1TSEG 0x00001
> +#define PPC_HASH64_AMR 0x00002
> + unsigned flags;
> struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> };
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 10/12] target/ppc: Fold ci_large_pages flag into PPCHash64Options
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (8 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 09/12] target/ppc: Move 1T segment and AMR options to PPCHash64Options David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-28 7:41 ` Cédric Le Goater
2018-03-28 8:50 ` Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model David Gibson
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 12/12] target/ppc: Get rid of POWERPC_MMU_VER() macros David Gibson
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash
MMU machines, indicating whether it's possible to map large (> 4kiB) pages
as cache-inhibitied (i.e. for IO, rather than memory). Fold it as another
flag into the PPCHash64Options structure.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 3 +--
target/ppc/cpu.h | 1 -
target/ppc/kvm.c | 6 +++++-
target/ppc/mmu-hash64.c | 2 +-
target/ppc/mmu-hash64.h | 1 +
target/ppc/translate_init.c | 3 ---
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 436ed39f7f..95063df54d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -263,7 +263,6 @@ static void spapr_populate_pa_features(sPAPRMachineState *spapr,
void *fdt, int offset,
bool legacy_guest)
{
- CPUPPCState *env = &cpu->env;
uint8_t pa_features_206[] = { 6, 0,
0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
uint8_t pa_features_207[] = { 24, 0,
@@ -315,7 +314,7 @@ static void spapr_populate_pa_features(sPAPRMachineState *spapr,
return;
}
- if (env->ci_large_pages) {
+ if (cpu->hash64_opts->flags & PPC_HASH64_CI_LARGEPAGE) {
/*
* Note: we keep CI large pages off by default because a 64K capable
* guest provisioned with large pages might otherwise try to map a qemu
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index fb6c578eb5..76ce67e9de 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1088,7 +1088,6 @@ struct CPUPPCState {
#if defined(TARGET_PPC64)
ppc_slb_t vrma_slb;
target_ulong rmls;
- bool ci_large_pages;
#endif
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 3424917381..6c45815ee6 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -448,7 +448,11 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
* host page size is smaller than 64K.
*/
if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) {
- env->ci_large_pages = getpagesize() >= 0x10000;
+ if (getpagesize() >= 0x10000) {
+ cpu->hash64_opts->flags |= PPC_HASH64_CI_LARGEPAGE;
+ } else {
+ cpu->hash64_opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
+ }
}
/*
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 1d785f50d7..3b00bdee91 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1128,7 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
};
const PPCHash64Options ppc_hash64_opts_POWER7 = {
- .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
+ .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
.sps = {
{
.page_shift = 12, /* 4K */
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 6cfca97a60..cddfe06a8b 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -154,6 +154,7 @@ struct ppc_one_seg_page_size {
struct PPCHash64Options {
#define PPC_HASH64_1TSEG 0x00001
#define PPC_HASH64_AMR 0x00002
+#define PPC_HASH64_CI_LARGEPAGE 0x00004
unsigned flags;
struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
};
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index ae005b2a54..a925cf5cd3 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8392,7 +8392,6 @@ static void init_proc_POWER7(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8547,7 +8546,6 @@ static void init_proc_POWER8(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8748,7 +8746,6 @@ static void init_proc_POWER9(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 10/12] target/ppc: Fold ci_large_pages flag into PPCHash64Options
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 10/12] target/ppc: Fold ci_large_pages flag into PPCHash64Options David Gibson
@ 2018-03-28 7:41 ` Cédric Le Goater
2018-03-28 8:50 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-28 7:41 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash
> MMU machines, indicating whether it's possible to map large (> 4kiB) pages
> as cache-inhibitied (i.e. for IO, rather than memory). Fold it as another
> flag into the PPCHash64Options structure.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/spapr.c | 3 +--
> target/ppc/cpu.h | 1 -
> target/ppc/kvm.c | 6 +++++-
> target/ppc/mmu-hash64.c | 2 +-
> target/ppc/mmu-hash64.h | 1 +
> target/ppc/translate_init.c | 3 ---
> 6 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 436ed39f7f..95063df54d 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -263,7 +263,6 @@ static void spapr_populate_pa_features(sPAPRMachineState *spapr,
> void *fdt, int offset,
> bool legacy_guest)
> {
> - CPUPPCState *env = &cpu->env;
> uint8_t pa_features_206[] = { 6, 0,
> 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
> uint8_t pa_features_207[] = { 24, 0,
> @@ -315,7 +314,7 @@ static void spapr_populate_pa_features(sPAPRMachineState *spapr,
> return;
> }
>
> - if (env->ci_large_pages) {
> + if (cpu->hash64_opts->flags & PPC_HASH64_CI_LARGEPAGE) {
> /*
> * Note: we keep CI large pages off by default because a 64K capable
> * guest provisioned with large pages might otherwise try to map a qemu
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index fb6c578eb5..76ce67e9de 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1088,7 +1088,6 @@ struct CPUPPCState {
> #if defined(TARGET_PPC64)
> ppc_slb_t vrma_slb;
> target_ulong rmls;
> - bool ci_large_pages;
> #endif
>
> #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 3424917381..6c45815ee6 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -448,7 +448,11 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> * host page size is smaller than 64K.
> */
> if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) {
> - env->ci_large_pages = getpagesize() >= 0x10000;
> + if (getpagesize() >= 0x10000) {
> + cpu->hash64_opts->flags |= PPC_HASH64_CI_LARGEPAGE;
> + } else {
> + cpu->hash64_opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
> + }
> }
>
> /*
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 1d785f50d7..3b00bdee91 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1128,7 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
> };
>
> const PPCHash64Options ppc_hash64_opts_POWER7 = {
> - .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
> + .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
> .sps = {
> {
> .page_shift = 12, /* 4K */
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 6cfca97a60..cddfe06a8b 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -154,6 +154,7 @@ struct ppc_one_seg_page_size {
> struct PPCHash64Options {
> #define PPC_HASH64_1TSEG 0x00001
> #define PPC_HASH64_AMR 0x00002
> +#define PPC_HASH64_CI_LARGEPAGE 0x00004
> unsigned flags;
> struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> };
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index ae005b2a54..a925cf5cd3 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8392,7 +8392,6 @@ static void init_proc_POWER7(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->slb_nr = 32;
> #endif
> - env->ci_large_pages = true;
> env->dcache_line_size = 128;
> env->icache_line_size = 128;
>
> @@ -8547,7 +8546,6 @@ static void init_proc_POWER8(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->slb_nr = 32;
> #endif
> - env->ci_large_pages = true;
> env->dcache_line_size = 128;
> env->icache_line_size = 128;
>
> @@ -8748,7 +8746,6 @@ static void init_proc_POWER9(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->slb_nr = 32;
> #endif
> - env->ci_large_pages = true;
> env->dcache_line_size = 128;
> env->icache_line_size = 128;
>
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 10/12] target/ppc: Fold ci_large_pages flag into PPCHash64Options
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 10/12] target/ppc: Fold ci_large_pages flag into PPCHash64Options David Gibson
2018-03-28 7:41 ` Cédric Le Goater
@ 2018-03-28 8:50 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-28 8:50 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:39 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash
> MMU machines, indicating whether it's possible to map large (> 4kiB) pages
> as cache-inhibitied (i.e. for IO, rather than memory). Fold it as another
> flag into the PPCHash64Options structure.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> hw/ppc/spapr.c | 3 +--
> target/ppc/cpu.h | 1 -
> target/ppc/kvm.c | 6 +++++-
> target/ppc/mmu-hash64.c | 2 +-
> target/ppc/mmu-hash64.h | 1 +
> target/ppc/translate_init.c | 3 ---
> 6 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 436ed39f7f..95063df54d 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -263,7 +263,6 @@ static void spapr_populate_pa_features(sPAPRMachineState *spapr,
> void *fdt, int offset,
> bool legacy_guest)
> {
> - CPUPPCState *env = &cpu->env;
> uint8_t pa_features_206[] = { 6, 0,
> 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
> uint8_t pa_features_207[] = { 24, 0,
> @@ -315,7 +314,7 @@ static void spapr_populate_pa_features(sPAPRMachineState *spapr,
> return;
> }
>
> - if (env->ci_large_pages) {
> + if (cpu->hash64_opts->flags & PPC_HASH64_CI_LARGEPAGE) {
> /*
> * Note: we keep CI large pages off by default because a 64K capable
> * guest provisioned with large pages might otherwise try to map a qemu
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index fb6c578eb5..76ce67e9de 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1088,7 +1088,6 @@ struct CPUPPCState {
> #if defined(TARGET_PPC64)
> ppc_slb_t vrma_slb;
> target_ulong rmls;
> - bool ci_large_pages;
> #endif
>
> #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 3424917381..6c45815ee6 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -448,7 +448,11 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
> * host page size is smaller than 64K.
> */
> if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) {
> - env->ci_large_pages = getpagesize() >= 0x10000;
> + if (getpagesize() >= 0x10000) {
> + cpu->hash64_opts->flags |= PPC_HASH64_CI_LARGEPAGE;
> + } else {
> + cpu->hash64_opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
> + }
> }
>
> /*
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 1d785f50d7..3b00bdee91 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1128,7 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
> };
>
> const PPCHash64Options ppc_hash64_opts_POWER7 = {
> - .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
> + .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
> .sps = {
> {
> .page_shift = 12, /* 4K */
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 6cfca97a60..cddfe06a8b 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -154,6 +154,7 @@ struct ppc_one_seg_page_size {
> struct PPCHash64Options {
> #define PPC_HASH64_1TSEG 0x00001
> #define PPC_HASH64_AMR 0x00002
> +#define PPC_HASH64_CI_LARGEPAGE 0x00004
> unsigned flags;
> struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
> };
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index ae005b2a54..a925cf5cd3 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8392,7 +8392,6 @@ static void init_proc_POWER7(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->slb_nr = 32;
> #endif
> - env->ci_large_pages = true;
> env->dcache_line_size = 128;
> env->icache_line_size = 128;
>
> @@ -8547,7 +8546,6 @@ static void init_proc_POWER8(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->slb_nr = 32;
> #endif
> - env->ci_large_pages = true;
> env->dcache_line_size = 128;
> env->icache_line_size = 128;
>
> @@ -8748,7 +8746,6 @@ static void init_proc_POWER9(CPUPPCState *env)
> #if !defined(CONFIG_USER_ONLY)
> env->slb_nr = 32;
> #endif
> - env->ci_large_pages = true;
> env->dcache_line_size = 128;
> env->icache_line_size = 128;
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (9 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 10/12] target/ppc: Fold ci_large_pages flag into PPCHash64Options David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-28 7:43 ` Cédric Le Goater
2018-03-28 9:10 ` Greg Kurz
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 12/12] target/ppc: Get rid of POWERPC_MMU_VER() macros David Gibson
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
The only place we test this flag is in conjunction with
ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-qom.h | 4 +---
target/ppc/mmu-hash64.c | 2 +-
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 2bd58b2a84..ef96d42cf2 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -68,7 +68,6 @@ enum powerpc_mmu_t {
/* PowerPC 601 MMU model (specific BATs format) */
POWERPC_MMU_601 = 0x0000000A,
#define POWERPC_MMU_64 0x00010000
-#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
@@ -78,8 +77,7 @@ enum powerpc_mmu_t {
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
/* Architecture 3.00 variant */
- POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
- | 0x00000005,
+ POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
};
#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 3b00bdee91..d964f2f5b0 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -761,7 +761,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
slb = slb_lookup(cpu, eaddr);
if (!slb) {
/* No entry found, check if in-memory segment tables are in use */
- if ((env->mmu_model & POWERPC_MMU_V3) && ppc64_use_proc_tbl(cpu)) {
+ if (ppc64_use_proc_tbl(cpu)) {
/* TODO - Unsupported */
error_report("Segment Table Support Unimplemented");
exit(1);
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model David Gibson
@ 2018-03-28 7:43 ` Cédric Le Goater
2018-03-28 7:49 ` Cédric Le Goater
2018-03-28 9:10 ` Greg Kurz
1 sibling, 1 reply; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-28 7:43 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> The only place we test this flag is in conjunction with
> ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
> ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
hmm, ok, but what will I use for the PowerNV hash MMU support then ?
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
C.
> ---
> target/ppc/cpu-qom.h | 4 +---
> target/ppc/mmu-hash64.c | 2 +-
> 2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index 2bd58b2a84..ef96d42cf2 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -68,7 +68,6 @@ enum powerpc_mmu_t {
> /* PowerPC 601 MMU model (specific BATs format) */
> POWERPC_MMU_601 = 0x0000000A,
> #define POWERPC_MMU_64 0x00010000
> -#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> /* 64 bits PowerPC MMU */
> POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> /* Architecture 2.03 and later (has LPCR) */
> @@ -78,8 +77,7 @@ enum powerpc_mmu_t {
> /* Architecture 2.07 variant */
> POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
> /* Architecture 3.00 variant */
> - POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
> - | 0x00000005,
> + POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
> };
> #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
> #define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B)
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 3b00bdee91..d964f2f5b0 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -761,7 +761,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
> slb = slb_lookup(cpu, eaddr);
> if (!slb) {
> /* No entry found, check if in-memory segment tables are in use */
> - if ((env->mmu_model & POWERPC_MMU_V3) && ppc64_use_proc_tbl(cpu)) {
> + if (ppc64_use_proc_tbl(cpu)) {
> /* TODO - Unsupported */
> error_report("Segment Table Support Unimplemented");
> exit(1);
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
2018-03-28 7:43 ` Cédric Le Goater
@ 2018-03-28 7:49 ` Cédric Le Goater
2018-03-28 8:47 ` David Gibson
0 siblings, 1 reply; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-28 7:49 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/28/2018 09:43 AM, Cédric Le Goater wrote:
> On 03/27/2018 06:37 AM, David Gibson wrote:
>> The only place we test this flag is in conjunction with
>> ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
>> ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
>
> hmm, ok, but what will I use for the PowerNV hash MMU support then ?
That will be POWERPC_MMU_3_00. I didn't realize mmu_model was so
crowded ..
C.
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
2018-03-28 7:49 ` Cédric Le Goater
@ 2018-03-28 8:47 ` David Gibson
2018-03-28 10:19 ` Cédric Le Goater
0 siblings, 1 reply; 45+ messages in thread
From: David Gibson @ 2018-03-28 8:47 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, groug, agraf, qemu-devel, benh, bharata
[-- Attachment #1: Type: text/plain, Size: 1491 bytes --]
On Wed, Mar 28, 2018 at 09:49:25AM +0200, Cédric Le Goater wrote:
> On 03/28/2018 09:43 AM, Cédric Le Goater wrote:
> > On 03/27/2018 06:37 AM, David Gibson wrote:
> >> The only place we test this flag is in conjunction with
> >> ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
> >> ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
> >
> > hmm, ok, but what will I use for the PowerNV hash MMU support then ?
>
> That will be POWERPC_MMU_3_00.
You could check for that explicitly, or you could just check for
presence of non-NULL hash64_opts. The idea is that will always be the
case for cpus capable of using the hash MMU.
I'm also considering adding a similar radix_opts with radix specific
details. POWER9 would have both, since it can support either mode.
> I didn't realize mmu_model was so
> crowded ..
It's not so that it's short of space. It's more that the mix of enum
like pieces and bitflag like pieces like bits makes it confusing to
know whether it should be tested with simple equality or with &. And
if testing with equality which bits should be masked for a sensible
comparison.
Additionally, I'd like to get options that are strictly related to the
hash mmu out of the general structures.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
2018-03-28 8:47 ` David Gibson
@ 2018-03-28 10:19 ` Cédric Le Goater
2018-03-29 5:02 ` David Gibson
0 siblings, 1 reply; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-28 10:19 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, groug, agraf, qemu-devel, benh, bharata
On 03/28/2018 10:47 AM, David Gibson wrote:
> On Wed, Mar 28, 2018 at 09:49:25AM +0200, Cédric Le Goater wrote:
>> On 03/28/2018 09:43 AM, Cédric Le Goater wrote:
>>> On 03/27/2018 06:37 AM, David Gibson wrote:
>>>> The only place we test this flag is in conjunction with
>>>> ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
>>>> ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
>>>
>>> hmm, ok, but what will I use for the PowerNV hash MMU support then ?
>>
>> That will be POWERPC_MMU_3_00.
>
> You could check for that explicitly, or you could just check for
> presence of non-NULL hash64_opts. The idea is that will always be the
> case for cpus capable of using the hash MMU.
ok. I will rebase when your patchset is merged.
> I'm also considering adding a similar radix_opts with radix specific
> details.
yes. It looks a bit unbalanced now.
> POWER9 would have both, since it can support either mode.
>
>> I didn't realize mmu_model was so
>> crowded ..
>
> It's not so that it's short of space. It's more that the mix of enum
> like pieces and bitflag like pieces like bits makes it confusing to
> know whether it should be tested with simple equality or with &. And
> if testing with equality which bits should be masked for a sensible
> comparison.
>
> Additionally, I'd like to get options that are strictly related to the
> hash mmu out of the general structures.
which are ? vrma_slb, rmls ?
C.
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
2018-03-28 10:19 ` Cédric Le Goater
@ 2018-03-29 5:02 ` David Gibson
0 siblings, 0 replies; 45+ messages in thread
From: David Gibson @ 2018-03-29 5:02 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, groug, agraf, qemu-devel, benh, bharata
[-- Attachment #1: Type: text/plain, Size: 2374 bytes --]
On Wed, Mar 28, 2018 at 12:19:37PM +0200, Cédric Le Goater wrote:
> On 03/28/2018 10:47 AM, David Gibson wrote:
> > On Wed, Mar 28, 2018 at 09:49:25AM +0200, Cédric Le Goater wrote:
> >> On 03/28/2018 09:43 AM, Cédric Le Goater wrote:
> >>> On 03/27/2018 06:37 AM, David Gibson wrote:
> >>>> The only place we test this flag is in conjunction with
> >>>> ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
> >>>> ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
> >>>
> >>> hmm, ok, but what will I use for the PowerNV hash MMU support then ?
> >>
> >> That will be POWERPC_MMU_3_00.
> >
> > You could check for that explicitly, or you could just check for
> > presence of non-NULL hash64_opts. The idea is that will always be the
> > case for cpus capable of using the hash MMU.
>
> ok. I will rebase when your patchset is merged.
>
> > I'm also considering adding a similar radix_opts with radix specific
> > details.
>
> yes. It looks a bit unbalanced now.
Right. In theory it would be nice to split out hash32 / BookE /
whatever options into their own substructures as well, but I doubt
anyone will ever care enough to actually do it.
> > POWER9 would have both, since it can support either mode.
> >
> >> I didn't realize mmu_model was so
> >> crowded ..
> >
> > It's not so that it's short of space. It's more that the mix of enum
> > like pieces and bitflag like pieces like bits makes it confusing to
> > know whether it should be tested with simple equality or with &. And
> > if testing with equality which bits should be masked for a sensible
> > comparison.
> >
> > Additionally, I'd like to get options that are strictly related to the
> > hash mmu out of the general structures.
>
> which are ? vrma_slb, rmls ?
Ah.. so.. for now I'm just thinking about MMU options / capabilities
rather than MMU state. That is, things which are set at
initialization but then don't change. rmls and vrma_slb don't fit in
that category. slb_nr does, though - I had a shot at moving it to
hash64_opts, but hit some complications, so I might come back to it
later.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model David Gibson
2018-03-28 7:43 ` Cédric Le Goater
@ 2018-03-28 9:10 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-28 9:10 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:40 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> The only place we test this flag is in conjunction with
> ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
> ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> target/ppc/cpu-qom.h | 4 +---
> target/ppc/mmu-hash64.c | 2 +-
> 2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index 2bd58b2a84..ef96d42cf2 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -68,7 +68,6 @@ enum powerpc_mmu_t {
> /* PowerPC 601 MMU model (specific BATs format) */
> POWERPC_MMU_601 = 0x0000000A,
> #define POWERPC_MMU_64 0x00010000
> -#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
> /* 64 bits PowerPC MMU */
> POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
> /* Architecture 2.03 and later (has LPCR) */
> @@ -78,8 +77,7 @@ enum powerpc_mmu_t {
> /* Architecture 2.07 variant */
> POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
> /* Architecture 3.00 variant */
> - POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
> - | 0x00000005,
> + POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
> };
> #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
> #define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B)
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 3b00bdee91..d964f2f5b0 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -761,7 +761,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
> slb = slb_lookup(cpu, eaddr);
> if (!slb) {
> /* No entry found, check if in-memory segment tables are in use */
> - if ((env->mmu_model & POWERPC_MMU_V3) && ppc64_use_proc_tbl(cpu)) {
> + if (ppc64_use_proc_tbl(cpu)) {
> /* TODO - Unsupported */
> error_report("Segment Table Support Unimplemented");
> exit(1);
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Qemu-devel] [RFC for-2.13 12/12] target/ppc: Get rid of POWERPC_MMU_VER() macros
2018-03-27 4:37 [Qemu-devel] [RFC for-2.13 00/12] target/ppc: Assorted cpu cleanups (esp. hash64 MMU) David Gibson
` (10 preceding siblings ...)
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 11/12] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model David Gibson
@ 2018-03-27 4:37 ` David Gibson
2018-03-28 7:50 ` Cédric Le Goater
2018-03-28 9:26 ` Greg Kurz
11 siblings, 2 replies; 45+ messages in thread
From: David Gibson @ 2018-03-27 4:37 UTC (permalink / raw)
To: qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata, clg, David Gibson
These macros were introduced to deal with the fact that the mmu_model
field has bit flags mixed in with what's otherwise an enum of various mmu
types.
We've now eliminated all those flags except for one, and that one -
POWERPC_MMU_64 - is already included/compared in the MMU_VER macros. So,
we can get rid of those macros and just directly compare mmu_model values
in the places it was used.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-qom.h | 6 ------
target/ppc/kvm.c | 8 ++++----
target/ppc/mmu-hash64.c | 12 ++++++------
target/ppc/mmu_helper.c | 24 ++++++++++++------------
target/ppc/translate.c | 12 ++++++------
5 files changed, 28 insertions(+), 34 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index ef96d42cf2..433a71e484 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -79,12 +79,6 @@ enum powerpc_mmu_t {
/* Architecture 3.00 variant */
POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
};
-#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
-#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B)
-#define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03)
-#define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06)
-#define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07)
-#define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00)
/*****************************************************************************/
/* Exception model */
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 6c45815ee6..9f3f567dda 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -306,8 +306,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
info->flags |= KVM_PPC_1T_SEGMENTS;
}
- if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 ||
- POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) {
+ if (env->mmu_model == POWERPC_MMU_2_06 ||
+ env->mmu_model == POWERPC_MMU_2_07) {
info->slb_size = 32;
} else {
info->slb_size = 64;
@@ -321,8 +321,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
i++;
/* 64K on MMU 2.06 and later */
- if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 ||
- POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) {
+ if (env->mmu_model == POWERPC_MMU_2_06 ||
+ env->mmu_model == POWERPC_MMU_2_07) {
info->sps[i].page_shift = 16;
info->sps[i].slb_enc = 0x110;
info->sps[i].enc[0].page_shift = 16;
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index d964f2f5b0..3514995e16 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1033,8 +1033,8 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
uint64_t lpcr = 0;
/* Filter out bits */
- switch (POWERPC_MMU_VER(env->mmu_model)) {
- case POWERPC_MMU_VER_64B: /* 970 */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_64B: /* 970 */
if (val & 0x40) {
lpcr |= LPCR_LPES0;
}
@@ -1060,26 +1060,26 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
* to dig HRMOR out of HID5
*/
break;
- case POWERPC_MMU_VER_2_03: /* P5p */
+ case POWERPC_MMU_2_03: /* P5p */
lpcr = val & (LPCR_RMLS | LPCR_ILE |
LPCR_LPES0 | LPCR_LPES1 |
LPCR_RMI | LPCR_HDICE);
break;
- case POWERPC_MMU_VER_2_06: /* P7 */
+ case POWERPC_MMU_2_06: /* P7 */
lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
LPCR_MER | LPCR_TC |
LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
break;
- case POWERPC_MMU_VER_2_07: /* P8 */
+ case POWERPC_MMU_2_07: /* P8 */
lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
break;
- case POWERPC_MMU_VER_3_00: /* P9 */
+ case POWERPC_MMU_3_00: /* P9 */
lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
(LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 5568d1642b..8075b7149a 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1266,7 +1266,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
{
- switch (POWERPC_MMU_VER(env->mmu_model)) {
+ switch (env->mmu_model) {
case POWERPC_MMU_BOOKE:
mmubooke_dump_mmu(f, cpu_fprintf, env);
break;
@@ -1278,13 +1278,13 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
mmu6xx_dump_mmu(f, cpu_fprintf, env);
break;
#if defined(TARGET_PPC64)
- case POWERPC_MMU_VER_64B:
- case POWERPC_MMU_VER_2_03:
- case POWERPC_MMU_VER_2_06:
- case POWERPC_MMU_VER_2_07:
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_2_03:
+ case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_07:
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
break;
- case POWERPC_MMU_VER_3_00:
+ case POWERPC_MMU_3_00:
if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
/* TODO - Unsupported */
} else {
@@ -1423,14 +1423,14 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
CPUPPCState *env = &cpu->env;
mmu_ctx_t ctx;
- switch (POWERPC_MMU_VER(env->mmu_model)) {
+ switch (env->mmu_model) {
#if defined(TARGET_PPC64)
- case POWERPC_MMU_VER_64B:
- case POWERPC_MMU_VER_2_03:
- case POWERPC_MMU_VER_2_06:
- case POWERPC_MMU_VER_2_07:
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_2_03:
+ case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_07:
return ppc_hash64_get_phys_page_debug(cpu, addr);
- case POWERPC_MMU_VER_3_00:
+ case POWERPC_MMU_3_00:
if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
return ppc_radix64_get_phys_page_debug(cpu, addr);
} else {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3457d29f8e..22ac7caa04 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7121,17 +7121,17 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
if (env->spr_cb[SPR_LPCR].name)
cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
- switch (POWERPC_MMU_VER(env->mmu_model)) {
+ switch (env->mmu_model) {
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
#if defined(TARGET_PPC64)
- case POWERPC_MMU_VER_64B:
- case POWERPC_MMU_VER_2_03:
- case POWERPC_MMU_VER_2_06:
- case POWERPC_MMU_VER_2_07:
- case POWERPC_MMU_VER_3_00:
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_2_03:
+ case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_07:
+ case POWERPC_MMU_3_00:
#endif
if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
--
2.14.3
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 12/12] target/ppc: Get rid of POWERPC_MMU_VER() macros
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 12/12] target/ppc: Get rid of POWERPC_MMU_VER() macros David Gibson
@ 2018-03-28 7:50 ` Cédric Le Goater
2018-03-28 9:26 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Cédric Le Goater @ 2018-03-28 7:50 UTC (permalink / raw)
To: David Gibson, qemu-ppc, groug; +Cc: agraf, qemu-devel, benh, bharata
On 03/27/2018 06:37 AM, David Gibson wrote:
> These macros were introduced to deal with the fact that the mmu_model
> field has bit flags mixed in with what's otherwise an enum of various mmu
> types.
>
> We've now eliminated all those flags except for one, and that one -
> POWERPC_MMU_64 - is already included/compared in the MMU_VER macros. So,
> we can get rid of those macros and just directly compare mmu_model values
> in the places it was used.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/cpu-qom.h | 6 ------
> target/ppc/kvm.c | 8 ++++----
> target/ppc/mmu-hash64.c | 12 ++++++------
> target/ppc/mmu_helper.c | 24 ++++++++++++------------
> target/ppc/translate.c | 12 ++++++------
> 5 files changed, 28 insertions(+), 34 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index ef96d42cf2..433a71e484 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -79,12 +79,6 @@ enum powerpc_mmu_t {
> /* Architecture 3.00 variant */
> POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
> };
> -#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
> -#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B)
> -#define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03)
> -#define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06)
> -#define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07)
> -#define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00)
>
> /*****************************************************************************/
> /* Exception model */
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 6c45815ee6..9f3f567dda 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -306,8 +306,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
> info->flags |= KVM_PPC_1T_SEGMENTS;
> }
>
> - if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 ||
> - POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) {
> + if (env->mmu_model == POWERPC_MMU_2_06 ||
> + env->mmu_model == POWERPC_MMU_2_07) {
> info->slb_size = 32;
> } else {
> info->slb_size = 64;
> @@ -321,8 +321,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
> i++;
>
> /* 64K on MMU 2.06 and later */
> - if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 ||
> - POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) {
> + if (env->mmu_model == POWERPC_MMU_2_06 ||
> + env->mmu_model == POWERPC_MMU_2_07) {
> info->sps[i].page_shift = 16;
> info->sps[i].slb_enc = 0x110;
> info->sps[i].enc[0].page_shift = 16;
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index d964f2f5b0..3514995e16 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1033,8 +1033,8 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> uint64_t lpcr = 0;
>
> /* Filter out bits */
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> - case POWERPC_MMU_VER_64B: /* 970 */
> + switch (env->mmu_model) {
> + case POWERPC_MMU_64B: /* 970 */
> if (val & 0x40) {
> lpcr |= LPCR_LPES0;
> }
> @@ -1060,26 +1060,26 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> * to dig HRMOR out of HID5
> */
> break;
> - case POWERPC_MMU_VER_2_03: /* P5p */
> + case POWERPC_MMU_2_03: /* P5p */
> lpcr = val & (LPCR_RMLS | LPCR_ILE |
> LPCR_LPES0 | LPCR_LPES1 |
> LPCR_RMI | LPCR_HDICE);
> break;
> - case POWERPC_MMU_VER_2_06: /* P7 */
> + case POWERPC_MMU_2_06: /* P7 */
> lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
> LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
> LPCR_MER | LPCR_TC |
> LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
> break;
> - case POWERPC_MMU_VER_2_07: /* P8 */
> + case POWERPC_MMU_2_07: /* P8 */
> lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
> LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
> LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
> LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
> break;
> - case POWERPC_MMU_VER_3_00: /* P9 */
> + case POWERPC_MMU_3_00: /* P9 */
> lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 5568d1642b..8075b7149a 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -1266,7 +1266,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
>
> void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
> {
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> + switch (env->mmu_model) {
> case POWERPC_MMU_BOOKE:
> mmubooke_dump_mmu(f, cpu_fprintf, env);
> break;
> @@ -1278,13 +1278,13 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
> mmu6xx_dump_mmu(f, cpu_fprintf, env);
> break;
> #if defined(TARGET_PPC64)
> - case POWERPC_MMU_VER_64B:
> - case POWERPC_MMU_VER_2_03:
> - case POWERPC_MMU_VER_2_06:
> - case POWERPC_MMU_VER_2_07:
> + case POWERPC_MMU_64B:
> + case POWERPC_MMU_2_03:
> + case POWERPC_MMU_2_06:
> + case POWERPC_MMU_2_07:
> dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> break;
> - case POWERPC_MMU_VER_3_00:
> + case POWERPC_MMU_3_00:
> if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> /* TODO - Unsupported */
> } else {
> @@ -1423,14 +1423,14 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> CPUPPCState *env = &cpu->env;
> mmu_ctx_t ctx;
>
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> + switch (env->mmu_model) {
> #if defined(TARGET_PPC64)
> - case POWERPC_MMU_VER_64B:
> - case POWERPC_MMU_VER_2_03:
> - case POWERPC_MMU_VER_2_06:
> - case POWERPC_MMU_VER_2_07:
> + case POWERPC_MMU_64B:
> + case POWERPC_MMU_2_03:
> + case POWERPC_MMU_2_06:
> + case POWERPC_MMU_2_07:
> return ppc_hash64_get_phys_page_debug(cpu, addr);
> - case POWERPC_MMU_VER_3_00:
> + case POWERPC_MMU_3_00:
> if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> return ppc_radix64_get_phys_page_debug(cpu, addr);
> } else {
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 3457d29f8e..22ac7caa04 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7121,17 +7121,17 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
> if (env->spr_cb[SPR_LPCR].name)
> cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
>
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> + switch (env->mmu_model) {
> case POWERPC_MMU_32B:
> case POWERPC_MMU_601:
> case POWERPC_MMU_SOFT_6xx:
> case POWERPC_MMU_SOFT_74xx:
> #if defined(TARGET_PPC64)
> - case POWERPC_MMU_VER_64B:
> - case POWERPC_MMU_VER_2_03:
> - case POWERPC_MMU_VER_2_06:
> - case POWERPC_MMU_VER_2_07:
> - case POWERPC_MMU_VER_3_00:
> + case POWERPC_MMU_64B:
> + case POWERPC_MMU_2_03:
> + case POWERPC_MMU_2_06:
> + case POWERPC_MMU_2_07:
> + case POWERPC_MMU_3_00:
> #endif
> if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
> cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Qemu-devel] [RFC for-2.13 12/12] target/ppc: Get rid of POWERPC_MMU_VER() macros
2018-03-27 4:37 ` [Qemu-devel] [RFC for-2.13 12/12] target/ppc: Get rid of POWERPC_MMU_VER() macros David Gibson
2018-03-28 7:50 ` Cédric Le Goater
@ 2018-03-28 9:26 ` Greg Kurz
1 sibling, 0 replies; 45+ messages in thread
From: Greg Kurz @ 2018-03-28 9:26 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, agraf, qemu-devel, benh, bharata, clg
On Tue, 27 Mar 2018 15:37:41 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> These macros were introduced to deal with the fact that the mmu_model
> field has bit flags mixed in with what's otherwise an enum of various mmu
> types.
>
> We've now eliminated all those flags except for one, and that one -
> POWERPC_MMU_64 - is already included/compared in the MMU_VER macros. So,
> we can get rid of those macros and just directly compare mmu_model values
> in the places it was used.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> target/ppc/cpu-qom.h | 6 ------
> target/ppc/kvm.c | 8 ++++----
> target/ppc/mmu-hash64.c | 12 ++++++------
> target/ppc/mmu_helper.c | 24 ++++++++++++------------
> target/ppc/translate.c | 12 ++++++------
> 5 files changed, 28 insertions(+), 34 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index ef96d42cf2..433a71e484 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -79,12 +79,6 @@ enum powerpc_mmu_t {
> /* Architecture 3.00 variant */
> POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
> };
> -#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
> -#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B)
> -#define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03)
> -#define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06)
> -#define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07)
> -#define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00)
>
> /*****************************************************************************/
> /* Exception model */
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 6c45815ee6..9f3f567dda 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -306,8 +306,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
> info->flags |= KVM_PPC_1T_SEGMENTS;
> }
>
> - if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 ||
> - POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) {
> + if (env->mmu_model == POWERPC_MMU_2_06 ||
> + env->mmu_model == POWERPC_MMU_2_07) {
> info->slb_size = 32;
> } else {
> info->slb_size = 64;
> @@ -321,8 +321,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
> i++;
>
> /* 64K on MMU 2.06 and later */
> - if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 ||
> - POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) {
> + if (env->mmu_model == POWERPC_MMU_2_06 ||
> + env->mmu_model == POWERPC_MMU_2_07) {
> info->sps[i].page_shift = 16;
> info->sps[i].slb_enc = 0x110;
> info->sps[i].enc[0].page_shift = 16;
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index d964f2f5b0..3514995e16 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1033,8 +1033,8 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> uint64_t lpcr = 0;
>
> /* Filter out bits */
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> - case POWERPC_MMU_VER_64B: /* 970 */
> + switch (env->mmu_model) {
> + case POWERPC_MMU_64B: /* 970 */
> if (val & 0x40) {
> lpcr |= LPCR_LPES0;
> }
> @@ -1060,26 +1060,26 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> * to dig HRMOR out of HID5
> */
> break;
> - case POWERPC_MMU_VER_2_03: /* P5p */
> + case POWERPC_MMU_2_03: /* P5p */
> lpcr = val & (LPCR_RMLS | LPCR_ILE |
> LPCR_LPES0 | LPCR_LPES1 |
> LPCR_RMI | LPCR_HDICE);
> break;
> - case POWERPC_MMU_VER_2_06: /* P7 */
> + case POWERPC_MMU_2_06: /* P7 */
> lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
> LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
> LPCR_MER | LPCR_TC |
> LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
> break;
> - case POWERPC_MMU_VER_2_07: /* P8 */
> + case POWERPC_MMU_2_07: /* P8 */
> lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
> LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
> LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
> LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
> break;
> - case POWERPC_MMU_VER_3_00: /* P9 */
> + case POWERPC_MMU_3_00: /* P9 */
> lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 5568d1642b..8075b7149a 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -1266,7 +1266,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
>
> void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
> {
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> + switch (env->mmu_model) {
> case POWERPC_MMU_BOOKE:
> mmubooke_dump_mmu(f, cpu_fprintf, env);
> break;
> @@ -1278,13 +1278,13 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
> mmu6xx_dump_mmu(f, cpu_fprintf, env);
> break;
> #if defined(TARGET_PPC64)
> - case POWERPC_MMU_VER_64B:
> - case POWERPC_MMU_VER_2_03:
> - case POWERPC_MMU_VER_2_06:
> - case POWERPC_MMU_VER_2_07:
> + case POWERPC_MMU_64B:
> + case POWERPC_MMU_2_03:
> + case POWERPC_MMU_2_06:
> + case POWERPC_MMU_2_07:
> dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> break;
> - case POWERPC_MMU_VER_3_00:
> + case POWERPC_MMU_3_00:
> if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> /* TODO - Unsupported */
> } else {
> @@ -1423,14 +1423,14 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> CPUPPCState *env = &cpu->env;
> mmu_ctx_t ctx;
>
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> + switch (env->mmu_model) {
> #if defined(TARGET_PPC64)
> - case POWERPC_MMU_VER_64B:
> - case POWERPC_MMU_VER_2_03:
> - case POWERPC_MMU_VER_2_06:
> - case POWERPC_MMU_VER_2_07:
> + case POWERPC_MMU_64B:
> + case POWERPC_MMU_2_03:
> + case POWERPC_MMU_2_06:
> + case POWERPC_MMU_2_07:
> return ppc_hash64_get_phys_page_debug(cpu, addr);
> - case POWERPC_MMU_VER_3_00:
> + case POWERPC_MMU_3_00:
> if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> return ppc_radix64_get_phys_page_debug(cpu, addr);
> } else {
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 3457d29f8e..22ac7caa04 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7121,17 +7121,17 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
> if (env->spr_cb[SPR_LPCR].name)
> cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
>
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> + switch (env->mmu_model) {
> case POWERPC_MMU_32B:
> case POWERPC_MMU_601:
> case POWERPC_MMU_SOFT_6xx:
> case POWERPC_MMU_SOFT_74xx:
> #if defined(TARGET_PPC64)
> - case POWERPC_MMU_VER_64B:
> - case POWERPC_MMU_VER_2_03:
> - case POWERPC_MMU_VER_2_06:
> - case POWERPC_MMU_VER_2_07:
> - case POWERPC_MMU_VER_3_00:
> + case POWERPC_MMU_64B:
> + case POWERPC_MMU_2_03:
> + case POWERPC_MMU_2_06:
> + case POWERPC_MMU_2_07:
> + case POWERPC_MMU_3_00:
> #endif
> if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
> cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
^ permalink raw reply [flat|nested] 45+ messages in thread