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From: <Conor.Dooley@microchip.com>
To: <anup@brainfault.org>, <palmer@dabbelt.com>
Cc: <apatel@ventanamicro.com>, <arnd@arndb.de>,
	<paul.walmsley@sifive.com>, <linux-kernel@vger.kernel.org>,
	<heinrich.schuchardt@canonical.com>, <atishp@atishpatra.org>,
	<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output
Date: Tue, 26 Jul 2022 13:40:18 +0000	[thread overview]
Message-ID: <659c6aa4-1100-0945-4965-3e106dfd490f@microchip.com> (raw)
In-Reply-To: <CAAhSdy0mHbxQ3QVP9j1==oTG75Z9_T2bDSif-UGKppG+-hoJng@mail.gmail.com>

Hey Anup,

On 26/07/2022 12:57, Anup Patel wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi Palmer,
> 
> On Mon, Jun 20, 2022 at 5:26 PM Anup Patel <apatel@ventanamicro.com> wrote:
>>
>> Identifying the underlying RISC-V implementation can be important
>> for some of the user space applications. For example, the perf tool
>> uses arch specific CPU implementation id (i.e. CPUID) to select a
>> JSON file describing custom perf events on a CPU.
>>
>> Currently, there is no way to identify RISC-V implementation so we
>> add mvendorid, marchid, and mimpid to /proc/cpuinfo output.
>>
>> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> 
> Can this patch be considered for 5.20 ?

iirc I mentioned the consistency of using defined() for
CONFIG_RISCV_SBI versus IS_ENABLED() elsewhere in arch/riscv/
but I don't recall a response.

Thanks,
Conor.

WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com>
To: <anup@brainfault.org>, <palmer@dabbelt.com>
Cc: <apatel@ventanamicro.com>, <arnd@arndb.de>,
	<paul.walmsley@sifive.com>, <linux-kernel@vger.kernel.org>,
	<heinrich.schuchardt@canonical.com>, <atishp@atishpatra.org>,
	<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output
Date: Tue, 26 Jul 2022 13:40:18 +0000	[thread overview]
Message-ID: <659c6aa4-1100-0945-4965-3e106dfd490f@microchip.com> (raw)
In-Reply-To: <CAAhSdy0mHbxQ3QVP9j1==oTG75Z9_T2bDSif-UGKppG+-hoJng@mail.gmail.com>

Hey Anup,

On 26/07/2022 12:57, Anup Patel wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi Palmer,
> 
> On Mon, Jun 20, 2022 at 5:26 PM Anup Patel <apatel@ventanamicro.com> wrote:
>>
>> Identifying the underlying RISC-V implementation can be important
>> for some of the user space applications. For example, the perf tool
>> uses arch specific CPU implementation id (i.e. CPUID) to select a
>> JSON file describing custom perf events on a CPU.
>>
>> Currently, there is no way to identify RISC-V implementation so we
>> add mvendorid, marchid, and mimpid to /proc/cpuinfo output.
>>
>> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> 
> Can this patch be considered for 5.20 ?

iirc I mentioned the consistency of using defined() for
CONFIG_RISCV_SBI versus IS_ENABLED() elsewhere in arch/riscv/
but I don't recall a response.

Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-07-26 13:40 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-20 11:55 [PATCH] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output Anup Patel
2022-06-20 11:55 ` Anup Patel
2022-06-20 13:57 ` Heinrich Schuchardt
2022-06-20 13:57   ` Heinrich Schuchardt
2022-06-20 15:42 ` Conor.Dooley
2022-06-20 15:42   ` Conor.Dooley
2022-06-21  7:40 ` Nikita Shubin
2022-06-21  7:40   ` Nikita Shubin
2022-06-21  8:28   ` David Abdurachmanov
2022-06-21  8:28     ` David Abdurachmanov
2022-07-26 11:57 ` Anup Patel
2022-07-26 11:57   ` Anup Patel
2022-07-26 13:40   ` Conor.Dooley [this message]
2022-07-26 13:40     ` Conor.Dooley
2022-07-26 13:43     ` Anup Patel
2022-07-26 13:43       ` Anup Patel

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