* [PATCH V2 0/7] Add NSS clock controller support for IPQ9574
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add bindings, driver and devicetree node for networking sub system clock
controller on IPQ9574. Also add support for NSS Huayra type alpha PLL and
add support for gpll0_out_aux clock which serves as the parent for
some nss clocks.
The NSS clock controller driver depends on the below patchset which adds
support for multiple configurations for same frequency.
https://lore.kernel.org/linux-arm-msm/20230531222654.25475-1-ansuelsmth@gmail.com/
Changes in V2:
- Detailed change logs are added to the respective patches.
V1 can be found at:
https://lore.kernel.org/linux-arm-msm/20230711093529.18355-1-quic_devipriy@quicinc.com/
Devi Priya (7):
clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
clk: qcom: Add NSS clock Controller driver for IPQ9574
arm64: dts: qcom: ipq9574: Add support for nsscc node
arm64: defconfig: Build NSS Clock Controller driver for IPQ9574
.../bindings/clock/qcom,ipq9574-nsscc.yaml | 107 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 12 +
drivers/clk/qcom/clk-alpha-pll.h | 1 +
drivers/clk/qcom/gcc-ipq9574.c | 16 +
drivers/clk/qcom/nsscc-ipq9574.c | 3109 +++++++++++++++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 +
.../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 +
.../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +
12 files changed, 3589 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
--
2.34.1
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH V2 0/7] Add NSS clock controller support for IPQ9574
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add bindings, driver and devicetree node for networking sub system clock
controller on IPQ9574. Also add support for NSS Huayra type alpha PLL and
add support for gpll0_out_aux clock which serves as the parent for
some nss clocks.
The NSS clock controller driver depends on the below patchset which adds
support for multiple configurations for same frequency.
https://lore.kernel.org/linux-arm-msm/20230531222654.25475-1-ansuelsmth@gmail.com/
Changes in V2:
- Detailed change logs are added to the respective patches.
V1 can be found at:
https://lore.kernel.org/linux-arm-msm/20230711093529.18355-1-quic_devipriy@quicinc.com/
Devi Priya (7):
clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
clk: qcom: Add NSS clock Controller driver for IPQ9574
arm64: dts: qcom: ipq9574: Add support for nsscc node
arm64: defconfig: Build NSS Clock Controller driver for IPQ9574
.../bindings/clock/qcom,ipq9574-nsscc.yaml | 107 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 12 +
drivers/clk/qcom/clk-alpha-pll.h | 1 +
drivers/clk/qcom/gcc-ipq9574.c | 16 +
drivers/clk/qcom/nsscc-ipq9574.c | 3109 +++++++++++++++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 +
.../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 +
.../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +
12 files changed, 3589 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH V2 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 9:12 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add support for NSS Huayra alpha pll found on ipq9574 SoCs.
Programming sequence is the same as that of Huayra type Alpha PLL,
so we can re-use the same.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in V2:
- Picked up the R-b tag
drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index e4ef645f65d1..1c2a72840cd2 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_ALPHA_VAL] = 0x24,
[PLL_OFF_ALPHA_VAL_U] = 0x28,
},
+
+ [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_TEST_CTL] = 0x0c,
+ [PLL_OFF_TEST_CTL_U] = 0x10,
+ [PLL_OFF_USER_CTL] = 0x14,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL_U] = 0x1c,
+ [PLL_OFF_STATUS] = 0x20,
+ },
+
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index e4bd863027ab..cb079a6ed96a 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -28,6 +28,7 @@ enum {
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
CLK_ALPHA_PLL_TYPE_STROMER,
CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
+ CLK_ALPHA_PLL_TYPE_NSS_HUAYRA,
CLK_ALPHA_PLL_TYPE_MAX,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add support for NSS Huayra alpha pll found on ipq9574 SoCs.
Programming sequence is the same as that of Huayra type Alpha PLL,
so we can re-use the same.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in V2:
- Picked up the R-b tag
drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index e4ef645f65d1..1c2a72840cd2 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_ALPHA_VAL] = 0x24,
[PLL_OFF_ALPHA_VAL_U] = 0x28,
},
+
+ [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_TEST_CTL] = 0x0c,
+ [PLL_OFF_TEST_CTL_U] = 0x10,
+ [PLL_OFF_USER_CTL] = 0x14,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL_U] = 0x1c,
+ [PLL_OFF_STATUS] = 0x20,
+ },
+
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index e4bd863027ab..cb079a6ed96a 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -28,6 +28,7 @@ enum {
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
CLK_ALPHA_PLL_TYPE_STROMER,
CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
+ CLK_ALPHA_PLL_TYPE_NSS_HUAYRA,
CLK_ALPHA_PLL_TYPE_MAX,
};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 9:12 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add the definition for GPLL0_OUT_AUX clock.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 08fd3a37acaa..f5749bf53898 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -216,4 +216,5 @@
#define GCC_CRYPTO_AHB_CLK 207
#define GCC_USB0_PIPE_CLK 208
#define GCC_USB0_SLEEP_CLK 209
+#define GPLL0_OUT_AUX 210
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add the definition for GPLL0_OUT_AUX clock.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 08fd3a37acaa..f5749bf53898 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -216,4 +216,5 @@
#define GCC_CRYPTO_AHB_CLK 207
#define GCC_USB0_PIPE_CLK 208
#define GCC_USB0_SLEEP_CLK 209
+#define GPLL0_OUT_AUX 210
#endif
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 3/7] clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 9:12 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (nss) clocks.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
drivers/clk/qcom/gcc-ipq9574.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 8f430367299e..495a66f7d29a 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -107,6 +107,21 @@ static struct clk_alpha_pll_postdiv gpll0 = {
},
};
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpll0_out_aux",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
static struct clk_alpha_pll gpll4_main = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -4144,6 +4159,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
+ [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
};
static const struct qcom_reset_map gcc_ipq9574_resets[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 3/7] clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (nss) clocks.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
drivers/clk/qcom/gcc-ipq9574.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 8f430367299e..495a66f7d29a 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -107,6 +107,21 @@ static struct clk_alpha_pll_postdiv gpll0 = {
},
};
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpll0_out_aux",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
static struct clk_alpha_pll gpll4_main = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -4144,6 +4159,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
+ [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
};
static const struct qcom_reset_map gcc_ipq9574_resets[] = {
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 9:12 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add NSSCC clock and reset definitions for ipq9574.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Referenced gcc.yaml and dropped the duplicate properties from
the binding
- Updated Uniphy clock names
- Added nssnoc clocks and clock-names
.../bindings/clock/qcom,ipq9574-nsscc.yaml | 107 ++++++++++++
.../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++
.../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++
3 files changed, 393 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
new file mode 100644
index 000000000000..570a9c654781
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Anusha Rao <quic_anusha@quicinc.com>
+
+description: |
+ Qualcomm networking sub system clock control module provides the clocks,
+ resets and power domains on IPQ9574
+
+ See also::
+ include/dt-bindings/clock/qcom,ipq9574-nsscc.h
+ include/dt-bindings/reset/qcom,ipq9574-nsscc.h
+
+properties:
+ compatible:
+ const: qcom,ipq9574-nsscc
+
+ clocks:
+ items:
+ - description: NSSNOC NSSCC clock source
+ - description: NSSNOC SNOC clock source
+ - description: NSSNOC SNOC_1 clock source
+ - description: Bias PLL cc clock source
+ - description: Bias PLL nss noc clock source
+ - description: Bias PLL ubi nc clock source
+ - description: GCC GPLL0 OUT AUX clock source
+ - description: Uniphy0 NSS Rx clock source
+ - description: Uniphy0 NSS Tx clock source
+ - description: Uniphy1 NSS Rx clock source
+ - description: Uniphy1 NSS Tx clock source
+ - description: Uniphy2 NSS Rx clock source
+ - description: Uniphy2 NSS Tx clock source
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: nssnoc_nsscc
+ - const: nssnoc_snoc
+ - const: nssnoc_snoc_1
+ - const: bias_pll_cc_clk
+ - const: bias_pll_nss_noc_clk
+ - const: bias_pll_ubi_nc_clk
+ - const: gpll0_out_aux
+ - const: uniphy0_nss_rx_clk
+ - const: uniphy0_nss_tx_clk
+ - const: uniphy1_nss_rx_clk
+ - const: uniphy1_nss_tx_clk
+ - const: uniphy2_nss_rx_clk
+ - const: uniphy2_nss_tx_clk
+ - const: xo_board_clk
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+ clock-controller@39b00000 {
+ compatible = "qcom,ipq9574-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_1_CLK>,
+ <&bias_pll_cc_clk>,
+ <&bias_pll_nss_noc_clk>,
+ <&bias_pll_ubi_nc_clk>,
+ <&gcc GPLL0_OUT_AUX>,
+ <&uniphy 0>,
+ <&uniphy 1>,
+ <&uniphy 2>,
+ <&uniphy 3>,
+ <&uniphy 4>,
+ <&uniphy 5>,
+ <&xo_board_clk>;
+ clock-names = "nssnoc_nsscc",
+ "nssnoc_snoc",
+ "nssnoc_snoc_1",
+ "bias_pll_cc_clk",
+ "bias_pll_nss_noc_clk",
+ "bias_pll_ubi_nc_clk",
+ "gpll0_out_aux",
+ "uniphy0_nss_rx_clk",
+ "uniphy0_nss_tx_clk",
+ "uniphy1_nss_rx_clk",
+ "uniphy1_nss_tx_clk",
+ "uniphy2_nss_rx_clk",
+ "uniphy2_nss_tx_clk",
+ "xo_board_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
new file mode 100644
index 000000000000..59d57d9c788c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
+#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
+
+#define NSS_CC_CE_APB_CLK 0
+#define NSS_CC_CE_AXI_CLK 1
+#define NSS_CC_CE_CLK_SRC 2
+#define NSS_CC_CFG_CLK_SRC 3
+#define NSS_CC_CLC_AXI_CLK 4
+#define NSS_CC_CLC_CLK_SRC 5
+#define NSS_CC_CRYPTO_CLK 6
+#define NSS_CC_CRYPTO_CLK_SRC 7
+#define NSS_CC_CRYPTO_PPE_CLK 8
+#define NSS_CC_HAQ_AHB_CLK 9
+#define NSS_CC_HAQ_AXI_CLK 10
+#define NSS_CC_HAQ_CLK_SRC 11
+#define NSS_CC_IMEM_AHB_CLK 12
+#define NSS_CC_IMEM_CLK_SRC 13
+#define NSS_CC_IMEM_QSB_CLK 14
+#define NSS_CC_INT_CFG_CLK_SRC 15
+#define NSS_CC_NSS_CSR_CLK 16
+#define NSS_CC_NSSNOC_CE_APB_CLK 17
+#define NSS_CC_NSSNOC_CE_AXI_CLK 18
+#define NSS_CC_NSSNOC_CLC_AXI_CLK 19
+#define NSS_CC_NSSNOC_CRYPTO_CLK 20
+#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21
+#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22
+#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23
+#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24
+#define NSS_CC_NSSNOC_NSS_CSR_CLK 25
+#define NSS_CC_NSSNOC_PPE_CFG_CLK 26
+#define NSS_CC_NSSNOC_PPE_CLK 27
+#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28
+#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29
+#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30
+#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31
+#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32
+#define NSS_CC_PORT1_MAC_CLK 33
+#define NSS_CC_PORT1_RX_CLK 34
+#define NSS_CC_PORT1_RX_CLK_SRC 35
+#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36
+#define NSS_CC_PORT1_TX_CLK 37
+#define NSS_CC_PORT1_TX_CLK_SRC 38
+#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39
+#define NSS_CC_PORT2_MAC_CLK 40
+#define NSS_CC_PORT2_RX_CLK 41
+#define NSS_CC_PORT2_RX_CLK_SRC 42
+#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43
+#define NSS_CC_PORT2_TX_CLK 44
+#define NSS_CC_PORT2_TX_CLK_SRC 45
+#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46
+#define NSS_CC_PORT3_MAC_CLK 47
+#define NSS_CC_PORT3_RX_CLK 48
+#define NSS_CC_PORT3_RX_CLK_SRC 49
+#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50
+#define NSS_CC_PORT3_TX_CLK 51
+#define NSS_CC_PORT3_TX_CLK_SRC 52
+#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53
+#define NSS_CC_PORT4_MAC_CLK 54
+#define NSS_CC_PORT4_RX_CLK 55
+#define NSS_CC_PORT4_RX_CLK_SRC 56
+#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57
+#define NSS_CC_PORT4_TX_CLK 58
+#define NSS_CC_PORT4_TX_CLK_SRC 59
+#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60
+#define NSS_CC_PORT5_MAC_CLK 61
+#define NSS_CC_PORT5_RX_CLK 62
+#define NSS_CC_PORT5_RX_CLK_SRC 63
+#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64
+#define NSS_CC_PORT5_TX_CLK 65
+#define NSS_CC_PORT5_TX_CLK_SRC 66
+#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67
+#define NSS_CC_PORT6_MAC_CLK 68
+#define NSS_CC_PORT6_RX_CLK 69
+#define NSS_CC_PORT6_RX_CLK_SRC 70
+#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71
+#define NSS_CC_PORT6_TX_CLK 72
+#define NSS_CC_PORT6_TX_CLK_SRC 73
+#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74
+#define NSS_CC_PPE_CLK_SRC 75
+#define NSS_CC_PPE_EDMA_CFG_CLK 76
+#define NSS_CC_PPE_EDMA_CLK 77
+#define NSS_CC_PPE_SWITCH_BTQ_CLK 78
+#define NSS_CC_PPE_SWITCH_CFG_CLK 79
+#define NSS_CC_PPE_SWITCH_CLK 80
+#define NSS_CC_PPE_SWITCH_IPE_CLK 81
+#define NSS_CC_UBI0_CLK_SRC 82
+#define NSS_CC_UBI0_DIV_CLK_SRC 83
+#define NSS_CC_UBI1_CLK_SRC 84
+#define NSS_CC_UBI1_DIV_CLK_SRC 85
+#define NSS_CC_UBI2_CLK_SRC 86
+#define NSS_CC_UBI2_DIV_CLK_SRC 87
+#define NSS_CC_UBI32_AHB0_CLK 88
+#define NSS_CC_UBI32_AHB1_CLK 89
+#define NSS_CC_UBI32_AHB2_CLK 90
+#define NSS_CC_UBI32_AHB3_CLK 91
+#define NSS_CC_UBI32_AXI0_CLK 92
+#define NSS_CC_UBI32_AXI1_CLK 93
+#define NSS_CC_UBI32_AXI2_CLK 94
+#define NSS_CC_UBI32_AXI3_CLK 95
+#define NSS_CC_UBI32_CORE0_CLK 96
+#define NSS_CC_UBI32_CORE1_CLK 97
+#define NSS_CC_UBI32_CORE2_CLK 98
+#define NSS_CC_UBI32_CORE3_CLK 99
+#define NSS_CC_UBI32_INTR0_AHB_CLK 100
+#define NSS_CC_UBI32_INTR1_AHB_CLK 101
+#define NSS_CC_UBI32_INTR2_AHB_CLK 102
+#define NSS_CC_UBI32_INTR3_AHB_CLK 103
+#define NSS_CC_UBI32_NC_AXI0_CLK 104
+#define NSS_CC_UBI32_NC_AXI1_CLK 105
+#define NSS_CC_UBI32_NC_AXI2_CLK 106
+#define NSS_CC_UBI32_NC_AXI3_CLK 107
+#define NSS_CC_UBI32_UTCM0_CLK 108
+#define NSS_CC_UBI32_UTCM1_CLK 109
+#define NSS_CC_UBI32_UTCM2_CLK 110
+#define NSS_CC_UBI32_UTCM3_CLK 111
+#define NSS_CC_UBI3_CLK_SRC 112
+#define NSS_CC_UBI3_DIV_CLK_SRC 113
+#define NSS_CC_UBI_AXI_CLK_SRC 114
+#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115
+#define NSS_CC_UNIPHY_PORT1_RX_CLK 116
+#define NSS_CC_UNIPHY_PORT1_TX_CLK 117
+#define NSS_CC_UNIPHY_PORT2_RX_CLK 118
+#define NSS_CC_UNIPHY_PORT2_TX_CLK 119
+#define NSS_CC_UNIPHY_PORT3_RX_CLK 120
+#define NSS_CC_UNIPHY_PORT3_TX_CLK 121
+#define NSS_CC_UNIPHY_PORT4_RX_CLK 122
+#define NSS_CC_UNIPHY_PORT4_TX_CLK 123
+#define NSS_CC_UNIPHY_PORT5_RX_CLK 124
+#define NSS_CC_UNIPHY_PORT5_TX_CLK 125
+#define NSS_CC_UNIPHY_PORT6_RX_CLK 126
+#define NSS_CC_UNIPHY_PORT6_TX_CLK 127
+#define NSS_CC_XGMAC0_PTP_REF_CLK 128
+#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129
+#define NSS_CC_XGMAC1_PTP_REF_CLK 130
+#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131
+#define NSS_CC_XGMAC2_PTP_REF_CLK 132
+#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133
+#define NSS_CC_XGMAC3_PTP_REF_CLK 134
+#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135
+#define NSS_CC_XGMAC4_PTP_REF_CLK 136
+#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137
+#define NSS_CC_XGMAC5_PTP_REF_CLK 138
+#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139
+#define UBI32_PLL 140
+#define UBI32_PLL_MAIN 141
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
new file mode 100644
index 000000000000..6910db0cff51
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
+#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
+
+#define EDMA_HW_RESET 0
+#define NSS_CC_CE_BCR 1
+#define NSS_CC_CLC_BCR 2
+#define NSS_CC_EIP197_BCR 3
+#define NSS_CC_HAQ_BCR 4
+#define NSS_CC_IMEM_BCR 5
+#define NSS_CC_MAC_BCR 6
+#define NSS_CC_PPE_BCR 7
+#define NSS_CC_UBI_BCR 8
+#define NSS_CC_UNIPHY_BCR 9
+#define UBI3_CLKRST_CLAMP_ENABLE 10
+#define UBI3_CORE_CLAMP_ENABLE 11
+#define UBI2_CLKRST_CLAMP_ENABLE 12
+#define UBI2_CORE_CLAMP_ENABLE 13
+#define UBI1_CLKRST_CLAMP_ENABLE 14
+#define UBI1_CORE_CLAMP_ENABLE 15
+#define UBI0_CLKRST_CLAMP_ENABLE 16
+#define UBI0_CORE_CLAMP_ENABLE 17
+#define NSSNOC_NSS_CSR_ARES 18
+#define NSS_CSR_ARES 19
+#define PPE_BTQ_ARES 20
+#define PPE_IPE_ARES 21
+#define PPE_ARES 22
+#define PPE_CFG_ARES 23
+#define PPE_EDMA_ARES 24
+#define PPE_EDMA_CFG_ARES 25
+#define CRY_PPE_ARES 26
+#define NSSNOC_PPE_ARES 27
+#define NSSNOC_PPE_CFG_ARES 28
+#define PORT1_MAC_ARES 29
+#define PORT2_MAC_ARES 30
+#define PORT3_MAC_ARES 31
+#define PORT4_MAC_ARES 32
+#define PORT5_MAC_ARES 33
+#define PORT6_MAC_ARES 34
+#define XGMAC0_PTP_REF_ARES 35
+#define XGMAC1_PTP_REF_ARES 36
+#define XGMAC2_PTP_REF_ARES 37
+#define XGMAC3_PTP_REF_ARES 38
+#define XGMAC4_PTP_REF_ARES 39
+#define XGMAC5_PTP_REF_ARES 40
+#define HAQ_AHB_ARES 41
+#define HAQ_AXI_ARES 42
+#define NSSNOC_HAQ_AHB_ARES 43
+#define NSSNOC_HAQ_AXI_ARES 44
+#define CE_APB_ARES 45
+#define CE_AXI_ARES 46
+#define NSSNOC_CE_APB_ARES 47
+#define NSSNOC_CE_AXI_ARES 48
+#define CRYPTO_ARES 49
+#define NSSNOC_CRYPTO_ARES 50
+#define NSSNOC_NC_AXI0_1_ARES 51
+#define UBI0_CORE_ARES 52
+#define UBI1_CORE_ARES 53
+#define UBI2_CORE_ARES 54
+#define UBI3_CORE_ARES 55
+#define NC_AXI0_ARES 56
+#define UTCM0_ARES 57
+#define NC_AXI1_ARES 58
+#define UTCM1_ARES 59
+#define NC_AXI2_ARES 60
+#define UTCM2_ARES 61
+#define NC_AXI3_ARES 62
+#define UTCM3_ARES 63
+#define NSSNOC_NC_AXI0_ARES 64
+#define AHB0_ARES 65
+#define INTR0_AHB_ARES 66
+#define AHB1_ARES 67
+#define INTR1_AHB_ARES 68
+#define AHB2_ARES 69
+#define INTR2_AHB_ARES 70
+#define AHB3_ARES 71
+#define INTR3_AHB_ARES 72
+#define NSSNOC_AHB0_ARES 73
+#define NSSNOC_INT0_AHB_ARES 74
+#define AXI0_ARES 75
+#define AXI1_ARES 76
+#define AXI2_ARES 77
+#define AXI3_ARES 78
+#define NSSNOC_AXI0_ARES 79
+#define IMEM_QSB_ARES 80
+#define NSSNOC_IMEM_QSB_ARES 81
+#define IMEM_AHB_ARES 82
+#define NSSNOC_IMEM_AHB_ARES 83
+#define UNIPHY_PORT1_RX_ARES 84
+#define UNIPHY_PORT1_TX_ARES 85
+#define UNIPHY_PORT2_RX_ARES 86
+#define UNIPHY_PORT2_TX_ARES 87
+#define UNIPHY_PORT3_RX_ARES 88
+#define UNIPHY_PORT3_TX_ARES 89
+#define UNIPHY_PORT4_RX_ARES 90
+#define UNIPHY_PORT4_TX_ARES 91
+#define UNIPHY_PORT5_RX_ARES 92
+#define UNIPHY_PORT5_TX_ARES 93
+#define UNIPHY_PORT6_RX_ARES 94
+#define UNIPHY_PORT6_TX_ARES 95
+#define PORT1_RX_ARES 96
+#define PORT1_TX_ARES 97
+#define PORT2_RX_ARES 98
+#define PORT2_TX_ARES 99
+#define PORT3_RX_ARES 100
+#define PORT3_TX_ARES 101
+#define PORT4_RX_ARES 102
+#define PORT4_TX_ARES 103
+#define PORT5_RX_ARES 104
+#define PORT5_TX_ARES 105
+#define PORT6_RX_ARES 106
+#define PORT6_TX_ARES 107
+#define PPE_FULL_RESET 108
+#define UNIPHY0_SOFT_RESET 109
+#define UNIPHY1_SOFT_RESET 110
+#define UNIPHY2_SOFT_RESET 111
+#define UNIPHY_PORT1_ARES 112
+#define UNIPHY_PORT2_ARES 113
+#define UNIPHY_PORT3_ARES 114
+#define UNIPHY_PORT4_ARES 115
+#define UNIPHY_PORT5_ARES 116
+#define UNIPHY_PORT6_ARES 117
+#define NSSPORT1_RESET 118
+#define NSSPORT2_RESET 119
+#define NSSPORT3_RESET 120
+#define NSSPORT4_RESET 121
+#define NSSPORT5_RESET 122
+#define NSSPORT6_RESET 123
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add NSSCC clock and reset definitions for ipq9574.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Referenced gcc.yaml and dropped the duplicate properties from
the binding
- Updated Uniphy clock names
- Added nssnoc clocks and clock-names
.../bindings/clock/qcom,ipq9574-nsscc.yaml | 107 ++++++++++++
.../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++
.../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++
3 files changed, 393 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
new file mode 100644
index 000000000000..570a9c654781
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Anusha Rao <quic_anusha@quicinc.com>
+
+description: |
+ Qualcomm networking sub system clock control module provides the clocks,
+ resets and power domains on IPQ9574
+
+ See also::
+ include/dt-bindings/clock/qcom,ipq9574-nsscc.h
+ include/dt-bindings/reset/qcom,ipq9574-nsscc.h
+
+properties:
+ compatible:
+ const: qcom,ipq9574-nsscc
+
+ clocks:
+ items:
+ - description: NSSNOC NSSCC clock source
+ - description: NSSNOC SNOC clock source
+ - description: NSSNOC SNOC_1 clock source
+ - description: Bias PLL cc clock source
+ - description: Bias PLL nss noc clock source
+ - description: Bias PLL ubi nc clock source
+ - description: GCC GPLL0 OUT AUX clock source
+ - description: Uniphy0 NSS Rx clock source
+ - description: Uniphy0 NSS Tx clock source
+ - description: Uniphy1 NSS Rx clock source
+ - description: Uniphy1 NSS Tx clock source
+ - description: Uniphy2 NSS Rx clock source
+ - description: Uniphy2 NSS Tx clock source
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: nssnoc_nsscc
+ - const: nssnoc_snoc
+ - const: nssnoc_snoc_1
+ - const: bias_pll_cc_clk
+ - const: bias_pll_nss_noc_clk
+ - const: bias_pll_ubi_nc_clk
+ - const: gpll0_out_aux
+ - const: uniphy0_nss_rx_clk
+ - const: uniphy0_nss_tx_clk
+ - const: uniphy1_nss_rx_clk
+ - const: uniphy1_nss_tx_clk
+ - const: uniphy2_nss_rx_clk
+ - const: uniphy2_nss_tx_clk
+ - const: xo_board_clk
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+ clock-controller@39b00000 {
+ compatible = "qcom,ipq9574-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_1_CLK>,
+ <&bias_pll_cc_clk>,
+ <&bias_pll_nss_noc_clk>,
+ <&bias_pll_ubi_nc_clk>,
+ <&gcc GPLL0_OUT_AUX>,
+ <&uniphy 0>,
+ <&uniphy 1>,
+ <&uniphy 2>,
+ <&uniphy 3>,
+ <&uniphy 4>,
+ <&uniphy 5>,
+ <&xo_board_clk>;
+ clock-names = "nssnoc_nsscc",
+ "nssnoc_snoc",
+ "nssnoc_snoc_1",
+ "bias_pll_cc_clk",
+ "bias_pll_nss_noc_clk",
+ "bias_pll_ubi_nc_clk",
+ "gpll0_out_aux",
+ "uniphy0_nss_rx_clk",
+ "uniphy0_nss_tx_clk",
+ "uniphy1_nss_rx_clk",
+ "uniphy1_nss_tx_clk",
+ "uniphy2_nss_rx_clk",
+ "uniphy2_nss_tx_clk",
+ "xo_board_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
new file mode 100644
index 000000000000..59d57d9c788c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
+#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
+
+#define NSS_CC_CE_APB_CLK 0
+#define NSS_CC_CE_AXI_CLK 1
+#define NSS_CC_CE_CLK_SRC 2
+#define NSS_CC_CFG_CLK_SRC 3
+#define NSS_CC_CLC_AXI_CLK 4
+#define NSS_CC_CLC_CLK_SRC 5
+#define NSS_CC_CRYPTO_CLK 6
+#define NSS_CC_CRYPTO_CLK_SRC 7
+#define NSS_CC_CRYPTO_PPE_CLK 8
+#define NSS_CC_HAQ_AHB_CLK 9
+#define NSS_CC_HAQ_AXI_CLK 10
+#define NSS_CC_HAQ_CLK_SRC 11
+#define NSS_CC_IMEM_AHB_CLK 12
+#define NSS_CC_IMEM_CLK_SRC 13
+#define NSS_CC_IMEM_QSB_CLK 14
+#define NSS_CC_INT_CFG_CLK_SRC 15
+#define NSS_CC_NSS_CSR_CLK 16
+#define NSS_CC_NSSNOC_CE_APB_CLK 17
+#define NSS_CC_NSSNOC_CE_AXI_CLK 18
+#define NSS_CC_NSSNOC_CLC_AXI_CLK 19
+#define NSS_CC_NSSNOC_CRYPTO_CLK 20
+#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21
+#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22
+#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23
+#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24
+#define NSS_CC_NSSNOC_NSS_CSR_CLK 25
+#define NSS_CC_NSSNOC_PPE_CFG_CLK 26
+#define NSS_CC_NSSNOC_PPE_CLK 27
+#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28
+#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29
+#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30
+#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31
+#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32
+#define NSS_CC_PORT1_MAC_CLK 33
+#define NSS_CC_PORT1_RX_CLK 34
+#define NSS_CC_PORT1_RX_CLK_SRC 35
+#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36
+#define NSS_CC_PORT1_TX_CLK 37
+#define NSS_CC_PORT1_TX_CLK_SRC 38
+#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39
+#define NSS_CC_PORT2_MAC_CLK 40
+#define NSS_CC_PORT2_RX_CLK 41
+#define NSS_CC_PORT2_RX_CLK_SRC 42
+#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43
+#define NSS_CC_PORT2_TX_CLK 44
+#define NSS_CC_PORT2_TX_CLK_SRC 45
+#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46
+#define NSS_CC_PORT3_MAC_CLK 47
+#define NSS_CC_PORT3_RX_CLK 48
+#define NSS_CC_PORT3_RX_CLK_SRC 49
+#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50
+#define NSS_CC_PORT3_TX_CLK 51
+#define NSS_CC_PORT3_TX_CLK_SRC 52
+#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53
+#define NSS_CC_PORT4_MAC_CLK 54
+#define NSS_CC_PORT4_RX_CLK 55
+#define NSS_CC_PORT4_RX_CLK_SRC 56
+#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57
+#define NSS_CC_PORT4_TX_CLK 58
+#define NSS_CC_PORT4_TX_CLK_SRC 59
+#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60
+#define NSS_CC_PORT5_MAC_CLK 61
+#define NSS_CC_PORT5_RX_CLK 62
+#define NSS_CC_PORT5_RX_CLK_SRC 63
+#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64
+#define NSS_CC_PORT5_TX_CLK 65
+#define NSS_CC_PORT5_TX_CLK_SRC 66
+#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67
+#define NSS_CC_PORT6_MAC_CLK 68
+#define NSS_CC_PORT6_RX_CLK 69
+#define NSS_CC_PORT6_RX_CLK_SRC 70
+#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71
+#define NSS_CC_PORT6_TX_CLK 72
+#define NSS_CC_PORT6_TX_CLK_SRC 73
+#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74
+#define NSS_CC_PPE_CLK_SRC 75
+#define NSS_CC_PPE_EDMA_CFG_CLK 76
+#define NSS_CC_PPE_EDMA_CLK 77
+#define NSS_CC_PPE_SWITCH_BTQ_CLK 78
+#define NSS_CC_PPE_SWITCH_CFG_CLK 79
+#define NSS_CC_PPE_SWITCH_CLK 80
+#define NSS_CC_PPE_SWITCH_IPE_CLK 81
+#define NSS_CC_UBI0_CLK_SRC 82
+#define NSS_CC_UBI0_DIV_CLK_SRC 83
+#define NSS_CC_UBI1_CLK_SRC 84
+#define NSS_CC_UBI1_DIV_CLK_SRC 85
+#define NSS_CC_UBI2_CLK_SRC 86
+#define NSS_CC_UBI2_DIV_CLK_SRC 87
+#define NSS_CC_UBI32_AHB0_CLK 88
+#define NSS_CC_UBI32_AHB1_CLK 89
+#define NSS_CC_UBI32_AHB2_CLK 90
+#define NSS_CC_UBI32_AHB3_CLK 91
+#define NSS_CC_UBI32_AXI0_CLK 92
+#define NSS_CC_UBI32_AXI1_CLK 93
+#define NSS_CC_UBI32_AXI2_CLK 94
+#define NSS_CC_UBI32_AXI3_CLK 95
+#define NSS_CC_UBI32_CORE0_CLK 96
+#define NSS_CC_UBI32_CORE1_CLK 97
+#define NSS_CC_UBI32_CORE2_CLK 98
+#define NSS_CC_UBI32_CORE3_CLK 99
+#define NSS_CC_UBI32_INTR0_AHB_CLK 100
+#define NSS_CC_UBI32_INTR1_AHB_CLK 101
+#define NSS_CC_UBI32_INTR2_AHB_CLK 102
+#define NSS_CC_UBI32_INTR3_AHB_CLK 103
+#define NSS_CC_UBI32_NC_AXI0_CLK 104
+#define NSS_CC_UBI32_NC_AXI1_CLK 105
+#define NSS_CC_UBI32_NC_AXI2_CLK 106
+#define NSS_CC_UBI32_NC_AXI3_CLK 107
+#define NSS_CC_UBI32_UTCM0_CLK 108
+#define NSS_CC_UBI32_UTCM1_CLK 109
+#define NSS_CC_UBI32_UTCM2_CLK 110
+#define NSS_CC_UBI32_UTCM3_CLK 111
+#define NSS_CC_UBI3_CLK_SRC 112
+#define NSS_CC_UBI3_DIV_CLK_SRC 113
+#define NSS_CC_UBI_AXI_CLK_SRC 114
+#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115
+#define NSS_CC_UNIPHY_PORT1_RX_CLK 116
+#define NSS_CC_UNIPHY_PORT1_TX_CLK 117
+#define NSS_CC_UNIPHY_PORT2_RX_CLK 118
+#define NSS_CC_UNIPHY_PORT2_TX_CLK 119
+#define NSS_CC_UNIPHY_PORT3_RX_CLK 120
+#define NSS_CC_UNIPHY_PORT3_TX_CLK 121
+#define NSS_CC_UNIPHY_PORT4_RX_CLK 122
+#define NSS_CC_UNIPHY_PORT4_TX_CLK 123
+#define NSS_CC_UNIPHY_PORT5_RX_CLK 124
+#define NSS_CC_UNIPHY_PORT5_TX_CLK 125
+#define NSS_CC_UNIPHY_PORT6_RX_CLK 126
+#define NSS_CC_UNIPHY_PORT6_TX_CLK 127
+#define NSS_CC_XGMAC0_PTP_REF_CLK 128
+#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129
+#define NSS_CC_XGMAC1_PTP_REF_CLK 130
+#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131
+#define NSS_CC_XGMAC2_PTP_REF_CLK 132
+#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133
+#define NSS_CC_XGMAC3_PTP_REF_CLK 134
+#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135
+#define NSS_CC_XGMAC4_PTP_REF_CLK 136
+#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137
+#define NSS_CC_XGMAC5_PTP_REF_CLK 138
+#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139
+#define UBI32_PLL 140
+#define UBI32_PLL_MAIN 141
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
new file mode 100644
index 000000000000..6910db0cff51
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
+#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
+
+#define EDMA_HW_RESET 0
+#define NSS_CC_CE_BCR 1
+#define NSS_CC_CLC_BCR 2
+#define NSS_CC_EIP197_BCR 3
+#define NSS_CC_HAQ_BCR 4
+#define NSS_CC_IMEM_BCR 5
+#define NSS_CC_MAC_BCR 6
+#define NSS_CC_PPE_BCR 7
+#define NSS_CC_UBI_BCR 8
+#define NSS_CC_UNIPHY_BCR 9
+#define UBI3_CLKRST_CLAMP_ENABLE 10
+#define UBI3_CORE_CLAMP_ENABLE 11
+#define UBI2_CLKRST_CLAMP_ENABLE 12
+#define UBI2_CORE_CLAMP_ENABLE 13
+#define UBI1_CLKRST_CLAMP_ENABLE 14
+#define UBI1_CORE_CLAMP_ENABLE 15
+#define UBI0_CLKRST_CLAMP_ENABLE 16
+#define UBI0_CORE_CLAMP_ENABLE 17
+#define NSSNOC_NSS_CSR_ARES 18
+#define NSS_CSR_ARES 19
+#define PPE_BTQ_ARES 20
+#define PPE_IPE_ARES 21
+#define PPE_ARES 22
+#define PPE_CFG_ARES 23
+#define PPE_EDMA_ARES 24
+#define PPE_EDMA_CFG_ARES 25
+#define CRY_PPE_ARES 26
+#define NSSNOC_PPE_ARES 27
+#define NSSNOC_PPE_CFG_ARES 28
+#define PORT1_MAC_ARES 29
+#define PORT2_MAC_ARES 30
+#define PORT3_MAC_ARES 31
+#define PORT4_MAC_ARES 32
+#define PORT5_MAC_ARES 33
+#define PORT6_MAC_ARES 34
+#define XGMAC0_PTP_REF_ARES 35
+#define XGMAC1_PTP_REF_ARES 36
+#define XGMAC2_PTP_REF_ARES 37
+#define XGMAC3_PTP_REF_ARES 38
+#define XGMAC4_PTP_REF_ARES 39
+#define XGMAC5_PTP_REF_ARES 40
+#define HAQ_AHB_ARES 41
+#define HAQ_AXI_ARES 42
+#define NSSNOC_HAQ_AHB_ARES 43
+#define NSSNOC_HAQ_AXI_ARES 44
+#define CE_APB_ARES 45
+#define CE_AXI_ARES 46
+#define NSSNOC_CE_APB_ARES 47
+#define NSSNOC_CE_AXI_ARES 48
+#define CRYPTO_ARES 49
+#define NSSNOC_CRYPTO_ARES 50
+#define NSSNOC_NC_AXI0_1_ARES 51
+#define UBI0_CORE_ARES 52
+#define UBI1_CORE_ARES 53
+#define UBI2_CORE_ARES 54
+#define UBI3_CORE_ARES 55
+#define NC_AXI0_ARES 56
+#define UTCM0_ARES 57
+#define NC_AXI1_ARES 58
+#define UTCM1_ARES 59
+#define NC_AXI2_ARES 60
+#define UTCM2_ARES 61
+#define NC_AXI3_ARES 62
+#define UTCM3_ARES 63
+#define NSSNOC_NC_AXI0_ARES 64
+#define AHB0_ARES 65
+#define INTR0_AHB_ARES 66
+#define AHB1_ARES 67
+#define INTR1_AHB_ARES 68
+#define AHB2_ARES 69
+#define INTR2_AHB_ARES 70
+#define AHB3_ARES 71
+#define INTR3_AHB_ARES 72
+#define NSSNOC_AHB0_ARES 73
+#define NSSNOC_INT0_AHB_ARES 74
+#define AXI0_ARES 75
+#define AXI1_ARES 76
+#define AXI2_ARES 77
+#define AXI3_ARES 78
+#define NSSNOC_AXI0_ARES 79
+#define IMEM_QSB_ARES 80
+#define NSSNOC_IMEM_QSB_ARES 81
+#define IMEM_AHB_ARES 82
+#define NSSNOC_IMEM_AHB_ARES 83
+#define UNIPHY_PORT1_RX_ARES 84
+#define UNIPHY_PORT1_TX_ARES 85
+#define UNIPHY_PORT2_RX_ARES 86
+#define UNIPHY_PORT2_TX_ARES 87
+#define UNIPHY_PORT3_RX_ARES 88
+#define UNIPHY_PORT3_TX_ARES 89
+#define UNIPHY_PORT4_RX_ARES 90
+#define UNIPHY_PORT4_TX_ARES 91
+#define UNIPHY_PORT5_RX_ARES 92
+#define UNIPHY_PORT5_TX_ARES 93
+#define UNIPHY_PORT6_RX_ARES 94
+#define UNIPHY_PORT6_TX_ARES 95
+#define PORT1_RX_ARES 96
+#define PORT1_TX_ARES 97
+#define PORT2_RX_ARES 98
+#define PORT2_TX_ARES 99
+#define PORT3_RX_ARES 100
+#define PORT3_TX_ARES 101
+#define PORT4_RX_ARES 102
+#define PORT4_TX_ARES 103
+#define PORT5_RX_ARES 104
+#define PORT5_TX_ARES 105
+#define PORT6_RX_ARES 106
+#define PORT6_TX_ARES 107
+#define PPE_FULL_RESET 108
+#define UNIPHY0_SOFT_RESET 109
+#define UNIPHY1_SOFT_RESET 110
+#define UNIPHY2_SOFT_RESET 111
+#define UNIPHY_PORT1_ARES 112
+#define UNIPHY_PORT2_ARES 113
+#define UNIPHY_PORT3_ARES 114
+#define UNIPHY_PORT4_ARES 115
+#define UNIPHY_PORT5_ARES 116
+#define UNIPHY_PORT6_ARES 117
+#define NSSPORT1_RESET 118
+#define NSSPORT2_RESET 119
+#define NSSPORT3_RESET 120
+#define NSSPORT4_RESET 121
+#define NSSPORT5_RESET 122
+#define NSSPORT6_RESET 123
+
+#endif
--
2.34.1
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^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 9:12 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
devices.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Added depends on ARM64 || COMPILE_TEST in Kconfig
- Added module_platform_driver
- Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc clocks as critical
& added pm_clk for nssnoc clocks
- Updated the uniphy clock names
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
3 files changed, 3117 insertions(+)
create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index bd9bfb11b328..3ecc11e2c8e3 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -203,6 +203,13 @@ config IPQ_GCC_9574
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq9574.
+config IPQ_NSSCC_9574
+ tristate "IPQ9574 NSS Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ depends on IPQ_GCC_9574
+ help
+ Support for NSS clock controller on ipq9574 devices.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 4790c8cca426..3f084928962e 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
+obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9574.c
new file mode 100644
index 000000000000..65bdb449ae5f
--- /dev/null
+++ b/drivers/clk/qcom/nsscc-ipq9574.c
@@ -0,0 +1,3109 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_runtime.h>
+
+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+/* Need to match the order of clocks in DT binding */
+enum {
+ DT_NSSNOC_NSSCC_CLK,
+ DT_NSSNOC_SNOC_CLK,
+ DT_NSSNOC_SNOC_1_CLK,
+ DT_BIAS_PLL_CC_CLK,
+ DT_BIAS_PLL_NSS_NOC_CLK,
+ DT_BIAS_PLL_UBI_NC_CLK,
+ DT_GCC_GPLL0_OUT_AUX,
+ DT_UNIPHY0_NSS_RX_CLK,
+ DT_UNIPHY0_NSS_TX_CLK,
+ DT_UNIPHY1_NSS_RX_CLK,
+ DT_UNIPHY1_NSS_TX_CLK,
+ DT_UNIPHY2_NSS_RX_CLK,
+ DT_UNIPHY2_NSS_TX_CLK,
+ DT_XO,
+};
+
+enum {
+ P_BIAS_PLL_CC_CLK,
+ P_BIAS_PLL_NSS_NOC_CLK,
+ P_BIAS_PLL_UBI_NC_CLK,
+ P_GCC_GPLL0_OUT_AUX,
+ P_UBI32_PLL_OUT_MAIN,
+ P_UNIPHY0_NSS_RX_CLK,
+ P_UNIPHY0_NSS_TX_CLK,
+ P_UNIPHY1_NSS_RX_CLK,
+ P_UNIPHY1_NSS_TX_CLK,
+ P_UNIPHY2_NSS_RX_CLK,
+ P_UNIPHY2_NSS_TX_CLK,
+ P_XO,
+};
+
+static const struct alpha_pll_config ubi32_pll_config = {
+ .l = 0x3e,
+ .alpha = 0x6666,
+ .config_ctl_val = 0x200d4aa8,
+ .config_ctl_hi_val = 0x3c,
+ .main_output_mask = BIT(0),
+ .aux_output_mask = BIT(1),
+ .pre_div_val = 0x0,
+ .pre_div_mask = BIT(12),
+ .post_div_val = 0x0,
+ .post_div_mask = GENMASK(9, 8),
+ .alpha_en_mask = BIT(24),
+ .test_ctl_val = 0x1c0000c0,
+ .test_ctl_hi_val = 0x4000,
+};
+
+static struct clk_alpha_pll ubi32_pll_main = {
+ .offset = 0x28000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ubi32_pll_main",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_XO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv ubi32_pll = {
+ .offset = 0x28000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
+ .width = 2,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ubi32_pll",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi32_pll_main.clkr.hw
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct parent_map nss_cc_parent_map_0[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_CC_CLK, 1 },
+ { P_UNIPHY0_NSS_RX_CLK, 2 },
+ { P_UNIPHY0_NSS_TX_CLK, 3 },
+ { P_UNIPHY1_NSS_RX_CLK, 4 },
+ { P_UNIPHY1_NSS_TX_CLK, 5 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_0[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_CC_CLK },
+ { .index = DT_UNIPHY0_NSS_RX_CLK },
+ { .index = DT_UNIPHY0_NSS_TX_CLK },
+ { .index = DT_UNIPHY1_NSS_RX_CLK },
+ { .index = DT_UNIPHY1_NSS_TX_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_1[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_UBI_NC_CLK, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_BIAS_PLL_CC_CLK, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_1[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_UBI_NC_CLK },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_BIAS_PLL_CC_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_2[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_2[] = {
+ { .index = DT_XO },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+};
+
+static const struct parent_map nss_cc_parent_map_3[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_CC_CLK, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_3[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_CC_CLK },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+};
+
+static const struct parent_map nss_cc_parent_map_4[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_CC_CLK, 1 },
+ { P_UNIPHY0_NSS_RX_CLK, 2 },
+ { P_UNIPHY0_NSS_TX_CLK, 3 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_4[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_CC_CLK },
+ { .index = DT_UNIPHY0_NSS_RX_CLK },
+ { .index = DT_UNIPHY0_NSS_TX_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_5[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_CC_CLK, 1 },
+ { P_UNIPHY2_NSS_RX_CLK, 2 },
+ { P_UNIPHY2_NSS_TX_CLK, 3 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_5[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_CC_CLK },
+ { .index = DT_UNIPHY2_NSS_RX_CLK },
+ { .index = DT_UNIPHY2_NSS_TX_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_6[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC_CLK, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_BIAS_PLL_CC_CLK, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_6[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_NSS_NOC_CLK },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_BIAS_PLL_CC_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_7[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_BIAS_PLL_CC_CLK, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_7[] = {
+ { .index = DT_XO },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_BIAS_PLL_CC_CLK },
+};
+
+static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(353000000, P_BIAS_PLL_UBI_NC_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_ce_clk_src = {
+ .cmd_rcgr = 0x28404,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
+ F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_cfg_clk_src = {
+ .cmd_rcgr = 0x28104,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_3,
+ .freq_tbl = ftbl_nss_cc_cfg_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_cfg_clk_src",
+ .parent_data = nss_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_clc_clk_src[] = {
+ F(533333333, P_GCC_GPLL0_OUT_AUX, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_clc_clk_src = {
+ .cmd_rcgr = 0x28604,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_6,
+ .freq_tbl = ftbl_nss_cc_clc_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_clc_clk_src",
+ .parent_data = nss_cc_parent_data_6,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_6),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_crypto_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(300000000, P_BIAS_PLL_CC_CLK, 4, 0, 0),
+ F(600000000, P_BIAS_PLL_CC_CLK, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_crypto_clk_src = {
+ .cmd_rcgr = 0x16008,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_3,
+ .freq_tbl = ftbl_nss_cc_crypto_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_crypto_clk_src",
+ .parent_data = nss_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_haq_clk_src = {
+ .cmd_rcgr = 0x28304,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_haq_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_imem_clk_src = {
+ .cmd_rcgr = 0xe008,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_imem_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_int_cfg_clk_src[] = {
+ F(200000000, P_GCC_GPLL0_OUT_AUX, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_int_cfg_clk_src = {
+ .cmd_rcgr = 0x287b4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_3,
+ .freq_tbl = ftbl_nss_cc_int_cfg_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_int_cfg_clk_src",
+ .parent_data = nss_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
+ C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
+ C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
+ FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
+ C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
+ C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
+ FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_312p5[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port5_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port5_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port5_rx_clk_src_125),
+ FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
+ FM(312500000, ftbl_nss_cc_port5_rx_clk_src_312p5),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_312p5[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port5_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port5_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port5_tx_clk_src_125),
+ FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
+ FM(312500000, ftbl_nss_cc_port5_tx_clk_src_312p5),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_25[] = {
+ C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_125[] = {
+ C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port6_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port6_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port6_rx_clk_src_125),
+ FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_25[] = {
+ C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_125[] = {
+ C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port6_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port6_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port6_tx_clk_src_125),
+ FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
+ .cmd_rcgr = 0x28110,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
+ .cmd_rcgr = 0x2811c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
+ .cmd_rcgr = 0x28128,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
+ .cmd_rcgr = 0x28134,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port3_rx_clk_src = {
+ .cmd_rcgr = 0x28140,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_rx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port3_tx_clk_src = {
+ .cmd_rcgr = 0x2814c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_tx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port4_rx_clk_src = {
+ .cmd_rcgr = 0x28158,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_rx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port4_tx_clk_src = {
+ .cmd_rcgr = 0x28164,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_tx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port5_rx_clk_src = {
+ .cmd_rcgr = 0x28170,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_multi_tbl = ftbl_nss_cc_port5_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_rx_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port5_tx_clk_src = {
+ .cmd_rcgr = 0x2817c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_multi_tbl = ftbl_nss_cc_port5_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_tx_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port6_rx_clk_src = {
+ .cmd_rcgr = 0x28188,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_5,
+ .freq_multi_tbl = ftbl_nss_cc_port6_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_rx_clk_src",
+ .parent_data = nss_cc_parent_data_5,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port6_tx_clk_src = {
+ .cmd_rcgr = 0x28194,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_5,
+ .freq_multi_tbl = ftbl_nss_cc_port6_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_tx_clk_src",
+ .parent_data = nss_cc_parent_data_5,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ppe_clk_src = {
+ .cmd_rcgr = 0x28204,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_ubi0_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(187200000, P_UBI32_PLL_OUT_MAIN, 8, 0, 0),
+ F(748800000, P_UBI32_PLL_OUT_MAIN, 2, 0, 0),
+ F(1497600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
+ F(1689600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_ubi0_clk_src = {
+ .cmd_rcgr = 0x28704,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi0_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi1_clk_src = {
+ .cmd_rcgr = 0x2870c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi1_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi2_clk_src = {
+ .cmd_rcgr = 0x28714,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi2_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi3_clk_src = {
+ .cmd_rcgr = 0x2871c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi3_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi_axi_clk_src = {
+ .cmd_rcgr = 0x28724,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_7,
+ .freq_tbl = ftbl_nss_cc_clc_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi_axi_clk_src",
+ .parent_data = nss_cc_parent_data_7,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_7),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi_nc_axi_bfdcd_clk_src = {
+ .cmd_rcgr = 0x2872c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi_nc_axi_bfdcd_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
+ .reg = 0x28118,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
+ .reg = 0x28124,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
+ .reg = 0x28130,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
+ .reg = 0x2813c,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = {
+ .reg = 0x28148,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = {
+ .reg = 0x28154,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port4_rx_div_clk_src = {
+ .reg = 0x28160,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port4_tx_div_clk_src = {
+ .reg = 0x2816c,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port5_rx_div_clk_src = {
+ .reg = 0x28178,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port5_tx_div_clk_src = {
+ .reg = 0x28184,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port6_rx_div_clk_src = {
+ .reg = 0x28190,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port6_tx_div_clk_src = {
+ .reg = 0x2819c,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_ubi0_div_clk_src = {
+ .reg = 0x287a4,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi0_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_ubi1_div_clk_src = {
+ .reg = 0x287a8,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi1_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_ubi2_div_clk_src = {
+ .reg = 0x287ac,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi2_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_ubi3_div_clk_src = {
+ .reg = 0x287b0,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi3_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
+ .reg = 0x28214,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
+ .reg = 0x28218,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = {
+ .reg = 0x2821c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac2_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac3_ptp_ref_div_clk_src = {
+ .reg = 0x28220,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac3_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac4_ptp_ref_div_clk_src = {
+ .reg = 0x28224,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac4_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac5_ptp_ref_div_clk_src = {
+ .reg = 0x28228,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac5_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch nss_cc_ce_apb_clk = {
+ .halt_reg = 0x2840c,
+ .clkr = {
+ .enable_reg = 0x2840c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_apb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ce_axi_clk = {
+ .halt_reg = 0x28410,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28410,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_clc_axi_clk = {
+ .halt_reg = 0x2860c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2860c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_clc_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_clc_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_crypto_clk = {
+ .halt_reg = 0x1601c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1601c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_crypto_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_crypto_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_crypto_ppe_clk = {
+ .halt_reg = 0x28240,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28240,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_crypto_ppe_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_haq_ahb_clk = {
+ .halt_reg = 0x2830c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2830c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_haq_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_haq_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_haq_axi_clk = {
+ .halt_reg = 0x28310,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28310,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_haq_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_haq_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_imem_ahb_clk = {
+ .halt_reg = 0xe018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_imem_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_imem_qsb_clk = {
+ .halt_reg = 0xe010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_imem_qsb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_imem_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nss_csr_clk = {
+ .halt_reg = 0x281d0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281d0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nss_csr_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
+ .halt_reg = 0x28414,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28414,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ce_apb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
+ .halt_reg = 0x28418,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28418,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ce_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_clc_axi_clk = {
+ .halt_reg = 0x28610,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28610,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_clc_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_clc_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_crypto_clk = {
+ .halt_reg = 0x16020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_crypto_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_crypto_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_haq_ahb_clk = {
+ .halt_reg = 0x28314,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28314,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_haq_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_haq_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_haq_axi_clk = {
+ .halt_reg = 0x28318,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28318,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_haq_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_haq_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_imem_ahb_clk = {
+ .halt_reg = 0xe01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_imem_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_imem_qsb_clk = {
+ .halt_reg = 0xe014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_imem_qsb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_imem_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
+ .halt_reg = 0x281d4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281d4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_nss_csr_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
+ .halt_reg = 0x28248,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28248,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ppe_cfg_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ppe_clk = {
+ .halt_reg = 0x28244,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28244,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ppe_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_ahb0_clk = {
+ .halt_reg = 0x28788,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28788,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_ahb0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_axi0_clk = {
+ .halt_reg = 0x287a0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x287a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_axi0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_int0_ahb_clk = {
+ .halt_reg = 0x2878c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2878c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_int0_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_1_clk = {
+ .halt_reg = 0x287bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x287bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_nc_axi0_1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_clk = {
+ .halt_reg = 0x28764,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28764,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_nc_axi0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_mac_clk = {
+ .halt_reg = 0x2824c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2824c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_rx_clk = {
+ .halt_reg = 0x281a0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_tx_clk = {
+ .halt_reg = 0x281a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_mac_clk = {
+ .halt_reg = 0x28250,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28250,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_rx_clk = {
+ .halt_reg = 0x281a8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281a8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_tx_clk = {
+ .halt_reg = 0x281ac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port3_mac_clk = {
+ .halt_reg = 0x28254,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28254,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port3_rx_clk = {
+ .halt_reg = 0x281b0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281b0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port3_tx_clk = {
+ .halt_reg = 0x281b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port4_mac_clk = {
+ .halt_reg = 0x28258,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28258,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port4_rx_clk = {
+ .halt_reg = 0x281b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port4_tx_clk = {
+ .halt_reg = 0x281bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port5_mac_clk = {
+ .halt_reg = 0x2825c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2825c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port5_rx_clk = {
+ .halt_reg = 0x281c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port5_tx_clk = {
+ .halt_reg = 0x281c4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281c4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port6_mac_clk = {
+ .halt_reg = 0x28260,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28260,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port6_rx_clk = {
+ .halt_reg = 0x281c8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281c8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port6_tx_clk = {
+ .halt_reg = 0x281cc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281cc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
+ .halt_reg = 0x2823c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2823c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_edma_cfg_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_edma_clk = {
+ .halt_reg = 0x28238,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28238,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_edma_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_btq_clk = {
+ .halt_reg = 0x2827c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2827c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_btq_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
+ .halt_reg = 0x28234,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28234,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_cfg_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_clk = {
+ .halt_reg = 0x28230,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28230,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
+ .halt_reg = 0x2822c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2822c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_ipe_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_ahb0_clk = {
+ .halt_reg = 0x28768,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28768,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_ahb0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_ahb1_clk = {
+ .halt_reg = 0x28770,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28770,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_ahb1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_ahb2_clk = {
+ .halt_reg = 0x28778,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28778,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_ahb2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_ahb3_clk = {
+ .halt_reg = 0x28780,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28780,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_ahb3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_axi0_clk = {
+ .halt_reg = 0x28790,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28790,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_axi0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_axi1_clk = {
+ .halt_reg = 0x28794,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28794,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_axi1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_axi2_clk = {
+ .halt_reg = 0x28798,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28798,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_axi2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_axi3_clk = {
+ .halt_reg = 0x2879c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2879c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_axi3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_core0_clk = {
+ .halt_reg = 0x28734,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28734,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_core0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi0_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_core1_clk = {
+ .halt_reg = 0x28738,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28738,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_core1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi1_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_core2_clk = {
+ .halt_reg = 0x2873c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2873c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_core2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi2_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_core3_clk = {
+ .halt_reg = 0x28740,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28740,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_core3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi3_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_intr0_ahb_clk = {
+ .halt_reg = 0x2876c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2876c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_intr0_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_intr1_ahb_clk = {
+ .halt_reg = 0x28774,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28774,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_intr1_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_intr2_ahb_clk = {
+ .halt_reg = 0x2877c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2877c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_intr2_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_intr3_ahb_clk = {
+ .halt_reg = 0x28784,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28784,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_intr3_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_nc_axi0_clk = {
+ .halt_reg = 0x28744,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28744,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_nc_axi0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_nc_axi1_clk = {
+ .halt_reg = 0x2874c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2874c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_nc_axi1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_nc_axi2_clk = {
+ .halt_reg = 0x28754,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28754,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_nc_axi2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_nc_axi3_clk = {
+ .halt_reg = 0x2875c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2875c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_nc_axi3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_utcm0_clk = {
+ .halt_reg = 0x28748,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28748,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_utcm0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_utcm1_clk = {
+ .halt_reg = 0x28750,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28750,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_utcm1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_utcm2_clk = {
+ .halt_reg = 0x28758,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28758,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_utcm2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_utcm3_clk = {
+ .halt_reg = 0x28760,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28760,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_utcm3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
+ .halt_reg = 0x28904,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28904,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port1_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
+ .halt_reg = 0x28908,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28908,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port1_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
+ .halt_reg = 0x2890c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2890c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port2_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
+ .halt_reg = 0x28910,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28910,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port2_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port3_rx_clk = {
+ .halt_reg = 0x28914,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28914,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port3_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port3_tx_clk = {
+ .halt_reg = 0x28918,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28918,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port3_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port4_rx_clk = {
+ .halt_reg = 0x2891c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2891c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port4_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port4_tx_clk = {
+ .halt_reg = 0x28920,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28920,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port4_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port5_rx_clk = {
+ .halt_reg = 0x28924,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28924,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port5_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port5_tx_clk = {
+ .halt_reg = 0x28928,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28928,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port5_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port6_rx_clk = {
+ .halt_reg = 0x2892c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2892c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port6_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port6_tx_clk = {
+ .halt_reg = 0x28930,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28930,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port6_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
+ .halt_reg = 0x28264,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28264,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac0_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
+ .halt_reg = 0x28268,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28268,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac1_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = {
+ .halt_reg = 0x2826c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2826c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac2_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac3_ptp_ref_clk = {
+ .halt_reg = 0x28270,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28270,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac3_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac4_ptp_ref_clk = {
+ .halt_reg = 0x28274,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28274,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac4_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac5_ptp_ref_clk = {
+ .halt_reg = 0x28278,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28278,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac5_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *nss_cc_ipq9574_clocks[] = {
+ [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
+ [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
+ [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
+ [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
+ [NSS_CC_CLC_AXI_CLK] = &nss_cc_clc_axi_clk.clkr,
+ [NSS_CC_CLC_CLK_SRC] = &nss_cc_clc_clk_src.clkr,
+ [NSS_CC_CRYPTO_CLK] = &nss_cc_crypto_clk.clkr,
+ [NSS_CC_CRYPTO_CLK_SRC] = &nss_cc_crypto_clk_src.clkr,
+ [NSS_CC_CRYPTO_PPE_CLK] = &nss_cc_crypto_ppe_clk.clkr,
+ [NSS_CC_HAQ_AHB_CLK] = &nss_cc_haq_ahb_clk.clkr,
+ [NSS_CC_HAQ_AXI_CLK] = &nss_cc_haq_axi_clk.clkr,
+ [NSS_CC_HAQ_CLK_SRC] = &nss_cc_haq_clk_src.clkr,
+ [NSS_CC_IMEM_AHB_CLK] = &nss_cc_imem_ahb_clk.clkr,
+ [NSS_CC_IMEM_CLK_SRC] = &nss_cc_imem_clk_src.clkr,
+ [NSS_CC_IMEM_QSB_CLK] = &nss_cc_imem_qsb_clk.clkr,
+ [NSS_CC_INT_CFG_CLK_SRC] = &nss_cc_int_cfg_clk_src.clkr,
+ [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
+ [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
+ [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
+ [NSS_CC_NSSNOC_CLC_AXI_CLK] = &nss_cc_nssnoc_clc_axi_clk.clkr,
+ [NSS_CC_NSSNOC_CRYPTO_CLK] = &nss_cc_nssnoc_crypto_clk.clkr,
+ [NSS_CC_NSSNOC_HAQ_AHB_CLK] = &nss_cc_nssnoc_haq_ahb_clk.clkr,
+ [NSS_CC_NSSNOC_HAQ_AXI_CLK] = &nss_cc_nssnoc_haq_axi_clk.clkr,
+ [NSS_CC_NSSNOC_IMEM_AHB_CLK] = &nss_cc_nssnoc_imem_ahb_clk.clkr,
+ [NSS_CC_NSSNOC_IMEM_QSB_CLK] = &nss_cc_nssnoc_imem_qsb_clk.clkr,
+ [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
+ [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
+ [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_AHB0_CLK] = &nss_cc_nssnoc_ubi32_ahb0_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_AXI0_CLK] = &nss_cc_nssnoc_ubi32_axi0_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK] =
+ &nss_cc_nssnoc_ubi32_int0_ahb_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK] =
+ &nss_cc_nssnoc_ubi32_nc_axi0_1_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK] =
+ &nss_cc_nssnoc_ubi32_nc_axi0_clk.clkr,
+ [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
+ [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
+ [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
+ [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
+ [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
+ [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
+ [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
+ [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
+ [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
+ [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
+ [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
+ [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
+ [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
+ [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
+ [NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr,
+ [NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr,
+ [NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr,
+ [NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr,
+ [NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr,
+ [NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr,
+ [NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr,
+ [NSS_CC_PORT4_MAC_CLK] = &nss_cc_port4_mac_clk.clkr,
+ [NSS_CC_PORT4_RX_CLK] = &nss_cc_port4_rx_clk.clkr,
+ [NSS_CC_PORT4_RX_CLK_SRC] = &nss_cc_port4_rx_clk_src.clkr,
+ [NSS_CC_PORT4_RX_DIV_CLK_SRC] = &nss_cc_port4_rx_div_clk_src.clkr,
+ [NSS_CC_PORT4_TX_CLK] = &nss_cc_port4_tx_clk.clkr,
+ [NSS_CC_PORT4_TX_CLK_SRC] = &nss_cc_port4_tx_clk_src.clkr,
+ [NSS_CC_PORT4_TX_DIV_CLK_SRC] = &nss_cc_port4_tx_div_clk_src.clkr,
+ [NSS_CC_PORT5_MAC_CLK] = &nss_cc_port5_mac_clk.clkr,
+ [NSS_CC_PORT5_RX_CLK] = &nss_cc_port5_rx_clk.clkr,
+ [NSS_CC_PORT5_RX_CLK_SRC] = &nss_cc_port5_rx_clk_src.clkr,
+ [NSS_CC_PORT5_RX_DIV_CLK_SRC] = &nss_cc_port5_rx_div_clk_src.clkr,
+ [NSS_CC_PORT5_TX_CLK] = &nss_cc_port5_tx_clk.clkr,
+ [NSS_CC_PORT5_TX_CLK_SRC] = &nss_cc_port5_tx_clk_src.clkr,
+ [NSS_CC_PORT5_TX_DIV_CLK_SRC] = &nss_cc_port5_tx_div_clk_src.clkr,
+ [NSS_CC_PORT6_MAC_CLK] = &nss_cc_port6_mac_clk.clkr,
+ [NSS_CC_PORT6_RX_CLK] = &nss_cc_port6_rx_clk.clkr,
+ [NSS_CC_PORT6_RX_CLK_SRC] = &nss_cc_port6_rx_clk_src.clkr,
+ [NSS_CC_PORT6_RX_DIV_CLK_SRC] = &nss_cc_port6_rx_div_clk_src.clkr,
+ [NSS_CC_PORT6_TX_CLK] = &nss_cc_port6_tx_clk.clkr,
+ [NSS_CC_PORT6_TX_CLK_SRC] = &nss_cc_port6_tx_clk_src.clkr,
+ [NSS_CC_PORT6_TX_DIV_CLK_SRC] = &nss_cc_port6_tx_div_clk_src.clkr,
+ [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
+ [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
+ [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
+ [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
+ [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
+ [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
+ [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
+ [NSS_CC_UBI0_CLK_SRC] = &nss_cc_ubi0_clk_src.clkr,
+ [NSS_CC_UBI0_DIV_CLK_SRC] = &nss_cc_ubi0_div_clk_src.clkr,
+ [NSS_CC_UBI1_CLK_SRC] = &nss_cc_ubi1_clk_src.clkr,
+ [NSS_CC_UBI1_DIV_CLK_SRC] = &nss_cc_ubi1_div_clk_src.clkr,
+ [NSS_CC_UBI2_CLK_SRC] = &nss_cc_ubi2_clk_src.clkr,
+ [NSS_CC_UBI2_DIV_CLK_SRC] = &nss_cc_ubi2_div_clk_src.clkr,
+ [NSS_CC_UBI32_AHB0_CLK] = &nss_cc_ubi32_ahb0_clk.clkr,
+ [NSS_CC_UBI32_AHB1_CLK] = &nss_cc_ubi32_ahb1_clk.clkr,
+ [NSS_CC_UBI32_AHB2_CLK] = &nss_cc_ubi32_ahb2_clk.clkr,
+ [NSS_CC_UBI32_AHB3_CLK] = &nss_cc_ubi32_ahb3_clk.clkr,
+ [NSS_CC_UBI32_AXI0_CLK] = &nss_cc_ubi32_axi0_clk.clkr,
+ [NSS_CC_UBI32_AXI1_CLK] = &nss_cc_ubi32_axi1_clk.clkr,
+ [NSS_CC_UBI32_AXI2_CLK] = &nss_cc_ubi32_axi2_clk.clkr,
+ [NSS_CC_UBI32_AXI3_CLK] = &nss_cc_ubi32_axi3_clk.clkr,
+ [NSS_CC_UBI32_CORE0_CLK] = &nss_cc_ubi32_core0_clk.clkr,
+ [NSS_CC_UBI32_CORE1_CLK] = &nss_cc_ubi32_core1_clk.clkr,
+ [NSS_CC_UBI32_CORE2_CLK] = &nss_cc_ubi32_core2_clk.clkr,
+ [NSS_CC_UBI32_CORE3_CLK] = &nss_cc_ubi32_core3_clk.clkr,
+ [NSS_CC_UBI32_INTR0_AHB_CLK] = &nss_cc_ubi32_intr0_ahb_clk.clkr,
+ [NSS_CC_UBI32_INTR1_AHB_CLK] = &nss_cc_ubi32_intr1_ahb_clk.clkr,
+ [NSS_CC_UBI32_INTR2_AHB_CLK] = &nss_cc_ubi32_intr2_ahb_clk.clkr,
+ [NSS_CC_UBI32_INTR3_AHB_CLK] = &nss_cc_ubi32_intr3_ahb_clk.clkr,
+ [NSS_CC_UBI32_NC_AXI0_CLK] = &nss_cc_ubi32_nc_axi0_clk.clkr,
+ [NSS_CC_UBI32_NC_AXI1_CLK] = &nss_cc_ubi32_nc_axi1_clk.clkr,
+ [NSS_CC_UBI32_NC_AXI2_CLK] = &nss_cc_ubi32_nc_axi2_clk.clkr,
+ [NSS_CC_UBI32_NC_AXI3_CLK] = &nss_cc_ubi32_nc_axi3_clk.clkr,
+ [NSS_CC_UBI32_UTCM0_CLK] = &nss_cc_ubi32_utcm0_clk.clkr,
+ [NSS_CC_UBI32_UTCM1_CLK] = &nss_cc_ubi32_utcm1_clk.clkr,
+ [NSS_CC_UBI32_UTCM2_CLK] = &nss_cc_ubi32_utcm2_clk.clkr,
+ [NSS_CC_UBI32_UTCM3_CLK] = &nss_cc_ubi32_utcm3_clk.clkr,
+ [NSS_CC_UBI3_CLK_SRC] = &nss_cc_ubi3_clk_src.clkr,
+ [NSS_CC_UBI3_DIV_CLK_SRC] = &nss_cc_ubi3_div_clk_src.clkr,
+ [NSS_CC_UBI_AXI_CLK_SRC] = &nss_cc_ubi_axi_clk_src.clkr,
+ [NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC] =
+ &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr,
+ [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT4_RX_CLK] = &nss_cc_uniphy_port4_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT4_TX_CLK] = &nss_cc_uniphy_port4_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT5_RX_CLK] = &nss_cc_uniphy_port5_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT5_TX_CLK] = &nss_cc_uniphy_port5_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT6_RX_CLK] = &nss_cc_uniphy_port6_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT6_TX_CLK] = &nss_cc_uniphy_port6_tx_clk.clkr,
+ [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC3_PTP_REF_CLK] = &nss_cc_xgmac3_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC4_PTP_REF_CLK] = &nss_cc_xgmac4_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC5_PTP_REF_CLK] = &nss_cc_xgmac5_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr,
+ [UBI32_PLL] = &ubi32_pll.clkr,
+ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
+};
+
+static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
+ [NSS_CC_CE_BCR] = { 0x28400, 0 },
+ [NSS_CC_CLC_BCR] = { 0x28600, 0 },
+ [NSS_CC_EIP197_BCR] = { 0x16004, 0 },
+ [NSS_CC_HAQ_BCR] = { 0x28300, 0 },
+ [NSS_CC_IMEM_BCR] = { 0xe004, 0 },
+ [NSS_CC_MAC_BCR] = { 0x28100, 0 },
+ [NSS_CC_PPE_BCR] = { 0x28200, 0 },
+ [NSS_CC_UBI_BCR] = { 0x28700, 0 },
+ [NSS_CC_UNIPHY_BCR] = { 0x28900, 0 },
+ [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
+ [UBI3_CORE_CLAMP_ENABLE] = { 0x28A04, 8 },
+ [UBI2_CLKRST_CLAMP_ENABLE] = { 0x28A04, 7 },
+ [UBI2_CORE_CLAMP_ENABLE] = { 0x28A04, 6 },
+ [UBI1_CLKRST_CLAMP_ENABLE] = { 0x28A04, 5 },
+ [UBI1_CORE_CLAMP_ENABLE] = { 0x28A04, 4 },
+ [UBI0_CLKRST_CLAMP_ENABLE] = { 0x28A04, 3 },
+ [UBI0_CORE_CLAMP_ENABLE] = { 0x28A04, 2 },
+ [NSSNOC_NSS_CSR_ARES] = { 0x28A04, 1 },
+ [NSS_CSR_ARES] = { 0x28A04, 0 },
+ [PPE_BTQ_ARES] = { 0x28A08, 20 },
+ [PPE_IPE_ARES] = { 0x28A08, 19 },
+ [PPE_ARES] = { 0x28A08, 18 },
+ [PPE_CFG_ARES] = { 0x28A08, 17 },
+ [PPE_EDMA_ARES] = { 0x28A08, 16 },
+ [PPE_EDMA_CFG_ARES] = { 0x28A08, 15 },
+ [CRY_PPE_ARES] = { 0x28A08, 14 },
+ [NSSNOC_PPE_ARES] = { 0x28A08, 13 },
+ [NSSNOC_PPE_CFG_ARES] = { 0x28A08, 12 },
+ [PORT1_MAC_ARES] = { 0x28A08, 11 },
+ [PORT2_MAC_ARES] = { 0x28A08, 10 },
+ [PORT3_MAC_ARES] = { 0x28A08, 9 },
+ [PORT4_MAC_ARES] = { 0x28A08, 8 },
+ [PORT5_MAC_ARES] = { 0x28A08, 7 },
+ [PORT6_MAC_ARES] = { 0x28A08, 6 },
+ [XGMAC0_PTP_REF_ARES] = { 0x28A08, 5 },
+ [XGMAC1_PTP_REF_ARES] = { 0x28A08, 4 },
+ [XGMAC2_PTP_REF_ARES] = { 0x28A08, 3 },
+ [XGMAC3_PTP_REF_ARES] = { 0x28A08, 2 },
+ [XGMAC4_PTP_REF_ARES] = { 0x28A08, 1 },
+ [XGMAC5_PTP_REF_ARES] = { 0x28A08, 0 },
+ [HAQ_AHB_ARES] = { 0x28A0C, 3 },
+ [HAQ_AXI_ARES] = { 0x28A0C, 2 },
+ [NSSNOC_HAQ_AHB_ARES] = { 0x28A0C, 1 },
+ [NSSNOC_HAQ_AXI_ARES] = { 0x28A0C, 0 },
+ [CE_APB_ARES] = { 0x28A10, 3 },
+ [CE_AXI_ARES] = { 0x28A10, 2 },
+ [NSSNOC_CE_APB_ARES] = { 0x28A10, 1 },
+ [NSSNOC_CE_AXI_ARES] = { 0x28A10, 0 },
+ [CRYPTO_ARES] = { 0x28A14, 1 },
+ [NSSNOC_CRYPTO_ARES] = { 0x28A14, 0 },
+ [NSSNOC_NC_AXI0_1_ARES] = { 0x28A1C, 28 },
+ [UBI0_CORE_ARES] = { 0x28A1C, 27 },
+ [UBI1_CORE_ARES] = { 0x28A1C, 26 },
+ [UBI2_CORE_ARES] = { 0x28A1C, 25 },
+ [UBI3_CORE_ARES] = { 0x28A1C, 24 },
+ [NC_AXI0_ARES] = { 0x28A1C, 23 },
+ [UTCM0_ARES] = { 0x28A1C, 22 },
+ [NC_AXI1_ARES] = { 0x28A1C, 21 },
+ [UTCM1_ARES] = { 0x28A1C, 20 },
+ [NC_AXI2_ARES] = { 0x28A1C, 19 },
+ [UTCM2_ARES] = { 0x28A1C, 18 },
+ [NC_AXI3_ARES] = { 0x28A1C, 17 },
+ [UTCM3_ARES] = { 0x28A1C, 16 },
+ [NSSNOC_NC_AXI0_ARES] = { 0x28A1C, 15 },
+ [AHB0_ARES] = { 0x28A1C, 14 },
+ [INTR0_AHB_ARES] = { 0x28A1C, 13 },
+ [AHB1_ARES] = { 0x28A1C, 12 },
+ [INTR1_AHB_ARES] = { 0x28A1C, 11 },
+ [AHB2_ARES] = { 0x28A1C, 10 },
+ [INTR2_AHB_ARES] = { 0x28A1C, 9 },
+ [AHB3_ARES] = { 0x28A1C, 8 },
+ [INTR3_AHB_ARES] = { 0x28A1C, 7 },
+ [NSSNOC_AHB0_ARES] = { 0x28A1C, 6 },
+ [NSSNOC_INT0_AHB_ARES] = { 0x28A1C, 5 },
+ [AXI0_ARES] = { 0x28A1C, 4 },
+ [AXI1_ARES] = { 0x28A1C, 3 },
+ [AXI2_ARES] = { 0x28A1C, 2 },
+ [AXI3_ARES] = { 0x28A1C, 1 },
+ [NSSNOC_AXI0_ARES] = { 0x28A1C, 0 },
+ [IMEM_QSB_ARES] = { 0x28A20, 3 },
+ [NSSNOC_IMEM_QSB_ARES] = { 0x28A20, 2 },
+ [IMEM_AHB_ARES] = { 0x28A20, 1 },
+ [NSSNOC_IMEM_AHB_ARES] = { 0x28A20, 0 },
+ [UNIPHY_PORT1_RX_ARES] = { 0x28A24, 23 },
+ [UNIPHY_PORT1_TX_ARES] = { 0x28A24, 22 },
+ [UNIPHY_PORT2_RX_ARES] = { 0x28A24, 21 },
+ [UNIPHY_PORT2_TX_ARES] = { 0x28A24, 20 },
+ [UNIPHY_PORT3_RX_ARES] = { 0x28A24, 19 },
+ [UNIPHY_PORT3_TX_ARES] = { 0x28A24, 18 },
+ [UNIPHY_PORT4_RX_ARES] = { 0x28A24, 17 },
+ [UNIPHY_PORT4_TX_ARES] = { 0x28A24, 16 },
+ [UNIPHY_PORT5_RX_ARES] = { 0x28A24, 15 },
+ [UNIPHY_PORT5_TX_ARES] = { 0x28A24, 14 },
+ [UNIPHY_PORT6_RX_ARES] = { 0x28A24, 13 },
+ [UNIPHY_PORT6_TX_ARES] = { 0x28A24, 12 },
+ [PORT1_RX_ARES] = { 0x28A24, 11 },
+ [PORT1_TX_ARES] = { 0x28A24, 10 },
+ [PORT2_RX_ARES] = { 0x28A24, 9 },
+ [PORT2_TX_ARES] = { 0x28A24, 8 },
+ [PORT3_RX_ARES] = { 0x28A24, 7 },
+ [PORT3_TX_ARES] = { 0x28A24, 6 },
+ [PORT4_RX_ARES] = { 0x28A24, 5 },
+ [PORT4_TX_ARES] = { 0x28A24, 4 },
+ [PORT5_RX_ARES] = { 0x28A24, 3 },
+ [PORT5_TX_ARES] = { 0x28A24, 2 },
+ [PORT6_RX_ARES] = { 0x28A24, 1 },
+ [PORT6_TX_ARES] = { 0x28A24, 0 },
+ [PPE_FULL_RESET] = { 0x28A08, 0, 1, 0x1E0000 },
+ [UNIPHY0_SOFT_RESET] = {0x28A24, 0, 1, 0xFFC000 },
+ [UNIPHY1_SOFT_RESET] = {0x28A24, 0, 1, 0xC000 },
+ [UNIPHY2_SOFT_RESET] = {0x28A24, 0, 1, 0x3000 },
+ [UNIPHY_PORT1_ARES] = {0x28A24, 0, 1, 0xC00000 },
+ [UNIPHY_PORT2_ARES] = {0x28A24, 0, 1, 0x300000 },
+ [UNIPHY_PORT3_ARES] = {0x28A24, 0, 1, 0xC0000 },
+ [UNIPHY_PORT4_ARES] = {0x28A24, 0, 1, 0x30000 },
+ [UNIPHY_PORT5_ARES] = {0x28A24, 0, 1, 0xC000 },
+ [UNIPHY_PORT6_ARES] = {0x28A24, 0, 1, 0x3000 },
+ [NSSPORT1_RESET] = { 0x28A24, 0, 1, 0xC00 },
+ [NSSPORT2_RESET] = { 0x28A24, 0, 1, 0x300 },
+ [NSSPORT3_RESET] = { 0x28A24, 0, 1, 0xC0 },
+ [NSSPORT4_RESET] = { 0x28A24, 0, 1, 0x30 },
+ [NSSPORT5_RESET] = { 0x28A24, 0, 1, 0xC },
+ [NSSPORT6_RESET] = { 0x28A24, 0, 1, 0x3 },
+ [EDMA_HW_RESET] = { 0x28A08, 0, 1, 0x18000 },
+};
+
+static const struct regmap_config nss_cc_ipq9574_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x28a34,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc nss_cc_ipq9574_desc = {
+ .config = &nss_cc_ipq9574_regmap_config,
+ .clks = nss_cc_ipq9574_clocks,
+ .num_clks = ARRAY_SIZE(nss_cc_ipq9574_clocks),
+ .resets = nss_cc_ipq9574_resets,
+ .num_resets = ARRAY_SIZE(nss_cc_ipq9574_resets),
+};
+
+static const struct of_device_id nss_cc_ipq9574_match_table[] = {
+ { .compatible = "qcom,ipq9574-nsscc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
+
+static int nss_cc_ipq9574_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
+
+ int ret;
+
+ ret = devm_pm_runtime_enable(&pdev->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = devm_pm_clk_create(&pdev->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
+ return ret;
+ }
+
+ ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc clock\n");
+ return ret;
+ }
+
+ ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1 clock\n");
+ return ret;
+ }
+
+ ret = pm_runtime_get(&pdev->dev);
+ if (ret)
+ return ret;
+
+ regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
+
+ return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
+}
+
+static const struct dev_pm_ops nss_cc_pm_ops = {
+ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
+};
+
+static struct platform_driver nss_cc_ipq9574_driver = {
+ .probe = nss_cc_ipq9574_probe,
+ .driver = {
+ .name = "qcom,nsscc-ipq9574",
+ .of_match_table = nss_cc_ipq9574_match_table,
+ .pm = &nss_cc_pm_ops,
+ },
+};
+
+module_platform_driver(nss_cc_ipq9574_driver);
+
+MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
devices.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Added depends on ARM64 || COMPILE_TEST in Kconfig
- Added module_platform_driver
- Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc clocks as critical
& added pm_clk for nssnoc clocks
- Updated the uniphy clock names
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
3 files changed, 3117 insertions(+)
create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index bd9bfb11b328..3ecc11e2c8e3 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -203,6 +203,13 @@ config IPQ_GCC_9574
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq9574.
+config IPQ_NSSCC_9574
+ tristate "IPQ9574 NSS Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ depends on IPQ_GCC_9574
+ help
+ Support for NSS clock controller on ipq9574 devices.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 4790c8cca426..3f084928962e 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
+obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9574.c
new file mode 100644
index 000000000000..65bdb449ae5f
--- /dev/null
+++ b/drivers/clk/qcom/nsscc-ipq9574.c
@@ -0,0 +1,3109 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_runtime.h>
+
+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+/* Need to match the order of clocks in DT binding */
+enum {
+ DT_NSSNOC_NSSCC_CLK,
+ DT_NSSNOC_SNOC_CLK,
+ DT_NSSNOC_SNOC_1_CLK,
+ DT_BIAS_PLL_CC_CLK,
+ DT_BIAS_PLL_NSS_NOC_CLK,
+ DT_BIAS_PLL_UBI_NC_CLK,
+ DT_GCC_GPLL0_OUT_AUX,
+ DT_UNIPHY0_NSS_RX_CLK,
+ DT_UNIPHY0_NSS_TX_CLK,
+ DT_UNIPHY1_NSS_RX_CLK,
+ DT_UNIPHY1_NSS_TX_CLK,
+ DT_UNIPHY2_NSS_RX_CLK,
+ DT_UNIPHY2_NSS_TX_CLK,
+ DT_XO,
+};
+
+enum {
+ P_BIAS_PLL_CC_CLK,
+ P_BIAS_PLL_NSS_NOC_CLK,
+ P_BIAS_PLL_UBI_NC_CLK,
+ P_GCC_GPLL0_OUT_AUX,
+ P_UBI32_PLL_OUT_MAIN,
+ P_UNIPHY0_NSS_RX_CLK,
+ P_UNIPHY0_NSS_TX_CLK,
+ P_UNIPHY1_NSS_RX_CLK,
+ P_UNIPHY1_NSS_TX_CLK,
+ P_UNIPHY2_NSS_RX_CLK,
+ P_UNIPHY2_NSS_TX_CLK,
+ P_XO,
+};
+
+static const struct alpha_pll_config ubi32_pll_config = {
+ .l = 0x3e,
+ .alpha = 0x6666,
+ .config_ctl_val = 0x200d4aa8,
+ .config_ctl_hi_val = 0x3c,
+ .main_output_mask = BIT(0),
+ .aux_output_mask = BIT(1),
+ .pre_div_val = 0x0,
+ .pre_div_mask = BIT(12),
+ .post_div_val = 0x0,
+ .post_div_mask = GENMASK(9, 8),
+ .alpha_en_mask = BIT(24),
+ .test_ctl_val = 0x1c0000c0,
+ .test_ctl_hi_val = 0x4000,
+};
+
+static struct clk_alpha_pll ubi32_pll_main = {
+ .offset = 0x28000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "ubi32_pll_main",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_XO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv ubi32_pll = {
+ .offset = 0x28000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
+ .width = 2,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "ubi32_pll",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi32_pll_main.clkr.hw
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct parent_map nss_cc_parent_map_0[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_CC_CLK, 1 },
+ { P_UNIPHY0_NSS_RX_CLK, 2 },
+ { P_UNIPHY0_NSS_TX_CLK, 3 },
+ { P_UNIPHY1_NSS_RX_CLK, 4 },
+ { P_UNIPHY1_NSS_TX_CLK, 5 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_0[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_CC_CLK },
+ { .index = DT_UNIPHY0_NSS_RX_CLK },
+ { .index = DT_UNIPHY0_NSS_TX_CLK },
+ { .index = DT_UNIPHY1_NSS_RX_CLK },
+ { .index = DT_UNIPHY1_NSS_TX_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_1[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_UBI_NC_CLK, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_BIAS_PLL_CC_CLK, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_1[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_UBI_NC_CLK },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_BIAS_PLL_CC_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_2[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_2[] = {
+ { .index = DT_XO },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+};
+
+static const struct parent_map nss_cc_parent_map_3[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_CC_CLK, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_3[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_CC_CLK },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+};
+
+static const struct parent_map nss_cc_parent_map_4[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_CC_CLK, 1 },
+ { P_UNIPHY0_NSS_RX_CLK, 2 },
+ { P_UNIPHY0_NSS_TX_CLK, 3 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_4[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_CC_CLK },
+ { .index = DT_UNIPHY0_NSS_RX_CLK },
+ { .index = DT_UNIPHY0_NSS_TX_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_5[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_CC_CLK, 1 },
+ { P_UNIPHY2_NSS_RX_CLK, 2 },
+ { P_UNIPHY2_NSS_TX_CLK, 3 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_5[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_CC_CLK },
+ { .index = DT_UNIPHY2_NSS_RX_CLK },
+ { .index = DT_UNIPHY2_NSS_TX_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_6[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC_CLK, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_BIAS_PLL_CC_CLK, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_6[] = {
+ { .index = DT_XO },
+ { .index = DT_BIAS_PLL_NSS_NOC_CLK },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_BIAS_PLL_CC_CLK },
+};
+
+static const struct parent_map nss_cc_parent_map_7[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_BIAS_PLL_CC_CLK, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_7[] = {
+ { .index = DT_XO },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_BIAS_PLL_CC_CLK },
+};
+
+static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(353000000, P_BIAS_PLL_UBI_NC_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_ce_clk_src = {
+ .cmd_rcgr = 0x28404,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
+ F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_cfg_clk_src = {
+ .cmd_rcgr = 0x28104,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_3,
+ .freq_tbl = ftbl_nss_cc_cfg_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_cfg_clk_src",
+ .parent_data = nss_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_clc_clk_src[] = {
+ F(533333333, P_GCC_GPLL0_OUT_AUX, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_clc_clk_src = {
+ .cmd_rcgr = 0x28604,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_6,
+ .freq_tbl = ftbl_nss_cc_clc_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_clc_clk_src",
+ .parent_data = nss_cc_parent_data_6,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_6),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_crypto_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(300000000, P_BIAS_PLL_CC_CLK, 4, 0, 0),
+ F(600000000, P_BIAS_PLL_CC_CLK, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_crypto_clk_src = {
+ .cmd_rcgr = 0x16008,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_3,
+ .freq_tbl = ftbl_nss_cc_crypto_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_crypto_clk_src",
+ .parent_data = nss_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_haq_clk_src = {
+ .cmd_rcgr = 0x28304,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_haq_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_imem_clk_src = {
+ .cmd_rcgr = 0xe008,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_imem_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_int_cfg_clk_src[] = {
+ F(200000000, P_GCC_GPLL0_OUT_AUX, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_int_cfg_clk_src = {
+ .cmd_rcgr = 0x287b4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_3,
+ .freq_tbl = ftbl_nss_cc_int_cfg_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_int_cfg_clk_src",
+ .parent_data = nss_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
+ C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
+ C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
+ FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
+ C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
+ C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
+ FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_312p5[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port5_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port5_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port5_rx_clk_src_125),
+ FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
+ FM(312500000, ftbl_nss_cc_port5_rx_clk_src_312p5),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_312p5[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port5_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port5_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port5_tx_clk_src_125),
+ FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
+ FM(312500000, ftbl_nss_cc_port5_tx_clk_src_312p5),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_25[] = {
+ C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_125[] = {
+ C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port6_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port6_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port6_rx_clk_src_125),
+ FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
+ { }
+};
+
+static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_25[] = {
+ C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_125[] = {
+ C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port6_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port6_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port6_tx_clk_src_125),
+ FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
+ .cmd_rcgr = 0x28110,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
+ .cmd_rcgr = 0x2811c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
+ .cmd_rcgr = 0x28128,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
+ .cmd_rcgr = 0x28134,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port3_rx_clk_src = {
+ .cmd_rcgr = 0x28140,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_rx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port3_tx_clk_src = {
+ .cmd_rcgr = 0x2814c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_tx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port4_rx_clk_src = {
+ .cmd_rcgr = 0x28158,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_rx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port4_tx_clk_src = {
+ .cmd_rcgr = 0x28164,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_4,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_tx_clk_src",
+ .parent_data = nss_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port5_rx_clk_src = {
+ .cmd_rcgr = 0x28170,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_multi_tbl = ftbl_nss_cc_port5_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_rx_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port5_tx_clk_src = {
+ .cmd_rcgr = 0x2817c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_multi_tbl = ftbl_nss_cc_port5_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_tx_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port6_rx_clk_src = {
+ .cmd_rcgr = 0x28188,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_5,
+ .freq_multi_tbl = ftbl_nss_cc_port6_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_rx_clk_src",
+ .parent_data = nss_cc_parent_data_5,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_port6_tx_clk_src = {
+ .cmd_rcgr = 0x28194,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_5,
+ .freq_multi_tbl = ftbl_nss_cc_port6_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_tx_clk_src",
+ .parent_data = nss_cc_parent_data_5,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ppe_clk_src = {
+ .cmd_rcgr = 0x28204,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_ubi0_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(187200000, P_UBI32_PLL_OUT_MAIN, 8, 0, 0),
+ F(748800000, P_UBI32_PLL_OUT_MAIN, 2, 0, 0),
+ F(1497600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
+ F(1689600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_ubi0_clk_src = {
+ .cmd_rcgr = 0x28704,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi0_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi1_clk_src = {
+ .cmd_rcgr = 0x2870c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi1_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi2_clk_src = {
+ .cmd_rcgr = 0x28714,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi2_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi3_clk_src = {
+ .cmd_rcgr = 0x2871c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi3_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi_axi_clk_src = {
+ .cmd_rcgr = 0x28724,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_7,
+ .freq_tbl = ftbl_nss_cc_clc_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi_axi_clk_src",
+ .parent_data = nss_cc_parent_data_7,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_7),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ubi_nc_axi_bfdcd_clk_src = {
+ .cmd_rcgr = 0x2872c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi_nc_axi_bfdcd_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
+ .reg = 0x28118,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
+ .reg = 0x28124,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
+ .reg = 0x28130,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
+ .reg = 0x2813c,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = {
+ .reg = 0x28148,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = {
+ .reg = 0x28154,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port4_rx_div_clk_src = {
+ .reg = 0x28160,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port4_tx_div_clk_src = {
+ .reg = 0x2816c,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port5_rx_div_clk_src = {
+ .reg = 0x28178,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port5_tx_div_clk_src = {
+ .reg = 0x28184,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port6_rx_div_clk_src = {
+ .reg = 0x28190,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_rx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port6_tx_div_clk_src = {
+ .reg = 0x2819c,
+ .shift = 0,
+ .width = 9,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_tx_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_ubi0_div_clk_src = {
+ .reg = 0x287a4,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi0_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_ubi1_div_clk_src = {
+ .reg = 0x287a8,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi1_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_ubi2_div_clk_src = {
+ .reg = 0x287ac,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi2_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_ubi3_div_clk_src = {
+ .reg = 0x287b0,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi3_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
+ .reg = 0x28214,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
+ .reg = 0x28218,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = {
+ .reg = 0x2821c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac2_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac3_ptp_ref_div_clk_src = {
+ .reg = 0x28220,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac3_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac4_ptp_ref_div_clk_src = {
+ .reg = 0x28224,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac4_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac5_ptp_ref_div_clk_src = {
+ .reg = 0x28228,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac5_ptp_ref_div_clk_src",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch nss_cc_ce_apb_clk = {
+ .halt_reg = 0x2840c,
+ .clkr = {
+ .enable_reg = 0x2840c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_apb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ce_axi_clk = {
+ .halt_reg = 0x28410,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28410,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_clc_axi_clk = {
+ .halt_reg = 0x2860c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2860c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_clc_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_clc_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_crypto_clk = {
+ .halt_reg = 0x1601c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1601c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_crypto_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_crypto_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_crypto_ppe_clk = {
+ .halt_reg = 0x28240,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28240,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_crypto_ppe_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_haq_ahb_clk = {
+ .halt_reg = 0x2830c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2830c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_haq_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_haq_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_haq_axi_clk = {
+ .halt_reg = 0x28310,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28310,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_haq_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_haq_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_imem_ahb_clk = {
+ .halt_reg = 0xe018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_imem_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_imem_qsb_clk = {
+ .halt_reg = 0xe010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_imem_qsb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_imem_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nss_csr_clk = {
+ .halt_reg = 0x281d0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281d0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nss_csr_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
+ .halt_reg = 0x28414,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28414,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ce_apb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
+ .halt_reg = 0x28418,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28418,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ce_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_clc_axi_clk = {
+ .halt_reg = 0x28610,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28610,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_clc_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_clc_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_crypto_clk = {
+ .halt_reg = 0x16020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_crypto_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_crypto_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_haq_ahb_clk = {
+ .halt_reg = 0x28314,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28314,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_haq_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_haq_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_haq_axi_clk = {
+ .halt_reg = 0x28318,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28318,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_haq_axi_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_haq_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_imem_ahb_clk = {
+ .halt_reg = 0xe01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_imem_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_imem_qsb_clk = {
+ .halt_reg = 0xe014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_imem_qsb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_imem_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
+ .halt_reg = 0x281d4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281d4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_nss_csr_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
+ .halt_reg = 0x28248,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28248,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ppe_cfg_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ppe_clk = {
+ .halt_reg = 0x28244,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28244,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ppe_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_ahb0_clk = {
+ .halt_reg = 0x28788,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28788,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_ahb0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_axi0_clk = {
+ .halt_reg = 0x287a0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x287a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_axi0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_int0_ahb_clk = {
+ .halt_reg = 0x2878c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2878c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_int0_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_1_clk = {
+ .halt_reg = 0x287bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x287bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_nc_axi0_1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_clk = {
+ .halt_reg = 0x28764,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28764,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ubi32_nc_axi0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_mac_clk = {
+ .halt_reg = 0x2824c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2824c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_rx_clk = {
+ .halt_reg = 0x281a0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_tx_clk = {
+ .halt_reg = 0x281a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_mac_clk = {
+ .halt_reg = 0x28250,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28250,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_rx_clk = {
+ .halt_reg = 0x281a8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281a8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_tx_clk = {
+ .halt_reg = 0x281ac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port3_mac_clk = {
+ .halt_reg = 0x28254,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28254,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port3_rx_clk = {
+ .halt_reg = 0x281b0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281b0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port3_tx_clk = {
+ .halt_reg = 0x281b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port3_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port4_mac_clk = {
+ .halt_reg = 0x28258,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28258,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port4_rx_clk = {
+ .halt_reg = 0x281b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port4_tx_clk = {
+ .halt_reg = 0x281bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port4_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port5_mac_clk = {
+ .halt_reg = 0x2825c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2825c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port5_rx_clk = {
+ .halt_reg = 0x281c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port5_tx_clk = {
+ .halt_reg = 0x281c4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281c4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port5_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port6_mac_clk = {
+ .halt_reg = 0x28260,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28260,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_mac_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port6_rx_clk = {
+ .halt_reg = 0x281c8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281c8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port6_tx_clk = {
+ .halt_reg = 0x281cc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x281cc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port6_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
+ .halt_reg = 0x2823c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2823c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_edma_cfg_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_edma_clk = {
+ .halt_reg = 0x28238,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28238,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_edma_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_btq_clk = {
+ .halt_reg = 0x2827c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2827c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_btq_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
+ .halt_reg = 0x28234,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28234,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_cfg_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_clk = {
+ .halt_reg = 0x28230,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28230,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
+ .halt_reg = 0x2822c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2822c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_ipe_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_ahb0_clk = {
+ .halt_reg = 0x28768,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28768,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_ahb0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_ahb1_clk = {
+ .halt_reg = 0x28770,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28770,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_ahb1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_ahb2_clk = {
+ .halt_reg = 0x28778,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28778,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_ahb2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_ahb3_clk = {
+ .halt_reg = 0x28780,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28780,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_ahb3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_axi0_clk = {
+ .halt_reg = 0x28790,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28790,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_axi0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_axi1_clk = {
+ .halt_reg = 0x28794,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28794,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_axi1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_axi2_clk = {
+ .halt_reg = 0x28798,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28798,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_axi2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_axi3_clk = {
+ .halt_reg = 0x2879c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2879c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_axi3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_core0_clk = {
+ .halt_reg = 0x28734,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28734,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_core0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi0_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_core1_clk = {
+ .halt_reg = 0x28738,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28738,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_core1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi1_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_core2_clk = {
+ .halt_reg = 0x2873c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2873c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_core2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi2_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_core3_clk = {
+ .halt_reg = 0x28740,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28740,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_core3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi3_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_intr0_ahb_clk = {
+ .halt_reg = 0x2876c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2876c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_intr0_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_intr1_ahb_clk = {
+ .halt_reg = 0x28774,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28774,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_intr1_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_intr2_ahb_clk = {
+ .halt_reg = 0x2877c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2877c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_intr2_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_intr3_ahb_clk = {
+ .halt_reg = 0x28784,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28784,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_intr3_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_nc_axi0_clk = {
+ .halt_reg = 0x28744,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28744,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_nc_axi0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_nc_axi1_clk = {
+ .halt_reg = 0x2874c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2874c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_nc_axi1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_nc_axi2_clk = {
+ .halt_reg = 0x28754,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28754,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_nc_axi2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_nc_axi3_clk = {
+ .halt_reg = 0x2875c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2875c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_nc_axi3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_utcm0_clk = {
+ .halt_reg = 0x28748,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28748,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_utcm0_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_utcm1_clk = {
+ .halt_reg = 0x28750,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28750,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_utcm1_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_utcm2_clk = {
+ .halt_reg = 0x28758,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28758,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_utcm2_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ubi32_utcm3_clk = {
+ .halt_reg = 0x28760,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28760,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ubi32_utcm3_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
+ .halt_reg = 0x28904,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28904,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port1_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
+ .halt_reg = 0x28908,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28908,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port1_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
+ .halt_reg = 0x2890c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2890c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port2_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
+ .halt_reg = 0x28910,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28910,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port2_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port3_rx_clk = {
+ .halt_reg = 0x28914,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28914,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port3_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port3_tx_clk = {
+ .halt_reg = 0x28918,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28918,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port3_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port4_rx_clk = {
+ .halt_reg = 0x2891c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2891c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port4_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port4_tx_clk = {
+ .halt_reg = 0x28920,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28920,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port4_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port5_rx_clk = {
+ .halt_reg = 0x28924,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28924,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port5_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port5_tx_clk = {
+ .halt_reg = 0x28928,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28928,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port5_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port6_rx_clk = {
+ .halt_reg = 0x2892c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2892c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port6_rx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port6_tx_clk = {
+ .halt_reg = 0x28930,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28930,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port6_tx_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
+ .halt_reg = 0x28264,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28264,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac0_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
+ .halt_reg = 0x28268,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28268,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac1_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = {
+ .halt_reg = 0x2826c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2826c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac2_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac3_ptp_ref_clk = {
+ .halt_reg = 0x28270,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28270,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac3_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac4_ptp_ref_clk = {
+ .halt_reg = 0x28274,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28274,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac4_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac5_ptp_ref_clk = {
+ .halt_reg = 0x28278,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28278,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac5_ptp_ref_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *nss_cc_ipq9574_clocks[] = {
+ [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
+ [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
+ [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
+ [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
+ [NSS_CC_CLC_AXI_CLK] = &nss_cc_clc_axi_clk.clkr,
+ [NSS_CC_CLC_CLK_SRC] = &nss_cc_clc_clk_src.clkr,
+ [NSS_CC_CRYPTO_CLK] = &nss_cc_crypto_clk.clkr,
+ [NSS_CC_CRYPTO_CLK_SRC] = &nss_cc_crypto_clk_src.clkr,
+ [NSS_CC_CRYPTO_PPE_CLK] = &nss_cc_crypto_ppe_clk.clkr,
+ [NSS_CC_HAQ_AHB_CLK] = &nss_cc_haq_ahb_clk.clkr,
+ [NSS_CC_HAQ_AXI_CLK] = &nss_cc_haq_axi_clk.clkr,
+ [NSS_CC_HAQ_CLK_SRC] = &nss_cc_haq_clk_src.clkr,
+ [NSS_CC_IMEM_AHB_CLK] = &nss_cc_imem_ahb_clk.clkr,
+ [NSS_CC_IMEM_CLK_SRC] = &nss_cc_imem_clk_src.clkr,
+ [NSS_CC_IMEM_QSB_CLK] = &nss_cc_imem_qsb_clk.clkr,
+ [NSS_CC_INT_CFG_CLK_SRC] = &nss_cc_int_cfg_clk_src.clkr,
+ [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
+ [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
+ [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
+ [NSS_CC_NSSNOC_CLC_AXI_CLK] = &nss_cc_nssnoc_clc_axi_clk.clkr,
+ [NSS_CC_NSSNOC_CRYPTO_CLK] = &nss_cc_nssnoc_crypto_clk.clkr,
+ [NSS_CC_NSSNOC_HAQ_AHB_CLK] = &nss_cc_nssnoc_haq_ahb_clk.clkr,
+ [NSS_CC_NSSNOC_HAQ_AXI_CLK] = &nss_cc_nssnoc_haq_axi_clk.clkr,
+ [NSS_CC_NSSNOC_IMEM_AHB_CLK] = &nss_cc_nssnoc_imem_ahb_clk.clkr,
+ [NSS_CC_NSSNOC_IMEM_QSB_CLK] = &nss_cc_nssnoc_imem_qsb_clk.clkr,
+ [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
+ [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
+ [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_AHB0_CLK] = &nss_cc_nssnoc_ubi32_ahb0_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_AXI0_CLK] = &nss_cc_nssnoc_ubi32_axi0_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK] =
+ &nss_cc_nssnoc_ubi32_int0_ahb_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK] =
+ &nss_cc_nssnoc_ubi32_nc_axi0_1_clk.clkr,
+ [NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK] =
+ &nss_cc_nssnoc_ubi32_nc_axi0_clk.clkr,
+ [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
+ [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
+ [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
+ [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
+ [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
+ [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
+ [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
+ [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
+ [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
+ [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
+ [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
+ [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
+ [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
+ [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
+ [NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr,
+ [NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr,
+ [NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr,
+ [NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr,
+ [NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr,
+ [NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr,
+ [NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr,
+ [NSS_CC_PORT4_MAC_CLK] = &nss_cc_port4_mac_clk.clkr,
+ [NSS_CC_PORT4_RX_CLK] = &nss_cc_port4_rx_clk.clkr,
+ [NSS_CC_PORT4_RX_CLK_SRC] = &nss_cc_port4_rx_clk_src.clkr,
+ [NSS_CC_PORT4_RX_DIV_CLK_SRC] = &nss_cc_port4_rx_div_clk_src.clkr,
+ [NSS_CC_PORT4_TX_CLK] = &nss_cc_port4_tx_clk.clkr,
+ [NSS_CC_PORT4_TX_CLK_SRC] = &nss_cc_port4_tx_clk_src.clkr,
+ [NSS_CC_PORT4_TX_DIV_CLK_SRC] = &nss_cc_port4_tx_div_clk_src.clkr,
+ [NSS_CC_PORT5_MAC_CLK] = &nss_cc_port5_mac_clk.clkr,
+ [NSS_CC_PORT5_RX_CLK] = &nss_cc_port5_rx_clk.clkr,
+ [NSS_CC_PORT5_RX_CLK_SRC] = &nss_cc_port5_rx_clk_src.clkr,
+ [NSS_CC_PORT5_RX_DIV_CLK_SRC] = &nss_cc_port5_rx_div_clk_src.clkr,
+ [NSS_CC_PORT5_TX_CLK] = &nss_cc_port5_tx_clk.clkr,
+ [NSS_CC_PORT5_TX_CLK_SRC] = &nss_cc_port5_tx_clk_src.clkr,
+ [NSS_CC_PORT5_TX_DIV_CLK_SRC] = &nss_cc_port5_tx_div_clk_src.clkr,
+ [NSS_CC_PORT6_MAC_CLK] = &nss_cc_port6_mac_clk.clkr,
+ [NSS_CC_PORT6_RX_CLK] = &nss_cc_port6_rx_clk.clkr,
+ [NSS_CC_PORT6_RX_CLK_SRC] = &nss_cc_port6_rx_clk_src.clkr,
+ [NSS_CC_PORT6_RX_DIV_CLK_SRC] = &nss_cc_port6_rx_div_clk_src.clkr,
+ [NSS_CC_PORT6_TX_CLK] = &nss_cc_port6_tx_clk.clkr,
+ [NSS_CC_PORT6_TX_CLK_SRC] = &nss_cc_port6_tx_clk_src.clkr,
+ [NSS_CC_PORT6_TX_DIV_CLK_SRC] = &nss_cc_port6_tx_div_clk_src.clkr,
+ [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
+ [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
+ [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
+ [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
+ [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
+ [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
+ [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
+ [NSS_CC_UBI0_CLK_SRC] = &nss_cc_ubi0_clk_src.clkr,
+ [NSS_CC_UBI0_DIV_CLK_SRC] = &nss_cc_ubi0_div_clk_src.clkr,
+ [NSS_CC_UBI1_CLK_SRC] = &nss_cc_ubi1_clk_src.clkr,
+ [NSS_CC_UBI1_DIV_CLK_SRC] = &nss_cc_ubi1_div_clk_src.clkr,
+ [NSS_CC_UBI2_CLK_SRC] = &nss_cc_ubi2_clk_src.clkr,
+ [NSS_CC_UBI2_DIV_CLK_SRC] = &nss_cc_ubi2_div_clk_src.clkr,
+ [NSS_CC_UBI32_AHB0_CLK] = &nss_cc_ubi32_ahb0_clk.clkr,
+ [NSS_CC_UBI32_AHB1_CLK] = &nss_cc_ubi32_ahb1_clk.clkr,
+ [NSS_CC_UBI32_AHB2_CLK] = &nss_cc_ubi32_ahb2_clk.clkr,
+ [NSS_CC_UBI32_AHB3_CLK] = &nss_cc_ubi32_ahb3_clk.clkr,
+ [NSS_CC_UBI32_AXI0_CLK] = &nss_cc_ubi32_axi0_clk.clkr,
+ [NSS_CC_UBI32_AXI1_CLK] = &nss_cc_ubi32_axi1_clk.clkr,
+ [NSS_CC_UBI32_AXI2_CLK] = &nss_cc_ubi32_axi2_clk.clkr,
+ [NSS_CC_UBI32_AXI3_CLK] = &nss_cc_ubi32_axi3_clk.clkr,
+ [NSS_CC_UBI32_CORE0_CLK] = &nss_cc_ubi32_core0_clk.clkr,
+ [NSS_CC_UBI32_CORE1_CLK] = &nss_cc_ubi32_core1_clk.clkr,
+ [NSS_CC_UBI32_CORE2_CLK] = &nss_cc_ubi32_core2_clk.clkr,
+ [NSS_CC_UBI32_CORE3_CLK] = &nss_cc_ubi32_core3_clk.clkr,
+ [NSS_CC_UBI32_INTR0_AHB_CLK] = &nss_cc_ubi32_intr0_ahb_clk.clkr,
+ [NSS_CC_UBI32_INTR1_AHB_CLK] = &nss_cc_ubi32_intr1_ahb_clk.clkr,
+ [NSS_CC_UBI32_INTR2_AHB_CLK] = &nss_cc_ubi32_intr2_ahb_clk.clkr,
+ [NSS_CC_UBI32_INTR3_AHB_CLK] = &nss_cc_ubi32_intr3_ahb_clk.clkr,
+ [NSS_CC_UBI32_NC_AXI0_CLK] = &nss_cc_ubi32_nc_axi0_clk.clkr,
+ [NSS_CC_UBI32_NC_AXI1_CLK] = &nss_cc_ubi32_nc_axi1_clk.clkr,
+ [NSS_CC_UBI32_NC_AXI2_CLK] = &nss_cc_ubi32_nc_axi2_clk.clkr,
+ [NSS_CC_UBI32_NC_AXI3_CLK] = &nss_cc_ubi32_nc_axi3_clk.clkr,
+ [NSS_CC_UBI32_UTCM0_CLK] = &nss_cc_ubi32_utcm0_clk.clkr,
+ [NSS_CC_UBI32_UTCM1_CLK] = &nss_cc_ubi32_utcm1_clk.clkr,
+ [NSS_CC_UBI32_UTCM2_CLK] = &nss_cc_ubi32_utcm2_clk.clkr,
+ [NSS_CC_UBI32_UTCM3_CLK] = &nss_cc_ubi32_utcm3_clk.clkr,
+ [NSS_CC_UBI3_CLK_SRC] = &nss_cc_ubi3_clk_src.clkr,
+ [NSS_CC_UBI3_DIV_CLK_SRC] = &nss_cc_ubi3_div_clk_src.clkr,
+ [NSS_CC_UBI_AXI_CLK_SRC] = &nss_cc_ubi_axi_clk_src.clkr,
+ [NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC] =
+ &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr,
+ [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT4_RX_CLK] = &nss_cc_uniphy_port4_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT4_TX_CLK] = &nss_cc_uniphy_port4_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT5_RX_CLK] = &nss_cc_uniphy_port5_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT5_TX_CLK] = &nss_cc_uniphy_port5_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT6_RX_CLK] = &nss_cc_uniphy_port6_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT6_TX_CLK] = &nss_cc_uniphy_port6_tx_clk.clkr,
+ [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC3_PTP_REF_CLK] = &nss_cc_xgmac3_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC4_PTP_REF_CLK] = &nss_cc_xgmac4_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC5_PTP_REF_CLK] = &nss_cc_xgmac5_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC] =
+ &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr,
+ [UBI32_PLL] = &ubi32_pll.clkr,
+ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
+};
+
+static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
+ [NSS_CC_CE_BCR] = { 0x28400, 0 },
+ [NSS_CC_CLC_BCR] = { 0x28600, 0 },
+ [NSS_CC_EIP197_BCR] = { 0x16004, 0 },
+ [NSS_CC_HAQ_BCR] = { 0x28300, 0 },
+ [NSS_CC_IMEM_BCR] = { 0xe004, 0 },
+ [NSS_CC_MAC_BCR] = { 0x28100, 0 },
+ [NSS_CC_PPE_BCR] = { 0x28200, 0 },
+ [NSS_CC_UBI_BCR] = { 0x28700, 0 },
+ [NSS_CC_UNIPHY_BCR] = { 0x28900, 0 },
+ [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
+ [UBI3_CORE_CLAMP_ENABLE] = { 0x28A04, 8 },
+ [UBI2_CLKRST_CLAMP_ENABLE] = { 0x28A04, 7 },
+ [UBI2_CORE_CLAMP_ENABLE] = { 0x28A04, 6 },
+ [UBI1_CLKRST_CLAMP_ENABLE] = { 0x28A04, 5 },
+ [UBI1_CORE_CLAMP_ENABLE] = { 0x28A04, 4 },
+ [UBI0_CLKRST_CLAMP_ENABLE] = { 0x28A04, 3 },
+ [UBI0_CORE_CLAMP_ENABLE] = { 0x28A04, 2 },
+ [NSSNOC_NSS_CSR_ARES] = { 0x28A04, 1 },
+ [NSS_CSR_ARES] = { 0x28A04, 0 },
+ [PPE_BTQ_ARES] = { 0x28A08, 20 },
+ [PPE_IPE_ARES] = { 0x28A08, 19 },
+ [PPE_ARES] = { 0x28A08, 18 },
+ [PPE_CFG_ARES] = { 0x28A08, 17 },
+ [PPE_EDMA_ARES] = { 0x28A08, 16 },
+ [PPE_EDMA_CFG_ARES] = { 0x28A08, 15 },
+ [CRY_PPE_ARES] = { 0x28A08, 14 },
+ [NSSNOC_PPE_ARES] = { 0x28A08, 13 },
+ [NSSNOC_PPE_CFG_ARES] = { 0x28A08, 12 },
+ [PORT1_MAC_ARES] = { 0x28A08, 11 },
+ [PORT2_MAC_ARES] = { 0x28A08, 10 },
+ [PORT3_MAC_ARES] = { 0x28A08, 9 },
+ [PORT4_MAC_ARES] = { 0x28A08, 8 },
+ [PORT5_MAC_ARES] = { 0x28A08, 7 },
+ [PORT6_MAC_ARES] = { 0x28A08, 6 },
+ [XGMAC0_PTP_REF_ARES] = { 0x28A08, 5 },
+ [XGMAC1_PTP_REF_ARES] = { 0x28A08, 4 },
+ [XGMAC2_PTP_REF_ARES] = { 0x28A08, 3 },
+ [XGMAC3_PTP_REF_ARES] = { 0x28A08, 2 },
+ [XGMAC4_PTP_REF_ARES] = { 0x28A08, 1 },
+ [XGMAC5_PTP_REF_ARES] = { 0x28A08, 0 },
+ [HAQ_AHB_ARES] = { 0x28A0C, 3 },
+ [HAQ_AXI_ARES] = { 0x28A0C, 2 },
+ [NSSNOC_HAQ_AHB_ARES] = { 0x28A0C, 1 },
+ [NSSNOC_HAQ_AXI_ARES] = { 0x28A0C, 0 },
+ [CE_APB_ARES] = { 0x28A10, 3 },
+ [CE_AXI_ARES] = { 0x28A10, 2 },
+ [NSSNOC_CE_APB_ARES] = { 0x28A10, 1 },
+ [NSSNOC_CE_AXI_ARES] = { 0x28A10, 0 },
+ [CRYPTO_ARES] = { 0x28A14, 1 },
+ [NSSNOC_CRYPTO_ARES] = { 0x28A14, 0 },
+ [NSSNOC_NC_AXI0_1_ARES] = { 0x28A1C, 28 },
+ [UBI0_CORE_ARES] = { 0x28A1C, 27 },
+ [UBI1_CORE_ARES] = { 0x28A1C, 26 },
+ [UBI2_CORE_ARES] = { 0x28A1C, 25 },
+ [UBI3_CORE_ARES] = { 0x28A1C, 24 },
+ [NC_AXI0_ARES] = { 0x28A1C, 23 },
+ [UTCM0_ARES] = { 0x28A1C, 22 },
+ [NC_AXI1_ARES] = { 0x28A1C, 21 },
+ [UTCM1_ARES] = { 0x28A1C, 20 },
+ [NC_AXI2_ARES] = { 0x28A1C, 19 },
+ [UTCM2_ARES] = { 0x28A1C, 18 },
+ [NC_AXI3_ARES] = { 0x28A1C, 17 },
+ [UTCM3_ARES] = { 0x28A1C, 16 },
+ [NSSNOC_NC_AXI0_ARES] = { 0x28A1C, 15 },
+ [AHB0_ARES] = { 0x28A1C, 14 },
+ [INTR0_AHB_ARES] = { 0x28A1C, 13 },
+ [AHB1_ARES] = { 0x28A1C, 12 },
+ [INTR1_AHB_ARES] = { 0x28A1C, 11 },
+ [AHB2_ARES] = { 0x28A1C, 10 },
+ [INTR2_AHB_ARES] = { 0x28A1C, 9 },
+ [AHB3_ARES] = { 0x28A1C, 8 },
+ [INTR3_AHB_ARES] = { 0x28A1C, 7 },
+ [NSSNOC_AHB0_ARES] = { 0x28A1C, 6 },
+ [NSSNOC_INT0_AHB_ARES] = { 0x28A1C, 5 },
+ [AXI0_ARES] = { 0x28A1C, 4 },
+ [AXI1_ARES] = { 0x28A1C, 3 },
+ [AXI2_ARES] = { 0x28A1C, 2 },
+ [AXI3_ARES] = { 0x28A1C, 1 },
+ [NSSNOC_AXI0_ARES] = { 0x28A1C, 0 },
+ [IMEM_QSB_ARES] = { 0x28A20, 3 },
+ [NSSNOC_IMEM_QSB_ARES] = { 0x28A20, 2 },
+ [IMEM_AHB_ARES] = { 0x28A20, 1 },
+ [NSSNOC_IMEM_AHB_ARES] = { 0x28A20, 0 },
+ [UNIPHY_PORT1_RX_ARES] = { 0x28A24, 23 },
+ [UNIPHY_PORT1_TX_ARES] = { 0x28A24, 22 },
+ [UNIPHY_PORT2_RX_ARES] = { 0x28A24, 21 },
+ [UNIPHY_PORT2_TX_ARES] = { 0x28A24, 20 },
+ [UNIPHY_PORT3_RX_ARES] = { 0x28A24, 19 },
+ [UNIPHY_PORT3_TX_ARES] = { 0x28A24, 18 },
+ [UNIPHY_PORT4_RX_ARES] = { 0x28A24, 17 },
+ [UNIPHY_PORT4_TX_ARES] = { 0x28A24, 16 },
+ [UNIPHY_PORT5_RX_ARES] = { 0x28A24, 15 },
+ [UNIPHY_PORT5_TX_ARES] = { 0x28A24, 14 },
+ [UNIPHY_PORT6_RX_ARES] = { 0x28A24, 13 },
+ [UNIPHY_PORT6_TX_ARES] = { 0x28A24, 12 },
+ [PORT1_RX_ARES] = { 0x28A24, 11 },
+ [PORT1_TX_ARES] = { 0x28A24, 10 },
+ [PORT2_RX_ARES] = { 0x28A24, 9 },
+ [PORT2_TX_ARES] = { 0x28A24, 8 },
+ [PORT3_RX_ARES] = { 0x28A24, 7 },
+ [PORT3_TX_ARES] = { 0x28A24, 6 },
+ [PORT4_RX_ARES] = { 0x28A24, 5 },
+ [PORT4_TX_ARES] = { 0x28A24, 4 },
+ [PORT5_RX_ARES] = { 0x28A24, 3 },
+ [PORT5_TX_ARES] = { 0x28A24, 2 },
+ [PORT6_RX_ARES] = { 0x28A24, 1 },
+ [PORT6_TX_ARES] = { 0x28A24, 0 },
+ [PPE_FULL_RESET] = { 0x28A08, 0, 1, 0x1E0000 },
+ [UNIPHY0_SOFT_RESET] = {0x28A24, 0, 1, 0xFFC000 },
+ [UNIPHY1_SOFT_RESET] = {0x28A24, 0, 1, 0xC000 },
+ [UNIPHY2_SOFT_RESET] = {0x28A24, 0, 1, 0x3000 },
+ [UNIPHY_PORT1_ARES] = {0x28A24, 0, 1, 0xC00000 },
+ [UNIPHY_PORT2_ARES] = {0x28A24, 0, 1, 0x300000 },
+ [UNIPHY_PORT3_ARES] = {0x28A24, 0, 1, 0xC0000 },
+ [UNIPHY_PORT4_ARES] = {0x28A24, 0, 1, 0x30000 },
+ [UNIPHY_PORT5_ARES] = {0x28A24, 0, 1, 0xC000 },
+ [UNIPHY_PORT6_ARES] = {0x28A24, 0, 1, 0x3000 },
+ [NSSPORT1_RESET] = { 0x28A24, 0, 1, 0xC00 },
+ [NSSPORT2_RESET] = { 0x28A24, 0, 1, 0x300 },
+ [NSSPORT3_RESET] = { 0x28A24, 0, 1, 0xC0 },
+ [NSSPORT4_RESET] = { 0x28A24, 0, 1, 0x30 },
+ [NSSPORT5_RESET] = { 0x28A24, 0, 1, 0xC },
+ [NSSPORT6_RESET] = { 0x28A24, 0, 1, 0x3 },
+ [EDMA_HW_RESET] = { 0x28A08, 0, 1, 0x18000 },
+};
+
+static const struct regmap_config nss_cc_ipq9574_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x28a34,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc nss_cc_ipq9574_desc = {
+ .config = &nss_cc_ipq9574_regmap_config,
+ .clks = nss_cc_ipq9574_clocks,
+ .num_clks = ARRAY_SIZE(nss_cc_ipq9574_clocks),
+ .resets = nss_cc_ipq9574_resets,
+ .num_resets = ARRAY_SIZE(nss_cc_ipq9574_resets),
+};
+
+static const struct of_device_id nss_cc_ipq9574_match_table[] = {
+ { .compatible = "qcom,ipq9574-nsscc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
+
+static int nss_cc_ipq9574_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
+
+ int ret;
+
+ ret = devm_pm_runtime_enable(&pdev->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = devm_pm_clk_create(&pdev->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
+ return ret;
+ }
+
+ ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc clock\n");
+ return ret;
+ }
+
+ ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1 clock\n");
+ return ret;
+ }
+
+ ret = pm_runtime_get(&pdev->dev);
+ if (ret)
+ return ret;
+
+ regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
+
+ return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
+}
+
+static const struct dev_pm_ops nss_cc_pm_ops = {
+ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
+};
+
+static struct platform_driver nss_cc_ipq9574_driver = {
+ .probe = nss_cc_ipq9574_probe,
+ .driver = {
+ .name = "qcom,nsscc-ipq9574",
+ .of_match_table = nss_cc_ipq9574_match_table,
+ .pm = &nss_cc_pm_ops,
+ },
+};
+
+module_platform_driver(nss_cc_ipq9574_driver);
+
+MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 9:12 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add a node for the nss clock controller found on ipq9574 based devices.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Dropped the fixed clock node gcc_gpll0_out_aux and added
support for the same in gcc driver
- Updated the node name to clock-controller@39b00000
- Added clock-names to retrieve the nssnoc clocks and add them
to the list of pm clocks in nss driver
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 51aba071c1eb..903311547e96 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -10,6 +10,8 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -18,6 +20,24 @@ / {
#size-cells = <2>;
clocks {
+ bias_pll_cc_clk: bias-pll-cc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1200000000>;
+ #clock-cells = <0>;
+ };
+
+ bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <461500000>;
+ #clock-cells = <0>;
+ };
+
+ bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <353000000>;
+ #clock-cells = <0>;
+ };
+
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -722,6 +742,34 @@ frame@b128000 {
status = "disabled";
};
};
+
+ nsscc: clock-controller@39b00000 {
+ compatible = "qcom,ipq9574-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_1_CLK>,
+ <&bias_pll_cc_clk>,
+ <&bias_pll_nss_noc_clk>,
+ <&bias_pll_ubi_nc_clk>,
+ <&gcc GPLL0_OUT_AUX>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&xo_board_clk>;
+ clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
+ "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
+ "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
+ "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
+ "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
+ "uniphy2_nss_tx_clk", "xo_board_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
};
thermal-zones {
--
2.34.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Add a node for the nss clock controller found on ipq9574 based devices.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Dropped the fixed clock node gcc_gpll0_out_aux and added
support for the same in gcc driver
- Updated the node name to clock-controller@39b00000
- Added clock-names to retrieve the nssnoc clocks and add them
to the list of pm clocks in nss driver
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 51aba071c1eb..903311547e96 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -10,6 +10,8 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -18,6 +20,24 @@ / {
#size-cells = <2>;
clocks {
+ bias_pll_cc_clk: bias-pll-cc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1200000000>;
+ #clock-cells = <0>;
+ };
+
+ bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <461500000>;
+ #clock-cells = <0>;
+ };
+
+ bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <353000000>;
+ #clock-cells = <0>;
+ };
+
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -722,6 +742,34 @@ frame@b128000 {
status = "disabled";
};
};
+
+ nsscc: clock-controller@39b00000 {
+ compatible = "qcom,ipq9574-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_1_CLK>,
+ <&bias_pll_cc_clk>,
+ <&bias_pll_nss_noc_clk>,
+ <&bias_pll_ubi_nc_clk>,
+ <&gcc GPLL0_OUT_AUX>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&xo_board_clk>;
+ clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
+ "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
+ "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
+ "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
+ "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
+ "uniphy2_nss_tx_clk", "xo_board_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
};
thermal-zones {
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 7/7] arm64: defconfig: Build NSS Clock Controller driver for IPQ9574
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 9:12 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Build Qualcomm IPQ9574 NSSCC driver.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Build IPQ9574 NSSCC driver as a module
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5315789f4868..a6406eef43c8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1211,6 +1211,7 @@ CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_6018=y
CONFIG_IPQ_GCC_8074=y
CONFIG_IPQ_GCC_9574=y
+CONFIG_IPQ_NSSCC_9574=m
CONFIG_MSM_GCC_8916=y
CONFIG_MSM_GCC_8994=y
CONFIG_MSM_GCC_8996=y
--
2.34.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH V2 7/7] arm64: defconfig: Build NSS Clock Controller driver for IPQ9574
@ 2023-08-25 9:12 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-25 9:12 UTC (permalink / raw)
To: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_devipriy, quic_saahtoma
Build Qualcomm IPQ9574 NSSCC driver.
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Build IPQ9574 NSSCC driver as a module
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5315789f4868..a6406eef43c8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1211,6 +1211,7 @@ CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_6018=y
CONFIG_IPQ_GCC_8074=y
CONFIG_IPQ_GCC_9574=y
+CONFIG_IPQ_NSSCC_9574=m
CONFIG_MSM_GCC_8916=y
CONFIG_MSM_GCC_8994=y
CONFIG_MSM_GCC_8996=y
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* Re: [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 10:14 ` Rob Herring
-1 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2023-08-25 10:14 UTC (permalink / raw)
To: Devi Priya
Cc: rafal, agross, linux-kernel, mturquette, richardcochran, p.zabel,
catalin.marinas, will, conor+dt, nfraprado, quic_saahtoma, sboyd,
konrad.dybcio, linux-arm-msm, krzysztof.kozlowski+dt, devicetree,
robh+dt, linux-clk, arnd, andersson, linux-arm-kernel, peng.fan,
netdev, geert+renesas
On Fri, 25 Aug 2023 14:42:31 +0530, Devi Priya wrote:
> Add NSSCC clock and reset definitions for ipq9574.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V2:
> - Referenced gcc.yaml and dropped the duplicate properties from
> the binding
> - Updated Uniphy clock names
> - Added nssnoc clocks and clock-names
>
> .../bindings/clock/qcom,ipq9574-nsscc.yaml | 107 ++++++++++++
> .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++
> .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++
> 3 files changed, 393 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
> create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.example.dts:28.26-27 syntax error
FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500: dt_binding_check] Error 2
make: *** [Makefile:234: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230825091234.32713-5-quic_devipriy@quicinc.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
@ 2023-08-25 10:14 ` Rob Herring
0 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2023-08-25 10:14 UTC (permalink / raw)
To: Devi Priya
Cc: rafal, agross, linux-kernel, mturquette, richardcochran, p.zabel,
catalin.marinas, will, conor+dt, nfraprado, quic_saahtoma, sboyd,
konrad.dybcio, linux-arm-msm, krzysztof.kozlowski+dt, devicetree,
robh+dt, linux-clk, arnd, andersson, linux-arm-kernel, peng.fan,
netdev, geert+renesas
On Fri, 25 Aug 2023 14:42:31 +0530, Devi Priya wrote:
> Add NSSCC clock and reset definitions for ipq9574.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V2:
> - Referenced gcc.yaml and dropped the duplicate properties from
> the binding
> - Updated Uniphy clock names
> - Added nssnoc clocks and clock-names
>
> .../bindings/clock/qcom,ipq9574-nsscc.yaml | 107 ++++++++++++
> .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++
> .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++
> 3 files changed, 393 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
> create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.example.dts:28.26-27 syntax error
FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500: dt_binding_check] Error 2
make: *** [Makefile:234: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230825091234.32713-5-quic_devipriy@quicinc.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 11:28 ` Dmitry Baryshkov
-1 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-08-25 11:28 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
> Add a node for the nss clock controller found on ipq9574 based devices.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V2:
> - Dropped the fixed clock node gcc_gpll0_out_aux and added
> support for the same in gcc driver
> - Updated the node name to clock-controller@39b00000
> - Added clock-names to retrieve the nssnoc clocks and add them
> to the list of pm clocks in nss driver
>
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 51aba071c1eb..903311547e96 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -10,6 +10,8 @@
> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> #include <dt-bindings/thermal/thermal.h>
>
> / {
> @@ -18,6 +20,24 @@ / {
> #size-cells = <2>;
>
> clocks {
> + bias_pll_cc_clk: bias-pll-cc-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <1200000000>;
> + #clock-cells = <0>;
> + };
> +
> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <461500000>;
> + #clock-cells = <0>;
> + };
> +
> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <353000000>;
> + #clock-cells = <0>;
> + };
Which part provides these clocks?
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -722,6 +742,34 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + nsscc: clock-controller@39b00000 {
> + compatible = "qcom,ipq9574-nsscc";
> + reg = <0x39b00000 0x80000>;
> + clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
> + <&gcc GCC_NSSNOC_SNOC_CLK>,
> + <&gcc GCC_NSSNOC_SNOC_1_CLK>,
> + <&bias_pll_cc_clk>,
> + <&bias_pll_nss_noc_clk>,
> + <&bias_pll_ubi_nc_clk>,
> + <&gcc GPLL0_OUT_AUX>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <&xo_board_clk>;
If you move xo_board closer to the start of the list, it will be
slightly easier to review.
> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
> + "uniphy2_nss_tx_clk", "xo_board_clk";
You are using clock indices. Please drop clock-names.
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> };
>
> thermal-zones {
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
@ 2023-08-25 11:28 ` Dmitry Baryshkov
0 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-08-25 11:28 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
> Add a node for the nss clock controller found on ipq9574 based devices.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V2:
> - Dropped the fixed clock node gcc_gpll0_out_aux and added
> support for the same in gcc driver
> - Updated the node name to clock-controller@39b00000
> - Added clock-names to retrieve the nssnoc clocks and add them
> to the list of pm clocks in nss driver
>
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 51aba071c1eb..903311547e96 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -10,6 +10,8 @@
> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> #include <dt-bindings/thermal/thermal.h>
>
> / {
> @@ -18,6 +20,24 @@ / {
> #size-cells = <2>;
>
> clocks {
> + bias_pll_cc_clk: bias-pll-cc-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <1200000000>;
> + #clock-cells = <0>;
> + };
> +
> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <461500000>;
> + #clock-cells = <0>;
> + };
> +
> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <353000000>;
> + #clock-cells = <0>;
> + };
Which part provides these clocks?
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -722,6 +742,34 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + nsscc: clock-controller@39b00000 {
> + compatible = "qcom,ipq9574-nsscc";
> + reg = <0x39b00000 0x80000>;
> + clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
> + <&gcc GCC_NSSNOC_SNOC_CLK>,
> + <&gcc GCC_NSSNOC_SNOC_1_CLK>,
> + <&bias_pll_cc_clk>,
> + <&bias_pll_nss_noc_clk>,
> + <&bias_pll_ubi_nc_clk>,
> + <&gcc GPLL0_OUT_AUX>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <&xo_board_clk>;
If you move xo_board closer to the start of the list, it will be
slightly easier to review.
> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
> + "uniphy2_nss_tx_clk", "xo_board_clk";
You are using clock indices. Please drop clock-names.
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> };
>
> thermal-zones {
> --
> 2.34.1
>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 11:44 ` Dmitry Baryshkov
-1 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-08-25 11:44 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
> devices.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V2:
> - Added depends on ARM64 || COMPILE_TEST in Kconfig
> - Added module_platform_driver
> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc clocks as critical
> & added pm_clk for nssnoc clocks
> - Updated the uniphy clock names
>
> drivers/clk/qcom/Kconfig | 7 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
> 3 files changed, 3117 insertions(+)
> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index bd9bfb11b328..3ecc11e2c8e3 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
> i2c, USB, SD/eMMC, etc. Select this for the root clock
> of ipq9574.
>
> +config IPQ_NSSCC_9574
> + tristate "IPQ9574 NSS Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + depends on IPQ_GCC_9574
> + help
> + Support for NSS clock controller on ipq9574 devices.
> +
> config MSM_GCC_8660
> tristate "MSM8660 Global Clock Controller"
> depends on ARM || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 4790c8cca426..3f084928962e 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9574.c
> new file mode 100644
> index 000000000000..65bdb449ae5f
> --- /dev/null
> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
> @@ -0,0 +1,3109 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +
> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +#include "reset.h"
> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> + DT_NSSNOC_NSSCC_CLK,
> + DT_NSSNOC_SNOC_CLK,
> + DT_NSSNOC_SNOC_1_CLK,
Not using the index makes it seem that these clocks are not used,
until one scrolls down to pm_clks.
BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
here (not a simple NIU).
> + DT_BIAS_PLL_CC_CLK,
> + DT_BIAS_PLL_NSS_NOC_CLK,
> + DT_BIAS_PLL_UBI_NC_CLK,
> + DT_GCC_GPLL0_OUT_AUX,
> + DT_UNIPHY0_NSS_RX_CLK,
> + DT_UNIPHY0_NSS_TX_CLK,
> + DT_UNIPHY1_NSS_RX_CLK,
> + DT_UNIPHY1_NSS_TX_CLK,
> + DT_UNIPHY2_NSS_RX_CLK,
> + DT_UNIPHY2_NSS_TX_CLK,
> + DT_XO,
As I wrote, please move DT_XO closer to the beginning of the list.
> +};
> +
> +enum {
> + P_BIAS_PLL_CC_CLK,
> + P_BIAS_PLL_NSS_NOC_CLK,
> + P_BIAS_PLL_UBI_NC_CLK,
> + P_GCC_GPLL0_OUT_AUX,
> + P_UBI32_PLL_OUT_MAIN,
> + P_UNIPHY0_NSS_RX_CLK,
> + P_UNIPHY0_NSS_TX_CLK,
> + P_UNIPHY1_NSS_RX_CLK,
> + P_UNIPHY1_NSS_TX_CLK,
> + P_UNIPHY2_NSS_RX_CLK,
> + P_UNIPHY2_NSS_TX_CLK,
> + P_XO,
> +};
> +
> +static const struct alpha_pll_config ubi32_pll_config = {
> + .l = 0x3e,
> + .alpha = 0x6666,
> + .config_ctl_val = 0x200d4aa8,
> + .config_ctl_hi_val = 0x3c,
> + .main_output_mask = BIT(0),
> + .aux_output_mask = BIT(1),
> + .pre_div_val = 0x0,
> + .pre_div_mask = BIT(12),
> + .post_div_val = 0x0,
> + .post_div_mask = GENMASK(9, 8),
> + .alpha_en_mask = BIT(24),
> + .test_ctl_val = 0x1c0000c0,
> + .test_ctl_hi_val = 0x4000,
> +};
> +
> +static struct clk_alpha_pll ubi32_pll_main = {
> + .offset = 0x28000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
> + .flags = SUPPORTS_DYNAMIC_UPDATE,
> + .clkr = {
> + .hw.init = &(const struct clk_init_data) {
> + .name = "ubi32_pll_main",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_XO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv ubi32_pll = {
> + .offset = 0x28000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
> + .width = 2,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "ubi32_pll",
> + .parent_hws = (const struct clk_hw *[]) {
> + &ubi32_pll_main.clkr.hw
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
[skipped clock tables, LGTM]
> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
> + { .compatible = "qcom,ipq9574-nsscc" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
> +
> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
> +
> + int ret;
> +
> + ret = devm_pm_runtime_enable(&pdev->dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = devm_pm_clk_create(&pdev->dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
As we are switching to DT indices, better add new API that takes index
rather than mixing indices and names.
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
> + return ret;
> + }
> +
> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc clock\n");
> + return ret;
> + }
> +
> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1 clock\n");
> + return ret;
> + }
> +
> + ret = pm_runtime_get(&pdev->dev);
> + if (ret)
> + return ret;
> +
> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
> +
> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
> +}
> +
> +static const struct dev_pm_ops nss_cc_pm_ops = {
> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
> +};
> +
> +static struct platform_driver nss_cc_ipq9574_driver = {
> + .probe = nss_cc_ipq9574_probe,
> + .driver = {
> + .name = "qcom,nsscc-ipq9574",
> + .of_match_table = nss_cc_ipq9574_match_table,
> + .pm = &nss_cc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(nss_cc_ipq9574_driver);
> +
> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-08-25 11:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-08-25 11:44 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
> devices.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V2:
> - Added depends on ARM64 || COMPILE_TEST in Kconfig
> - Added module_platform_driver
> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc clocks as critical
> & added pm_clk for nssnoc clocks
> - Updated the uniphy clock names
>
> drivers/clk/qcom/Kconfig | 7 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
> 3 files changed, 3117 insertions(+)
> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index bd9bfb11b328..3ecc11e2c8e3 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
> i2c, USB, SD/eMMC, etc. Select this for the root clock
> of ipq9574.
>
> +config IPQ_NSSCC_9574
> + tristate "IPQ9574 NSS Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + depends on IPQ_GCC_9574
> + help
> + Support for NSS clock controller on ipq9574 devices.
> +
> config MSM_GCC_8660
> tristate "MSM8660 Global Clock Controller"
> depends on ARM || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 4790c8cca426..3f084928962e 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9574.c
> new file mode 100644
> index 000000000000..65bdb449ae5f
> --- /dev/null
> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
> @@ -0,0 +1,3109 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +
> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +#include "reset.h"
> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> + DT_NSSNOC_NSSCC_CLK,
> + DT_NSSNOC_SNOC_CLK,
> + DT_NSSNOC_SNOC_1_CLK,
Not using the index makes it seem that these clocks are not used,
until one scrolls down to pm_clks.
BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
here (not a simple NIU).
> + DT_BIAS_PLL_CC_CLK,
> + DT_BIAS_PLL_NSS_NOC_CLK,
> + DT_BIAS_PLL_UBI_NC_CLK,
> + DT_GCC_GPLL0_OUT_AUX,
> + DT_UNIPHY0_NSS_RX_CLK,
> + DT_UNIPHY0_NSS_TX_CLK,
> + DT_UNIPHY1_NSS_RX_CLK,
> + DT_UNIPHY1_NSS_TX_CLK,
> + DT_UNIPHY2_NSS_RX_CLK,
> + DT_UNIPHY2_NSS_TX_CLK,
> + DT_XO,
As I wrote, please move DT_XO closer to the beginning of the list.
> +};
> +
> +enum {
> + P_BIAS_PLL_CC_CLK,
> + P_BIAS_PLL_NSS_NOC_CLK,
> + P_BIAS_PLL_UBI_NC_CLK,
> + P_GCC_GPLL0_OUT_AUX,
> + P_UBI32_PLL_OUT_MAIN,
> + P_UNIPHY0_NSS_RX_CLK,
> + P_UNIPHY0_NSS_TX_CLK,
> + P_UNIPHY1_NSS_RX_CLK,
> + P_UNIPHY1_NSS_TX_CLK,
> + P_UNIPHY2_NSS_RX_CLK,
> + P_UNIPHY2_NSS_TX_CLK,
> + P_XO,
> +};
> +
> +static const struct alpha_pll_config ubi32_pll_config = {
> + .l = 0x3e,
> + .alpha = 0x6666,
> + .config_ctl_val = 0x200d4aa8,
> + .config_ctl_hi_val = 0x3c,
> + .main_output_mask = BIT(0),
> + .aux_output_mask = BIT(1),
> + .pre_div_val = 0x0,
> + .pre_div_mask = BIT(12),
> + .post_div_val = 0x0,
> + .post_div_mask = GENMASK(9, 8),
> + .alpha_en_mask = BIT(24),
> + .test_ctl_val = 0x1c0000c0,
> + .test_ctl_hi_val = 0x4000,
> +};
> +
> +static struct clk_alpha_pll ubi32_pll_main = {
> + .offset = 0x28000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
> + .flags = SUPPORTS_DYNAMIC_UPDATE,
> + .clkr = {
> + .hw.init = &(const struct clk_init_data) {
> + .name = "ubi32_pll_main",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_XO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv ubi32_pll = {
> + .offset = 0x28000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
> + .width = 2,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "ubi32_pll",
> + .parent_hws = (const struct clk_hw *[]) {
> + &ubi32_pll_main.clkr.hw
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
[skipped clock tables, LGTM]
> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
> + { .compatible = "qcom,ipq9574-nsscc" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
> +
> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
> +
> + int ret;
> +
> + ret = devm_pm_runtime_enable(&pdev->dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = devm_pm_clk_create(&pdev->dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
As we are switching to DT indices, better add new API that takes index
rather than mixing indices and names.
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
> + return ret;
> + }
> +
> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc clock\n");
> + return ret;
> + }
> +
> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1 clock\n");
> + return ret;
> + }
> +
> + ret = pm_runtime_get(&pdev->dev);
> + if (ret)
> + return ret;
> +
> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
> +
> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
> +}
> +
> +static const struct dev_pm_ops nss_cc_pm_ops = {
> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
> +};
> +
> +static struct platform_driver nss_cc_ipq9574_driver = {
> + .probe = nss_cc_ipq9574_probe,
> + .driver = {
> + .name = "qcom,nsscc-ipq9574",
> + .of_match_table = nss_cc_ipq9574_match_table,
> + .pm = &nss_cc_pm_ops,
> + },
> +};
> +
> +module_platform_driver(nss_cc_ipq9574_driver);
> +
> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 12:27 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-25 12:27 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25/08/2023 11:12, Devi Priya wrote:
> Add the definition for GPLL0_OUT_AUX clock.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 +
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
@ 2023-08-25 12:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-25 12:27 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25/08/2023 11:12, Devi Priya wrote:
> Add the definition for GPLL0_OUT_AUX clock.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 +
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 12:28 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-25 12:28 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25/08/2023 11:12, Devi Priya wrote:
> Add the definition for GPLL0_OUT_AUX clock.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> index 08fd3a37acaa..f5749bf53898 100644
> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> @@ -216,4 +216,5 @@
> #define GCC_CRYPTO_AHB_CLK 207
> #define GCC_USB0_PIPE_CLK 208
> #define GCC_USB0_SLEEP_CLK 209
> +#define GPLL0_OUT_AUX 210
Although you remove here blank line...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
@ 2023-08-25 12:28 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-25 12:28 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25/08/2023 11:12, Devi Priya wrote:
> Add the definition for GPLL0_OUT_AUX clock.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> index 08fd3a37acaa..f5749bf53898 100644
> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> @@ -216,4 +216,5 @@
> #define GCC_CRYPTO_AHB_CLK 207
> #define GCC_USB0_PIPE_CLK 208
> #define GCC_USB0_SLEEP_CLK 209
> +#define GPLL0_OUT_AUX 210
Although you remove here blank line...
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 12:30 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-25 12:30 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25/08/2023 11:12, Devi Priya wrote:
> Add NSSCC clock and reset definitions for ipq9574.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V2:
> - Referenced gcc.yaml and dropped the duplicate properties from
> the binding
> - Updated Uniphy clock names
> - Added nssnoc clocks and clock-names
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Rob's bot report is a result of patch #2 failing to apply.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
@ 2023-08-25 12:30 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-25 12:30 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25/08/2023 11:12, Devi Priya wrote:
> Add NSSCC clock and reset definitions for ipq9574.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V2:
> - Referenced gcc.yaml and dropped the duplicate properties from
> the binding
> - Updated Uniphy clock names
> - Added nssnoc clocks and clock-names
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Rob's bot report is a result of patch #2 failing to apply.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
2023-08-25 9:12 ` Devi Priya
@ 2023-08-25 20:58 ` Stephen Boyd
-1 siblings, 0 replies; 70+ messages in thread
From: Stephen Boyd @ 2023-08-25 20:58 UTC (permalink / raw)
To: Devi Priya, agross, andersson, arnd, catalin.marinas, conor+dt,
devicetree, geert+renesas, konrad.dybcio, krzysztof.kozlowski+dt,
linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
mturquette, netdev, nfraprado, p.zabel, peng.fan, rafal,
richardcochran, robh+dt, will
Cc: quic_devipriy, quic_saahtoma
Quoting Devi Priya (2023-08-25 02:12:28)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index e4ef645f65d1..1c2a72840cd2 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_ALPHA_VAL] = 0x24,
> [PLL_OFF_ALPHA_VAL_U] = 0x28,
> },
> +
Why the extra newline? All other types aren't this way.
> + [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_TEST_CTL] = 0x0c,
> + [PLL_OFF_TEST_CTL_U] = 0x10,
> + [PLL_OFF_USER_CTL] = 0x14,
> + [PLL_OFF_CONFIG_CTL] = 0x18,
> + [PLL_OFF_CONFIG_CTL_U] = 0x1c,
> + [PLL_OFF_STATUS] = 0x20,
> + },
> +
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
@ 2023-08-25 20:58 ` Stephen Boyd
0 siblings, 0 replies; 70+ messages in thread
From: Stephen Boyd @ 2023-08-25 20:58 UTC (permalink / raw)
To: Devi Priya, agross, andersson, arnd, catalin.marinas, conor+dt,
devicetree, geert+renesas, konrad.dybcio, krzysztof.kozlowski+dt,
linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
mturquette, netdev, nfraprado, p.zabel, peng.fan, rafal,
richardcochran, robh+dt, will
Cc: quic_devipriy, quic_saahtoma
Quoting Devi Priya (2023-08-25 02:12:28)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index e4ef645f65d1..1c2a72840cd2 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_ALPHA_VAL] = 0x24,
> [PLL_OFF_ALPHA_VAL_U] = 0x28,
> },
> +
Why the extra newline? All other types aren't this way.
> + [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_TEST_CTL] = 0x0c,
> + [PLL_OFF_TEST_CTL_U] = 0x10,
> + [PLL_OFF_USER_CTL] = 0x14,
> + [PLL_OFF_CONFIG_CTL] = 0x18,
> + [PLL_OFF_CONFIG_CTL_U] = 0x1c,
> + [PLL_OFF_STATUS] = 0x20,
> + },
> +
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-08-25 9:12 ` Devi Priya
@ 2023-08-28 12:35 ` Konrad Dybcio
-1 siblings, 0 replies; 70+ messages in thread
From: Konrad Dybcio @ 2023-08-28 12:35 UTC (permalink / raw)
To: Devi Priya, andersson, agross, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25.08.2023 11:12, Devi Priya wrote:
> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
> devices.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
[...]
> + [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
Please make all hex lowercase.
[...]
> + [PPE_FULL_RESET] = { 0x28A08, 0, 1, 0x1E0000 },
{ .reg = 0x28a08, .bitmask = GENMASK(foo,bar) },
[...]
> + ret = devm_pm_runtime_enable(&pdev->dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = devm_pm_clk_create(&pdev->dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
> + return ret;
dev_err_probe, everywhere?
Konrad
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-08-28 12:35 ` Konrad Dybcio
0 siblings, 0 replies; 70+ messages in thread
From: Konrad Dybcio @ 2023-08-28 12:35 UTC (permalink / raw)
To: Devi Priya, andersson, agross, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25.08.2023 11:12, Devi Priya wrote:
> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
> devices.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
[...]
> + [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
Please make all hex lowercase.
[...]
> + [PPE_FULL_RESET] = { 0x28A08, 0, 1, 0x1E0000 },
{ .reg = 0x28a08, .bitmask = GENMASK(foo,bar) },
[...]
> + ret = devm_pm_runtime_enable(&pdev->dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = devm_pm_clk_create(&pdev->dev);
> + if (ret < 0)
> + return ret;
> +
> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
> + return ret;
dev_err_probe, everywhere?
Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
2023-08-25 20:58 ` Stephen Boyd
@ 2023-08-29 3:28 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-29 3:28 UTC (permalink / raw)
To: Stephen Boyd, agross, andersson, arnd, catalin.marinas, conor+dt,
devicetree, geert+renesas, konrad.dybcio, krzysztof.kozlowski+dt,
linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
mturquette, netdev, nfraprado, p.zabel, peng.fan, rafal,
richardcochran, robh+dt, will
Cc: quic_saahtoma
On 8/26/2023 2:28 AM, Stephen Boyd wrote:
> Quoting Devi Priya (2023-08-25 02:12:28)
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index e4ef645f65d1..1c2a72840cd2 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
>> [PLL_OFF_ALPHA_VAL] = 0x24,
>> [PLL_OFF_ALPHA_VAL_U] = 0x28,
>> },
>> +
>
> Why the extra newline? All other types aren't this way.
Sure, will drop it in V3
Thanks,
Devi Priya
>
>> + [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
>> + [PLL_OFF_L_VAL] = 0x04,
>> + [PLL_OFF_ALPHA_VAL] = 0x08,
>> + [PLL_OFF_TEST_CTL] = 0x0c,
>> + [PLL_OFF_TEST_CTL_U] = 0x10,
>> + [PLL_OFF_USER_CTL] = 0x14,
>> + [PLL_OFF_CONFIG_CTL] = 0x18,
>> + [PLL_OFF_CONFIG_CTL_U] = 0x1c,
>> + [PLL_OFF_STATUS] = 0x20,
>> + },
>> +
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
@ 2023-08-29 3:28 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-29 3:28 UTC (permalink / raw)
To: Stephen Boyd, agross, andersson, arnd, catalin.marinas, conor+dt,
devicetree, geert+renesas, konrad.dybcio, krzysztof.kozlowski+dt,
linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
mturquette, netdev, nfraprado, p.zabel, peng.fan, rafal,
richardcochran, robh+dt, will
Cc: quic_saahtoma
On 8/26/2023 2:28 AM, Stephen Boyd wrote:
> Quoting Devi Priya (2023-08-25 02:12:28)
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index e4ef645f65d1..1c2a72840cd2 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
>> [PLL_OFF_ALPHA_VAL] = 0x24,
>> [PLL_OFF_ALPHA_VAL_U] = 0x28,
>> },
>> +
>
> Why the extra newline? All other types aren't this way.
Sure, will drop it in V3
Thanks,
Devi Priya
>
>> + [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
>> + [PLL_OFF_L_VAL] = 0x04,
>> + [PLL_OFF_ALPHA_VAL] = 0x08,
>> + [PLL_OFF_TEST_CTL] = 0x0c,
>> + [PLL_OFF_TEST_CTL_U] = 0x10,
>> + [PLL_OFF_USER_CTL] = 0x14,
>> + [PLL_OFF_CONFIG_CTL] = 0x18,
>> + [PLL_OFF_CONFIG_CTL_U] = 0x1c,
>> + [PLL_OFF_STATUS] = 0x20,
>> + },
>> +
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-08-28 12:35 ` Konrad Dybcio
@ 2023-08-29 3:42 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-29 3:42 UTC (permalink / raw)
To: Konrad Dybcio, andersson, agross, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 8/28/2023 6:05 PM, Konrad Dybcio wrote:
> On 25.08.2023 11:12, Devi Priya wrote:
>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
>> devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
> [...]
>
>> + [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
> Please make all hex lowercase.
Okay
>
> [...]
>
>> + [PPE_FULL_RESET] = { 0x28A08, 0, 1, 0x1E0000 },
> { .reg = 0x28a08, .bitmask = GENMASK(foo,bar) },
Sure, okay
>
> [...]
>
>> + ret = devm_pm_runtime_enable(&pdev->dev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = devm_pm_clk_create(&pdev->dev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
>> + return ret;
> dev_err_probe, everywhere?
Okay
Thanks,
Devi Priya
>
> Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-08-29 3:42 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-08-29 3:42 UTC (permalink / raw)
To: Konrad Dybcio, andersson, agross, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 8/28/2023 6:05 PM, Konrad Dybcio wrote:
> On 25.08.2023 11:12, Devi Priya wrote:
>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
>> devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
> [...]
>
>> + [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28A04, 9 },
> Please make all hex lowercase.
Okay
>
> [...]
>
>> + [PPE_FULL_RESET] = { 0x28A08, 0, 1, 0x1E0000 },
> { .reg = 0x28a08, .bitmask = GENMASK(foo,bar) },
Sure, okay
>
> [...]
>
>> + ret = devm_pm_runtime_enable(&pdev->dev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = devm_pm_clk_create(&pdev->dev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
>> + return ret;
> dev_err_probe, everywhere?
Okay
Thanks,
Devi Priya
>
> Konrad
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 3/7] clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock
2023-08-25 9:12 ` Devi Priya
@ 2023-09-01 16:15 ` Kathiravan T
-1 siblings, 0 replies; 70+ messages in thread
From: Kathiravan T @ 2023-09-01 16:15 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 8/25/2023 2:42 PM, Devi Priya wrote:
> Add support for gpll0_out_aux clock which acts as the parent for
> certain networking subsystem (nss) clocks.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> drivers/clk/qcom/gcc-ipq9574.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index 8f430367299e..495a66f7d29a 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -107,6 +107,21 @@ static struct clk_alpha_pll_postdiv gpll0 = {
> },
> };
>
> +static struct clk_alpha_pll_postdiv gpll0_out_aux = {
> + .offset = 0x20000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .width = 4,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gpll0_out_aux",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll0_main.clkr.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
You might need to drop the member 'flags '. Please refer
https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/
I will send the patch to drop the flags in the existing driver sometime
next week.
Thanks,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + },
> +};
> +
> static struct clk_alpha_pll gpll4_main = {
> .offset = 0x22000,
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> @@ -4144,6 +4159,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
> [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
> [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
> [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
> + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
> };
>
> static const struct qcom_reset_map gcc_ipq9574_resets[] = {
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 3/7] clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock
@ 2023-09-01 16:15 ` Kathiravan T
0 siblings, 0 replies; 70+ messages in thread
From: Kathiravan T @ 2023-09-01 16:15 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 8/25/2023 2:42 PM, Devi Priya wrote:
> Add support for gpll0_out_aux clock which acts as the parent for
> certain networking subsystem (nss) clocks.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> drivers/clk/qcom/gcc-ipq9574.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index 8f430367299e..495a66f7d29a 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -107,6 +107,21 @@ static struct clk_alpha_pll_postdiv gpll0 = {
> },
> };
>
> +static struct clk_alpha_pll_postdiv gpll0_out_aux = {
> + .offset = 0x20000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .width = 4,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gpll0_out_aux",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll0_main.clkr.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
You might need to drop the member 'flags '. Please refer
https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/
I will send the patch to drop the flags in the existing driver sometime
next week.
Thanks,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + },
> +};
> +
> static struct clk_alpha_pll gpll4_main = {
> .offset = 0x22000,
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> @@ -4144,6 +4159,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
> [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
> [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
> [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
> + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
> };
>
> static const struct qcom_reset_map gcc_ipq9574_resets[] = {
_______________________________________________
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^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-08-25 11:44 ` Dmitry Baryshkov
@ 2023-09-12 14:08 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-09-12 14:08 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
>> devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>> Changes in V2:
>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>> - Added module_platform_driver
>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc clocks as critical
>> & added pm_clk for nssnoc clocks
>> - Updated the uniphy clock names
>>
>> drivers/clk/qcom/Kconfig | 7 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
>> 3 files changed, 3117 insertions(+)
>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index bd9bfb11b328..3ecc11e2c8e3 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>> of ipq9574.
>>
>> +config IPQ_NSSCC_9574
>> + tristate "IPQ9574 NSS Clock Controller"
>> + depends on ARM64 || COMPILE_TEST
>> + depends on IPQ_GCC_9574
>> + help
>> + Support for NSS clock controller on ipq9574 devices.
>> +
>> config MSM_GCC_8660
>> tristate "MSM8660 Global Clock Controller"
>> depends on ARM || COMPILE_TEST
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 4790c8cca426..3f084928962e 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9574.c
>> new file mode 100644
>> index 000000000000..65bdb449ae5f
>> --- /dev/null
>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>> @@ -0,0 +1,3109 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/err.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/pm_clock.h>
>> +#include <linux/pm_runtime.h>
>> +
>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-pll.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "common.h"
>> +#include "reset.h"
>> +
>> +/* Need to match the order of clocks in DT binding */
>> +enum {
>> + DT_NSSNOC_NSSCC_CLK,
>> + DT_NSSNOC_SNOC_CLK,
>> + DT_NSSNOC_SNOC_1_CLK,
>
> Not using the index makes it seem that these clocks are not used,
> until one scrolls down to pm_clks.
Okay, got it
>
> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
> here (not a simple NIU).
Hi Dmitry, We are exploring on the ICC driver. In the meantime to
unblock PCIe/NSS changes getting merged, shall we use regmap_update_bits
and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
probe function of the gcc driver itself as like sm8550 driver to get the
changes merged?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>
>> + DT_BIAS_PLL_CC_CLK,
>> + DT_BIAS_PLL_NSS_NOC_CLK,
>> + DT_BIAS_PLL_UBI_NC_CLK,
>> + DT_GCC_GPLL0_OUT_AUX,
>> + DT_UNIPHY0_NSS_RX_CLK,
>> + DT_UNIPHY0_NSS_TX_CLK,
>> + DT_UNIPHY1_NSS_RX_CLK,
>> + DT_UNIPHY1_NSS_TX_CLK,
>> + DT_UNIPHY2_NSS_RX_CLK,
>> + DT_UNIPHY2_NSS_TX_CLK,
>> + DT_XO,
>
> As I wrote, please move DT_XO closer to the beginning of the list.
>
>> +};
>> +
>> +enum {
>> + P_BIAS_PLL_CC_CLK,
>> + P_BIAS_PLL_NSS_NOC_CLK,
>> + P_BIAS_PLL_UBI_NC_CLK,
>> + P_GCC_GPLL0_OUT_AUX,
>> + P_UBI32_PLL_OUT_MAIN,
>> + P_UNIPHY0_NSS_RX_CLK,
>> + P_UNIPHY0_NSS_TX_CLK,
>> + P_UNIPHY1_NSS_RX_CLK,
>> + P_UNIPHY1_NSS_TX_CLK,
>> + P_UNIPHY2_NSS_RX_CLK,
>> + P_UNIPHY2_NSS_TX_CLK,
>> + P_XO,
>> +};
>> +
>> +static const struct alpha_pll_config ubi32_pll_config = {
>> + .l = 0x3e,
>> + .alpha = 0x6666,
>> + .config_ctl_val = 0x200d4aa8,
>> + .config_ctl_hi_val = 0x3c,
>> + .main_output_mask = BIT(0),
>> + .aux_output_mask = BIT(1),
>> + .pre_div_val = 0x0,
>> + .pre_div_mask = BIT(12),
>> + .post_div_val = 0x0,
>> + .post_div_mask = GENMASK(9, 8),
>> + .alpha_en_mask = BIT(24),
>> + .test_ctl_val = 0x1c0000c0,
>> + .test_ctl_hi_val = 0x4000,
>> +};
>> +
>> +static struct clk_alpha_pll ubi32_pll_main = {
>> + .offset = 0x28000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
>> + .clkr = {
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "ubi32_pll_main",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_XO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_huayra_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>> + .offset = 0x28000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>> + .width = 2,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "ubi32_pll",
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &ubi32_pll_main.clkr.hw
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>
> [skipped clock tables, LGTM]
>
>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
>> + { .compatible = "qcom,ipq9574-nsscc" },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
>> +
>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>> +{
>> + struct regmap *regmap;
>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>> +
>> + int ret;
>> +
>> + ret = devm_pm_runtime_enable(&pdev->dev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = devm_pm_clk_create(&pdev->dev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>
> As we are switching to DT indices, better add new API that takes index
> rather than mixing indices and names.
sure okay
Thanks,
Devi Priya
>
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
>> + return ret;
>> + }
>> +
>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc clock\n");
>> + return ret;
>> + }
>> +
>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1 clock\n");
>> + return ret;
>> + }
>> +
>> + ret = pm_runtime_get(&pdev->dev);
>> + if (ret)
>> + return ret;
>> +
>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
>> +
>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
>> +}
>> +
>> +static const struct dev_pm_ops nss_cc_pm_ops = {
>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
>> +};
>> +
>> +static struct platform_driver nss_cc_ipq9574_driver = {
>> + .probe = nss_cc_ipq9574_probe,
>> + .driver = {
>> + .name = "qcom,nsscc-ipq9574",
>> + .of_match_table = nss_cc_ipq9574_match_table,
>> + .pm = &nss_cc_pm_ops,
>> + },
>> +};
>> +
>> +module_platform_driver(nss_cc_ipq9574_driver);
>> +
>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.34.1
>>
>
>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-09-12 14:08 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-09-12 14:08 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
>> devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>> Changes in V2:
>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>> - Added module_platform_driver
>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc clocks as critical
>> & added pm_clk for nssnoc clocks
>> - Updated the uniphy clock names
>>
>> drivers/clk/qcom/Kconfig | 7 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
>> 3 files changed, 3117 insertions(+)
>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index bd9bfb11b328..3ecc11e2c8e3 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>> of ipq9574.
>>
>> +config IPQ_NSSCC_9574
>> + tristate "IPQ9574 NSS Clock Controller"
>> + depends on ARM64 || COMPILE_TEST
>> + depends on IPQ_GCC_9574
>> + help
>> + Support for NSS clock controller on ipq9574 devices.
>> +
>> config MSM_GCC_8660
>> tristate "MSM8660 Global Clock Controller"
>> depends on ARM || COMPILE_TEST
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 4790c8cca426..3f084928962e 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9574.c
>> new file mode 100644
>> index 000000000000..65bdb449ae5f
>> --- /dev/null
>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>> @@ -0,0 +1,3109 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/err.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/pm_clock.h>
>> +#include <linux/pm_runtime.h>
>> +
>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-pll.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "common.h"
>> +#include "reset.h"
>> +
>> +/* Need to match the order of clocks in DT binding */
>> +enum {
>> + DT_NSSNOC_NSSCC_CLK,
>> + DT_NSSNOC_SNOC_CLK,
>> + DT_NSSNOC_SNOC_1_CLK,
>
> Not using the index makes it seem that these clocks are not used,
> until one scrolls down to pm_clks.
Okay, got it
>
> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
> here (not a simple NIU).
Hi Dmitry, We are exploring on the ICC driver. In the meantime to
unblock PCIe/NSS changes getting merged, shall we use regmap_update_bits
and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
probe function of the gcc driver itself as like sm8550 driver to get the
changes merged?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>
>> + DT_BIAS_PLL_CC_CLK,
>> + DT_BIAS_PLL_NSS_NOC_CLK,
>> + DT_BIAS_PLL_UBI_NC_CLK,
>> + DT_GCC_GPLL0_OUT_AUX,
>> + DT_UNIPHY0_NSS_RX_CLK,
>> + DT_UNIPHY0_NSS_TX_CLK,
>> + DT_UNIPHY1_NSS_RX_CLK,
>> + DT_UNIPHY1_NSS_TX_CLK,
>> + DT_UNIPHY2_NSS_RX_CLK,
>> + DT_UNIPHY2_NSS_TX_CLK,
>> + DT_XO,
>
> As I wrote, please move DT_XO closer to the beginning of the list.
>
>> +};
>> +
>> +enum {
>> + P_BIAS_PLL_CC_CLK,
>> + P_BIAS_PLL_NSS_NOC_CLK,
>> + P_BIAS_PLL_UBI_NC_CLK,
>> + P_GCC_GPLL0_OUT_AUX,
>> + P_UBI32_PLL_OUT_MAIN,
>> + P_UNIPHY0_NSS_RX_CLK,
>> + P_UNIPHY0_NSS_TX_CLK,
>> + P_UNIPHY1_NSS_RX_CLK,
>> + P_UNIPHY1_NSS_TX_CLK,
>> + P_UNIPHY2_NSS_RX_CLK,
>> + P_UNIPHY2_NSS_TX_CLK,
>> + P_XO,
>> +};
>> +
>> +static const struct alpha_pll_config ubi32_pll_config = {
>> + .l = 0x3e,
>> + .alpha = 0x6666,
>> + .config_ctl_val = 0x200d4aa8,
>> + .config_ctl_hi_val = 0x3c,
>> + .main_output_mask = BIT(0),
>> + .aux_output_mask = BIT(1),
>> + .pre_div_val = 0x0,
>> + .pre_div_mask = BIT(12),
>> + .post_div_val = 0x0,
>> + .post_div_mask = GENMASK(9, 8),
>> + .alpha_en_mask = BIT(24),
>> + .test_ctl_val = 0x1c0000c0,
>> + .test_ctl_hi_val = 0x4000,
>> +};
>> +
>> +static struct clk_alpha_pll ubi32_pll_main = {
>> + .offset = 0x28000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
>> + .clkr = {
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "ubi32_pll_main",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_XO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_huayra_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>> + .offset = 0x28000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>> + .width = 2,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "ubi32_pll",
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &ubi32_pll_main.clkr.hw
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>
> [skipped clock tables, LGTM]
>
>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
>> + { .compatible = "qcom,ipq9574-nsscc" },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
>> +
>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>> +{
>> + struct regmap *regmap;
>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>> +
>> + int ret;
>> +
>> + ret = devm_pm_runtime_enable(&pdev->dev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = devm_pm_clk_create(&pdev->dev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>
> As we are switching to DT indices, better add new API that takes index
> rather than mixing indices and names.
sure okay
Thanks,
Devi Priya
>
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc clock\n");
>> + return ret;
>> + }
>> +
>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc clock\n");
>> + return ret;
>> + }
>> +
>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1 clock\n");
>> + return ret;
>> + }
>> +
>> + ret = pm_runtime_get(&pdev->dev);
>> + if (ret)
>> + return ret;
>> +
>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
>> +
>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
>> +}
>> +
>> +static const struct dev_pm_ops nss_cc_pm_ops = {
>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
>> +};
>> +
>> +static struct platform_driver nss_cc_ipq9574_driver = {
>> + .probe = nss_cc_ipq9574_probe,
>> + .driver = {
>> + .name = "qcom,nsscc-ipq9574",
>> + .of_match_table = nss_cc_ipq9574_match_table,
>> + .pm = &nss_cc_pm_ops,
>> + },
>> +};
>> +
>> +module_platform_driver(nss_cc_ipq9574_driver);
>> +
>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.34.1
>>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
2023-08-25 11:28 ` Dmitry Baryshkov
@ 2023-09-13 3:32 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-09-13 3:32 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 8/25/2023 4:58 PM, Dmitry Baryshkov wrote:
> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>> Add a node for the nss clock controller found on ipq9574 based devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>> Changes in V2:
>> - Dropped the fixed clock node gcc_gpll0_out_aux and added
>> support for the same in gcc driver
>> - Updated the node name to clock-controller@39b00000
>> - Added clock-names to retrieve the nssnoc clocks and add them
>> to the list of pm clocks in nss driver
>>
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++
>> 1 file changed, 48 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 51aba071c1eb..903311547e96 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -10,6 +10,8 @@
>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>> #include <dt-bindings/thermal/thermal.h>
>>
>> / {
>> @@ -18,6 +20,24 @@ / {
>> #size-cells = <2>;
>>
>> clocks {
>> + bias_pll_cc_clk: bias-pll-cc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <1200000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <461500000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <353000000>;
>> + #clock-cells = <0>;
>> + };
>
> Which part provides these clocks?
The Bias PLL generates these clocks based on the reference clock.
>
>> +
>> sleep_clk: sleep-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> @@ -722,6 +742,34 @@ frame@b128000 {
>> status = "disabled";
>> };
>> };
>> +
>> + nsscc: clock-controller@39b00000 {
>> + compatible = "qcom,ipq9574-nsscc";
>> + reg = <0x39b00000 0x80000>;
>> + clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
>> + <&gcc GCC_NSSNOC_SNOC_CLK>,
>> + <&gcc GCC_NSSNOC_SNOC_1_CLK>,
>> + <&bias_pll_cc_clk>,
>> + <&bias_pll_nss_noc_clk>,
>> + <&bias_pll_ubi_nc_clk>,
>> + <&gcc GPLL0_OUT_AUX>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <&xo_board_clk>;
>
> If you move xo_board closer to the start of the list, it will be
> slightly easier to review.
Sure okay
>
>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
>> + "uniphy2_nss_tx_clk", "xo_board_clk";
>
> You are using clock indices. Please drop clock-names.
Sure okay
Thanks,
Devi Priya
>
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> };
>>
>> thermal-zones {
>> --
>> 2.34.1
>>
>
>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
@ 2023-09-13 3:32 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-09-13 3:32 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 8/25/2023 4:58 PM, Dmitry Baryshkov wrote:
> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>> Add a node for the nss clock controller found on ipq9574 based devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>> Changes in V2:
>> - Dropped the fixed clock node gcc_gpll0_out_aux and added
>> support for the same in gcc driver
>> - Updated the node name to clock-controller@39b00000
>> - Added clock-names to retrieve the nssnoc clocks and add them
>> to the list of pm clocks in nss driver
>>
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++
>> 1 file changed, 48 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 51aba071c1eb..903311547e96 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -10,6 +10,8 @@
>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>> #include <dt-bindings/thermal/thermal.h>
>>
>> / {
>> @@ -18,6 +20,24 @@ / {
>> #size-cells = <2>;
>>
>> clocks {
>> + bias_pll_cc_clk: bias-pll-cc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <1200000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <461500000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <353000000>;
>> + #clock-cells = <0>;
>> + };
>
> Which part provides these clocks?
The Bias PLL generates these clocks based on the reference clock.
>
>> +
>> sleep_clk: sleep-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> @@ -722,6 +742,34 @@ frame@b128000 {
>> status = "disabled";
>> };
>> };
>> +
>> + nsscc: clock-controller@39b00000 {
>> + compatible = "qcom,ipq9574-nsscc";
>> + reg = <0x39b00000 0x80000>;
>> + clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
>> + <&gcc GCC_NSSNOC_SNOC_CLK>,
>> + <&gcc GCC_NSSNOC_SNOC_1_CLK>,
>> + <&bias_pll_cc_clk>,
>> + <&bias_pll_nss_noc_clk>,
>> + <&bias_pll_ubi_nc_clk>,
>> + <&gcc GPLL0_OUT_AUX>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <&xo_board_clk>;
>
> If you move xo_board closer to the start of the list, it will be
> slightly easier to review.
Sure okay
>
>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
>> + "uniphy2_nss_tx_clk", "xo_board_clk";
>
> You are using clock indices. Please drop clock-names.
Sure okay
Thanks,
Devi Priya
>
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> };
>>
>> thermal-zones {
>> --
>> 2.34.1
>>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
2023-08-25 11:28 ` Dmitry Baryshkov
@ 2023-09-13 8:23 ` Geert Uytterhoeven
-1 siblings, 0 replies; 70+ messages in thread
From: Geert Uytterhoeven @ 2023-09-13 8:23 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
Hi Dmitry,
On Fri, Aug 25, 2023 at 1:28 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
> > Add a node for the nss clock controller found on ipq9574 based devices.
> >
> > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> > ---
> > Changes in V2:
> > - Dropped the fixed clock node gcc_gpll0_out_aux and added
> > support for the same in gcc driver
> > - Updated the node name to clock-controller@39b00000
> > - Added clock-names to retrieve the nssnoc clocks and add them
> > to the list of pm clocks in nss driver
> >
> > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++
> > 1 file changed, 48 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > index 51aba071c1eb..903311547e96 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > @@ -722,6 +742,34 @@ frame@b128000 {
> > status = "disabled";
> > };
> > };
> > +
> > + nsscc: clock-controller@39b00000 {
> > + compatible = "qcom,ipq9574-nsscc";
> > + reg = <0x39b00000 0x80000>;
> > + clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
> > + <&gcc GCC_NSSNOC_SNOC_CLK>,
> > + <&gcc GCC_NSSNOC_SNOC_1_CLK>,
> > + <&bias_pll_cc_clk>,
> > + <&bias_pll_nss_noc_clk>,
> > + <&bias_pll_ubi_nc_clk>,
> > + <&gcc GPLL0_OUT_AUX>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <&xo_board_clk>;
>
> If you move xo_board closer to the start of the list, it will be
> slightly easier to review.
>
> > + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
> > + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
> > + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
> > + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
> > + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
> > + "uniphy2_nss_tx_clk", "xo_board_clk";
>
> You are using clock indices. Please drop clock-names.
What do you mean by "using clock indices"?
Note that the "clock-names" property is required according to the DT bindings.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
@ 2023-09-13 8:23 ` Geert Uytterhoeven
0 siblings, 0 replies; 70+ messages in thread
From: Geert Uytterhoeven @ 2023-09-13 8:23 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
Hi Dmitry,
On Fri, Aug 25, 2023 at 1:28 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com> wrote:
> > Add a node for the nss clock controller found on ipq9574 based devices.
> >
> > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> > ---
> > Changes in V2:
> > - Dropped the fixed clock node gcc_gpll0_out_aux and added
> > support for the same in gcc driver
> > - Updated the node name to clock-controller@39b00000
> > - Added clock-names to retrieve the nssnoc clocks and add them
> > to the list of pm clocks in nss driver
> >
> > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++
> > 1 file changed, 48 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > index 51aba071c1eb..903311547e96 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > @@ -722,6 +742,34 @@ frame@b128000 {
> > status = "disabled";
> > };
> > };
> > +
> > + nsscc: clock-controller@39b00000 {
> > + compatible = "qcom,ipq9574-nsscc";
> > + reg = <0x39b00000 0x80000>;
> > + clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>,
> > + <&gcc GCC_NSSNOC_SNOC_CLK>,
> > + <&gcc GCC_NSSNOC_SNOC_1_CLK>,
> > + <&bias_pll_cc_clk>,
> > + <&bias_pll_nss_noc_clk>,
> > + <&bias_pll_ubi_nc_clk>,
> > + <&gcc GPLL0_OUT_AUX>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <&xo_board_clk>;
>
> If you move xo_board closer to the start of the list, it will be
> slightly easier to review.
>
> > + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
> > + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
> > + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
> > + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
> > + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
> > + "uniphy2_nss_tx_clk", "xo_board_clk";
>
> You are using clock indices. Please drop clock-names.
What do you mean by "using clock indices"?
Note that the "clock-names" property is required according to the DT bindings.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
2023-09-13 8:23 ` Geert Uytterhoeven
@ 2023-09-13 8:26 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 8:26 UTC (permalink / raw)
To: Geert Uytterhoeven, Dmitry Baryshkov
Cc: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 13/09/2023 10:23, Geert Uytterhoeven wrote:
>>
>>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
>>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
>>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
>>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
>>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
>>> + "uniphy2_nss_tx_clk", "xo_board_clk";
>>
>> You are using clock indices. Please drop clock-names.
>
> What do you mean by "using clock indices"?
> Note that the "clock-names" property is required according to the DT bindings.
Indeed, thanks for pointing this out. Probably bindings should be changed.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
@ 2023-09-13 8:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 8:26 UTC (permalink / raw)
To: Geert Uytterhoeven, Dmitry Baryshkov
Cc: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 13/09/2023 10:23, Geert Uytterhoeven wrote:
>>
>>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
>>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
>>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
>>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
>>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
>>> + "uniphy2_nss_tx_clk", "xo_board_clk";
>>
>> You are using clock indices. Please drop clock-names.
>
> What do you mean by "using clock indices"?
> Note that the "clock-names" property is required according to the DT bindings.
Indeed, thanks for pointing this out. Probably bindings should be changed.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
2023-08-25 12:30 ` Krzysztof Kozlowski
@ 2023-09-13 8:28 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 8:28 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25/08/2023 14:30, Krzysztof Kozlowski wrote:
> On 25/08/2023 11:12, Devi Priya wrote:
>> Add NSSCC clock and reset definitions for ipq9574.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>> Changes in V2:
>> - Referenced gcc.yaml and dropped the duplicate properties from
>> the binding
>> - Updated Uniphy clock names
>> - Added nssnoc clocks and clock-names
>
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Rob's bot report is a result of patch #2 failing to apply.
I assume changes will be needed here to drop clock-names.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
@ 2023-09-13 8:28 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 8:28 UTC (permalink / raw)
To: Devi Priya, andersson, agross, konrad.dybcio, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will,
p.zabel, richardcochran, arnd, geert+renesas, nfraprado, rafal,
peng.fan, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev
Cc: quic_saahtoma
On 25/08/2023 14:30, Krzysztof Kozlowski wrote:
> On 25/08/2023 11:12, Devi Priya wrote:
>> Add NSSCC clock and reset definitions for ipq9574.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>> Changes in V2:
>> - Referenced gcc.yaml and dropped the duplicate properties from
>> the binding
>> - Updated Uniphy clock names
>> - Added nssnoc clocks and clock-names
>
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Rob's bot report is a result of patch #2 failing to apply.
I assume changes will be needed here to drop clock-names.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
2023-09-13 8:26 ` Krzysztof Kozlowski
@ 2023-09-13 8:38 ` Geert Uytterhoeven
-1 siblings, 0 replies; 70+ messages in thread
From: Geert Uytterhoeven @ 2023-09-13 8:38 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Dmitry Baryshkov, Devi Priya, andersson, agross, konrad.dybcio,
mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt, conor+dt,
catalin.marinas, will, p.zabel, richardcochran, arnd,
geert+renesas, nfraprado, rafal, peng.fan, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-arm-kernel, netdev,
quic_saahtoma
Hi Krzysztof,
On Wed, Sep 13, 2023 at 10:26 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 13/09/2023 10:23, Geert Uytterhoeven wrote:
> >>
> >>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
> >>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
> >>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
> >>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
> >>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
> >>> + "uniphy2_nss_tx_clk", "xo_board_clk";
> >>
> >> You are using clock indices. Please drop clock-names.
> >
> > What do you mean by "using clock indices"?
> > Note that the "clock-names" property is required according to the DT bindings.
>
> Indeed, thanks for pointing this out. Probably bindings should be changed.
But what's so great about not having "clock-names"?
There are _14_ input clocks.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
@ 2023-09-13 8:38 ` Geert Uytterhoeven
0 siblings, 0 replies; 70+ messages in thread
From: Geert Uytterhoeven @ 2023-09-13 8:38 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Dmitry Baryshkov, Devi Priya, andersson, agross, konrad.dybcio,
mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt, conor+dt,
catalin.marinas, will, p.zabel, richardcochran, arnd,
geert+renesas, nfraprado, rafal, peng.fan, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-arm-kernel, netdev,
quic_saahtoma
Hi Krzysztof,
On Wed, Sep 13, 2023 at 10:26 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 13/09/2023 10:23, Geert Uytterhoeven wrote:
> >>
> >>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
> >>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
> >>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
> >>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
> >>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
> >>> + "uniphy2_nss_tx_clk", "xo_board_clk";
> >>
> >> You are using clock indices. Please drop clock-names.
> >
> > What do you mean by "using clock indices"?
> > Note that the "clock-names" property is required according to the DT bindings.
>
> Indeed, thanks for pointing this out. Probably bindings should be changed.
But what's so great about not having "clock-names"?
There are _14_ input clocks.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
2023-09-13 8:38 ` Geert Uytterhoeven
@ 2023-09-13 8:43 ` Konrad Dybcio
-1 siblings, 0 replies; 70+ messages in thread
From: Konrad Dybcio @ 2023-09-13 8:43 UTC (permalink / raw)
To: Geert Uytterhoeven, Krzysztof Kozlowski
Cc: Dmitry Baryshkov, Devi Priya, andersson, agross, mturquette,
sboyd, robh+dt, krzysztof.kozlowski+dt, conor+dt,
catalin.marinas, will, p.zabel, richardcochran, arnd,
geert+renesas, nfraprado, rafal, peng.fan, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-arm-kernel, netdev,
quic_saahtoma
On 13.09.2023 10:38, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Wed, Sep 13, 2023 at 10:26 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 13/09/2023 10:23, Geert Uytterhoeven wrote:
>>>>
>>>>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
>>>>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
>>>>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
>>>>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
>>>>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
>>>>> + "uniphy2_nss_tx_clk", "xo_board_clk";
>>>>
>>>> You are using clock indices. Please drop clock-names.
>>>
>>> What do you mean by "using clock indices"?
>>> Note that the "clock-names" property is required according to the DT bindings.
>>
>> Indeed, thanks for pointing this out. Probably bindings should be changed.
>
> But what's so great about not having "clock-names"?
> There are _14_ input clocks.
clk_parent_data has an "index" member, which lets us bind
clocks[n] to parent[n]. With the DT properties being ABI,
including the order of entries within, that lets us get rid
of clock-names and the matching is marginally faster.
Konrad
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
@ 2023-09-13 8:43 ` Konrad Dybcio
0 siblings, 0 replies; 70+ messages in thread
From: Konrad Dybcio @ 2023-09-13 8:43 UTC (permalink / raw)
To: Geert Uytterhoeven, Krzysztof Kozlowski
Cc: Dmitry Baryshkov, Devi Priya, andersson, agross, mturquette,
sboyd, robh+dt, krzysztof.kozlowski+dt, conor+dt,
catalin.marinas, will, p.zabel, richardcochran, arnd,
geert+renesas, nfraprado, rafal, peng.fan, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-arm-kernel, netdev,
quic_saahtoma
On 13.09.2023 10:38, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Wed, Sep 13, 2023 at 10:26 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 13/09/2023 10:23, Geert Uytterhoeven wrote:
>>>>
>>>>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
>>>>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
>>>>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
>>>>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
>>>>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
>>>>> + "uniphy2_nss_tx_clk", "xo_board_clk";
>>>>
>>>> You are using clock indices. Please drop clock-names.
>>>
>>> What do you mean by "using clock indices"?
>>> Note that the "clock-names" property is required according to the DT bindings.
>>
>> Indeed, thanks for pointing this out. Probably bindings should be changed.
>
> But what's so great about not having "clock-names"?
> There are _14_ input clocks.
clk_parent_data has an "index" member, which lets us bind
clocks[n] to parent[n]. With the DT properties being ABI,
including the order of entries within, that lets us get rid
of clock-names and the matching is marginally faster.
Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
2023-09-13 8:38 ` Geert Uytterhoeven
@ 2023-09-13 8:55 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 8:55 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Dmitry Baryshkov, Devi Priya, andersson, agross, konrad.dybcio,
mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt, conor+dt,
catalin.marinas, will, p.zabel, richardcochran, arnd,
geert+renesas, nfraprado, rafal, peng.fan, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-arm-kernel, netdev,
quic_saahtoma
On 13/09/2023 10:38, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Wed, Sep 13, 2023 at 10:26 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 13/09/2023 10:23, Geert Uytterhoeven wrote:
>>>>
>>>>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
>>>>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
>>>>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
>>>>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
>>>>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
>>>>> + "uniphy2_nss_tx_clk", "xo_board_clk";
>>>>
>>>> You are using clock indices. Please drop clock-names.
>>>
>>> What do you mean by "using clock indices"?
>>> Note that the "clock-names" property is required according to the DT bindings.
>>
>> Indeed, thanks for pointing this out. Probably bindings should be changed.
>
> But what's so great about not having "clock-names"?
> There are _14_ input clocks.
There is nothing particularly wrong. They are just not used by Linux
implementation and they confuse people into thinking items are not
strictly ordered. Thus agreement long time ago for Qualcomm clock
controllers was to drop the clock-names to avoid that confusion and make
it explicit.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node
@ 2023-09-13 8:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 8:55 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Dmitry Baryshkov, Devi Priya, andersson, agross, konrad.dybcio,
mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt, conor+dt,
catalin.marinas, will, p.zabel, richardcochran, arnd,
geert+renesas, nfraprado, rafal, peng.fan, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-arm-kernel, netdev,
quic_saahtoma
On 13/09/2023 10:38, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Wed, Sep 13, 2023 at 10:26 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 13/09/2023 10:23, Geert Uytterhoeven wrote:
>>>>
>>>>> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1",
>>>>> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk",
>>>>> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk",
>>>>> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk",
>>>>> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk",
>>>>> + "uniphy2_nss_tx_clk", "xo_board_clk";
>>>>
>>>> You are using clock indices. Please drop clock-names.
>>>
>>> What do you mean by "using clock indices"?
>>> Note that the "clock-names" property is required according to the DT bindings.
>>
>> Indeed, thanks for pointing this out. Probably bindings should be changed.
>
> But what's so great about not having "clock-names"?
> There are _14_ input clocks.
There is nothing particularly wrong. They are just not used by Linux
implementation and they confuse people into thinking items are not
strictly ordered. Thus agreement long time ago for Qualcomm clock
controllers was to drop the clock-names to avoid that confusion and make
it explicit.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-09-12 14:08 ` Devi Priya
@ 2023-09-20 6:39 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-09-20 6:39 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 9/12/2023 7:38 PM, Devi Priya wrote:
>
>
> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>> wrote:
>>>
>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>> based
>>> devices.
>>>
>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>> ---
>>> Changes in V2:
>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>> - Added module_platform_driver
>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>> clocks as critical
>>> & added pm_clk for nssnoc clocks
>>> - Updated the uniphy clock names
>>>
>>> drivers/clk/qcom/Kconfig | 7 +
>>> drivers/clk/qcom/Makefile | 1 +
>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
>>> 3 files changed, 3117 insertions(+)
>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>
>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>> --- a/drivers/clk/qcom/Kconfig
>>> +++ b/drivers/clk/qcom/Kconfig
>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>> of ipq9574.
>>>
>>> +config IPQ_NSSCC_9574
>>> + tristate "IPQ9574 NSS Clock Controller"
>>> + depends on ARM64 || COMPILE_TEST
>>> + depends on IPQ_GCC_9574
>>> + help
>>> + Support for NSS clock controller on ipq9574 devices.
>>> +
>>> config MSM_GCC_8660
>>> tristate "MSM8660 Global Clock Controller"
>>> depends on ARM || COMPILE_TEST
>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>> index 4790c8cca426..3f084928962e 100644
>>> --- a/drivers/clk/qcom/Makefile
>>> +++ b/drivers/clk/qcom/Makefile
>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>> new file mode 100644
>>> index 000000000000..65bdb449ae5f
>>> --- /dev/null
>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>> @@ -0,0 +1,3109 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>> reserved.
>>> + */
>>> +
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/err.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/pm_clock.h>
>>> +#include <linux/pm_runtime.h>
>>> +
>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>> +
>>> +#include "clk-alpha-pll.h"
>>> +#include "clk-branch.h"
>>> +#include "clk-pll.h"
>>> +#include "clk-rcg.h"
>>> +#include "clk-regmap.h"
>>> +#include "clk-regmap-divider.h"
>>> +#include "clk-regmap-mux.h"
>>> +#include "common.h"
>>> +#include "reset.h"
>>> +
>>> +/* Need to match the order of clocks in DT binding */
>>> +enum {
>>> + DT_NSSNOC_NSSCC_CLK,
>>> + DT_NSSNOC_SNOC_CLK,
>>> + DT_NSSNOC_SNOC_1_CLK,
>>
>> Not using the index makes it seem that these clocks are not used,
>> until one scrolls down to pm_clks.
> Okay, got it
>>
>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>> here (not a simple NIU).
>
> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
> unblock PCIe/NSS changes getting merged, shall we use regmap_update_bits
> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
> probe function of the gcc driver itself as like sm8550 driver to get the
> changes merged?
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
Hi Dmitry,
Just curious to know if we could send out the next series with the
proposed approach if that holds good.
Thanks,
Devi Priya
>>
>>> + DT_BIAS_PLL_CC_CLK,
>>> + DT_BIAS_PLL_NSS_NOC_CLK,
>>> + DT_BIAS_PLL_UBI_NC_CLK,
>>> + DT_GCC_GPLL0_OUT_AUX,
>>> + DT_UNIPHY0_NSS_RX_CLK,
>>> + DT_UNIPHY0_NSS_TX_CLK,
>>> + DT_UNIPHY1_NSS_RX_CLK,
>>> + DT_UNIPHY1_NSS_TX_CLK,
>>> + DT_UNIPHY2_NSS_RX_CLK,
>>> + DT_UNIPHY2_NSS_TX_CLK,
>>> + DT_XO,
>>
>> As I wrote, please move DT_XO closer to the beginning of the list.
>>
>>> +};
>>> +
>>> +enum {
>>> + P_BIAS_PLL_CC_CLK,
>>> + P_BIAS_PLL_NSS_NOC_CLK,
>>> + P_BIAS_PLL_UBI_NC_CLK,
>>> + P_GCC_GPLL0_OUT_AUX,
>>> + P_UBI32_PLL_OUT_MAIN,
>>> + P_UNIPHY0_NSS_RX_CLK,
>>> + P_UNIPHY0_NSS_TX_CLK,
>>> + P_UNIPHY1_NSS_RX_CLK,
>>> + P_UNIPHY1_NSS_TX_CLK,
>>> + P_UNIPHY2_NSS_RX_CLK,
>>> + P_UNIPHY2_NSS_TX_CLK,
>>> + P_XO,
>>> +};
>>> +
>>> +static const struct alpha_pll_config ubi32_pll_config = {
>>> + .l = 0x3e,
>>> + .alpha = 0x6666,
>>> + .config_ctl_val = 0x200d4aa8,
>>> + .config_ctl_hi_val = 0x3c,
>>> + .main_output_mask = BIT(0),
>>> + .aux_output_mask = BIT(1),
>>> + .pre_div_val = 0x0,
>>> + .pre_div_mask = BIT(12),
>>> + .post_div_val = 0x0,
>>> + .post_div_mask = GENMASK(9, 8),
>>> + .alpha_en_mask = BIT(24),
>>> + .test_ctl_val = 0x1c0000c0,
>>> + .test_ctl_hi_val = 0x4000,
>>> +};
>>> +
>>> +static struct clk_alpha_pll ubi32_pll_main = {
>>> + .offset = 0x28000,
>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
>>> + .clkr = {
>>> + .hw.init = &(const struct clk_init_data) {
>>> + .name = "ubi32_pll_main",
>>> + .parent_data = &(const struct clk_parent_data) {
>>> + .index = DT_XO,
>>> + },
>>> + .num_parents = 1,
>>> + .ops = &clk_alpha_pll_huayra_ops,
>>> + },
>>> + },
>>> +};
>>> +
>>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>>> + .offset = 0x28000,
>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>> + .width = 2,
>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>> + .name = "ubi32_pll",
>>> + .parent_hws = (const struct clk_hw *[]) {
>>> + &ubi32_pll_main.clkr.hw
>>> + },
>>> + .num_parents = 1,
>>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
>>> + .flags = CLK_SET_RATE_PARENT,
>>> + },
>>> +};
>>> +
>>
>> [skipped clock tables, LGTM]
>>
>>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
>>> + { .compatible = "qcom,ipq9574-nsscc" },
>>> + { }
>>> +};
>>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
>>> +
>>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>>> +{
>>> + struct regmap *regmap;
>>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>>> +
>>> + int ret;
>>> +
>>> + ret = devm_pm_runtime_enable(&pdev->dev);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + ret = devm_pm_clk_create(&pdev->dev);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>>
>> As we are switching to DT indices, better add new API that takes index
>> rather than mixing indices and names.
> sure okay
>
> Thanks,
> Devi Priya
>>
>>> + if (ret < 0) {
>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc
>>> clock\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
>>> + if (ret < 0) {
>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc
>>> clock\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
>>> + if (ret < 0) {
>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1
>>> clock\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = pm_runtime_get(&pdev->dev);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>>> + if (IS_ERR(regmap))
>>> + return PTR_ERR(regmap);
>>> +
>>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap,
>>> &ubi32_pll_config);
>>> +
>>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
>>> +}
>>> +
>>> +static const struct dev_pm_ops nss_cc_pm_ops = {
>>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
>>> +};
>>> +
>>> +static struct platform_driver nss_cc_ipq9574_driver = {
>>> + .probe = nss_cc_ipq9574_probe,
>>> + .driver = {
>>> + .name = "qcom,nsscc-ipq9574",
>>> + .of_match_table = nss_cc_ipq9574_match_table,
>>> + .pm = &nss_cc_pm_ops,
>>> + },
>>> +};
>>> +
>>> +module_platform_driver(nss_cc_ipq9574_driver);
>>> +
>>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>>> +MODULE_LICENSE("GPL");
>>> --
>>> 2.34.1
>>>
>>
>>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-09-20 6:39 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-09-20 6:39 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 9/12/2023 7:38 PM, Devi Priya wrote:
>
>
> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>> wrote:
>>>
>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>> based
>>> devices.
>>>
>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>> ---
>>> Changes in V2:
>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>> - Added module_platform_driver
>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>> clocks as critical
>>> & added pm_clk for nssnoc clocks
>>> - Updated the uniphy clock names
>>>
>>> drivers/clk/qcom/Kconfig | 7 +
>>> drivers/clk/qcom/Makefile | 1 +
>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
>>> 3 files changed, 3117 insertions(+)
>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>
>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>> --- a/drivers/clk/qcom/Kconfig
>>> +++ b/drivers/clk/qcom/Kconfig
>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>> of ipq9574.
>>>
>>> +config IPQ_NSSCC_9574
>>> + tristate "IPQ9574 NSS Clock Controller"
>>> + depends on ARM64 || COMPILE_TEST
>>> + depends on IPQ_GCC_9574
>>> + help
>>> + Support for NSS clock controller on ipq9574 devices.
>>> +
>>> config MSM_GCC_8660
>>> tristate "MSM8660 Global Clock Controller"
>>> depends on ARM || COMPILE_TEST
>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>> index 4790c8cca426..3f084928962e 100644
>>> --- a/drivers/clk/qcom/Makefile
>>> +++ b/drivers/clk/qcom/Makefile
>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>> new file mode 100644
>>> index 000000000000..65bdb449ae5f
>>> --- /dev/null
>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>> @@ -0,0 +1,3109 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>> reserved.
>>> + */
>>> +
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/err.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/pm_clock.h>
>>> +#include <linux/pm_runtime.h>
>>> +
>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>> +
>>> +#include "clk-alpha-pll.h"
>>> +#include "clk-branch.h"
>>> +#include "clk-pll.h"
>>> +#include "clk-rcg.h"
>>> +#include "clk-regmap.h"
>>> +#include "clk-regmap-divider.h"
>>> +#include "clk-regmap-mux.h"
>>> +#include "common.h"
>>> +#include "reset.h"
>>> +
>>> +/* Need to match the order of clocks in DT binding */
>>> +enum {
>>> + DT_NSSNOC_NSSCC_CLK,
>>> + DT_NSSNOC_SNOC_CLK,
>>> + DT_NSSNOC_SNOC_1_CLK,
>>
>> Not using the index makes it seem that these clocks are not used,
>> until one scrolls down to pm_clks.
> Okay, got it
>>
>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>> here (not a simple NIU).
>
> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
> unblock PCIe/NSS changes getting merged, shall we use regmap_update_bits
> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
> probe function of the gcc driver itself as like sm8550 driver to get the
> changes merged?
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
Hi Dmitry,
Just curious to know if we could send out the next series with the
proposed approach if that holds good.
Thanks,
Devi Priya
>>
>>> + DT_BIAS_PLL_CC_CLK,
>>> + DT_BIAS_PLL_NSS_NOC_CLK,
>>> + DT_BIAS_PLL_UBI_NC_CLK,
>>> + DT_GCC_GPLL0_OUT_AUX,
>>> + DT_UNIPHY0_NSS_RX_CLK,
>>> + DT_UNIPHY0_NSS_TX_CLK,
>>> + DT_UNIPHY1_NSS_RX_CLK,
>>> + DT_UNIPHY1_NSS_TX_CLK,
>>> + DT_UNIPHY2_NSS_RX_CLK,
>>> + DT_UNIPHY2_NSS_TX_CLK,
>>> + DT_XO,
>>
>> As I wrote, please move DT_XO closer to the beginning of the list.
>>
>>> +};
>>> +
>>> +enum {
>>> + P_BIAS_PLL_CC_CLK,
>>> + P_BIAS_PLL_NSS_NOC_CLK,
>>> + P_BIAS_PLL_UBI_NC_CLK,
>>> + P_GCC_GPLL0_OUT_AUX,
>>> + P_UBI32_PLL_OUT_MAIN,
>>> + P_UNIPHY0_NSS_RX_CLK,
>>> + P_UNIPHY0_NSS_TX_CLK,
>>> + P_UNIPHY1_NSS_RX_CLK,
>>> + P_UNIPHY1_NSS_TX_CLK,
>>> + P_UNIPHY2_NSS_RX_CLK,
>>> + P_UNIPHY2_NSS_TX_CLK,
>>> + P_XO,
>>> +};
>>> +
>>> +static const struct alpha_pll_config ubi32_pll_config = {
>>> + .l = 0x3e,
>>> + .alpha = 0x6666,
>>> + .config_ctl_val = 0x200d4aa8,
>>> + .config_ctl_hi_val = 0x3c,
>>> + .main_output_mask = BIT(0),
>>> + .aux_output_mask = BIT(1),
>>> + .pre_div_val = 0x0,
>>> + .pre_div_mask = BIT(12),
>>> + .post_div_val = 0x0,
>>> + .post_div_mask = GENMASK(9, 8),
>>> + .alpha_en_mask = BIT(24),
>>> + .test_ctl_val = 0x1c0000c0,
>>> + .test_ctl_hi_val = 0x4000,
>>> +};
>>> +
>>> +static struct clk_alpha_pll ubi32_pll_main = {
>>> + .offset = 0x28000,
>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
>>> + .clkr = {
>>> + .hw.init = &(const struct clk_init_data) {
>>> + .name = "ubi32_pll_main",
>>> + .parent_data = &(const struct clk_parent_data) {
>>> + .index = DT_XO,
>>> + },
>>> + .num_parents = 1,
>>> + .ops = &clk_alpha_pll_huayra_ops,
>>> + },
>>> + },
>>> +};
>>> +
>>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>>> + .offset = 0x28000,
>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>> + .width = 2,
>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>> + .name = "ubi32_pll",
>>> + .parent_hws = (const struct clk_hw *[]) {
>>> + &ubi32_pll_main.clkr.hw
>>> + },
>>> + .num_parents = 1,
>>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
>>> + .flags = CLK_SET_RATE_PARENT,
>>> + },
>>> +};
>>> +
>>
>> [skipped clock tables, LGTM]
>>
>>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
>>> + { .compatible = "qcom,ipq9574-nsscc" },
>>> + { }
>>> +};
>>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
>>> +
>>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>>> +{
>>> + struct regmap *regmap;
>>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>>> +
>>> + int ret;
>>> +
>>> + ret = devm_pm_runtime_enable(&pdev->dev);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + ret = devm_pm_clk_create(&pdev->dev);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>>
>> As we are switching to DT indices, better add new API that takes index
>> rather than mixing indices and names.
> sure okay
>
> Thanks,
> Devi Priya
>>
>>> + if (ret < 0) {
>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc
>>> clock\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
>>> + if (ret < 0) {
>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc
>>> clock\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
>>> + if (ret < 0) {
>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1
>>> clock\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = pm_runtime_get(&pdev->dev);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>>> + if (IS_ERR(regmap))
>>> + return PTR_ERR(regmap);
>>> +
>>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap,
>>> &ubi32_pll_config);
>>> +
>>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
>>> +}
>>> +
>>> +static const struct dev_pm_ops nss_cc_pm_ops = {
>>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
>>> +};
>>> +
>>> +static struct platform_driver nss_cc_ipq9574_driver = {
>>> + .probe = nss_cc_ipq9574_probe,
>>> + .driver = {
>>> + .name = "qcom,nsscc-ipq9574",
>>> + .of_match_table = nss_cc_ipq9574_match_table,
>>> + .pm = &nss_cc_pm_ops,
>>> + },
>>> +};
>>> +
>>> +module_platform_driver(nss_cc_ipq9574_driver);
>>> +
>>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>>> +MODULE_LICENSE("GPL");
>>> --
>>> 2.34.1
>>>
>>
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-09-20 6:39 ` Devi Priya
@ 2023-09-20 8:20 ` Dmitry Baryshkov
-1 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-09-20 8:20 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
>
>
> On 9/12/2023 7:38 PM, Devi Priya wrote:
> >
> >
> > On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
> >> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
> >> wrote:
> >>>
> >>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
> >>> based
> >>> devices.
> >>>
> >>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> >>> ---
> >>> Changes in V2:
> >>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
> >>> - Added module_platform_driver
> >>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
> >>> clocks as critical
> >>> & added pm_clk for nssnoc clocks
> >>> - Updated the uniphy clock names
> >>>
> >>> drivers/clk/qcom/Kconfig | 7 +
> >>> drivers/clk/qcom/Makefile | 1 +
> >>> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
> >>> 3 files changed, 3117 insertions(+)
> >>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
> >>>
> >>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >>> index bd9bfb11b328..3ecc11e2c8e3 100644
> >>> --- a/drivers/clk/qcom/Kconfig
> >>> +++ b/drivers/clk/qcom/Kconfig
> >>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
> >>> i2c, USB, SD/eMMC, etc. Select this for the root clock
> >>> of ipq9574.
> >>>
> >>> +config IPQ_NSSCC_9574
> >>> + tristate "IPQ9574 NSS Clock Controller"
> >>> + depends on ARM64 || COMPILE_TEST
> >>> + depends on IPQ_GCC_9574
> >>> + help
> >>> + Support for NSS clock controller on ipq9574 devices.
> >>> +
> >>> config MSM_GCC_8660
> >>> tristate "MSM8660 Global Clock Controller"
> >>> depends on ARM || COMPILE_TEST
> >>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >>> index 4790c8cca426..3f084928962e 100644
> >>> --- a/drivers/clk/qcom/Makefile
> >>> +++ b/drivers/clk/qcom/Makefile
> >>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> >>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> >>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> >>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
> >>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
> >>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> >>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
> >>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> >>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
> >>> b/drivers/clk/qcom/nsscc-ipq9574.c
> >>> new file mode 100644
> >>> index 000000000000..65bdb449ae5f
> >>> --- /dev/null
> >>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
> >>> @@ -0,0 +1,3109 @@
> >>> +// SPDX-License-Identifier: GPL-2.0-only
> >>> +/*
> >>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> >>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
> >>> reserved.
> >>> + */
> >>> +
> >>> +#include <linux/clk-provider.h>
> >>> +#include <linux/err.h>
> >>> +#include <linux/kernel.h>
> >>> +#include <linux/module.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/of_device.h>
> >>> +#include <linux/regmap.h>
> >>> +#include <linux/pm_clock.h>
> >>> +#include <linux/pm_runtime.h>
> >>> +
> >>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> >>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> >>> +
> >>> +#include "clk-alpha-pll.h"
> >>> +#include "clk-branch.h"
> >>> +#include "clk-pll.h"
> >>> +#include "clk-rcg.h"
> >>> +#include "clk-regmap.h"
> >>> +#include "clk-regmap-divider.h"
> >>> +#include "clk-regmap-mux.h"
> >>> +#include "common.h"
> >>> +#include "reset.h"
> >>> +
> >>> +/* Need to match the order of clocks in DT binding */
> >>> +enum {
> >>> + DT_NSSNOC_NSSCC_CLK,
> >>> + DT_NSSNOC_SNOC_CLK,
> >>> + DT_NSSNOC_SNOC_1_CLK,
> >>
> >> Not using the index makes it seem that these clocks are not used,
> >> until one scrolls down to pm_clks.
> > Okay, got it
> >>
> >> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
> >> here (not a simple NIU).
> >
> > Hi Dmitry, We are exploring on the ICC driver. In the meantime to
> > unblock PCIe/NSS changes getting merged, shall we use regmap_update_bits
> > and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
> > probe function of the gcc driver itself as like sm8550 driver to get the
> > changes merged?
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>
> Hi Dmitry,
> Just curious to know if we could send out the next series with the
> proposed approach if that holds good.
The answer really depends on the structure of your hardware. The issue
is that once you commit the device bindings,you have to support them
forever. So, if you commit the NSS clock support without interconnects
in place, you have to keep this ANOC/SNOC/etc code forever, even after
you land the interconnect. So I'd suggest landing the icc driver first
(or at least implementing and sending to the mailing list), so that we
can see how all these pieces fit together.
> Thanks,
> Devi Priya
>
> >>
> >>> + DT_BIAS_PLL_CC_CLK,
> >>> + DT_BIAS_PLL_NSS_NOC_CLK,
> >>> + DT_BIAS_PLL_UBI_NC_CLK,
> >>> + DT_GCC_GPLL0_OUT_AUX,
> >>> + DT_UNIPHY0_NSS_RX_CLK,
> >>> + DT_UNIPHY0_NSS_TX_CLK,
> >>> + DT_UNIPHY1_NSS_RX_CLK,
> >>> + DT_UNIPHY1_NSS_TX_CLK,
> >>> + DT_UNIPHY2_NSS_RX_CLK,
> >>> + DT_UNIPHY2_NSS_TX_CLK,
> >>> + DT_XO,
> >>
> >> As I wrote, please move DT_XO closer to the beginning of the list.
> >>
> >>> +};
> >>> +
> >>> +enum {
> >>> + P_BIAS_PLL_CC_CLK,
> >>> + P_BIAS_PLL_NSS_NOC_CLK,
> >>> + P_BIAS_PLL_UBI_NC_CLK,
> >>> + P_GCC_GPLL0_OUT_AUX,
> >>> + P_UBI32_PLL_OUT_MAIN,
> >>> + P_UNIPHY0_NSS_RX_CLK,
> >>> + P_UNIPHY0_NSS_TX_CLK,
> >>> + P_UNIPHY1_NSS_RX_CLK,
> >>> + P_UNIPHY1_NSS_TX_CLK,
> >>> + P_UNIPHY2_NSS_RX_CLK,
> >>> + P_UNIPHY2_NSS_TX_CLK,
> >>> + P_XO,
> >>> +};
> >>> +
> >>> +static const struct alpha_pll_config ubi32_pll_config = {
> >>> + .l = 0x3e,
> >>> + .alpha = 0x6666,
> >>> + .config_ctl_val = 0x200d4aa8,
> >>> + .config_ctl_hi_val = 0x3c,
> >>> + .main_output_mask = BIT(0),
> >>> + .aux_output_mask = BIT(1),
> >>> + .pre_div_val = 0x0,
> >>> + .pre_div_mask = BIT(12),
> >>> + .post_div_val = 0x0,
> >>> + .post_div_mask = GENMASK(9, 8),
> >>> + .alpha_en_mask = BIT(24),
> >>> + .test_ctl_val = 0x1c0000c0,
> >>> + .test_ctl_hi_val = 0x4000,
> >>> +};
> >>> +
> >>> +static struct clk_alpha_pll ubi32_pll_main = {
> >>> + .offset = 0x28000,
> >>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
> >>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
> >>> + .clkr = {
> >>> + .hw.init = &(const struct clk_init_data) {
> >>> + .name = "ubi32_pll_main",
> >>> + .parent_data = &(const struct clk_parent_data) {
> >>> + .index = DT_XO,
> >>> + },
> >>> + .num_parents = 1,
> >>> + .ops = &clk_alpha_pll_huayra_ops,
> >>> + },
> >>> + },
> >>> +};
> >>> +
> >>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
> >>> + .offset = 0x28000,
> >>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
> >>> + .width = 2,
> >>> + .clkr.hw.init = &(const struct clk_init_data) {
> >>> + .name = "ubi32_pll",
> >>> + .parent_hws = (const struct clk_hw *[]) {
> >>> + &ubi32_pll_main.clkr.hw
> >>> + },
> >>> + .num_parents = 1,
> >>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> >>> + .flags = CLK_SET_RATE_PARENT,
> >>> + },
> >>> +};
> >>> +
> >>
> >> [skipped clock tables, LGTM]
> >>
> >>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
> >>> + { .compatible = "qcom,ipq9574-nsscc" },
> >>> + { }
> >>> +};
> >>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
> >>> +
> >>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
> >>> +{
> >>> + struct regmap *regmap;
> >>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
> >>> +
> >>> + int ret;
> >>> +
> >>> + ret = devm_pm_runtime_enable(&pdev->dev);
> >>> + if (ret < 0)
> >>> + return ret;
> >>> +
> >>> + ret = devm_pm_clk_create(&pdev->dev);
> >>> + if (ret < 0)
> >>> + return ret;
> >>> +
> >>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
> >>
> >> As we are switching to DT indices, better add new API that takes index
> >> rather than mixing indices and names.
> > sure okay
> >
> > Thanks,
> > Devi Priya
> >>
> >>> + if (ret < 0) {
> >>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc
> >>> clock\n");
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
> >>> + if (ret < 0) {
> >>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc
> >>> clock\n");
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
> >>> + if (ret < 0) {
> >>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1
> >>> clock\n");
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = pm_runtime_get(&pdev->dev);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
> >>> + if (IS_ERR(regmap))
> >>> + return PTR_ERR(regmap);
> >>> +
> >>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap,
> >>> &ubi32_pll_config);
> >>> +
> >>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
> >>> +}
> >>> +
> >>> +static const struct dev_pm_ops nss_cc_pm_ops = {
> >>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
> >>> +};
> >>> +
> >>> +static struct platform_driver nss_cc_ipq9574_driver = {
> >>> + .probe = nss_cc_ipq9574_probe,
> >>> + .driver = {
> >>> + .name = "qcom,nsscc-ipq9574",
> >>> + .of_match_table = nss_cc_ipq9574_match_table,
> >>> + .pm = &nss_cc_pm_ops,
> >>> + },
> >>> +};
> >>> +
> >>> +module_platform_driver(nss_cc_ipq9574_driver);
> >>> +
> >>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
> >>> +MODULE_LICENSE("GPL");
> >>> --
> >>> 2.34.1
> >>>
> >>
> >>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-09-20 8:20 ` Dmitry Baryshkov
0 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-09-20 8:20 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
>
>
> On 9/12/2023 7:38 PM, Devi Priya wrote:
> >
> >
> > On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
> >> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
> >> wrote:
> >>>
> >>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
> >>> based
> >>> devices.
> >>>
> >>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> >>> ---
> >>> Changes in V2:
> >>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
> >>> - Added module_platform_driver
> >>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
> >>> clocks as critical
> >>> & added pm_clk for nssnoc clocks
> >>> - Updated the uniphy clock names
> >>>
> >>> drivers/clk/qcom/Kconfig | 7 +
> >>> drivers/clk/qcom/Makefile | 1 +
> >>> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
> >>> 3 files changed, 3117 insertions(+)
> >>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
> >>>
> >>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >>> index bd9bfb11b328..3ecc11e2c8e3 100644
> >>> --- a/drivers/clk/qcom/Kconfig
> >>> +++ b/drivers/clk/qcom/Kconfig
> >>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
> >>> i2c, USB, SD/eMMC, etc. Select this for the root clock
> >>> of ipq9574.
> >>>
> >>> +config IPQ_NSSCC_9574
> >>> + tristate "IPQ9574 NSS Clock Controller"
> >>> + depends on ARM64 || COMPILE_TEST
> >>> + depends on IPQ_GCC_9574
> >>> + help
> >>> + Support for NSS clock controller on ipq9574 devices.
> >>> +
> >>> config MSM_GCC_8660
> >>> tristate "MSM8660 Global Clock Controller"
> >>> depends on ARM || COMPILE_TEST
> >>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >>> index 4790c8cca426..3f084928962e 100644
> >>> --- a/drivers/clk/qcom/Makefile
> >>> +++ b/drivers/clk/qcom/Makefile
> >>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> >>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> >>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> >>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
> >>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
> >>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> >>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
> >>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> >>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
> >>> b/drivers/clk/qcom/nsscc-ipq9574.c
> >>> new file mode 100644
> >>> index 000000000000..65bdb449ae5f
> >>> --- /dev/null
> >>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
> >>> @@ -0,0 +1,3109 @@
> >>> +// SPDX-License-Identifier: GPL-2.0-only
> >>> +/*
> >>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> >>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
> >>> reserved.
> >>> + */
> >>> +
> >>> +#include <linux/clk-provider.h>
> >>> +#include <linux/err.h>
> >>> +#include <linux/kernel.h>
> >>> +#include <linux/module.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/of_device.h>
> >>> +#include <linux/regmap.h>
> >>> +#include <linux/pm_clock.h>
> >>> +#include <linux/pm_runtime.h>
> >>> +
> >>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> >>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> >>> +
> >>> +#include "clk-alpha-pll.h"
> >>> +#include "clk-branch.h"
> >>> +#include "clk-pll.h"
> >>> +#include "clk-rcg.h"
> >>> +#include "clk-regmap.h"
> >>> +#include "clk-regmap-divider.h"
> >>> +#include "clk-regmap-mux.h"
> >>> +#include "common.h"
> >>> +#include "reset.h"
> >>> +
> >>> +/* Need to match the order of clocks in DT binding */
> >>> +enum {
> >>> + DT_NSSNOC_NSSCC_CLK,
> >>> + DT_NSSNOC_SNOC_CLK,
> >>> + DT_NSSNOC_SNOC_1_CLK,
> >>
> >> Not using the index makes it seem that these clocks are not used,
> >> until one scrolls down to pm_clks.
> > Okay, got it
> >>
> >> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
> >> here (not a simple NIU).
> >
> > Hi Dmitry, We are exploring on the ICC driver. In the meantime to
> > unblock PCIe/NSS changes getting merged, shall we use regmap_update_bits
> > and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
> > probe function of the gcc driver itself as like sm8550 driver to get the
> > changes merged?
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>
> Hi Dmitry,
> Just curious to know if we could send out the next series with the
> proposed approach if that holds good.
The answer really depends on the structure of your hardware. The issue
is that once you commit the device bindings,you have to support them
forever. So, if you commit the NSS clock support without interconnects
in place, you have to keep this ANOC/SNOC/etc code forever, even after
you land the interconnect. So I'd suggest landing the icc driver first
(or at least implementing and sending to the mailing list), so that we
can see how all these pieces fit together.
> Thanks,
> Devi Priya
>
> >>
> >>> + DT_BIAS_PLL_CC_CLK,
> >>> + DT_BIAS_PLL_NSS_NOC_CLK,
> >>> + DT_BIAS_PLL_UBI_NC_CLK,
> >>> + DT_GCC_GPLL0_OUT_AUX,
> >>> + DT_UNIPHY0_NSS_RX_CLK,
> >>> + DT_UNIPHY0_NSS_TX_CLK,
> >>> + DT_UNIPHY1_NSS_RX_CLK,
> >>> + DT_UNIPHY1_NSS_TX_CLK,
> >>> + DT_UNIPHY2_NSS_RX_CLK,
> >>> + DT_UNIPHY2_NSS_TX_CLK,
> >>> + DT_XO,
> >>
> >> As I wrote, please move DT_XO closer to the beginning of the list.
> >>
> >>> +};
> >>> +
> >>> +enum {
> >>> + P_BIAS_PLL_CC_CLK,
> >>> + P_BIAS_PLL_NSS_NOC_CLK,
> >>> + P_BIAS_PLL_UBI_NC_CLK,
> >>> + P_GCC_GPLL0_OUT_AUX,
> >>> + P_UBI32_PLL_OUT_MAIN,
> >>> + P_UNIPHY0_NSS_RX_CLK,
> >>> + P_UNIPHY0_NSS_TX_CLK,
> >>> + P_UNIPHY1_NSS_RX_CLK,
> >>> + P_UNIPHY1_NSS_TX_CLK,
> >>> + P_UNIPHY2_NSS_RX_CLK,
> >>> + P_UNIPHY2_NSS_TX_CLK,
> >>> + P_XO,
> >>> +};
> >>> +
> >>> +static const struct alpha_pll_config ubi32_pll_config = {
> >>> + .l = 0x3e,
> >>> + .alpha = 0x6666,
> >>> + .config_ctl_val = 0x200d4aa8,
> >>> + .config_ctl_hi_val = 0x3c,
> >>> + .main_output_mask = BIT(0),
> >>> + .aux_output_mask = BIT(1),
> >>> + .pre_div_val = 0x0,
> >>> + .pre_div_mask = BIT(12),
> >>> + .post_div_val = 0x0,
> >>> + .post_div_mask = GENMASK(9, 8),
> >>> + .alpha_en_mask = BIT(24),
> >>> + .test_ctl_val = 0x1c0000c0,
> >>> + .test_ctl_hi_val = 0x4000,
> >>> +};
> >>> +
> >>> +static struct clk_alpha_pll ubi32_pll_main = {
> >>> + .offset = 0x28000,
> >>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
> >>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
> >>> + .clkr = {
> >>> + .hw.init = &(const struct clk_init_data) {
> >>> + .name = "ubi32_pll_main",
> >>> + .parent_data = &(const struct clk_parent_data) {
> >>> + .index = DT_XO,
> >>> + },
> >>> + .num_parents = 1,
> >>> + .ops = &clk_alpha_pll_huayra_ops,
> >>> + },
> >>> + },
> >>> +};
> >>> +
> >>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
> >>> + .offset = 0x28000,
> >>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
> >>> + .width = 2,
> >>> + .clkr.hw.init = &(const struct clk_init_data) {
> >>> + .name = "ubi32_pll",
> >>> + .parent_hws = (const struct clk_hw *[]) {
> >>> + &ubi32_pll_main.clkr.hw
> >>> + },
> >>> + .num_parents = 1,
> >>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> >>> + .flags = CLK_SET_RATE_PARENT,
> >>> + },
> >>> +};
> >>> +
> >>
> >> [skipped clock tables, LGTM]
> >>
> >>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
> >>> + { .compatible = "qcom,ipq9574-nsscc" },
> >>> + { }
> >>> +};
> >>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
> >>> +
> >>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
> >>> +{
> >>> + struct regmap *regmap;
> >>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
> >>> +
> >>> + int ret;
> >>> +
> >>> + ret = devm_pm_runtime_enable(&pdev->dev);
> >>> + if (ret < 0)
> >>> + return ret;
> >>> +
> >>> + ret = devm_pm_clk_create(&pdev->dev);
> >>> + if (ret < 0)
> >>> + return ret;
> >>> +
> >>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
> >>
> >> As we are switching to DT indices, better add new API that takes index
> >> rather than mixing indices and names.
> > sure okay
> >
> > Thanks,
> > Devi Priya
> >>
> >>> + if (ret < 0) {
> >>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc
> >>> clock\n");
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
> >>> + if (ret < 0) {
> >>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc
> >>> clock\n");
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
> >>> + if (ret < 0) {
> >>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1
> >>> clock\n");
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = pm_runtime_get(&pdev->dev);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
> >>> + if (IS_ERR(regmap))
> >>> + return PTR_ERR(regmap);
> >>> +
> >>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap,
> >>> &ubi32_pll_config);
> >>> +
> >>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
> >>> +}
> >>> +
> >>> +static const struct dev_pm_ops nss_cc_pm_ops = {
> >>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
> >>> +};
> >>> +
> >>> +static struct platform_driver nss_cc_ipq9574_driver = {
> >>> + .probe = nss_cc_ipq9574_probe,
> >>> + .driver = {
> >>> + .name = "qcom,nsscc-ipq9574",
> >>> + .of_match_table = nss_cc_ipq9574_match_table,
> >>> + .pm = &nss_cc_pm_ops,
> >>> + },
> >>> +};
> >>> +
> >>> +module_platform_driver(nss_cc_ipq9574_driver);
> >>> +
> >>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
> >>> +MODULE_LICENSE("GPL");
> >>> --
> >>> 2.34.1
> >>>
> >>
> >>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-09-20 8:20 ` Dmitry Baryshkov
@ 2023-09-22 12:01 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-09-22 12:01 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>>
>>
>> On 9/12/2023 7:38 PM, Devi Priya wrote:
>>>
>>>
>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>>>> wrote:
>>>>>
>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>>>> based
>>>>> devices.
>>>>>
>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>>> ---
>>>>> Changes in V2:
>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>>>> - Added module_platform_driver
>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>>>> clocks as critical
>>>>> & added pm_clk for nssnoc clocks
>>>>> - Updated the uniphy clock names
>>>>>
>>>>> drivers/clk/qcom/Kconfig | 7 +
>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
>>>>> 3 files changed, 3117 insertions(+)
>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>>>
>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>>>> --- a/drivers/clk/qcom/Kconfig
>>>>> +++ b/drivers/clk/qcom/Kconfig
>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>>>> of ipq9574.
>>>>>
>>>>> +config IPQ_NSSCC_9574
>>>>> + tristate "IPQ9574 NSS Clock Controller"
>>>>> + depends on ARM64 || COMPILE_TEST
>>>>> + depends on IPQ_GCC_9574
>>>>> + help
>>>>> + Support for NSS clock controller on ipq9574 devices.
>>>>> +
>>>>> config MSM_GCC_8660
>>>>> tristate "MSM8660 Global Clock Controller"
>>>>> depends on ARM || COMPILE_TEST
>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>>> index 4790c8cca426..3f084928962e 100644
>>>>> --- a/drivers/clk/qcom/Makefile
>>>>> +++ b/drivers/clk/qcom/Makefile
>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>> new file mode 100644
>>>>> index 000000000000..65bdb449ae5f
>>>>> --- /dev/null
>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>> @@ -0,0 +1,3109 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>> +/*
>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>>>> reserved.
>>>>> + */
>>>>> +
>>>>> +#include <linux/clk-provider.h>
>>>>> +#include <linux/err.h>
>>>>> +#include <linux/kernel.h>
>>>>> +#include <linux/module.h>
>>>>> +#include <linux/of.h>
>>>>> +#include <linux/of_device.h>
>>>>> +#include <linux/regmap.h>
>>>>> +#include <linux/pm_clock.h>
>>>>> +#include <linux/pm_runtime.h>
>>>>> +
>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>>>> +
>>>>> +#include "clk-alpha-pll.h"
>>>>> +#include "clk-branch.h"
>>>>> +#include "clk-pll.h"
>>>>> +#include "clk-rcg.h"
>>>>> +#include "clk-regmap.h"
>>>>> +#include "clk-regmap-divider.h"
>>>>> +#include "clk-regmap-mux.h"
>>>>> +#include "common.h"
>>>>> +#include "reset.h"
>>>>> +
>>>>> +/* Need to match the order of clocks in DT binding */
>>>>> +enum {
>>>>> + DT_NSSNOC_NSSCC_CLK,
>>>>> + DT_NSSNOC_SNOC_CLK,
>>>>> + DT_NSSNOC_SNOC_1_CLK,
>>>>
>>>> Not using the index makes it seem that these clocks are not used,
>>>> until one scrolls down to pm_clks.
>>> Okay, got it
>>>>
>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>>>> here (not a simple NIU).
>>>
>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
>>> unblock PCIe/NSS changes getting merged, shall we use regmap_update_bits
>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
>>> probe function of the gcc driver itself as like sm8550 driver to get the
>>> changes merged?
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>>
>> Hi Dmitry,
>> Just curious to know if we could send out the next series with the
>> proposed approach if that holds good.
>
> The answer really depends on the structure of your hardware. The issue
> is that once you commit the device bindings,you have to support them
> forever. So, if you commit the NSS clock support without interconnects
> in place, you have to keep this ANOC/SNOC/etc code forever, even after
> you land the interconnect. So I'd suggest landing the icc driver first
> (or at least implementing and sending to the mailing list), so that we
> can see how all these pieces fit together.
Hi Dmitry,
Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
NOC clocks have to be scaled. So if these clocks can be enabled in the
probe, there is no need for an interconnect driver at all. The same
applies to both ipq9574 and ipq5332 SoCs.
Thanks,
Devi Priya
>
>> Thanks,
>> Devi Priya
>>
>>>>
>>>>> + DT_BIAS_PLL_CC_CLK,
>>>>> + DT_BIAS_PLL_NSS_NOC_CLK,
>>>>> + DT_BIAS_PLL_UBI_NC_CLK,
>>>>> + DT_GCC_GPLL0_OUT_AUX,
>>>>> + DT_UNIPHY0_NSS_RX_CLK,
>>>>> + DT_UNIPHY0_NSS_TX_CLK,
>>>>> + DT_UNIPHY1_NSS_RX_CLK,
>>>>> + DT_UNIPHY1_NSS_TX_CLK,
>>>>> + DT_UNIPHY2_NSS_RX_CLK,
>>>>> + DT_UNIPHY2_NSS_TX_CLK,
>>>>> + DT_XO,
>>>>
>>>> As I wrote, please move DT_XO closer to the beginning of the list.
>>>>
>>>>> +};
>>>>> +
>>>>> +enum {
>>>>> + P_BIAS_PLL_CC_CLK,
>>>>> + P_BIAS_PLL_NSS_NOC_CLK,
>>>>> + P_BIAS_PLL_UBI_NC_CLK,
>>>>> + P_GCC_GPLL0_OUT_AUX,
>>>>> + P_UBI32_PLL_OUT_MAIN,
>>>>> + P_UNIPHY0_NSS_RX_CLK,
>>>>> + P_UNIPHY0_NSS_TX_CLK,
>>>>> + P_UNIPHY1_NSS_RX_CLK,
>>>>> + P_UNIPHY1_NSS_TX_CLK,
>>>>> + P_UNIPHY2_NSS_RX_CLK,
>>>>> + P_UNIPHY2_NSS_TX_CLK,
>>>>> + P_XO,
>>>>> +};
>>>>> +
>>>>> +static const struct alpha_pll_config ubi32_pll_config = {
>>>>> + .l = 0x3e,
>>>>> + .alpha = 0x6666,
>>>>> + .config_ctl_val = 0x200d4aa8,
>>>>> + .config_ctl_hi_val = 0x3c,
>>>>> + .main_output_mask = BIT(0),
>>>>> + .aux_output_mask = BIT(1),
>>>>> + .pre_div_val = 0x0,
>>>>> + .pre_div_mask = BIT(12),
>>>>> + .post_div_val = 0x0,
>>>>> + .post_div_mask = GENMASK(9, 8),
>>>>> + .alpha_en_mask = BIT(24),
>>>>> + .test_ctl_val = 0x1c0000c0,
>>>>> + .test_ctl_hi_val = 0x4000,
>>>>> +};
>>>>> +
>>>>> +static struct clk_alpha_pll ubi32_pll_main = {
>>>>> + .offset = 0x28000,
>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>>>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
>>>>> + .clkr = {
>>>>> + .hw.init = &(const struct clk_init_data) {
>>>>> + .name = "ubi32_pll_main",
>>>>> + .parent_data = &(const struct clk_parent_data) {
>>>>> + .index = DT_XO,
>>>>> + },
>>>>> + .num_parents = 1,
>>>>> + .ops = &clk_alpha_pll_huayra_ops,
>>>>> + },
>>>>> + },
>>>>> +};
>>>>> +
>>>>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>>>>> + .offset = 0x28000,
>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>>>> + .width = 2,
>>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>>> + .name = "ubi32_pll",
>>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>>> + &ubi32_pll_main.clkr.hw
>>>>> + },
>>>>> + .num_parents = 1,
>>>>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
>>>>> + .flags = CLK_SET_RATE_PARENT,
>>>>> + },
>>>>> +};
>>>>> +
>>>>
>>>> [skipped clock tables, LGTM]
>>>>
>>>>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
>>>>> + { .compatible = "qcom,ipq9574-nsscc" },
>>>>> + { }
>>>>> +};
>>>>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
>>>>> +
>>>>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>>>>> +{
>>>>> + struct regmap *regmap;
>>>>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>>>>> +
>>>>> + int ret;
>>>>> +
>>>>> + ret = devm_pm_runtime_enable(&pdev->dev);
>>>>> + if (ret < 0)
>>>>> + return ret;
>>>>> +
>>>>> + ret = devm_pm_clk_create(&pdev->dev);
>>>>> + if (ret < 0)
>>>>> + return ret;
>>>>> +
>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>>>>
>>>> As we are switching to DT indices, better add new API that takes index
>>>> rather than mixing indices and names.
>>> sure okay
>>>
>>> Thanks,
>>> Devi Priya
>>>>
>>>>> + if (ret < 0) {
>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc
>>>>> clock\n");
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
>>>>> + if (ret < 0) {
>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc
>>>>> clock\n");
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
>>>>> + if (ret < 0) {
>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1
>>>>> clock\n");
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + ret = pm_runtime_get(&pdev->dev);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>>>>> + if (IS_ERR(regmap))
>>>>> + return PTR_ERR(regmap);
>>>>> +
>>>>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap,
>>>>> &ubi32_pll_config);
>>>>> +
>>>>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
>>>>> +}
>>>>> +
>>>>> +static const struct dev_pm_ops nss_cc_pm_ops = {
>>>>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
>>>>> +};
>>>>> +
>>>>> +static struct platform_driver nss_cc_ipq9574_driver = {
>>>>> + .probe = nss_cc_ipq9574_probe,
>>>>> + .driver = {
>>>>> + .name = "qcom,nsscc-ipq9574",
>>>>> + .of_match_table = nss_cc_ipq9574_match_table,
>>>>> + .pm = &nss_cc_pm_ops,
>>>>> + },
>>>>> +};
>>>>> +
>>>>> +module_platform_driver(nss_cc_ipq9574_driver);
>>>>> +
>>>>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>>>>> +MODULE_LICENSE("GPL");
>>>>> --
>>>>> 2.34.1
>>>>>
>>>>
>>>>
>
>
>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-09-22 12:01 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-09-22 12:01 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>>
>>
>> On 9/12/2023 7:38 PM, Devi Priya wrote:
>>>
>>>
>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>>>> wrote:
>>>>>
>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>>>> based
>>>>> devices.
>>>>>
>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>>> ---
>>>>> Changes in V2:
>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>>>> - Added module_platform_driver
>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>>>> clocks as critical
>>>>> & added pm_clk for nssnoc clocks
>>>>> - Updated the uniphy clock names
>>>>>
>>>>> drivers/clk/qcom/Kconfig | 7 +
>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109 ++++++++++++++++++++++++++++++
>>>>> 3 files changed, 3117 insertions(+)
>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>>>
>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>>>> --- a/drivers/clk/qcom/Kconfig
>>>>> +++ b/drivers/clk/qcom/Kconfig
>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>>>> of ipq9574.
>>>>>
>>>>> +config IPQ_NSSCC_9574
>>>>> + tristate "IPQ9574 NSS Clock Controller"
>>>>> + depends on ARM64 || COMPILE_TEST
>>>>> + depends on IPQ_GCC_9574
>>>>> + help
>>>>> + Support for NSS clock controller on ipq9574 devices.
>>>>> +
>>>>> config MSM_GCC_8660
>>>>> tristate "MSM8660 Global Clock Controller"
>>>>> depends on ARM || COMPILE_TEST
>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>>> index 4790c8cca426..3f084928962e 100644
>>>>> --- a/drivers/clk/qcom/Makefile
>>>>> +++ b/drivers/clk/qcom/Makefile
>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>> new file mode 100644
>>>>> index 000000000000..65bdb449ae5f
>>>>> --- /dev/null
>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>> @@ -0,0 +1,3109 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>> +/*
>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>>>> reserved.
>>>>> + */
>>>>> +
>>>>> +#include <linux/clk-provider.h>
>>>>> +#include <linux/err.h>
>>>>> +#include <linux/kernel.h>
>>>>> +#include <linux/module.h>
>>>>> +#include <linux/of.h>
>>>>> +#include <linux/of_device.h>
>>>>> +#include <linux/regmap.h>
>>>>> +#include <linux/pm_clock.h>
>>>>> +#include <linux/pm_runtime.h>
>>>>> +
>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>>>> +
>>>>> +#include "clk-alpha-pll.h"
>>>>> +#include "clk-branch.h"
>>>>> +#include "clk-pll.h"
>>>>> +#include "clk-rcg.h"
>>>>> +#include "clk-regmap.h"
>>>>> +#include "clk-regmap-divider.h"
>>>>> +#include "clk-regmap-mux.h"
>>>>> +#include "common.h"
>>>>> +#include "reset.h"
>>>>> +
>>>>> +/* Need to match the order of clocks in DT binding */
>>>>> +enum {
>>>>> + DT_NSSNOC_NSSCC_CLK,
>>>>> + DT_NSSNOC_SNOC_CLK,
>>>>> + DT_NSSNOC_SNOC_1_CLK,
>>>>
>>>> Not using the index makes it seem that these clocks are not used,
>>>> until one scrolls down to pm_clks.
>>> Okay, got it
>>>>
>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>>>> here (not a simple NIU).
>>>
>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
>>> unblock PCIe/NSS changes getting merged, shall we use regmap_update_bits
>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
>>> probe function of the gcc driver itself as like sm8550 driver to get the
>>> changes merged?
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>>
>> Hi Dmitry,
>> Just curious to know if we could send out the next series with the
>> proposed approach if that holds good.
>
> The answer really depends on the structure of your hardware. The issue
> is that once you commit the device bindings,you have to support them
> forever. So, if you commit the NSS clock support without interconnects
> in place, you have to keep this ANOC/SNOC/etc code forever, even after
> you land the interconnect. So I'd suggest landing the icc driver first
> (or at least implementing and sending to the mailing list), so that we
> can see how all these pieces fit together.
Hi Dmitry,
Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
NOC clocks have to be scaled. So if these clocks can be enabled in the
probe, there is no need for an interconnect driver at all. The same
applies to both ipq9574 and ipq5332 SoCs.
Thanks,
Devi Priya
>
>> Thanks,
>> Devi Priya
>>
>>>>
>>>>> + DT_BIAS_PLL_CC_CLK,
>>>>> + DT_BIAS_PLL_NSS_NOC_CLK,
>>>>> + DT_BIAS_PLL_UBI_NC_CLK,
>>>>> + DT_GCC_GPLL0_OUT_AUX,
>>>>> + DT_UNIPHY0_NSS_RX_CLK,
>>>>> + DT_UNIPHY0_NSS_TX_CLK,
>>>>> + DT_UNIPHY1_NSS_RX_CLK,
>>>>> + DT_UNIPHY1_NSS_TX_CLK,
>>>>> + DT_UNIPHY2_NSS_RX_CLK,
>>>>> + DT_UNIPHY2_NSS_TX_CLK,
>>>>> + DT_XO,
>>>>
>>>> As I wrote, please move DT_XO closer to the beginning of the list.
>>>>
>>>>> +};
>>>>> +
>>>>> +enum {
>>>>> + P_BIAS_PLL_CC_CLK,
>>>>> + P_BIAS_PLL_NSS_NOC_CLK,
>>>>> + P_BIAS_PLL_UBI_NC_CLK,
>>>>> + P_GCC_GPLL0_OUT_AUX,
>>>>> + P_UBI32_PLL_OUT_MAIN,
>>>>> + P_UNIPHY0_NSS_RX_CLK,
>>>>> + P_UNIPHY0_NSS_TX_CLK,
>>>>> + P_UNIPHY1_NSS_RX_CLK,
>>>>> + P_UNIPHY1_NSS_TX_CLK,
>>>>> + P_UNIPHY2_NSS_RX_CLK,
>>>>> + P_UNIPHY2_NSS_TX_CLK,
>>>>> + P_XO,
>>>>> +};
>>>>> +
>>>>> +static const struct alpha_pll_config ubi32_pll_config = {
>>>>> + .l = 0x3e,
>>>>> + .alpha = 0x6666,
>>>>> + .config_ctl_val = 0x200d4aa8,
>>>>> + .config_ctl_hi_val = 0x3c,
>>>>> + .main_output_mask = BIT(0),
>>>>> + .aux_output_mask = BIT(1),
>>>>> + .pre_div_val = 0x0,
>>>>> + .pre_div_mask = BIT(12),
>>>>> + .post_div_val = 0x0,
>>>>> + .post_div_mask = GENMASK(9, 8),
>>>>> + .alpha_en_mask = BIT(24),
>>>>> + .test_ctl_val = 0x1c0000c0,
>>>>> + .test_ctl_hi_val = 0x4000,
>>>>> +};
>>>>> +
>>>>> +static struct clk_alpha_pll ubi32_pll_main = {
>>>>> + .offset = 0x28000,
>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>>>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
>>>>> + .clkr = {
>>>>> + .hw.init = &(const struct clk_init_data) {
>>>>> + .name = "ubi32_pll_main",
>>>>> + .parent_data = &(const struct clk_parent_data) {
>>>>> + .index = DT_XO,
>>>>> + },
>>>>> + .num_parents = 1,
>>>>> + .ops = &clk_alpha_pll_huayra_ops,
>>>>> + },
>>>>> + },
>>>>> +};
>>>>> +
>>>>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>>>>> + .offset = 0x28000,
>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>>>> + .width = 2,
>>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>>> + .name = "ubi32_pll",
>>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>>> + &ubi32_pll_main.clkr.hw
>>>>> + },
>>>>> + .num_parents = 1,
>>>>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
>>>>> + .flags = CLK_SET_RATE_PARENT,
>>>>> + },
>>>>> +};
>>>>> +
>>>>
>>>> [skipped clock tables, LGTM]
>>>>
>>>>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
>>>>> + { .compatible = "qcom,ipq9574-nsscc" },
>>>>> + { }
>>>>> +};
>>>>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
>>>>> +
>>>>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>>>>> +{
>>>>> + struct regmap *regmap;
>>>>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>>>>> +
>>>>> + int ret;
>>>>> +
>>>>> + ret = devm_pm_runtime_enable(&pdev->dev);
>>>>> + if (ret < 0)
>>>>> + return ret;
>>>>> +
>>>>> + ret = devm_pm_clk_create(&pdev->dev);
>>>>> + if (ret < 0)
>>>>> + return ret;
>>>>> +
>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>>>>
>>>> As we are switching to DT indices, better add new API that takes index
>>>> rather than mixing indices and names.
>>> sure okay
>>>
>>> Thanks,
>>> Devi Priya
>>>>
>>>>> + if (ret < 0) {
>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc
>>>>> clock\n");
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
>>>>> + if (ret < 0) {
>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc
>>>>> clock\n");
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
>>>>> + if (ret < 0) {
>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1
>>>>> clock\n");
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + ret = pm_runtime_get(&pdev->dev);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>>>>> + if (IS_ERR(regmap))
>>>>> + return PTR_ERR(regmap);
>>>>> +
>>>>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap,
>>>>> &ubi32_pll_config);
>>>>> +
>>>>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc, regmap);
>>>>> +}
>>>>> +
>>>>> +static const struct dev_pm_ops nss_cc_pm_ops = {
>>>>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
>>>>> +};
>>>>> +
>>>>> +static struct platform_driver nss_cc_ipq9574_driver = {
>>>>> + .probe = nss_cc_ipq9574_probe,
>>>>> + .driver = {
>>>>> + .name = "qcom,nsscc-ipq9574",
>>>>> + .of_match_table = nss_cc_ipq9574_match_table,
>>>>> + .pm = &nss_cc_pm_ops,
>>>>> + },
>>>>> +};
>>>>> +
>>>>> +module_platform_driver(nss_cc_ipq9574_driver);
>>>>> +
>>>>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>>>>> +MODULE_LICENSE("GPL");
>>>>> --
>>>>> 2.34.1
>>>>>
>>>>
>>>>
>
>
>
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^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-09-22 12:01 ` Devi Priya
@ 2023-10-05 6:25 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-10-05 6:25 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 9/22/2023 5:31 PM, Devi Priya wrote:
>
>
> On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
>> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
>> wrote:
>>>
>>>
>>>
>>> On 9/12/2023 7:38 PM, Devi Priya wrote:
>>>>
>>>>
>>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>>>>> wrote:
>>>>>>
>>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>>>>> based
>>>>>> devices.
>>>>>>
>>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>>>> ---
>>>>>> Changes in V2:
>>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>>>>> - Added module_platform_driver
>>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>>>>> clocks as critical
>>>>>> & added pm_clk for nssnoc clocks
>>>>>> - Updated the uniphy clock names
>>>>>>
>>>>>> drivers/clk/qcom/Kconfig | 7 +
>>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
>>>>>> ++++++++++++++++++++++++++++++
>>>>>> 3 files changed, 3117 insertions(+)
>>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>
>>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>>>>> --- a/drivers/clk/qcom/Kconfig
>>>>>> +++ b/drivers/clk/qcom/Kconfig
>>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>>>>> of ipq9574.
>>>>>>
>>>>>> +config IPQ_NSSCC_9574
>>>>>> + tristate "IPQ9574 NSS Clock Controller"
>>>>>> + depends on ARM64 || COMPILE_TEST
>>>>>> + depends on IPQ_GCC_9574
>>>>>> + help
>>>>>> + Support for NSS clock controller on ipq9574 devices.
>>>>>> +
>>>>>> config MSM_GCC_8660
>>>>>> tristate "MSM8660 Global Clock Controller"
>>>>>> depends on ARM || COMPILE_TEST
>>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>>>> index 4790c8cca426..3f084928962e 100644
>>>>>> --- a/drivers/clk/qcom/Makefile
>>>>>> +++ b/drivers/clk/qcom/Makefile
>>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>> new file mode 100644
>>>>>> index 000000000000..65bdb449ae5f
>>>>>> --- /dev/null
>>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>> @@ -0,0 +1,3109 @@
>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>>> +/*
>>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>>>>> reserved.
>>>>>> + */
>>>>>> +
>>>>>> +#include <linux/clk-provider.h>
>>>>>> +#include <linux/err.h>
>>>>>> +#include <linux/kernel.h>
>>>>>> +#include <linux/module.h>
>>>>>> +#include <linux/of.h>
>>>>>> +#include <linux/of_device.h>
>>>>>> +#include <linux/regmap.h>
>>>>>> +#include <linux/pm_clock.h>
>>>>>> +#include <linux/pm_runtime.h>
>>>>>> +
>>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>>>>> +
>>>>>> +#include "clk-alpha-pll.h"
>>>>>> +#include "clk-branch.h"
>>>>>> +#include "clk-pll.h"
>>>>>> +#include "clk-rcg.h"
>>>>>> +#include "clk-regmap.h"
>>>>>> +#include "clk-regmap-divider.h"
>>>>>> +#include "clk-regmap-mux.h"
>>>>>> +#include "common.h"
>>>>>> +#include "reset.h"
>>>>>> +
>>>>>> +/* Need to match the order of clocks in DT binding */
>>>>>> +enum {
>>>>>> + DT_NSSNOC_NSSCC_CLK,
>>>>>> + DT_NSSNOC_SNOC_CLK,
>>>>>> + DT_NSSNOC_SNOC_1_CLK,
>>>>>
>>>>> Not using the index makes it seem that these clocks are not used,
>>>>> until one scrolls down to pm_clks.
>>>> Okay, got it
>>>>>
>>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>>>>> here (not a simple NIU).
>>>>
>>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
>>>> unblock PCIe/NSS changes getting merged, shall we use
>>>> regmap_update_bits
>>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
>>>> probe function of the gcc driver itself as like sm8550 driver to get
>>>> the
>>>> changes merged?
>>>>
>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>>>
>>> Hi Dmitry,
>>> Just curious to know if we could send out the next series with the
>>> proposed approach if that holds good.
>>
>> The answer really depends on the structure of your hardware. The issue
>> is that once you commit the device bindings,you have to support them
>> forever. So, if you commit the NSS clock support without interconnects
>> in place, you have to keep this ANOC/SNOC/etc code forever, even after
>> you land the interconnect. So I'd suggest landing the icc driver first
>> (or at least implementing and sending to the mailing list), so that we
>> can see how all these pieces fit together.
>
> Hi Dmitry,
> Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
> NOC clocks have to be scaled. So if these clocks can be enabled in the
> probe, there is no need for an interconnect driver at all. The same
> applies to both ipq9574 and ipq5332 SoCs.
>
Hi Dmitry,
Just curious to know if we can go ahead with the proposed solution of
enabling the NOC clocks in the probe as these clocks need not be scaled
in IPQ chipsets & hence there would be no need for an ICC driver in
ipq9574 & ipq5332 targets.
Thanks,
Devi Priya
> Thanks,
> Devi Priya
>>
>>> Thanks,
>>> Devi Priya
>>>
>>>>>
>>>>>> + DT_BIAS_PLL_CC_CLK,
>>>>>> + DT_BIAS_PLL_NSS_NOC_CLK,
>>>>>> + DT_BIAS_PLL_UBI_NC_CLK,
>>>>>> + DT_GCC_GPLL0_OUT_AUX,
>>>>>> + DT_UNIPHY0_NSS_RX_CLK,
>>>>>> + DT_UNIPHY0_NSS_TX_CLK,
>>>>>> + DT_UNIPHY1_NSS_RX_CLK,
>>>>>> + DT_UNIPHY1_NSS_TX_CLK,
>>>>>> + DT_UNIPHY2_NSS_RX_CLK,
>>>>>> + DT_UNIPHY2_NSS_TX_CLK,
>>>>>> + DT_XO,
>>>>>
>>>>> As I wrote, please move DT_XO closer to the beginning of the list.
>>>>>
>>>>>> +};
>>>>>> +
>>>>>> +enum {
>>>>>> + P_BIAS_PLL_CC_CLK,
>>>>>> + P_BIAS_PLL_NSS_NOC_CLK,
>>>>>> + P_BIAS_PLL_UBI_NC_CLK,
>>>>>> + P_GCC_GPLL0_OUT_AUX,
>>>>>> + P_UBI32_PLL_OUT_MAIN,
>>>>>> + P_UNIPHY0_NSS_RX_CLK,
>>>>>> + P_UNIPHY0_NSS_TX_CLK,
>>>>>> + P_UNIPHY1_NSS_RX_CLK,
>>>>>> + P_UNIPHY1_NSS_TX_CLK,
>>>>>> + P_UNIPHY2_NSS_RX_CLK,
>>>>>> + P_UNIPHY2_NSS_TX_CLK,
>>>>>> + P_XO,
>>>>>> +};
>>>>>> +
>>>>>> +static const struct alpha_pll_config ubi32_pll_config = {
>>>>>> + .l = 0x3e,
>>>>>> + .alpha = 0x6666,
>>>>>> + .config_ctl_val = 0x200d4aa8,
>>>>>> + .config_ctl_hi_val = 0x3c,
>>>>>> + .main_output_mask = BIT(0),
>>>>>> + .aux_output_mask = BIT(1),
>>>>>> + .pre_div_val = 0x0,
>>>>>> + .pre_div_mask = BIT(12),
>>>>>> + .post_div_val = 0x0,
>>>>>> + .post_div_mask = GENMASK(9, 8),
>>>>>> + .alpha_en_mask = BIT(24),
>>>>>> + .test_ctl_val = 0x1c0000c0,
>>>>>> + .test_ctl_hi_val = 0x4000,
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_alpha_pll ubi32_pll_main = {
>>>>>> + .offset = 0x28000,
>>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>>>>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
>>>>>> + .clkr = {
>>>>>> + .hw.init = &(const struct clk_init_data) {
>>>>>> + .name = "ubi32_pll_main",
>>>>>> + .parent_data = &(const struct
>>>>>> clk_parent_data) {
>>>>>> + .index = DT_XO,
>>>>>> + },
>>>>>> + .num_parents = 1,
>>>>>> + .ops = &clk_alpha_pll_huayra_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>>>>>> + .offset = 0x28000,
>>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>>>>> + .width = 2,
>>>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>>>> + .name = "ubi32_pll",
>>>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>>>> + &ubi32_pll_main.clkr.hw
>>>>>> + },
>>>>>> + .num_parents = 1,
>>>>>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
>>>>>> + .flags = CLK_SET_RATE_PARENT,
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>
>>>>> [skipped clock tables, LGTM]
>>>>>
>>>>>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
>>>>>> + { .compatible = "qcom,ipq9574-nsscc" },
>>>>>> + { }
>>>>>> +};
>>>>>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
>>>>>> +
>>>>>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>>>>>> +{
>>>>>> + struct regmap *regmap;
>>>>>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>>>>>> +
>>>>>> + int ret;
>>>>>> +
>>>>>> + ret = devm_pm_runtime_enable(&pdev->dev);
>>>>>> + if (ret < 0)
>>>>>> + return ret;
>>>>>> +
>>>>>> + ret = devm_pm_clk_create(&pdev->dev);
>>>>>> + if (ret < 0)
>>>>>> + return ret;
>>>>>> +
>>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>>>>>
>>>>> As we are switching to DT indices, better add new API that takes index
>>>>> rather than mixing indices and names.
>>>> sure okay
>>>>
>>>> Thanks,
>>>> Devi Priya
>>>>>
>>>>>> + if (ret < 0) {
>>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc
>>>>>> clock\n");
>>>>>> + return ret;
>>>>>> + }
>>>>>> +
>>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
>>>>>> + if (ret < 0) {
>>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc
>>>>>> clock\n");
>>>>>> + return ret;
>>>>>> + }
>>>>>> +
>>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
>>>>>> + if (ret < 0) {
>>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1
>>>>>> clock\n");
>>>>>> + return ret;
>>>>>> + }
>>>>>> +
>>>>>> + ret = pm_runtime_get(&pdev->dev);
>>>>>> + if (ret)
>>>>>> + return ret;
>>>>>> +
>>>>>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>>>>>> + if (IS_ERR(regmap))
>>>>>> + return PTR_ERR(regmap);
>>>>>> +
>>>>>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap,
>>>>>> &ubi32_pll_config);
>>>>>> +
>>>>>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc,
>>>>>> regmap);
>>>>>> +}
>>>>>> +
>>>>>> +static const struct dev_pm_ops nss_cc_pm_ops = {
>>>>>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
>>>>>> +};
>>>>>> +
>>>>>> +static struct platform_driver nss_cc_ipq9574_driver = {
>>>>>> + .probe = nss_cc_ipq9574_probe,
>>>>>> + .driver = {
>>>>>> + .name = "qcom,nsscc-ipq9574",
>>>>>> + .of_match_table = nss_cc_ipq9574_match_table,
>>>>>> + .pm = &nss_cc_pm_ops,
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> +module_platform_driver(nss_cc_ipq9574_driver);
>>>>>> +
>>>>>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>>>>>> +MODULE_LICENSE("GPL");
>>>>>> --
>>>>>> 2.34.1
>>>>>>
>>>>>
>>>>>
>>
>>
>>
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^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-10-05 6:25 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-10-05 6:25 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 9/22/2023 5:31 PM, Devi Priya wrote:
>
>
> On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
>> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
>> wrote:
>>>
>>>
>>>
>>> On 9/12/2023 7:38 PM, Devi Priya wrote:
>>>>
>>>>
>>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>>>>> wrote:
>>>>>>
>>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>>>>> based
>>>>>> devices.
>>>>>>
>>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>>>> ---
>>>>>> Changes in V2:
>>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>>>>> - Added module_platform_driver
>>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>>>>> clocks as critical
>>>>>> & added pm_clk for nssnoc clocks
>>>>>> - Updated the uniphy clock names
>>>>>>
>>>>>> drivers/clk/qcom/Kconfig | 7 +
>>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
>>>>>> ++++++++++++++++++++++++++++++
>>>>>> 3 files changed, 3117 insertions(+)
>>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>
>>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>>>>> --- a/drivers/clk/qcom/Kconfig
>>>>>> +++ b/drivers/clk/qcom/Kconfig
>>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>>>>> of ipq9574.
>>>>>>
>>>>>> +config IPQ_NSSCC_9574
>>>>>> + tristate "IPQ9574 NSS Clock Controller"
>>>>>> + depends on ARM64 || COMPILE_TEST
>>>>>> + depends on IPQ_GCC_9574
>>>>>> + help
>>>>>> + Support for NSS clock controller on ipq9574 devices.
>>>>>> +
>>>>>> config MSM_GCC_8660
>>>>>> tristate "MSM8660 Global Clock Controller"
>>>>>> depends on ARM || COMPILE_TEST
>>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>>>> index 4790c8cca426..3f084928962e 100644
>>>>>> --- a/drivers/clk/qcom/Makefile
>>>>>> +++ b/drivers/clk/qcom/Makefile
>>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>> new file mode 100644
>>>>>> index 000000000000..65bdb449ae5f
>>>>>> --- /dev/null
>>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>> @@ -0,0 +1,3109 @@
>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>>> +/*
>>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>>>>> reserved.
>>>>>> + */
>>>>>> +
>>>>>> +#include <linux/clk-provider.h>
>>>>>> +#include <linux/err.h>
>>>>>> +#include <linux/kernel.h>
>>>>>> +#include <linux/module.h>
>>>>>> +#include <linux/of.h>
>>>>>> +#include <linux/of_device.h>
>>>>>> +#include <linux/regmap.h>
>>>>>> +#include <linux/pm_clock.h>
>>>>>> +#include <linux/pm_runtime.h>
>>>>>> +
>>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>>>>> +
>>>>>> +#include "clk-alpha-pll.h"
>>>>>> +#include "clk-branch.h"
>>>>>> +#include "clk-pll.h"
>>>>>> +#include "clk-rcg.h"
>>>>>> +#include "clk-regmap.h"
>>>>>> +#include "clk-regmap-divider.h"
>>>>>> +#include "clk-regmap-mux.h"
>>>>>> +#include "common.h"
>>>>>> +#include "reset.h"
>>>>>> +
>>>>>> +/* Need to match the order of clocks in DT binding */
>>>>>> +enum {
>>>>>> + DT_NSSNOC_NSSCC_CLK,
>>>>>> + DT_NSSNOC_SNOC_CLK,
>>>>>> + DT_NSSNOC_SNOC_1_CLK,
>>>>>
>>>>> Not using the index makes it seem that these clocks are not used,
>>>>> until one scrolls down to pm_clks.
>>>> Okay, got it
>>>>>
>>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>>>>> here (not a simple NIU).
>>>>
>>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
>>>> unblock PCIe/NSS changes getting merged, shall we use
>>>> regmap_update_bits
>>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
>>>> probe function of the gcc driver itself as like sm8550 driver to get
>>>> the
>>>> changes merged?
>>>>
>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>>>
>>> Hi Dmitry,
>>> Just curious to know if we could send out the next series with the
>>> proposed approach if that holds good.
>>
>> The answer really depends on the structure of your hardware. The issue
>> is that once you commit the device bindings,you have to support them
>> forever. So, if you commit the NSS clock support without interconnects
>> in place, you have to keep this ANOC/SNOC/etc code forever, even after
>> you land the interconnect. So I'd suggest landing the icc driver first
>> (or at least implementing and sending to the mailing list), so that we
>> can see how all these pieces fit together.
>
> Hi Dmitry,
> Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
> NOC clocks have to be scaled. So if these clocks can be enabled in the
> probe, there is no need for an interconnect driver at all. The same
> applies to both ipq9574 and ipq5332 SoCs.
>
Hi Dmitry,
Just curious to know if we can go ahead with the proposed solution of
enabling the NOC clocks in the probe as these clocks need not be scaled
in IPQ chipsets & hence there would be no need for an ICC driver in
ipq9574 & ipq5332 targets.
Thanks,
Devi Priya
> Thanks,
> Devi Priya
>>
>>> Thanks,
>>> Devi Priya
>>>
>>>>>
>>>>>> + DT_BIAS_PLL_CC_CLK,
>>>>>> + DT_BIAS_PLL_NSS_NOC_CLK,
>>>>>> + DT_BIAS_PLL_UBI_NC_CLK,
>>>>>> + DT_GCC_GPLL0_OUT_AUX,
>>>>>> + DT_UNIPHY0_NSS_RX_CLK,
>>>>>> + DT_UNIPHY0_NSS_TX_CLK,
>>>>>> + DT_UNIPHY1_NSS_RX_CLK,
>>>>>> + DT_UNIPHY1_NSS_TX_CLK,
>>>>>> + DT_UNIPHY2_NSS_RX_CLK,
>>>>>> + DT_UNIPHY2_NSS_TX_CLK,
>>>>>> + DT_XO,
>>>>>
>>>>> As I wrote, please move DT_XO closer to the beginning of the list.
>>>>>
>>>>>> +};
>>>>>> +
>>>>>> +enum {
>>>>>> + P_BIAS_PLL_CC_CLK,
>>>>>> + P_BIAS_PLL_NSS_NOC_CLK,
>>>>>> + P_BIAS_PLL_UBI_NC_CLK,
>>>>>> + P_GCC_GPLL0_OUT_AUX,
>>>>>> + P_UBI32_PLL_OUT_MAIN,
>>>>>> + P_UNIPHY0_NSS_RX_CLK,
>>>>>> + P_UNIPHY0_NSS_TX_CLK,
>>>>>> + P_UNIPHY1_NSS_RX_CLK,
>>>>>> + P_UNIPHY1_NSS_TX_CLK,
>>>>>> + P_UNIPHY2_NSS_RX_CLK,
>>>>>> + P_UNIPHY2_NSS_TX_CLK,
>>>>>> + P_XO,
>>>>>> +};
>>>>>> +
>>>>>> +static const struct alpha_pll_config ubi32_pll_config = {
>>>>>> + .l = 0x3e,
>>>>>> + .alpha = 0x6666,
>>>>>> + .config_ctl_val = 0x200d4aa8,
>>>>>> + .config_ctl_hi_val = 0x3c,
>>>>>> + .main_output_mask = BIT(0),
>>>>>> + .aux_output_mask = BIT(1),
>>>>>> + .pre_div_val = 0x0,
>>>>>> + .pre_div_mask = BIT(12),
>>>>>> + .post_div_val = 0x0,
>>>>>> + .post_div_mask = GENMASK(9, 8),
>>>>>> + .alpha_en_mask = BIT(24),
>>>>>> + .test_ctl_val = 0x1c0000c0,
>>>>>> + .test_ctl_hi_val = 0x4000,
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_alpha_pll ubi32_pll_main = {
>>>>>> + .offset = 0x28000,
>>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>>>>> + .flags = SUPPORTS_DYNAMIC_UPDATE,
>>>>>> + .clkr = {
>>>>>> + .hw.init = &(const struct clk_init_data) {
>>>>>> + .name = "ubi32_pll_main",
>>>>>> + .parent_data = &(const struct
>>>>>> clk_parent_data) {
>>>>>> + .index = DT_XO,
>>>>>> + },
>>>>>> + .num_parents = 1,
>>>>>> + .ops = &clk_alpha_pll_huayra_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>>>>>> + .offset = 0x28000,
>>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>>>>> + .width = 2,
>>>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>>>> + .name = "ubi32_pll",
>>>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>>>> + &ubi32_pll_main.clkr.hw
>>>>>> + },
>>>>>> + .num_parents = 1,
>>>>>> + .ops = &clk_alpha_pll_postdiv_ro_ops,
>>>>>> + .flags = CLK_SET_RATE_PARENT,
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>
>>>>> [skipped clock tables, LGTM]
>>>>>
>>>>>> +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
>>>>>> + { .compatible = "qcom,ipq9574-nsscc" },
>>>>>> + { }
>>>>>> +};
>>>>>> +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
>>>>>> +
>>>>>> +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
>>>>>> +{
>>>>>> + struct regmap *regmap;
>>>>>> + struct qcom_cc_desc nsscc_ipq9574_desc = nss_cc_ipq9574_desc;
>>>>>> +
>>>>>> + int ret;
>>>>>> +
>>>>>> + ret = devm_pm_runtime_enable(&pdev->dev);
>>>>>> + if (ret < 0)
>>>>>> + return ret;
>>>>>> +
>>>>>> + ret = devm_pm_clk_create(&pdev->dev);
>>>>>> + if (ret < 0)
>>>>>> + return ret;
>>>>>> +
>>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_nsscc");
>>>>>
>>>>> As we are switching to DT indices, better add new API that takes index
>>>>> rather than mixing indices and names.
>>>> sure okay
>>>>
>>>> Thanks,
>>>> Devi Priya
>>>>>
>>>>>> + if (ret < 0) {
>>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_nsscc
>>>>>> clock\n");
>>>>>> + return ret;
>>>>>> + }
>>>>>> +
>>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc");
>>>>>> + if (ret < 0) {
>>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc
>>>>>> clock\n");
>>>>>> + return ret;
>>>>>> + }
>>>>>> +
>>>>>> + ret = of_pm_clk_add_clk(&pdev->dev, "nssnoc_snoc_1");
>>>>>> + if (ret < 0) {
>>>>>> + dev_err(&pdev->dev, "Failed to acquire nssnoc_snoc_1
>>>>>> clock\n");
>>>>>> + return ret;
>>>>>> + }
>>>>>> +
>>>>>> + ret = pm_runtime_get(&pdev->dev);
>>>>>> + if (ret)
>>>>>> + return ret;
>>>>>> +
>>>>>> + regmap = qcom_cc_map(pdev, &nsscc_ipq9574_desc);
>>>>>> + if (IS_ERR(regmap))
>>>>>> + return PTR_ERR(regmap);
>>>>>> +
>>>>>> + clk_alpha_pll_configure(&ubi32_pll_main, regmap,
>>>>>> &ubi32_pll_config);
>>>>>> +
>>>>>> + return qcom_cc_really_probe(pdev, &nsscc_ipq9574_desc,
>>>>>> regmap);
>>>>>> +}
>>>>>> +
>>>>>> +static const struct dev_pm_ops nss_cc_pm_ops = {
>>>>>> + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
>>>>>> +};
>>>>>> +
>>>>>> +static struct platform_driver nss_cc_ipq9574_driver = {
>>>>>> + .probe = nss_cc_ipq9574_probe,
>>>>>> + .driver = {
>>>>>> + .name = "qcom,nsscc-ipq9574",
>>>>>> + .of_match_table = nss_cc_ipq9574_match_table,
>>>>>> + .pm = &nss_cc_pm_ops,
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> +module_platform_driver(nss_cc_ipq9574_driver);
>>>>>> +
>>>>>> +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
>>>>>> +MODULE_LICENSE("GPL");
>>>>>> --
>>>>>> 2.34.1
>>>>>>
>>>>>
>>>>>
>>
>>
>>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-10-05 6:25 ` Devi Priya
@ 2023-10-05 7:19 ` Dmitry Baryshkov
-1 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-10-05 7:19 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Thu, 5 Oct 2023 at 09:26, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
>
>
> On 9/22/2023 5:31 PM, Devi Priya wrote:
> >
> >
> > On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
> >> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 9/12/2023 7:38 PM, Devi Priya wrote:
> >>>>
> >>>>
> >>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
> >>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
> >>>>> wrote:
> >>>>>>
> >>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
> >>>>>> based
> >>>>>> devices.
> >>>>>>
> >>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> >>>>>> ---
> >>>>>> Changes in V2:
> >>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
> >>>>>> - Added module_platform_driver
> >>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
> >>>>>> clocks as critical
> >>>>>> & added pm_clk for nssnoc clocks
> >>>>>> - Updated the uniphy clock names
> >>>>>>
> >>>>>> drivers/clk/qcom/Kconfig | 7 +
> >>>>>> drivers/clk/qcom/Makefile | 1 +
> >>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
> >>>>>> ++++++++++++++++++++++++++++++
> >>>>>> 3 files changed, 3117 insertions(+)
> >>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>
> >>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
> >>>>>> --- a/drivers/clk/qcom/Kconfig
> >>>>>> +++ b/drivers/clk/qcom/Kconfig
> >>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
> >>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
> >>>>>> of ipq9574.
> >>>>>>
> >>>>>> +config IPQ_NSSCC_9574
> >>>>>> + tristate "IPQ9574 NSS Clock Controller"
> >>>>>> + depends on ARM64 || COMPILE_TEST
> >>>>>> + depends on IPQ_GCC_9574
> >>>>>> + help
> >>>>>> + Support for NSS clock controller on ipq9574 devices.
> >>>>>> +
> >>>>>> config MSM_GCC_8660
> >>>>>> tristate "MSM8660 Global Clock Controller"
> >>>>>> depends on ARM || COMPILE_TEST
> >>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >>>>>> index 4790c8cca426..3f084928962e 100644
> >>>>>> --- a/drivers/clk/qcom/Makefile
> >>>>>> +++ b/drivers/clk/qcom/Makefile
> >>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> >>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> >>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> >>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
> >>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
> >>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> >>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
> >>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> >>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>> new file mode 100644
> >>>>>> index 000000000000..65bdb449ae5f
> >>>>>> --- /dev/null
> >>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>> @@ -0,0 +1,3109 @@
> >>>>>> +// SPDX-License-Identifier: GPL-2.0-only
> >>>>>> +/*
> >>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> >>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
> >>>>>> reserved.
> >>>>>> + */
> >>>>>> +
> >>>>>> +#include <linux/clk-provider.h>
> >>>>>> +#include <linux/err.h>
> >>>>>> +#include <linux/kernel.h>
> >>>>>> +#include <linux/module.h>
> >>>>>> +#include <linux/of.h>
> >>>>>> +#include <linux/of_device.h>
> >>>>>> +#include <linux/regmap.h>
> >>>>>> +#include <linux/pm_clock.h>
> >>>>>> +#include <linux/pm_runtime.h>
> >>>>>> +
> >>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> >>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> >>>>>> +
> >>>>>> +#include "clk-alpha-pll.h"
> >>>>>> +#include "clk-branch.h"
> >>>>>> +#include "clk-pll.h"
> >>>>>> +#include "clk-rcg.h"
> >>>>>> +#include "clk-regmap.h"
> >>>>>> +#include "clk-regmap-divider.h"
> >>>>>> +#include "clk-regmap-mux.h"
> >>>>>> +#include "common.h"
> >>>>>> +#include "reset.h"
> >>>>>> +
> >>>>>> +/* Need to match the order of clocks in DT binding */
> >>>>>> +enum {
> >>>>>> + DT_NSSNOC_NSSCC_CLK,
> >>>>>> + DT_NSSNOC_SNOC_CLK,
> >>>>>> + DT_NSSNOC_SNOC_1_CLK,
> >>>>>
> >>>>> Not using the index makes it seem that these clocks are not used,
> >>>>> until one scrolls down to pm_clks.
> >>>> Okay, got it
> >>>>>
> >>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
> >>>>> here (not a simple NIU).
> >>>>
> >>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
> >>>> unblock PCIe/NSS changes getting merged, shall we use
> >>>> regmap_update_bits
> >>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
> >>>> probe function of the gcc driver itself as like sm8550 driver to get
> >>>> the
> >>>> changes merged?
> >>>>
> >>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
> >>>
> >>> Hi Dmitry,
> >>> Just curious to know if we could send out the next series with the
> >>> proposed approach if that holds good.
> >>
> >> The answer really depends on the structure of your hardware. The issue
> >> is that once you commit the device bindings,you have to support them
> >> forever. So, if you commit the NSS clock support without interconnects
> >> in place, you have to keep this ANOC/SNOC/etc code forever, even after
> >> you land the interconnect. So I'd suggest landing the icc driver first
> >> (or at least implementing and sending to the mailing list), so that we
> >> can see how all these pieces fit together.
> >
> > Hi Dmitry,
> > Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
> > NOC clocks have to be scaled. So if these clocks can be enabled in the
> > probe, there is no need for an interconnect driver at all. The same
> > applies to both ipq9574 and ipq5332 SoCs.
> >
>
> Hi Dmitry,
> Just curious to know if we can go ahead with the proposed solution of
> enabling the NOC clocks in the probe as these clocks need not be scaled
> in IPQ chipsets & hence there would be no need for an ICC driver in
> ipq9574 & ipq5332 targets.
In the probe of which driver?
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-10-05 7:19 ` Dmitry Baryshkov
0 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-10-05 7:19 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Thu, 5 Oct 2023 at 09:26, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
>
>
> On 9/22/2023 5:31 PM, Devi Priya wrote:
> >
> >
> > On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
> >> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 9/12/2023 7:38 PM, Devi Priya wrote:
> >>>>
> >>>>
> >>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
> >>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
> >>>>> wrote:
> >>>>>>
> >>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
> >>>>>> based
> >>>>>> devices.
> >>>>>>
> >>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> >>>>>> ---
> >>>>>> Changes in V2:
> >>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
> >>>>>> - Added module_platform_driver
> >>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
> >>>>>> clocks as critical
> >>>>>> & added pm_clk for nssnoc clocks
> >>>>>> - Updated the uniphy clock names
> >>>>>>
> >>>>>> drivers/clk/qcom/Kconfig | 7 +
> >>>>>> drivers/clk/qcom/Makefile | 1 +
> >>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
> >>>>>> ++++++++++++++++++++++++++++++
> >>>>>> 3 files changed, 3117 insertions(+)
> >>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>
> >>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
> >>>>>> --- a/drivers/clk/qcom/Kconfig
> >>>>>> +++ b/drivers/clk/qcom/Kconfig
> >>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
> >>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
> >>>>>> of ipq9574.
> >>>>>>
> >>>>>> +config IPQ_NSSCC_9574
> >>>>>> + tristate "IPQ9574 NSS Clock Controller"
> >>>>>> + depends on ARM64 || COMPILE_TEST
> >>>>>> + depends on IPQ_GCC_9574
> >>>>>> + help
> >>>>>> + Support for NSS clock controller on ipq9574 devices.
> >>>>>> +
> >>>>>> config MSM_GCC_8660
> >>>>>> tristate "MSM8660 Global Clock Controller"
> >>>>>> depends on ARM || COMPILE_TEST
> >>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >>>>>> index 4790c8cca426..3f084928962e 100644
> >>>>>> --- a/drivers/clk/qcom/Makefile
> >>>>>> +++ b/drivers/clk/qcom/Makefile
> >>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> >>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> >>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> >>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
> >>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
> >>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> >>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
> >>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> >>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>> new file mode 100644
> >>>>>> index 000000000000..65bdb449ae5f
> >>>>>> --- /dev/null
> >>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>> @@ -0,0 +1,3109 @@
> >>>>>> +// SPDX-License-Identifier: GPL-2.0-only
> >>>>>> +/*
> >>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> >>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
> >>>>>> reserved.
> >>>>>> + */
> >>>>>> +
> >>>>>> +#include <linux/clk-provider.h>
> >>>>>> +#include <linux/err.h>
> >>>>>> +#include <linux/kernel.h>
> >>>>>> +#include <linux/module.h>
> >>>>>> +#include <linux/of.h>
> >>>>>> +#include <linux/of_device.h>
> >>>>>> +#include <linux/regmap.h>
> >>>>>> +#include <linux/pm_clock.h>
> >>>>>> +#include <linux/pm_runtime.h>
> >>>>>> +
> >>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> >>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> >>>>>> +
> >>>>>> +#include "clk-alpha-pll.h"
> >>>>>> +#include "clk-branch.h"
> >>>>>> +#include "clk-pll.h"
> >>>>>> +#include "clk-rcg.h"
> >>>>>> +#include "clk-regmap.h"
> >>>>>> +#include "clk-regmap-divider.h"
> >>>>>> +#include "clk-regmap-mux.h"
> >>>>>> +#include "common.h"
> >>>>>> +#include "reset.h"
> >>>>>> +
> >>>>>> +/* Need to match the order of clocks in DT binding */
> >>>>>> +enum {
> >>>>>> + DT_NSSNOC_NSSCC_CLK,
> >>>>>> + DT_NSSNOC_SNOC_CLK,
> >>>>>> + DT_NSSNOC_SNOC_1_CLK,
> >>>>>
> >>>>> Not using the index makes it seem that these clocks are not used,
> >>>>> until one scrolls down to pm_clks.
> >>>> Okay, got it
> >>>>>
> >>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
> >>>>> here (not a simple NIU).
> >>>>
> >>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
> >>>> unblock PCIe/NSS changes getting merged, shall we use
> >>>> regmap_update_bits
> >>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
> >>>> probe function of the gcc driver itself as like sm8550 driver to get
> >>>> the
> >>>> changes merged?
> >>>>
> >>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
> >>>
> >>> Hi Dmitry,
> >>> Just curious to know if we could send out the next series with the
> >>> proposed approach if that holds good.
> >>
> >> The answer really depends on the structure of your hardware. The issue
> >> is that once you commit the device bindings,you have to support them
> >> forever. So, if you commit the NSS clock support without interconnects
> >> in place, you have to keep this ANOC/SNOC/etc code forever, even after
> >> you land the interconnect. So I'd suggest landing the icc driver first
> >> (or at least implementing and sending to the mailing list), so that we
> >> can see how all these pieces fit together.
> >
> > Hi Dmitry,
> > Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
> > NOC clocks have to be scaled. So if these clocks can be enabled in the
> > probe, there is no need for an interconnect driver at all. The same
> > applies to both ipq9574 and ipq5332 SoCs.
> >
>
> Hi Dmitry,
> Just curious to know if we can go ahead with the proposed solution of
> enabling the NOC clocks in the probe as these clocks need not be scaled
> in IPQ chipsets & hence there would be no need for an ICC driver in
> ipq9574 & ipq5332 targets.
In the probe of which driver?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-10-05 7:19 ` Dmitry Baryshkov
@ 2023-10-05 9:56 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-10-05 9:56 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 10/5/2023 12:49 PM, Dmitry Baryshkov wrote:
> On Thu, 5 Oct 2023 at 09:26, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>>
>>
>> On 9/22/2023 5:31 PM, Devi Priya wrote:
>>>
>>>
>>> On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
>>>> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
>>>> wrote:
>>>>>
>>>>>
>>>>>
>>>>> On 9/12/2023 7:38 PM, Devi Priya wrote:
>>>>>>
>>>>>>
>>>>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>>>>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>>>>>>> wrote:
>>>>>>>>
>>>>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>>>>>>> based
>>>>>>>> devices.
>>>>>>>>
>>>>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>>>>>> ---
>>>>>>>> Changes in V2:
>>>>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>>>>>>> - Added module_platform_driver
>>>>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>>>>>>> clocks as critical
>>>>>>>> & added pm_clk for nssnoc clocks
>>>>>>>> - Updated the uniphy clock names
>>>>>>>>
>>>>>>>> drivers/clk/qcom/Kconfig | 7 +
>>>>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
>>>>>>>> ++++++++++++++++++++++++++++++
>>>>>>>> 3 files changed, 3117 insertions(+)
>>>>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>
>>>>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>>>>>>> --- a/drivers/clk/qcom/Kconfig
>>>>>>>> +++ b/drivers/clk/qcom/Kconfig
>>>>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>>>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>>>>>>> of ipq9574.
>>>>>>>>
>>>>>>>> +config IPQ_NSSCC_9574
>>>>>>>> + tristate "IPQ9574 NSS Clock Controller"
>>>>>>>> + depends on ARM64 || COMPILE_TEST
>>>>>>>> + depends on IPQ_GCC_9574
>>>>>>>> + help
>>>>>>>> + Support for NSS clock controller on ipq9574 devices.
>>>>>>>> +
>>>>>>>> config MSM_GCC_8660
>>>>>>>> tristate "MSM8660 Global Clock Controller"
>>>>>>>> depends on ARM || COMPILE_TEST
>>>>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>>>>>> index 4790c8cca426..3f084928962e 100644
>>>>>>>> --- a/drivers/clk/qcom/Makefile
>>>>>>>> +++ b/drivers/clk/qcom/Makefile
>>>>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>>>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>>>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>>>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>>>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>>>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>>>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>>>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>>>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>> new file mode 100644
>>>>>>>> index 000000000000..65bdb449ae5f
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>> @@ -0,0 +1,3109 @@
>>>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>>>>> +/*
>>>>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>>>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>>>>>>> reserved.
>>>>>>>> + */
>>>>>>>> +
>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>> +#include <linux/err.h>
>>>>>>>> +#include <linux/kernel.h>
>>>>>>>> +#include <linux/module.h>
>>>>>>>> +#include <linux/of.h>
>>>>>>>> +#include <linux/of_device.h>
>>>>>>>> +#include <linux/regmap.h>
>>>>>>>> +#include <linux/pm_clock.h>
>>>>>>>> +#include <linux/pm_runtime.h>
>>>>>>>> +
>>>>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>>>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>>>>>>> +
>>>>>>>> +#include "clk-alpha-pll.h"
>>>>>>>> +#include "clk-branch.h"
>>>>>>>> +#include "clk-pll.h"
>>>>>>>> +#include "clk-rcg.h"
>>>>>>>> +#include "clk-regmap.h"
>>>>>>>> +#include "clk-regmap-divider.h"
>>>>>>>> +#include "clk-regmap-mux.h"
>>>>>>>> +#include "common.h"
>>>>>>>> +#include "reset.h"
>>>>>>>> +
>>>>>>>> +/* Need to match the order of clocks in DT binding */
>>>>>>>> +enum {
>>>>>>>> + DT_NSSNOC_NSSCC_CLK,
>>>>>>>> + DT_NSSNOC_SNOC_CLK,
>>>>>>>> + DT_NSSNOC_SNOC_1_CLK,
>>>>>>>
>>>>>>> Not using the index makes it seem that these clocks are not used,
>>>>>>> until one scrolls down to pm_clks.
>>>>>> Okay, got it
>>>>>>>
>>>>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>>>>>>> here (not a simple NIU).
>>>>>>
>>>>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
>>>>>> unblock PCIe/NSS changes getting merged, shall we use
>>>>>> regmap_update_bits
>>>>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
>>>>>> probe function of the gcc driver itself as like sm8550 driver to get
>>>>>> the
>>>>>> changes merged?
>>>>>>
>>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>>>>>
>>>>> Hi Dmitry,
>>>>> Just curious to know if we could send out the next series with the
>>>>> proposed approach if that holds good.
>>>>
>>>> The answer really depends on the structure of your hardware. The issue
>>>> is that once you commit the device bindings,you have to support them
>>>> forever. So, if you commit the NSS clock support without interconnects
>>>> in place, you have to keep this ANOC/SNOC/etc code forever, even after
>>>> you land the interconnect. So I'd suggest landing the icc driver first
>>>> (or at least implementing and sending to the mailing list), so that we
>>>> can see how all these pieces fit together.
>>>
>>> Hi Dmitry,
>>> Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
>>> NOC clocks have to be scaled. So if these clocks can be enabled in the
>>> probe, there is no need for an interconnect driver at all. The same
>>> applies to both ipq9574 and ipq5332 SoCs.
>>>
>>
>> Hi Dmitry,
>> Just curious to know if we can go ahead with the proposed solution of
>> enabling the NOC clocks in the probe as these clocks need not be scaled
>> in IPQ chipsets & hence there would be no need for an ICC driver in
>> ipq9574 & ipq5332 targets.
>
> In the probe of which driver?
GCC driver of ipq9574 & ipq5332 targets.
Thanks,
Devi Priya
>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-10-05 9:56 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-10-05 9:56 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 10/5/2023 12:49 PM, Dmitry Baryshkov wrote:
> On Thu, 5 Oct 2023 at 09:26, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>>
>>
>> On 9/22/2023 5:31 PM, Devi Priya wrote:
>>>
>>>
>>> On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
>>>> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
>>>> wrote:
>>>>>
>>>>>
>>>>>
>>>>> On 9/12/2023 7:38 PM, Devi Priya wrote:
>>>>>>
>>>>>>
>>>>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>>>>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>>>>>>> wrote:
>>>>>>>>
>>>>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>>>>>>> based
>>>>>>>> devices.
>>>>>>>>
>>>>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>>>>>> ---
>>>>>>>> Changes in V2:
>>>>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>>>>>>> - Added module_platform_driver
>>>>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>>>>>>> clocks as critical
>>>>>>>> & added pm_clk for nssnoc clocks
>>>>>>>> - Updated the uniphy clock names
>>>>>>>>
>>>>>>>> drivers/clk/qcom/Kconfig | 7 +
>>>>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
>>>>>>>> ++++++++++++++++++++++++++++++
>>>>>>>> 3 files changed, 3117 insertions(+)
>>>>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>
>>>>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>>>>>>> --- a/drivers/clk/qcom/Kconfig
>>>>>>>> +++ b/drivers/clk/qcom/Kconfig
>>>>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>>>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>>>>>>> of ipq9574.
>>>>>>>>
>>>>>>>> +config IPQ_NSSCC_9574
>>>>>>>> + tristate "IPQ9574 NSS Clock Controller"
>>>>>>>> + depends on ARM64 || COMPILE_TEST
>>>>>>>> + depends on IPQ_GCC_9574
>>>>>>>> + help
>>>>>>>> + Support for NSS clock controller on ipq9574 devices.
>>>>>>>> +
>>>>>>>> config MSM_GCC_8660
>>>>>>>> tristate "MSM8660 Global Clock Controller"
>>>>>>>> depends on ARM || COMPILE_TEST
>>>>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>>>>>> index 4790c8cca426..3f084928962e 100644
>>>>>>>> --- a/drivers/clk/qcom/Makefile
>>>>>>>> +++ b/drivers/clk/qcom/Makefile
>>>>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>>>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>>>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>>>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>>>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>>>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>>>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>>>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>>>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>> new file mode 100644
>>>>>>>> index 000000000000..65bdb449ae5f
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>> @@ -0,0 +1,3109 @@
>>>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>>>>> +/*
>>>>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>>>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>>>>>>> reserved.
>>>>>>>> + */
>>>>>>>> +
>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>> +#include <linux/err.h>
>>>>>>>> +#include <linux/kernel.h>
>>>>>>>> +#include <linux/module.h>
>>>>>>>> +#include <linux/of.h>
>>>>>>>> +#include <linux/of_device.h>
>>>>>>>> +#include <linux/regmap.h>
>>>>>>>> +#include <linux/pm_clock.h>
>>>>>>>> +#include <linux/pm_runtime.h>
>>>>>>>> +
>>>>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>>>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>>>>>>> +
>>>>>>>> +#include "clk-alpha-pll.h"
>>>>>>>> +#include "clk-branch.h"
>>>>>>>> +#include "clk-pll.h"
>>>>>>>> +#include "clk-rcg.h"
>>>>>>>> +#include "clk-regmap.h"
>>>>>>>> +#include "clk-regmap-divider.h"
>>>>>>>> +#include "clk-regmap-mux.h"
>>>>>>>> +#include "common.h"
>>>>>>>> +#include "reset.h"
>>>>>>>> +
>>>>>>>> +/* Need to match the order of clocks in DT binding */
>>>>>>>> +enum {
>>>>>>>> + DT_NSSNOC_NSSCC_CLK,
>>>>>>>> + DT_NSSNOC_SNOC_CLK,
>>>>>>>> + DT_NSSNOC_SNOC_1_CLK,
>>>>>>>
>>>>>>> Not using the index makes it seem that these clocks are not used,
>>>>>>> until one scrolls down to pm_clks.
>>>>>> Okay, got it
>>>>>>>
>>>>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>>>>>>> here (not a simple NIU).
>>>>>>
>>>>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
>>>>>> unblock PCIe/NSS changes getting merged, shall we use
>>>>>> regmap_update_bits
>>>>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
>>>>>> probe function of the gcc driver itself as like sm8550 driver to get
>>>>>> the
>>>>>> changes merged?
>>>>>>
>>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>>>>>
>>>>> Hi Dmitry,
>>>>> Just curious to know if we could send out the next series with the
>>>>> proposed approach if that holds good.
>>>>
>>>> The answer really depends on the structure of your hardware. The issue
>>>> is that once you commit the device bindings,you have to support them
>>>> forever. So, if you commit the NSS clock support without interconnects
>>>> in place, you have to keep this ANOC/SNOC/etc code forever, even after
>>>> you land the interconnect. So I'd suggest landing the icc driver first
>>>> (or at least implementing and sending to the mailing list), so that we
>>>> can see how all these pieces fit together.
>>>
>>> Hi Dmitry,
>>> Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
>>> NOC clocks have to be scaled. So if these clocks can be enabled in the
>>> probe, there is no need for an interconnect driver at all. The same
>>> applies to both ipq9574 and ipq5332 SoCs.
>>>
>>
>> Hi Dmitry,
>> Just curious to know if we can go ahead with the proposed solution of
>> enabling the NOC clocks in the probe as these clocks need not be scaled
>> in IPQ chipsets & hence there would be no need for an ICC driver in
>> ipq9574 & ipq5332 targets.
>
> In the probe of which driver?
GCC driver of ipq9574 & ipq5332 targets.
Thanks,
Devi Priya
>
>
>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-10-05 9:56 ` Devi Priya
@ 2023-10-06 21:21 ` Dmitry Baryshkov
-1 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-10-06 21:21 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Thu, 5 Oct 2023 at 12:56, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
>
>
> On 10/5/2023 12:49 PM, Dmitry Baryshkov wrote:
> > On Thu, 5 Oct 2023 at 09:26, Devi Priya <quic_devipriy@quicinc.com> wrote:
> >>
> >>
> >>
> >> On 9/22/2023 5:31 PM, Devi Priya wrote:
> >>>
> >>>
> >>> On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
> >>>> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
> >>>> wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>> On 9/12/2023 7:38 PM, Devi Priya wrote:
> >>>>>>
> >>>>>>
> >>>>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
> >>>>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
> >>>>>>> wrote:
> >>>>>>>>
> >>>>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
> >>>>>>>> based
> >>>>>>>> devices.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> >>>>>>>> ---
> >>>>>>>> Changes in V2:
> >>>>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
> >>>>>>>> - Added module_platform_driver
> >>>>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
> >>>>>>>> clocks as critical
> >>>>>>>> & added pm_clk for nssnoc clocks
> >>>>>>>> - Updated the uniphy clock names
> >>>>>>>>
> >>>>>>>> drivers/clk/qcom/Kconfig | 7 +
> >>>>>>>> drivers/clk/qcom/Makefile | 1 +
> >>>>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
> >>>>>>>> ++++++++++++++++++++++++++++++
> >>>>>>>> 3 files changed, 3117 insertions(+)
> >>>>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>>>
> >>>>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >>>>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
> >>>>>>>> --- a/drivers/clk/qcom/Kconfig
> >>>>>>>> +++ b/drivers/clk/qcom/Kconfig
> >>>>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
> >>>>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
> >>>>>>>> of ipq9574.
> >>>>>>>>
> >>>>>>>> +config IPQ_NSSCC_9574
> >>>>>>>> + tristate "IPQ9574 NSS Clock Controller"
> >>>>>>>> + depends on ARM64 || COMPILE_TEST
> >>>>>>>> + depends on IPQ_GCC_9574
> >>>>>>>> + help
> >>>>>>>> + Support for NSS clock controller on ipq9574 devices.
> >>>>>>>> +
> >>>>>>>> config MSM_GCC_8660
> >>>>>>>> tristate "MSM8660 Global Clock Controller"
> >>>>>>>> depends on ARM || COMPILE_TEST
> >>>>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >>>>>>>> index 4790c8cca426..3f084928962e 100644
> >>>>>>>> --- a/drivers/clk/qcom/Makefile
> >>>>>>>> +++ b/drivers/clk/qcom/Makefile
> >>>>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> >>>>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> >>>>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> >>>>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
> >>>>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
> >>>>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> >>>>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
> >>>>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> >>>>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>>> new file mode 100644
> >>>>>>>> index 000000000000..65bdb449ae5f
> >>>>>>>> --- /dev/null
> >>>>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>>> @@ -0,0 +1,3109 @@
> >>>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
> >>>>>>>> +/*
> >>>>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> >>>>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
> >>>>>>>> reserved.
> >>>>>>>> + */
> >>>>>>>> +
> >>>>>>>> +#include <linux/clk-provider.h>
> >>>>>>>> +#include <linux/err.h>
> >>>>>>>> +#include <linux/kernel.h>
> >>>>>>>> +#include <linux/module.h>
> >>>>>>>> +#include <linux/of.h>
> >>>>>>>> +#include <linux/of_device.h>
> >>>>>>>> +#include <linux/regmap.h>
> >>>>>>>> +#include <linux/pm_clock.h>
> >>>>>>>> +#include <linux/pm_runtime.h>
> >>>>>>>> +
> >>>>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> >>>>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> >>>>>>>> +
> >>>>>>>> +#include "clk-alpha-pll.h"
> >>>>>>>> +#include "clk-branch.h"
> >>>>>>>> +#include "clk-pll.h"
> >>>>>>>> +#include "clk-rcg.h"
> >>>>>>>> +#include "clk-regmap.h"
> >>>>>>>> +#include "clk-regmap-divider.h"
> >>>>>>>> +#include "clk-regmap-mux.h"
> >>>>>>>> +#include "common.h"
> >>>>>>>> +#include "reset.h"
> >>>>>>>> +
> >>>>>>>> +/* Need to match the order of clocks in DT binding */
> >>>>>>>> +enum {
> >>>>>>>> + DT_NSSNOC_NSSCC_CLK,
> >>>>>>>> + DT_NSSNOC_SNOC_CLK,
> >>>>>>>> + DT_NSSNOC_SNOC_1_CLK,
> >>>>>>>
> >>>>>>> Not using the index makes it seem that these clocks are not used,
> >>>>>>> until one scrolls down to pm_clks.
> >>>>>> Okay, got it
> >>>>>>>
> >>>>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
> >>>>>>> here (not a simple NIU).
> >>>>>>
> >>>>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
> >>>>>> unblock PCIe/NSS changes getting merged, shall we use
> >>>>>> regmap_update_bits
> >>>>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
> >>>>>> probe function of the gcc driver itself as like sm8550 driver to get
> >>>>>> the
> >>>>>> changes merged?
> >>>>>>
> >>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
> >>>>>
> >>>>> Hi Dmitry,
> >>>>> Just curious to know if we could send out the next series with the
> >>>>> proposed approach if that holds good.
> >>>>
> >>>> The answer really depends on the structure of your hardware. The issue
> >>>> is that once you commit the device bindings,you have to support them
> >>>> forever. So, if you commit the NSS clock support without interconnects
> >>>> in place, you have to keep this ANOC/SNOC/etc code forever, even after
> >>>> you land the interconnect. So I'd suggest landing the icc driver first
> >>>> (or at least implementing and sending to the mailing list), so that we
> >>>> can see how all these pieces fit together.
> >>>
> >>> Hi Dmitry,
> >>> Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
> >>> NOC clocks have to be scaled. So if these clocks can be enabled in the
> >>> probe, there is no need for an interconnect driver at all. The same
> >>> applies to both ipq9574 and ipq5332 SoCs.
> >>>
> >>
> >> Hi Dmitry,
> >> Just curious to know if we can go ahead with the proposed solution of
> >> enabling the NOC clocks in the probe as these clocks need not be scaled
> >> in IPQ chipsets & hence there would be no need for an ICC driver in
> >> ipq9574 & ipq5332 targets.
> >
> > In the probe of which driver?
> GCC driver of ipq9574 & ipq5332 targets.
Would you need to handle these clocks additionally in the
suspend/resume path? Will this increase the power consumption of the
board?
Generally, I'd say this looks like a bad idea. Consider all the
troubles we are undergoing now while sorting out the NIU clocks on RPM
and RPMH platforms.
So, unless you are 100% sure that this is a permanent solution (like
AHB clocks being always on), I'd kindly suggest implementing the NoC
attachment properly. In the end, other Qualcomm platforms use ICC
drivers, so by following this pattern we will have more common code
paths.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-10-06 21:21 ` Dmitry Baryshkov
0 siblings, 0 replies; 70+ messages in thread
From: Dmitry Baryshkov @ 2023-10-06 21:21 UTC (permalink / raw)
To: Devi Priya
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On Thu, 5 Oct 2023 at 12:56, Devi Priya <quic_devipriy@quicinc.com> wrote:
>
>
>
> On 10/5/2023 12:49 PM, Dmitry Baryshkov wrote:
> > On Thu, 5 Oct 2023 at 09:26, Devi Priya <quic_devipriy@quicinc.com> wrote:
> >>
> >>
> >>
> >> On 9/22/2023 5:31 PM, Devi Priya wrote:
> >>>
> >>>
> >>> On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
> >>>> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
> >>>> wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>> On 9/12/2023 7:38 PM, Devi Priya wrote:
> >>>>>>
> >>>>>>
> >>>>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
> >>>>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
> >>>>>>> wrote:
> >>>>>>>>
> >>>>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
> >>>>>>>> based
> >>>>>>>> devices.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> >>>>>>>> ---
> >>>>>>>> Changes in V2:
> >>>>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
> >>>>>>>> - Added module_platform_driver
> >>>>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
> >>>>>>>> clocks as critical
> >>>>>>>> & added pm_clk for nssnoc clocks
> >>>>>>>> - Updated the uniphy clock names
> >>>>>>>>
> >>>>>>>> drivers/clk/qcom/Kconfig | 7 +
> >>>>>>>> drivers/clk/qcom/Makefile | 1 +
> >>>>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
> >>>>>>>> ++++++++++++++++++++++++++++++
> >>>>>>>> 3 files changed, 3117 insertions(+)
> >>>>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>>>
> >>>>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >>>>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
> >>>>>>>> --- a/drivers/clk/qcom/Kconfig
> >>>>>>>> +++ b/drivers/clk/qcom/Kconfig
> >>>>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
> >>>>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
> >>>>>>>> of ipq9574.
> >>>>>>>>
> >>>>>>>> +config IPQ_NSSCC_9574
> >>>>>>>> + tristate "IPQ9574 NSS Clock Controller"
> >>>>>>>> + depends on ARM64 || COMPILE_TEST
> >>>>>>>> + depends on IPQ_GCC_9574
> >>>>>>>> + help
> >>>>>>>> + Support for NSS clock controller on ipq9574 devices.
> >>>>>>>> +
> >>>>>>>> config MSM_GCC_8660
> >>>>>>>> tristate "MSM8660 Global Clock Controller"
> >>>>>>>> depends on ARM || COMPILE_TEST
> >>>>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >>>>>>>> index 4790c8cca426..3f084928962e 100644
> >>>>>>>> --- a/drivers/clk/qcom/Makefile
> >>>>>>>> +++ b/drivers/clk/qcom/Makefile
> >>>>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> >>>>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> >>>>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> >>>>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
> >>>>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
> >>>>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> >>>>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
> >>>>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> >>>>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>>> new file mode 100644
> >>>>>>>> index 000000000000..65bdb449ae5f
> >>>>>>>> --- /dev/null
> >>>>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
> >>>>>>>> @@ -0,0 +1,3109 @@
> >>>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
> >>>>>>>> +/*
> >>>>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> >>>>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
> >>>>>>>> reserved.
> >>>>>>>> + */
> >>>>>>>> +
> >>>>>>>> +#include <linux/clk-provider.h>
> >>>>>>>> +#include <linux/err.h>
> >>>>>>>> +#include <linux/kernel.h>
> >>>>>>>> +#include <linux/module.h>
> >>>>>>>> +#include <linux/of.h>
> >>>>>>>> +#include <linux/of_device.h>
> >>>>>>>> +#include <linux/regmap.h>
> >>>>>>>> +#include <linux/pm_clock.h>
> >>>>>>>> +#include <linux/pm_runtime.h>
> >>>>>>>> +
> >>>>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
> >>>>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
> >>>>>>>> +
> >>>>>>>> +#include "clk-alpha-pll.h"
> >>>>>>>> +#include "clk-branch.h"
> >>>>>>>> +#include "clk-pll.h"
> >>>>>>>> +#include "clk-rcg.h"
> >>>>>>>> +#include "clk-regmap.h"
> >>>>>>>> +#include "clk-regmap-divider.h"
> >>>>>>>> +#include "clk-regmap-mux.h"
> >>>>>>>> +#include "common.h"
> >>>>>>>> +#include "reset.h"
> >>>>>>>> +
> >>>>>>>> +/* Need to match the order of clocks in DT binding */
> >>>>>>>> +enum {
> >>>>>>>> + DT_NSSNOC_NSSCC_CLK,
> >>>>>>>> + DT_NSSNOC_SNOC_CLK,
> >>>>>>>> + DT_NSSNOC_SNOC_1_CLK,
> >>>>>>>
> >>>>>>> Not using the index makes it seem that these clocks are not used,
> >>>>>>> until one scrolls down to pm_clks.
> >>>>>> Okay, got it
> >>>>>>>
> >>>>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
> >>>>>>> here (not a simple NIU).
> >>>>>>
> >>>>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
> >>>>>> unblock PCIe/NSS changes getting merged, shall we use
> >>>>>> regmap_update_bits
> >>>>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
> >>>>>> probe function of the gcc driver itself as like sm8550 driver to get
> >>>>>> the
> >>>>>> changes merged?
> >>>>>>
> >>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
> >>>>>
> >>>>> Hi Dmitry,
> >>>>> Just curious to know if we could send out the next series with the
> >>>>> proposed approach if that holds good.
> >>>>
> >>>> The answer really depends on the structure of your hardware. The issue
> >>>> is that once you commit the device bindings,you have to support them
> >>>> forever. So, if you commit the NSS clock support without interconnects
> >>>> in place, you have to keep this ANOC/SNOC/etc code forever, even after
> >>>> you land the interconnect. So I'd suggest landing the icc driver first
> >>>> (or at least implementing and sending to the mailing list), so that we
> >>>> can see how all these pieces fit together.
> >>>
> >>> Hi Dmitry,
> >>> Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
> >>> NOC clocks have to be scaled. So if these clocks can be enabled in the
> >>> probe, there is no need for an interconnect driver at all. The same
> >>> applies to both ipq9574 and ipq5332 SoCs.
> >>>
> >>
> >> Hi Dmitry,
> >> Just curious to know if we can go ahead with the proposed solution of
> >> enabling the NOC clocks in the probe as these clocks need not be scaled
> >> in IPQ chipsets & hence there would be no need for an ICC driver in
> >> ipq9574 & ipq5332 targets.
> >
> > In the probe of which driver?
> GCC driver of ipq9574 & ipq5332 targets.
Would you need to handle these clocks additionally in the
suspend/resume path? Will this increase the power consumption of the
board?
Generally, I'd say this looks like a bad idea. Consider all the
troubles we are undergoing now while sorting out the NIU clocks on RPM
and RPMH platforms.
So, unless you are 100% sure that this is a permanent solution (like
AHB clocks being always on), I'd kindly suggest implementing the NoC
attachment properly. In the end, other Qualcomm platforms use ICC
drivers, so by following this pattern we will have more common code
paths.
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
2023-10-06 21:21 ` Dmitry Baryshkov
@ 2023-10-17 20:48 ` Devi Priya
-1 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-10-17 20:48 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 10/7/2023 2:51 AM, Dmitry Baryshkov wrote:
> On Thu, 5 Oct 2023 at 12:56, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>>
>>
>> On 10/5/2023 12:49 PM, Dmitry Baryshkov wrote:
>>> On Thu, 5 Oct 2023 at 09:26, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 9/22/2023 5:31 PM, Devi Priya wrote:
>>>>>
>>>>>
>>>>> On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
>>>>>> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
>>>>>> wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On 9/12/2023 7:38 PM, Devi Priya wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>>>>>>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>>>>>>>>> wrote:
>>>>>>>>>>
>>>>>>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>>>>>>>>> based
>>>>>>>>>> devices.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>>>>>>>> ---
>>>>>>>>>> Changes in V2:
>>>>>>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>>>>>>>>> - Added module_platform_driver
>>>>>>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>>>>>>>>> clocks as critical
>>>>>>>>>> & added pm_clk for nssnoc clocks
>>>>>>>>>> - Updated the uniphy clock names
>>>>>>>>>>
>>>>>>>>>> drivers/clk/qcom/Kconfig | 7 +
>>>>>>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>>>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
>>>>>>>>>> ++++++++++++++++++++++++++++++
>>>>>>>>>> 3 files changed, 3117 insertions(+)
>>>>>>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>>>
>>>>>>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>>>>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>>>>>>>>> --- a/drivers/clk/qcom/Kconfig
>>>>>>>>>> +++ b/drivers/clk/qcom/Kconfig
>>>>>>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>>>>>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>>>>>>>>> of ipq9574.
>>>>>>>>>>
>>>>>>>>>> +config IPQ_NSSCC_9574
>>>>>>>>>> + tristate "IPQ9574 NSS Clock Controller"
>>>>>>>>>> + depends on ARM64 || COMPILE_TEST
>>>>>>>>>> + depends on IPQ_GCC_9574
>>>>>>>>>> + help
>>>>>>>>>> + Support for NSS clock controller on ipq9574 devices.
>>>>>>>>>> +
>>>>>>>>>> config MSM_GCC_8660
>>>>>>>>>> tristate "MSM8660 Global Clock Controller"
>>>>>>>>>> depends on ARM || COMPILE_TEST
>>>>>>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>>>>>>>> index 4790c8cca426..3f084928962e 100644
>>>>>>>>>> --- a/drivers/clk/qcom/Makefile
>>>>>>>>>> +++ b/drivers/clk/qcom/Makefile
>>>>>>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>>>>>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>>>>>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>>>>>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>>>>>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>>>>>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>>>>>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>>>>>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>>>>>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>>> new file mode 100644
>>>>>>>>>> index 000000000000..65bdb449ae5f
>>>>>>>>>> --- /dev/null
>>>>>>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>>> @@ -0,0 +1,3109 @@
>>>>>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>>>>>>> +/*
>>>>>>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>>>>>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>>>>>>>>> reserved.
>>>>>>>>>> + */
>>>>>>>>>> +
>>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>>> +#include <linux/err.h>
>>>>>>>>>> +#include <linux/kernel.h>
>>>>>>>>>> +#include <linux/module.h>
>>>>>>>>>> +#include <linux/of.h>
>>>>>>>>>> +#include <linux/of_device.h>
>>>>>>>>>> +#include <linux/regmap.h>
>>>>>>>>>> +#include <linux/pm_clock.h>
>>>>>>>>>> +#include <linux/pm_runtime.h>
>>>>>>>>>> +
>>>>>>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>>>>>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>>>>>>>>> +
>>>>>>>>>> +#include "clk-alpha-pll.h"
>>>>>>>>>> +#include "clk-branch.h"
>>>>>>>>>> +#include "clk-pll.h"
>>>>>>>>>> +#include "clk-rcg.h"
>>>>>>>>>> +#include "clk-regmap.h"
>>>>>>>>>> +#include "clk-regmap-divider.h"
>>>>>>>>>> +#include "clk-regmap-mux.h"
>>>>>>>>>> +#include "common.h"
>>>>>>>>>> +#include "reset.h"
>>>>>>>>>> +
>>>>>>>>>> +/* Need to match the order of clocks in DT binding */
>>>>>>>>>> +enum {
>>>>>>>>>> + DT_NSSNOC_NSSCC_CLK,
>>>>>>>>>> + DT_NSSNOC_SNOC_CLK,
>>>>>>>>>> + DT_NSSNOC_SNOC_1_CLK,
>>>>>>>>>
>>>>>>>>> Not using the index makes it seem that these clocks are not used,
>>>>>>>>> until one scrolls down to pm_clks.
>>>>>>>> Okay, got it
>>>>>>>>>
>>>>>>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>>>>>>>>> here (not a simple NIU).
>>>>>>>>
>>>>>>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
>>>>>>>> unblock PCIe/NSS changes getting merged, shall we use
>>>>>>>> regmap_update_bits
>>>>>>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
>>>>>>>> probe function of the gcc driver itself as like sm8550 driver to get
>>>>>>>> the
>>>>>>>> changes merged?
>>>>>>>>
>>>>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>>>>>>>
>>>>>>> Hi Dmitry,
>>>>>>> Just curious to know if we could send out the next series with the
>>>>>>> proposed approach if that holds good.
>>>>>>
>>>>>> The answer really depends on the structure of your hardware. The issue
>>>>>> is that once you commit the device bindings,you have to support them
>>>>>> forever. So, if you commit the NSS clock support without interconnects
>>>>>> in place, you have to keep this ANOC/SNOC/etc code forever, even after
>>>>>> you land the interconnect. So I'd suggest landing the icc driver first
>>>>>> (or at least implementing and sending to the mailing list), so that we
>>>>>> can see how all these pieces fit together.
>>>>>
>>>>> Hi Dmitry,
>>>>> Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
>>>>> NOC clocks have to be scaled. So if these clocks can be enabled in the
>>>>> probe, there is no need for an interconnect driver at all. The same
>>>>> applies to both ipq9574 and ipq5332 SoCs.
>>>>>
>>>>
>>>> Hi Dmitry,
>>>> Just curious to know if we can go ahead with the proposed solution of
>>>> enabling the NOC clocks in the probe as these clocks need not be scaled
>>>> in IPQ chipsets & hence there would be no need for an ICC driver in
>>>> ipq9574 & ipq5332 targets.
>>>
>>> In the probe of which driver?
>> GCC driver of ipq9574 & ipq5332 targets.
>
> Would you need to handle these clocks additionally in the
> suspend/resume path? Will this increase the power consumption of the
> board?
>
> Generally, I'd say this looks like a bad idea. Consider all the
> troubles we are undergoing now while sorting out the NIU clocks on RPM
> and RPMH platforms.
> So, unless you are 100% sure that this is a permanent solution (like
> AHB clocks being always on), I'd kindly suggest implementing the NoC
> attachment properly. In the end, other Qualcomm platforms use ICC
> drivers, so by following this pattern we will have more common code
> paths.
>
Hi Dmitry,
Having these clocks always on seems to be a permanent solution and
we do not foresee any issues in our SoCs.
Thanks,
Devi Priya
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
@ 2023-10-17 20:48 ` Devi Priya
0 siblings, 0 replies; 70+ messages in thread
From: Devi Priya @ 2023-10-17 20:48 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, agross, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, catalin.marinas, will, p.zabel,
richardcochran, arnd, geert+renesas, nfraprado, rafal, peng.fan,
linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, netdev, quic_saahtoma
On 10/7/2023 2:51 AM, Dmitry Baryshkov wrote:
> On Thu, 5 Oct 2023 at 12:56, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>
>>
>>
>> On 10/5/2023 12:49 PM, Dmitry Baryshkov wrote:
>>> On Thu, 5 Oct 2023 at 09:26, Devi Priya <quic_devipriy@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 9/22/2023 5:31 PM, Devi Priya wrote:
>>>>>
>>>>>
>>>>> On 9/20/2023 1:50 PM, Dmitry Baryshkov wrote:
>>>>>> On Wed, 20 Sept 2023 at 09:39, Devi Priya <quic_devipriy@quicinc.com>
>>>>>> wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On 9/12/2023 7:38 PM, Devi Priya wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 8/25/2023 5:14 PM, Dmitry Baryshkov wrote:
>>>>>>>>> On Fri, 25 Aug 2023 at 12:15, Devi Priya <quic_devipriy@quicinc.com>
>>>>>>>>> wrote:
>>>>>>>>>>
>>>>>>>>>> Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574
>>>>>>>>>> based
>>>>>>>>>> devices.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>>>>>>>> ---
>>>>>>>>>> Changes in V2:
>>>>>>>>>> - Added depends on ARM64 || COMPILE_TEST in Kconfig
>>>>>>>>>> - Added module_platform_driver
>>>>>>>>>> - Dropped patch [2/6] - clk: qcom: gcc-ipq9574: Mark nssnoc
>>>>>>>>>> clocks as critical
>>>>>>>>>> & added pm_clk for nssnoc clocks
>>>>>>>>>> - Updated the uniphy clock names
>>>>>>>>>>
>>>>>>>>>> drivers/clk/qcom/Kconfig | 7 +
>>>>>>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>>>>>>> drivers/clk/qcom/nsscc-ipq9574.c | 3109
>>>>>>>>>> ++++++++++++++++++++++++++++++
>>>>>>>>>> 3 files changed, 3117 insertions(+)
>>>>>>>>>> create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>>>
>>>>>>>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>>>>>>>> index bd9bfb11b328..3ecc11e2c8e3 100644
>>>>>>>>>> --- a/drivers/clk/qcom/Kconfig
>>>>>>>>>> +++ b/drivers/clk/qcom/Kconfig
>>>>>>>>>> @@ -203,6 +203,13 @@ config IPQ_GCC_9574
>>>>>>>>>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>>>>>>>>>> of ipq9574.
>>>>>>>>>>
>>>>>>>>>> +config IPQ_NSSCC_9574
>>>>>>>>>> + tristate "IPQ9574 NSS Clock Controller"
>>>>>>>>>> + depends on ARM64 || COMPILE_TEST
>>>>>>>>>> + depends on IPQ_GCC_9574
>>>>>>>>>> + help
>>>>>>>>>> + Support for NSS clock controller on ipq9574 devices.
>>>>>>>>>> +
>>>>>>>>>> config MSM_GCC_8660
>>>>>>>>>> tristate "MSM8660 Global Clock Controller"
>>>>>>>>>> depends on ARM || COMPILE_TEST
>>>>>>>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>>>>>>>> index 4790c8cca426..3f084928962e 100644
>>>>>>>>>> --- a/drivers/clk/qcom/Makefile
>>>>>>>>>> +++ b/drivers/clk/qcom/Makefile
>>>>>>>>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>>>>>>>>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>>>>>>>>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>>>>>>>>>> obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>>>>>>>>> +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
>>>>>>>>>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>>>>>>>>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>>>>>>>>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>>>>>>>>>> diff --git a/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>>> b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>>> new file mode 100644
>>>>>>>>>> index 000000000000..65bdb449ae5f
>>>>>>>>>> --- /dev/null
>>>>>>>>>> +++ b/drivers/clk/qcom/nsscc-ipq9574.c
>>>>>>>>>> @@ -0,0 +1,3109 @@
>>>>>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>>>>>>> +/*
>>>>>>>>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>>>>>>>>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
>>>>>>>>>> reserved.
>>>>>>>>>> + */
>>>>>>>>>> +
>>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>>> +#include <linux/err.h>
>>>>>>>>>> +#include <linux/kernel.h>
>>>>>>>>>> +#include <linux/module.h>
>>>>>>>>>> +#include <linux/of.h>
>>>>>>>>>> +#include <linux/of_device.h>
>>>>>>>>>> +#include <linux/regmap.h>
>>>>>>>>>> +#include <linux/pm_clock.h>
>>>>>>>>>> +#include <linux/pm_runtime.h>
>>>>>>>>>> +
>>>>>>>>>> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
>>>>>>>>>> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
>>>>>>>>>> +
>>>>>>>>>> +#include "clk-alpha-pll.h"
>>>>>>>>>> +#include "clk-branch.h"
>>>>>>>>>> +#include "clk-pll.h"
>>>>>>>>>> +#include "clk-rcg.h"
>>>>>>>>>> +#include "clk-regmap.h"
>>>>>>>>>> +#include "clk-regmap-divider.h"
>>>>>>>>>> +#include "clk-regmap-mux.h"
>>>>>>>>>> +#include "common.h"
>>>>>>>>>> +#include "reset.h"
>>>>>>>>>> +
>>>>>>>>>> +/* Need to match the order of clocks in DT binding */
>>>>>>>>>> +enum {
>>>>>>>>>> + DT_NSSNOC_NSSCC_CLK,
>>>>>>>>>> + DT_NSSNOC_SNOC_CLK,
>>>>>>>>>> + DT_NSSNOC_SNOC_1_CLK,
>>>>>>>>>
>>>>>>>>> Not using the index makes it seem that these clocks are not used,
>>>>>>>>> until one scrolls down to pm_clks.
>>>>>>>> Okay, got it
>>>>>>>>>
>>>>>>>>> BTW: The NSSNOC_SNOC clocks make it look like there is an interconnect
>>>>>>>>> here (not a simple NIU).
>>>>>>>>
>>>>>>>> Hi Dmitry, We are exploring on the ICC driver. In the meantime to
>>>>>>>> unblock PCIe/NSS changes getting merged, shall we use
>>>>>>>> regmap_update_bits
>>>>>>>> and turn on the critical NSSNOC clocks, ANOC & SNOC pcie clocks in the
>>>>>>>> probe function of the gcc driver itself as like sm8550 driver to get
>>>>>>>> the
>>>>>>>> changes merged?
>>>>>>>>
>>>>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c#n3347
>>>>>>>
>>>>>>> Hi Dmitry,
>>>>>>> Just curious to know if we could send out the next series with the
>>>>>>> proposed approach if that holds good.
>>>>>>
>>>>>> The answer really depends on the structure of your hardware. The issue
>>>>>> is that once you commit the device bindings,you have to support them
>>>>>> forever. So, if you commit the NSS clock support without interconnects
>>>>>> in place, you have to keep this ANOC/SNOC/etc code forever, even after
>>>>>> you land the interconnect. So I'd suggest landing the icc driver first
>>>>>> (or at least implementing and sending to the mailing list), so that we
>>>>>> can see how all these pieces fit together.
>>>>>
>>>>> Hi Dmitry,
>>>>> Unlike MSM chipsets, IPQ chipsets does not have any use case wherein the
>>>>> NOC clocks have to be scaled. So if these clocks can be enabled in the
>>>>> probe, there is no need for an interconnect driver at all. The same
>>>>> applies to both ipq9574 and ipq5332 SoCs.
>>>>>
>>>>
>>>> Hi Dmitry,
>>>> Just curious to know if we can go ahead with the proposed solution of
>>>> enabling the NOC clocks in the probe as these clocks need not be scaled
>>>> in IPQ chipsets & hence there would be no need for an ICC driver in
>>>> ipq9574 & ipq5332 targets.
>>>
>>> In the probe of which driver?
>> GCC driver of ipq9574 & ipq5332 targets.
>
> Would you need to handle these clocks additionally in the
> suspend/resume path? Will this increase the power consumption of the
> board?
>
> Generally, I'd say this looks like a bad idea. Consider all the
> troubles we are undergoing now while sorting out the NIU clocks on RPM
> and RPMH platforms.
> So, unless you are 100% sure that this is a permanent solution (like
> AHB clocks being always on), I'd kindly suggest implementing the NoC
> attachment properly. In the end, other Qualcomm platforms use ICC
> drivers, so by following this pattern we will have more common code
> paths.
>
Hi Dmitry,
Having these clocks always on seems to be a permanent solution and
we do not foresee any issues in our SoCs.
Thanks,
Devi Priya
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^ permalink raw reply [flat|nested] 70+ messages in thread
end of thread, other threads:[~2023-10-17 20:50 UTC | newest]
Thread overview: 70+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-25 9:12 [PATCH V2 0/7] Add NSS clock controller support for IPQ9574 Devi Priya
2023-08-25 9:12 ` Devi Priya
2023-08-25 9:12 ` [PATCH V2 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574 Devi Priya
2023-08-25 9:12 ` Devi Priya
2023-08-25 20:58 ` Stephen Boyd
2023-08-25 20:58 ` Stephen Boyd
2023-08-29 3:28 ` Devi Priya
2023-08-29 3:28 ` Devi Priya
2023-08-25 9:12 ` [PATCH V2 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX Devi Priya
2023-08-25 9:12 ` Devi Priya
2023-08-25 12:27 ` Krzysztof Kozlowski
2023-08-25 12:27 ` Krzysztof Kozlowski
2023-08-25 12:28 ` Krzysztof Kozlowski
2023-08-25 12:28 ` Krzysztof Kozlowski
2023-08-25 9:12 ` [PATCH V2 3/7] clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock Devi Priya
2023-08-25 9:12 ` Devi Priya
2023-09-01 16:15 ` Kathiravan T
2023-09-01 16:15 ` Kathiravan T
2023-08-25 9:12 ` [PATCH V2 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions Devi Priya
2023-08-25 9:12 ` Devi Priya
2023-08-25 10:14 ` Rob Herring
2023-08-25 10:14 ` Rob Herring
2023-08-25 12:30 ` Krzysztof Kozlowski
2023-08-25 12:30 ` Krzysztof Kozlowski
2023-09-13 8:28 ` Krzysztof Kozlowski
2023-09-13 8:28 ` Krzysztof Kozlowski
2023-08-25 9:12 ` [PATCH V2 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574 Devi Priya
2023-08-25 9:12 ` Devi Priya
2023-08-25 11:44 ` Dmitry Baryshkov
2023-08-25 11:44 ` Dmitry Baryshkov
2023-09-12 14:08 ` Devi Priya
2023-09-12 14:08 ` Devi Priya
2023-09-20 6:39 ` Devi Priya
2023-09-20 6:39 ` Devi Priya
2023-09-20 8:20 ` Dmitry Baryshkov
2023-09-20 8:20 ` Dmitry Baryshkov
2023-09-22 12:01 ` Devi Priya
2023-09-22 12:01 ` Devi Priya
2023-10-05 6:25 ` Devi Priya
2023-10-05 6:25 ` Devi Priya
2023-10-05 7:19 ` Dmitry Baryshkov
2023-10-05 7:19 ` Dmitry Baryshkov
2023-10-05 9:56 ` Devi Priya
2023-10-05 9:56 ` Devi Priya
2023-10-06 21:21 ` Dmitry Baryshkov
2023-10-06 21:21 ` Dmitry Baryshkov
2023-10-17 20:48 ` Devi Priya
2023-10-17 20:48 ` Devi Priya
2023-08-28 12:35 ` Konrad Dybcio
2023-08-28 12:35 ` Konrad Dybcio
2023-08-29 3:42 ` Devi Priya
2023-08-29 3:42 ` Devi Priya
2023-08-25 9:12 ` [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node Devi Priya
2023-08-25 9:12 ` Devi Priya
2023-08-25 11:28 ` Dmitry Baryshkov
2023-08-25 11:28 ` Dmitry Baryshkov
2023-09-13 3:32 ` Devi Priya
2023-09-13 3:32 ` Devi Priya
2023-09-13 8:23 ` Geert Uytterhoeven
2023-09-13 8:23 ` Geert Uytterhoeven
2023-09-13 8:26 ` Krzysztof Kozlowski
2023-09-13 8:26 ` Krzysztof Kozlowski
2023-09-13 8:38 ` Geert Uytterhoeven
2023-09-13 8:38 ` Geert Uytterhoeven
2023-09-13 8:43 ` Konrad Dybcio
2023-09-13 8:43 ` Konrad Dybcio
2023-09-13 8:55 ` Krzysztof Kozlowski
2023-09-13 8:55 ` Krzysztof Kozlowski
2023-08-25 9:12 ` [PATCH V2 7/7] arm64: defconfig: Build NSS Clock Controller driver for IPQ9574 Devi Priya
2023-08-25 9:12 ` Devi Priya
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