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From: Julien Grall <julien.grall@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
	Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org,
	Shanker Donthineni <shankerd@codeaurora.org>,
	Vijay Kilari <vijay.kilari@gmail.com>
Subject: Re: [PATCH v2 15/27] ARM: vITS: introduce translation table walks
Date: Fri, 24 Mar 2017 13:00:27 +0000	[thread overview]
Message-ID: <66a32eeb-dea1-e0b5-e3f7-960151e0520e@arm.com> (raw)
In-Reply-To: <20170316112030.20419-16-andre.przywara@arm.com>

Hi Andre,

On 03/16/2017 11:20 AM, Andre Przywara wrote:
> The ITS stores the target (v)CPU and the (virtual) LPI number in tables.
> Introduce functions to walk those tables and translate an device ID -
> event ID pair into a pair of virtual LPI and vCPU.
> Since the final interrupt translation tables can be smaller than a page,
> we map them on demand (which is cheap on arm64). Also we take care of
> the locking on the way, since we can't easily protect those ITTs from
> being altered by the guest.
>
> To allow compiling without warnings, we declare two functions as
> non-static for the moment.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  xen/arch/arm/vgic-v3-its.c | 135 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 135 insertions(+)
>
> diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
> index 5337638..267a573 100644
> --- a/xen/arch/arm/vgic-v3-its.c
> +++ b/xen/arch/arm/vgic-v3-its.c
> @@ -62,6 +62,141 @@ struct vits_itte
>      uint16_t collection;
>  };
>
> +#define UNMAPPED_COLLECTION      ((uint16_t)~0)
> +
> +/* Must be called with the ITS lock held. */

This is a call for an ASSERT in the function.

> +static struct vcpu *get_vcpu_from_collection(struct virt_its *its, int collid)

s/int/unsigned int/

> +{
> +    uint16_t vcpu_id;
> +
> +    if ( collid >= its->max_collections )
> +        return NULL;
> +
> +    vcpu_id = its->coll_table[collid];
> +    if ( vcpu_id == UNMAPPED_COLLECTION || vcpu_id >= its->d->max_vcpus )
> +        return NULL;
> +
> +    return its->d->vcpu[vcpu_id];
> +}
> +
> +#define DEV_TABLE_ITT_ADDR(x) ((x) & GENMASK(51, 8))
> +#define DEV_TABLE_ITT_SIZE(x) (BIT(((x) & GENMASK(7, 0)) + 1))
> +#define DEV_TABLE_ENTRY(addr, bits)                     \
> +        (((addr) & GENMASK(51, 8)) | (((bits) - 1) & GENMASK(7, 0)))

The layout of dev_table[...] really needs to be explained. It took me 
quite a while to understand how it works. For instance why you skip the 
first 8 bits for the address...

> +
> +static paddr_t get_itte_address(struct virt_its *its,
> +                                uint32_t devid, uint32_t evid)
> +{

I was expected to see the support of two-level page table for the vITS. 
Any plan for that?

> +    paddr_t addr;
> +
> +    if ( devid >= its->max_devices )
> +        return ~0;

Please don't hardcode invalid address and use INVALID_PADDR.

> +
> +    if ( evid >= DEV_TABLE_ITT_SIZE(its->dev_table[devid]) )
> +        return ~0;

Ditto.

> +
> +    addr = DEV_TABLE_ITT_ADDR(its->dev_table[devid]);

You read dev_table[...] multiple time. What prevents someone to modify 
dev_table after you did someone sanity check?

It would be safer to do a read_atomic(..) at the beginning and use a 
temporary variable.

> +
> +    return addr + evid * sizeof(struct vits_itte);
> +}
> +
> +/*
> + * Looks up a given deviceID/eventID pair on an ITS and returns a pointer to
> + * the corresponding ITTE. This maps the respective guest page into Xen.
> + * Once finished with handling the ITTE, call put_devid_evid() to unmap
> + * the page again.
> + * Must be called with the ITS lock held.

This is a call for an ASSERT in the code.

> + */
> +static struct vits_itte *get_devid_evid(struct virt_its *its,
> +                                        uint32_t devid, uint32_t evid)

The naming of the function is confusing. It doesn't look up a device 
ID/event ID but an IIT. So I would rename it to find_itte.

> +{
> +    paddr_t addr = get_itte_address(its, devid, evid);
> +
> +    if ( addr == ~0 )


Please use INVALID_PADDR.

> +        return NULL;
> +
> +    return map_guest_pages(its->d, addr, 1);
> +}
> +
> +/* Must be called with the ITS lock held. */
> +static void put_devid_evid(struct virt_its *its, struct vits_itte *itte)
> +{
> +    unmap_guest_pages(itte, 1);
> +}
> +
> +/*
> + * Queries the collection and device tables to get the vCPU and virtual
> + * LPI number for a given guest event. This takes care of mapping the
> + * respective tables and validating the values, since we can't efficiently
> + * protect the ITTs with their less-than-page-size granularity.
> + * Takes and drops the its_lock.

I am not sure to understand the usefulness of "takes and drops the 
its_lock".

> + */
> +bool read_itte(struct virt_its *its, uint32_t devid, uint32_t evid,
> +               struct vcpu **vcpu, uint32_t *vlpi)
> +{
> +    struct vits_itte *itte;
> +    int collid;
> +    uint32_t _vlpi;
> +    struct vcpu *_vcpu;
> +
> +    spin_lock(&its->its_lock);

Do we expect multiple vCPU calling read_itte at the same time? This 
needs to be clarify in the comments because this current function is not 
scalable.

> +    itte = get_devid_evid(its, devid, evid);
> +    if ( !itte )
> +    {
> +        spin_unlock(&its->its_lock);
> +        return false;
> +    }
> +    collid = itte->collection;
> +    _vlpi = itte->vlpi;
> +    put_devid_evid(its, itte);
> +
> +    _vcpu = get_vcpu_from_collection(its, collid);
> +    spin_unlock(&its->its_lock);
> +
> +    if ( !_vcpu )
> +        return false;
> +
> +    if ( collid >= its->max_collections )
> +        return false;

No need for this check. It is already done in get_vcpu_from_collection.

> +
> +    *vcpu = _vcpu;
> +    *vlpi = _vlpi;
> +
> +    return true;
> +}
> +
> +#define SKIP_LPI_UPDATE 1
> +bool write_itte(struct virt_its *its, uint32_t devid, uint32_t evid,
> +                uint32_t collid, uint32_t vlpi, struct vcpu **vcpu)
> +{
> +    struct vits_itte *itte;
> +
> +    if ( collid >= its->max_collections )
> +        return false;
> +
> +    /* TODO: validate vlpi */

This TODO needs to be fixed as soon as possible.

> +
> +    spin_lock(&its->its_lock);
> +    itte = get_devid_evid(its, devid, evid);
> +    if ( !itte )
> +    {
> +        spin_unlock(&its->its_lock);
> +        return false;
> +    }
> +
> +    itte->collection = collid;
> +    if ( vlpi != SKIP_LPI_UPDATE )
> +        itte->vlpi = vlpi;
> +
> +    if ( vcpu )
> +        *vcpu = get_vcpu_from_collection(its, collid);
> +
> +    put_devid_evid(its, itte);
> +    spin_unlock(&its->its_lock);
> +
> +    return true;
> +}
> +
>  /**************************************
>   * Functions that handle ITS commands *
>   **************************************/
>

Cheers,

-- 
Julien Grall

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  reply	other threads:[~2017-03-24 13:00 UTC|newest]

Thread overview: 119+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-16 11:20 [PATCH v2 00/27] arm64: Dom0 ITS emulation Andre Przywara
2017-03-16 11:20 ` [PATCH v2 01/27] ARM: GICv3 ITS: parse and store ITS subnodes from hardware DT Andre Przywara
2017-03-21 20:17   ` Julien Grall
2017-03-23 10:57     ` Andre Przywara
2017-03-23 17:32       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 02/27] ARM: GICv3: allocate LPI pending and property table Andre Przywara
2017-03-21 21:23   ` Julien Grall
2017-03-23 14:40     ` Andre Przywara
2017-03-23 17:42       ` Julien Grall
2017-03-23 17:45         ` Stefano Stabellini
2017-03-23 17:49           ` Julien Grall
2017-03-23 18:01             ` Stefano Stabellini
2017-03-23 18:21               ` Andre Przywara
2017-03-24 11:45                 ` Julien Grall
2017-03-24 17:22                   ` Stefano Stabellini
2017-03-21 22:57   ` Stefano Stabellini
2017-03-21 23:08     ` André Przywara
2017-03-21 23:27       ` Stefano Stabellini
2017-03-23 10:50         ` Andre Przywara
2017-03-23 17:47           ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 03/27] ARM: GICv3 ITS: allocate device and collection table Andre Przywara
2017-03-21 23:29   ` Stefano Stabellini
2017-03-22 13:52   ` Julien Grall
2017-03-22 16:08     ` André Przywara
2017-03-22 16:33       ` Julien Grall
2017-03-29 13:58         ` Andre Przywara
2017-03-16 11:20 ` [PATCH v2 04/27] ARM: GICv3 ITS: map ITS command buffer Andre Przywara
2017-03-21 23:48   ` Stefano Stabellini
2017-03-22 15:23   ` Julien Grall
2017-03-22 16:31     ` André Przywara
2017-03-22 16:41       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 05/27] ARM: GICv3 ITS: introduce ITS command handling Andre Przywara
2017-03-16 15:05   ` Shanker Donthineni
2017-03-16 15:18     ` Andre Przywara
2017-03-22  0:02   ` Stefano Stabellini
2017-03-22 15:59   ` Julien Grall
2017-04-03 10:58     ` Andre Przywara
2017-04-03 11:23       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 06/27] ARM: GICv3 ITS: introduce device mapping Andre Przywara
2017-03-22 17:29   ` Julien Grall
2017-04-03 20:08     ` Andre Przywara
2017-04-03 20:41       ` Julien Grall
2017-04-04  9:57         ` Andre Przywara
2017-03-22 22:45   ` Stefano Stabellini
2017-04-03 19:45     ` Andre Przywara
2017-03-30 11:17   ` Vijay Kilari
2017-03-16 11:20 ` [PATCH v2 07/27] ARM: arm64: activate atomic 64-bit accessors Andre Przywara
2017-03-22 17:30   ` Julien Grall
2017-03-22 22:49     ` Stefano Stabellini
2017-03-16 11:20 ` [PATCH v2 08/27] ARM: GICv3 ITS: introduce host LPI array Andre Przywara
2017-03-22 23:38   ` Stefano Stabellini
2017-03-23  8:48     ` Julien Grall
2017-03-23 10:21     ` Andre Przywara
2017-03-23 17:52       ` Stefano Stabellini
2017-03-24 11:54         ` Julien Grall
2017-03-23 19:08   ` Julien Grall
2017-04-03 19:30     ` Andre Przywara
2017-04-03 20:13       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 09/27] ARM: GICv3: introduce separate pending_irq structs for LPIs Andre Przywara
2017-03-22 23:44   ` Stefano Stabellini
2017-03-23 20:08     ` André Przywara
2017-03-24 10:59       ` Julien Grall
2017-03-24 11:40   ` Julien Grall
2017-03-24 15:50     ` Andre Przywara
2017-03-24 16:19       ` Julien Grall
2017-03-24 17:26       ` Stefano Stabellini
2017-03-27  9:02         ` Andre Przywara
2017-03-27 14:01           ` Julien Grall
2017-03-27 17:44             ` Stefano Stabellini
2017-03-27 17:49               ` Julien Grall
2017-03-27 18:39                 ` Stefano Stabellini
2017-03-27 21:24                   ` Julien Grall
2017-03-28  7:58                   ` Jan Beulich
2017-03-28 13:12                     ` Julien Grall
2017-03-28 13:34                       ` Jan Beulich
2017-03-16 11:20 ` [PATCH v2 10/27] ARM: GICv3: forward pending LPIs to guests Andre Przywara
2017-03-24 12:03   ` Julien Grall
2017-04-03 14:18     ` Andre Przywara
2017-04-04 11:49       ` Julien Grall
2017-04-04 12:51         ` Andre Przywara
2017-04-04 12:50           ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 11/27] ARM: GICv3: enable ITS and LPIs on the host Andre Przywara
2017-03-16 11:20 ` [PATCH v2 12/27] ARM: vGICv3: handle virtual LPI pending and property tables Andre Przywara
2017-03-24 12:09   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 13/27] ARM: vGICv3: Handle disabled LPIs Andre Przywara
2017-03-24 12:20   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 14/27] ARM: vGICv3: introduce basic ITS emulation bits Andre Przywara
2017-03-16 16:25   ` Shanker Donthineni
2017-03-20 12:17     ` Vijay Kilari
2017-03-24 12:41   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 15/27] ARM: vITS: introduce translation table walks Andre Przywara
2017-03-24 13:00   ` Julien Grall [this message]
2017-04-03 18:25     ` Andre Przywara
2017-04-04 15:59       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 16/27] ARM: vITS: handle CLEAR command Andre Przywara
2017-03-24 14:27   ` Julien Grall
2017-03-24 15:53     ` Andre Przywara
2017-03-24 17:17       ` Stefano Stabellini
2017-03-27  8:44         ` Andre Przywara
2017-03-27 14:12           ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 17/27] ARM: vITS: handle INT command Andre Przywara
2017-03-24 14:38   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 18/27] ARM: vITS: handle MAPC command Andre Przywara
2017-03-16 11:20 ` [PATCH v2 19/27] ARM: vITS: handle MAPD command Andre Przywara
2017-03-24 14:41   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 20/27] ARM: vITS: handle MAPTI command Andre Przywara
2017-03-24 14:54   ` Julien Grall
2017-04-03 18:47     ` Andre Przywara
2017-03-16 11:20 ` [PATCH v2 21/27] ARM: vITS: handle MOVI command Andre Przywara
2017-03-24 15:00   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 22/27] ARM: vITS: handle DISCARD command Andre Przywara
2017-03-16 11:20 ` [PATCH v2 23/27] ARM: vITS: handle INV command Andre Przywara
2017-03-16 11:20 ` [PATCH v2 24/27] ARM: vITS: handle INVALL command Andre Przywara
2017-03-24 15:12   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 25/27] ARM: vITS: create and initialize virtual ITSes for Dom0 Andre Przywara
2017-03-24 15:18   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 26/27] ARM: vITS: create ITS subnodes for Dom0 DT Andre Przywara
2017-03-16 11:20 ` [PATCH v2 27/27] ARM: vGIC: advertise LPI support Andre Przywara
2017-03-24 15:25   ` Julien Grall

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