* [PATCH] dt-bindings: riscv: update microchip.yaml's maintainership
@ 2022-08-29 13:41 ` Conor Dooley
0 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2022-08-29 13:41 UTC (permalink / raw)
To: Conor Dooley, Daire McNamara, Rob Herring, Krzysztof Kozlowski
Cc: Cyril Jean, Lewis Hanly, Paul Walmsley, Palmer Dabbelt,
Albert Ou, linux-riscv, devicetree, linux-kernel
Daire and I are the platform maintainers for Microchip's RISC-V
FPGAs. Update the maintainers in microchip.yaml to reflect this and
explicitly add the binding to the SoC's MAINTAINERS entry.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Two patches seemed overkill for this, but scream and I will split them.
I figured I would take this for 6.1 myself on top of my other changes
to microchip.yaml.
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 4 ++--
MAINTAINERS | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 37f97ee4fe46..9eaa21769457 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC-based boards
maintainers:
- - Cyril Jean <Cyril.Jean@microchip.com>
- - Lewis Hanly <lewis.hanly@microchip.com>
+ - Conor Dooley <conor.dooley@microchip.com>
+ - Daire McNamara <daire.mcnamara@microchip.com>
description:
Microchip PolarFire SoC-based boards
diff --git a/MAINTAINERS b/MAINTAINERS
index cc549debe20c..7d788e064390 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17572,6 +17572,7 @@ F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml
F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
+F: Documentation/devicetree/bindings/riscv/microchip.yaml
F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
F: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
--
2.36.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] dt-bindings: riscv: update microchip.yaml's maintainership
@ 2022-08-29 13:41 ` Conor Dooley
0 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2022-08-29 13:41 UTC (permalink / raw)
To: Conor Dooley, Daire McNamara, Rob Herring, Krzysztof Kozlowski
Cc: Cyril Jean, Lewis Hanly, Paul Walmsley, Palmer Dabbelt,
Albert Ou, linux-riscv, devicetree, linux-kernel
Daire and I are the platform maintainers for Microchip's RISC-V
FPGAs. Update the maintainers in microchip.yaml to reflect this and
explicitly add the binding to the SoC's MAINTAINERS entry.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Two patches seemed overkill for this, but scream and I will split them.
I figured I would take this for 6.1 myself on top of my other changes
to microchip.yaml.
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 4 ++--
MAINTAINERS | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 37f97ee4fe46..9eaa21769457 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC-based boards
maintainers:
- - Cyril Jean <Cyril.Jean@microchip.com>
- - Lewis Hanly <lewis.hanly@microchip.com>
+ - Conor Dooley <conor.dooley@microchip.com>
+ - Daire McNamara <daire.mcnamara@microchip.com>
description:
Microchip PolarFire SoC-based boards
diff --git a/MAINTAINERS b/MAINTAINERS
index cc549debe20c..7d788e064390 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17572,6 +17572,7 @@ F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml
F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
+F: Documentation/devicetree/bindings/riscv/microchip.yaml
F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
F: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] dt-bindings: riscv: update microchip.yaml's maintainership
2022-08-29 13:41 ` Conor Dooley
@ 2022-08-30 9:49 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 4+ messages in thread
From: Krzysztof Kozlowski @ 2022-08-30 9:49 UTC (permalink / raw)
To: Conor Dooley, Daire McNamara, Rob Herring, Krzysztof Kozlowski
Cc: Cyril Jean, Lewis Hanly, Paul Walmsley, Palmer Dabbelt,
Albert Ou, linux-riscv, devicetree, linux-kernel
On 29/08/2022 16:41, Conor Dooley wrote:
> Daire and I are the platform maintainers for Microchip's RISC-V
> FPGAs. Update the maintainers in microchip.yaml to reflect this and
> explicitly add the binding to the SoC's MAINTAINERS entry.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Two patches seemed overkill for this, but scream and I will split them.
> I figured I would take this for 6.1 myself on top of my other changes
> to microchip.yaml.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] dt-bindings: riscv: update microchip.yaml's maintainership
@ 2022-08-30 9:49 ` Krzysztof Kozlowski
0 siblings, 0 replies; 4+ messages in thread
From: Krzysztof Kozlowski @ 2022-08-30 9:49 UTC (permalink / raw)
To: Conor Dooley, Daire McNamara, Rob Herring, Krzysztof Kozlowski
Cc: Cyril Jean, Lewis Hanly, Paul Walmsley, Palmer Dabbelt,
Albert Ou, linux-riscv, devicetree, linux-kernel
On 29/08/2022 16:41, Conor Dooley wrote:
> Daire and I are the platform maintainers for Microchip's RISC-V
> FPGAs. Update the maintainers in microchip.yaml to reflect this and
> explicitly add the binding to the SoC's MAINTAINERS entry.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Two patches seemed overkill for this, but scream and I will split them.
> I figured I would take this for 6.1 myself on top of my other changes
> to microchip.yaml.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-08-30 9:49 UTC | newest]
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2022-08-29 13:41 [PATCH] dt-bindings: riscv: update microchip.yaml's maintainership Conor Dooley
2022-08-29 13:41 ` Conor Dooley
2022-08-30 9:49 ` Krzysztof Kozlowski
2022-08-30 9:49 ` Krzysztof Kozlowski
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