[Intel-gfx] [PATCH v2 00/12] Minor revid/stepping and workaround cleanup

[Intel-gfx] [PATCH v2 00/12] Minor revid/stepping and workaround cleanup

[Matt Roper]

PCI revision IDs don't always map to GT and display IP steppings in an
intuitive/sensible way.  On many of our recent platforms we've switched
to using revid->stepping lookup tables with the infrastructure in
intel_step.c to handle stepping lookups and comparisons.  This series
converts several of our older platforms over to the same table-based
scheme; this is good not only for consistency, but also because some
upcoming DMC work will rely on table-based lookups.  Going forward the
only place that revision ID's should really get used directly is when
checking to see if we're running on pre-production hardware.

Note:  I haven't added the stepping tables for CFL and its derivatives
(WHL, AML) yet since there are so many different variants and the
steppings work a bit strangely on some of them.  We don't have any
stepping-specific workarounds on these platforms, so the tables aren't
necessary until Anusha's DMC work arrives; I'll let her determine the
best way to handle the tables for those.  Ditto for CML.

Let's also take the opportunity to drop a bit of effectively dead code
in the workarounds file too.

v2:
 - Include an already-reviewed patch from Anusha's DMC series as the
   first patch here that changes the naming of the revision ID tables,
   and then adjust the naming of the new tables I add here to follow the
   same convention.
 - Drop the pre-production revisions for all gen11 and earlier
   platforms; we're past the point where we usually drop the
   pre-production support.  intel_detect_preproduction_hw() is updated
   with the proper revids for ICL to ensure we print an error and taint
   the kernel if the kernel is loaded on a pre-production platform.
 - ICL workarounds that only apply to pre-production steppings are
   dropped.
 - For platforms where GT stepping is always the same as display
   stepping, we use a macro to assign them both at once to make it more
   obvious how the platform works.
 - Stepping tables for BXT and GLK are added.  They're completely unused
   in our current code (we have no stepping-specific workarounds), but
   some DMC patches from Anusha will arrive shortly that require these.
   Note that the BXT revision macros we had previously were completely
   wrong; it's a good thing they weren't actually being used for
   anything.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>

Anusha Srivatsa (1):
  drm/i915/step: s/<platform>_revid_tbl/<platform>_revids

Matt Roper (11):
  drm/i915: Make pre-production detection use direct revid comparison
  drm/i915/skl: Use revid->stepping tables
  drm/i915/kbl: Drop pre-production revision from stepping table
  drm/i915/bxt: Use revid->stepping tables
  drm/i915/glk: Use revid->stepping tables
  drm/i915/icl: Use revid->stepping tables
  drm/i915/jsl_ehl: Use revid->stepping tables
  drm/i915/rkl: Use revid->stepping tables
  drm/i915/dg1: Use revid->stepping tables
  drm/i915/cnl: Drop all workarounds
  drm/i915/icl: Drop workarounds that only apply to pre-production
    steppings

 .../drm/i915/display/intel_display_power.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |   4 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c   |   2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 108 ++----------------
 drivers/gpu/drm/i915/i915_drv.c               |   9 +-
 drivers/gpu/drm/i915/i915_drv.h               |  79 ++-----------
 drivers/gpu/drm/i915/intel_pm.c               |   2 +-
 drivers/gpu/drm/i915/intel_step.c             | 104 ++++++++++++++---
 drivers/gpu/drm/i915/intel_step.h             |   4 +
 10 files changed, 119 insertions(+), 197 deletions(-)

-- 
2.25.4

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[Intel-gfx] [PATCH v2 01/12] drm/i915/step: s/<platform>_revid_tbl/<platform>_revids

[Matt Roper]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Simplify the stepping info array name.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_step.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index ba9479a67521..93ccd42f2514 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -26,7 +26,7 @@ static const struct intel_step_info kbl_revids[] = {
 	[7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },
 };
 
-static const struct intel_step_info tgl_uy_revid_step_tbl[] = {
+static const struct intel_step_info tgl_uy_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
 	[2] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
@@ -34,12 +34,12 @@ static const struct intel_step_info tgl_uy_revid_step_tbl[] = {
 };
 
 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
-static const struct intel_step_info tgl_revid_step_tbl[] = {
+static const struct intel_step_info tgl_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
 };
 
-static const struct intel_step_info adls_revid_step_tbl[] = {
+static const struct intel_step_info adls_revids[] = {
 	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
 	[0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
@@ -47,7 +47,7 @@ static const struct intel_step_info adls_revid_step_tbl[] = {
 	[0xC] = { .gt_step = STEP_D0, .display_step = STEP_C0 },
 };
 
-static const struct intel_step_info adlp_revid_step_tbl[] = {
+static const struct intel_step_info adlp_revids[] = {
 	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
 	[0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
@@ -62,17 +62,17 @@ void intel_step_init(struct drm_i915_private *i915)
 	struct intel_step_info step = {};
 
 	if (IS_ALDERLAKE_P(i915)) {
-		revids = adlp_revid_step_tbl;
-		size = ARRAY_SIZE(adlp_revid_step_tbl);
+		revids = adlp_revids;
+		size = ARRAY_SIZE(adlp_revids);
 	} else if (IS_ALDERLAKE_S(i915)) {
-		revids = adls_revid_step_tbl;
-		size = ARRAY_SIZE(adls_revid_step_tbl);
+		revids = adls_revids;
+		size = ARRAY_SIZE(adls_revids);
 	} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
-		revids = tgl_uy_revid_step_tbl;
-		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
+		revids = tgl_uy_revids;
+		size = ARRAY_SIZE(tgl_uy_revids);
 	} else if (IS_TIGERLAKE(i915)) {
-		revids = tgl_revid_step_tbl;
-		size = ARRAY_SIZE(tgl_revid_step_tbl);
+		revids = tgl_revids;
+		size = ARRAY_SIZE(tgl_revids);
 	} else if (IS_KABYLAKE(i915)) {
 		revids = kbl_revids;
 		size = ARRAY_SIZE(kbl_revids);
-- 
2.25.4

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[Intel-gfx] [PATCH v2 02/12] drm/i915: Make pre-production detection use direct revid comparison

[Matt Roper]

Although we're converting our workarounds to use a revid->stepping
lookup table, the function that detects pre-production hardware should
continue to compare against PCI revision ID values directly.  These are
listed in the bspec as integers, so it's easier to confirm their
correctness if we just use an integer literal rather than a symbolic
name anyway.

Bspec: 13620, 19131, 13626, 18329
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 30d8cd8c69b1..90136995f5eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -271,10 +271,10 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 	bool pre = false;
 
 	pre |= IS_HSW_EARLY_SDV(dev_priv);
-	pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
-	pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
-	pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
-	pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
+	pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
+	pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
+	pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
+	pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 
 	if (pre) {
 		drm_err(&dev_priv->drm, "This is a pre-production stepping. "
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 02/12] drm/i915: Make pre-production detection use direct revid comparison

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 02/12] drm/i915: Make pre-production detection use
> direct revid comparison
> 
> Although we're converting our workarounds to use a revid->stepping lookup
> table, the function that detects pre-production hardware should continue to
> compare against PCI revision ID values directly.  These are listed in the bspec
> as integers, so it's easier to confirm their correctness if we just use an integer
> literal rather than a symbolic name anyway.
> 
> Bspec: 13620, 19131, 13626, 18329
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c index 30d8cd8c69b1..90136995f5eb
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -271,10 +271,10 @@ static void intel_detect_preproduction_hw(struct
> drm_i915_private *dev_priv)
>  	bool pre = false;
> 
>  	pre |= IS_HSW_EARLY_SDV(dev_priv);
> -	pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
> -	pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
> -	pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
> -	pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
> +	pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
> +	pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
> +	pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> +	pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> 
>  	if (pre) {
>  		drm_err(&dev_priv->drm, "This is a pre-production stepping.
> "
> --
> 2.25.4

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[Intel-gfx] [PATCH v2 03/12] drm/i915/skl: Use revid->stepping tables

[Matt Roper]

Switch SKL to use a revid->stepping table as we're trying to do on all
platforms going forward.  Also drop the preproduction revisions and add
the newer steppings we hadn't already handled.

Note that SKL has a case where a newer revision ID corresponds to an
older GT/disp stepping (0x9 -> STEP_J0, 0xA -> STEP_I1).  Also, the lack
of a revision ID 0x8 in the table is intentional and not an oversight.
We'll re-write the KBL-specific comment to make it clear that these kind
of quirks are expected.

v2:
 - Since GT and display steppings are always identical on SKL use a
   macro to set both values at once in a more readable manner.  (Anusha)
 - Drop preproduction steppings.

Bspec: 13626
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h             | 11 +-------
 drivers/gpu/drm/i915/intel_step.c           | 30 +++++++++++++++++----
 drivers/gpu/drm/i915/intel_step.h           |  4 +++
 4 files changed, 31 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d9a5a445ceec..6dfd564e078f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -883,7 +883,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaInPlaceDecompressionHang:skl */
-	if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
+	if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))
 		wa_write_or(wal,
 			    GEN9_GAMT_ECO_REG_RW_IA,
 			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4747f4407ef..f30499ed6787 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1515,16 +1515,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TGL_Y(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
 
-#define SKL_REVID_A0		0x0
-#define SKL_REVID_B0		0x1
-#define SKL_REVID_C0		0x2
-#define SKL_REVID_D0		0x3
-#define SKL_REVID_E0		0x4
-#define SKL_REVID_F0		0x5
-#define SKL_REVID_G0		0x6
-#define SKL_REVID_H0		0x7
-
-#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
+#define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))
 
 #define BXT_REVID_A0		0x0
 #define BXT_REVID_A1		0x1
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 93ccd42f2514..69c928b046e8 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -7,14 +7,31 @@
 #include "intel_step.h"
 
 /*
- * KBL revision ID ordering is bizarre; higher revision ID's map to lower
- * steppings in some cases.  So rather than test against the revision ID
- * directly, let's map that into our own range of increasing ID's that we
- * can test against in a regular manner.
+ * Some platforms have unusual ways of mapping PCI revision ID to GT/display
+ * steppings.  E.g., in some cases a higher PCI revision may translate to a
+ * lower stepping of the GT and/or display IP.  This file provides lookup
+ * tables to map the PCI revision into a standard set of stepping values that
+ * can be compared numerically.
+ *
+ * Also note that some revisions/steppings may have been set aside as
+ * placeholders but never materialized in real hardware; in those cases there
+ * may be jumps in the revision IDs or stepping values in the tables below.
  */
 
+/*
+ * Some platforms always have the same stepping value for GT and display;
+ * use a macro to define these to make it easier to identify the platforms
+ * where the two steppings can deviate.
+ */
+#define COMMON_STEPPING(x)  .gt_step = STEP_##x, .display_step = STEP_##x
+
+static const struct intel_step_info skl_revids[] = {
+	[0x6] = { COMMON_STEPPING(G0) },
+	[0x7] = { COMMON_STEPPING(H0) },
+	[0x9] = { COMMON_STEPPING(J0) },
+	[0xA] = { COMMON_STEPPING(I1) },
+};
 
-/* FIXME: what about REVID_E0 */
 static const struct intel_step_info kbl_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
@@ -76,6 +93,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_KABYLAKE(i915)) {
 		revids = kbl_revids;
 		size = ARRAY_SIZE(kbl_revids);
+	} else if (IS_SKYLAKE(i915)) {
+		revids = skl_revids;
+		size = ARRAY_SIZE(skl_revids);
 	}
 
 	/* Not using the stepping scheme for the platform yet. */
diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
index 958a8bb5d677..88a77159703e 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -31,6 +31,10 @@ enum intel_step {
 	STEP_E0,
 	STEP_F0,
 	STEP_G0,
+	STEP_H0,
+	STEP_I0,
+	STEP_I1,
+	STEP_J0,
 	STEP_FUTURE,
 	STEP_FOREVER,
 };
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 03/12] drm/i915/skl: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 03/12] drm/i915/skl: Use revid->stepping tables
> 
> Switch SKL to use a revid->stepping table as we're trying to do on all
> platforms going forward.  Also drop the preproduction revisions and add the
> newer steppings we hadn't already handled.
> 
> Note that SKL has a case where a newer revision ID corresponds to an older
> GT/disp stepping (0x9 -> STEP_J0, 0xA -> STEP_I1).  Also, the lack of a revision
> ID 0x8 in the table is intentional and not an oversight.
> We'll re-write the KBL-specific comment to make it clear that these kind of
> quirks are expected.
> 
> v2:
>  - Since GT and display steppings are always identical on SKL use a
>    macro to set both values at once in a more readable manner.  (Anusha)
>  - Drop preproduction steppings.
> 
> Bspec: 13626
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h             | 11 +-------
>  drivers/gpu/drm/i915/intel_step.c           | 30 +++++++++++++++++----
>  drivers/gpu/drm/i915/intel_step.h           |  4 +++
>  4 files changed, 31 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d9a5a445ceec..6dfd564e078f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -883,7 +883,7 @@ skl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
>  		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
> 
>  	/* WaInPlaceDecompressionHang:skl */
> -	if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
> +	if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))
>  		wa_write_or(wal,
>  			    GEN9_GAMT_ECO_REG_RW_IA,
>  			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index c4747f4407ef..f30499ed6787
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1515,16 +1515,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_TGL_Y(dev_priv) \
>  	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE,
> INTEL_SUBPLATFORM_ULX)
> 
> -#define SKL_REVID_A0		0x0
> -#define SKL_REVID_B0		0x1
> -#define SKL_REVID_C0		0x2
> -#define SKL_REVID_D0		0x3
> -#define SKL_REVID_E0		0x4
> -#define SKL_REVID_F0		0x5
> -#define SKL_REVID_G0		0x6
> -#define SKL_REVID_H0		0x7
> -
> -#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
> until))
> +#define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p,
> +since, until))
> 
>  #define BXT_REVID_A0		0x0
>  #define BXT_REVID_A1		0x1
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 93ccd42f2514..69c928b046e8 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -7,14 +7,31 @@
>  #include "intel_step.h"
> 
>  /*
> - * KBL revision ID ordering is bizarre; higher revision ID's map to lower
> - * steppings in some cases.  So rather than test against the revision ID
> - * directly, let's map that into our own range of increasing ID's that we
> - * can test against in a regular manner.
> + * Some platforms have unusual ways of mapping PCI revision ID to
> + GT/display
> + * steppings.  E.g., in some cases a higher PCI revision may translate
> + to a
> + * lower stepping of the GT and/or display IP.  This file provides
> + lookup
> + * tables to map the PCI revision into a standard set of stepping
> + values that
> + * can be compared numerically.
> + *
> + * Also note that some revisions/steppings may have been set aside as
> + * placeholders but never materialized in real hardware; in those cases
> + there
> + * may be jumps in the revision IDs or stepping values in the tables below.
>   */
> 
> +/*
> + * Some platforms always have the same stepping value for GT and
> +display;
> + * use a macro to define these to make it easier to identify the
> +platforms
> + * where the two steppings can deviate.
> + */
> +#define COMMON_STEPPING(x)  .gt_step = STEP_##x, .display_step =
> +STEP_##x
> +
> +static const struct intel_step_info skl_revids[] = {
> +	[0x6] = { COMMON_STEPPING(G0) },
> +	[0x7] = { COMMON_STEPPING(H0) },
> +	[0x9] = { COMMON_STEPPING(J0) },
> +	[0xA] = { COMMON_STEPPING(I1) },
> +};
> 
> -/* FIXME: what about REVID_E0 */
>  static const struct intel_step_info kbl_revids[] = {
>  	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, @@ -76,6 +93,9
> @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_KABYLAKE(i915)) {
>  		revids = kbl_revids;
>  		size = ARRAY_SIZE(kbl_revids);
> +	} else if (IS_SKYLAKE(i915)) {
> +		revids = skl_revids;
> +		size = ARRAY_SIZE(skl_revids);
>  	}
> 
>  	/* Not using the stepping scheme for the platform yet. */ diff --git
> a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
> index 958a8bb5d677..88a77159703e 100644
> --- a/drivers/gpu/drm/i915/intel_step.h
> +++ b/drivers/gpu/drm/i915/intel_step.h
> @@ -31,6 +31,10 @@ enum intel_step {
>  	STEP_E0,
>  	STEP_F0,
>  	STEP_G0,
> +	STEP_H0,
> +	STEP_I0,
> +	STEP_I1,
> +	STEP_J0,
>  	STEP_FUTURE,
>  	STEP_FOREVER,
>  };
> --
> 2.25.4

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Re: [Intel-gfx] [PATCH v2 03/12] drm/i915/skl: Use revid->stepping tables

[Lucas De Marchi]

On Fri, Jul 09, 2021 at 08:37:15PM -0700, Matt Roper wrote:
>Switch SKL to use a revid->stepping table as we're trying to do on all
>platforms going forward.  Also drop the preproduction revisions and add
>the newer steppings we hadn't already handled.
>
>Note that SKL has a case where a newer revision ID corresponds to an
>older GT/disp stepping (0x9 -> STEP_J0, 0xA -> STEP_I1).  Also, the lack
>of a revision ID 0x8 in the table is intentional and not an oversight.
>We'll re-write the KBL-specific comment to make it clear that these kind
>of quirks are expected.
>
>v2:
> - Since GT and display steppings are always identical on SKL use a
>   macro to set both values at once in a more readable manner.  (Anusha)
> - Drop preproduction steppings.
>
>Bspec: 13626
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c |  2 +-
> drivers/gpu/drm/i915/i915_drv.h             | 11 +-------
> drivers/gpu/drm/i915/intel_step.c           | 30 +++++++++++++++++----
> drivers/gpu/drm/i915/intel_step.h           |  4 +++
> 4 files changed, 31 insertions(+), 16 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index d9a5a445ceec..6dfd564e078f 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -883,7 +883,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
>
> 	/* WaInPlaceDecompressionHang:skl */
>-	if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
>+	if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))
> 		wa_write_or(wal,
> 			    GEN9_GAMT_ECO_REG_RW_IA,
> 			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index c4747f4407ef..f30499ed6787 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1515,16 +1515,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TGL_Y(dev_priv) \
> 	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
>
>-#define SKL_REVID_A0		0x0
>-#define SKL_REVID_B0		0x1
>-#define SKL_REVID_C0		0x2
>-#define SKL_REVID_D0		0x3
>-#define SKL_REVID_E0		0x4
>-#define SKL_REVID_F0		0x5
>-#define SKL_REVID_G0		0x6
>-#define SKL_REVID_H0		0x7
>-
>-#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
>+#define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))
>
> #define BXT_REVID_A0		0x0
> #define BXT_REVID_A1		0x1
>diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
>index 93ccd42f2514..69c928b046e8 100644
>--- a/drivers/gpu/drm/i915/intel_step.c
>+++ b/drivers/gpu/drm/i915/intel_step.c
>@@ -7,14 +7,31 @@
> #include "intel_step.h"
>
> /*
>- * KBL revision ID ordering is bizarre; higher revision ID's map to lower
>- * steppings in some cases.  So rather than test against the revision ID
>- * directly, let's map that into our own range of increasing ID's that we
>- * can test against in a regular manner.
>+ * Some platforms have unusual ways of mapping PCI revision ID to GT/display
>+ * steppings.  E.g., in some cases a higher PCI revision may translate to a
>+ * lower stepping of the GT and/or display IP.  This file provides lookup
>+ * tables to map the PCI revision into a standard set of stepping values that
>+ * can be compared numerically.
>+ *
>+ * Also note that some revisions/steppings may have been set aside as
>+ * placeholders but never materialized in real hardware; in those cases there
>+ * may be jumps in the revision IDs or stepping values in the tables below.
>  */
>
>+/*
>+ * Some platforms always have the same stepping value for GT and display;
>+ * use a macro to define these to make it easier to identify the platforms
>+ * where the two steppings can deviate.
>+ */
>+#define COMMON_STEPPING(x)  .gt_step = STEP_##x, .display_step = STEP_##x

nitpick:

"stepping" is the proper word, but we settled on "step"
everyhere: functions, macros, tables, filename etc. Can we
continue doing that?  For the comments I think it's ok to
continue using the proper word, but for real code I think it
would be better to keep it consistent

thanks
Lucas De Marchi
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[Intel-gfx] [PATCH v2 04/12] drm/i915/kbl: Drop pre-production revision from stepping table

[Matt Roper]

We're long past the point where we need to care about pre-production
hardware, and we already warn the user and taint the kernel if we detect
the driver is being loaded on pre-production hardware.

Bspec: 18329
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_step.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 69c928b046e8..8987453aa172 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -33,7 +33,6 @@ static const struct intel_step_info skl_revids[] = {
 };
 
 static const struct intel_step_info kbl_revids[] = {
-	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
 	[2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
 	[3] = { .gt_step = STEP_D0, .display_step = STEP_B0 },
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 04/12] drm/i915/kbl: Drop pre-production revision from stepping table

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 04/12] drm/i915/kbl: Drop pre-production revision from
> stepping table
> 
> We're long past the point where we need to care about pre-production
> hardware, and we already warn the user and taint the kernel if we detect the
> driver is being loaded on pre-production hardware.
> 
> Bspec: 18329
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_step.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 69c928b046e8..8987453aa172 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -33,7 +33,6 @@ static const struct intel_step_info skl_revids[] = {  };
> 
>  static const struct intel_step_info kbl_revids[] = {
> -	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
>  	[2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
>  	[3] = { .gt_step = STEP_D0, .display_step = STEP_B0 },
> --
> 2.25.4

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[Intel-gfx] [PATCH v2 05/12] drm/i915/bxt: Use revid->stepping tables

[Matt Roper]

Switch BXT to use a revid->stepping table as we're trying to do on all
platforms going forward.  Note that the REVID macros we had before
weren't being used anywhere in the code and weren't even correct; the
table values come from the bspec (and omits all the placeholder and
preproduction revisions).

Although nothing in the code is using the data from this table at the
moment, we expect some upcoming DMC patches to start utilizing it.

Bspec: 13620
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  9 ---------
 drivers/gpu/drm/i915/intel_step.c | 10 ++++++++++
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f30499ed6787..afb159f2a658 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1517,15 +1517,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))
 
-#define BXT_REVID_A0		0x0
-#define BXT_REVID_A1		0x1
-#define BXT_REVID_B0		0x3
-#define BXT_REVID_B_LAST	0x8
-#define BXT_REVID_C0		0x9
-
-#define IS_BXT_REVID(dev_priv, since, until) \
-	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
-
 #define IS_KBL_GT_STEP(dev_priv, since, until) \
 	(IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 8987453aa172..41e3904ae6e8 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -42,6 +42,13 @@ static const struct intel_step_info kbl_revids[] = {
 	[7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },
 };
 
+static const struct intel_step_info bxt_revids[] = {
+	[0xA] = { COMMON_STEPPING(C0) },
+	[0xB] = { COMMON_STEPPING(C0) },
+	[0xC] = { COMMON_STEPPING(D0) },
+	[0xD] = { COMMON_STEPPING(E0) },
+};
+
 static const struct intel_step_info tgl_uy_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
@@ -89,6 +96,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
+	} else if (IS_BROXTON(i915)) {
+		revids = bxt_revids;
+		size = ARRAY_SIZE(bxt_revids);
 	} else if (IS_KABYLAKE(i915)) {
 		revids = kbl_revids;
 		size = ARRAY_SIZE(kbl_revids);
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/bxt: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 05/12] drm/i915/bxt: Use revid->stepping tables
> 
> Switch BXT to use a revid->stepping table as we're trying to do on all
> platforms going forward.  Note that the REVID macros we had before
> weren't being used anywhere in the code and weren't even correct; the
> table values come from the bspec (and omits all the placeholder and
> preproduction revisions).
> 
> Although nothing in the code is using the data from this table at the moment,
> we expect some upcoming DMC patches to start utilizing it.
> 
> Bspec: 13620
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Thanks for the patch,

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  9 ---------
>  drivers/gpu/drm/i915/intel_step.c | 10 ++++++++++
>  2 files changed, 10 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index f30499ed6787..afb159f2a658
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1517,15 +1517,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> 
>  #define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p,
> since, until))
> 
> -#define BXT_REVID_A0		0x0
> -#define BXT_REVID_A1		0x1
> -#define BXT_REVID_B0		0x3
> -#define BXT_REVID_B_LAST	0x8
> -#define BXT_REVID_C0		0x9
> -
> -#define IS_BXT_REVID(dev_priv, since, until) \
> -	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> -
>  #define IS_KBL_GT_STEP(dev_priv, since, until) \
>  	(IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
> #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ diff --git
> a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 8987453aa172..41e3904ae6e8 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -42,6 +42,13 @@ static const struct intel_step_info kbl_revids[] = {
>  	[7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },  };
> 
> +static const struct intel_step_info bxt_revids[] = {
> +	[0xA] = { COMMON_STEPPING(C0) },
> +	[0xB] = { COMMON_STEPPING(C0) },
> +	[0xC] = { COMMON_STEPPING(D0) },
> +	[0xD] = { COMMON_STEPPING(E0) },
> +};
> +
>  static const struct intel_step_info tgl_uy_revids[] = {
>  	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -89,6 +96,9
> @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_TIGERLAKE(i915)) {
>  		revids = tgl_revids;
>  		size = ARRAY_SIZE(tgl_revids);
> +	} else if (IS_BROXTON(i915)) {
> +		revids = bxt_revids;
> +		size = ARRAY_SIZE(bxt_revids);
>  	} else if (IS_KABYLAKE(i915)) {
>  		revids = kbl_revids;
>  		size = ARRAY_SIZE(kbl_revids);
> --
> 2.25.4

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[Intel-gfx] [PATCH v2 06/12] drm/i915/glk: Use revid->stepping tables

[Matt Roper]

Switch GLK to use a revid->stepping table as we're trying to do on all
platforms going forward.  Pre-production and placeholder revisions are
omitted.

Although nothing in the code is using the data from this table at the
moment, we expect some upcoming DMC patches to start utilizing it.

Bspec: 19131
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   | 8 --------
 drivers/gpu/drm/i915/intel_step.c | 7 +++++++
 2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index afb159f2a658..dac9ed2dfca5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1522,14 +1522,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 
-#define GLK_REVID_A0		0x0
-#define GLK_REVID_A1		0x1
-#define GLK_REVID_A2		0x2
-#define GLK_REVID_B0		0x3
-
-#define IS_GLK_REVID(dev_priv, since, until) \
-	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
-
 #define CNL_REVID_A0		0x0
 #define CNL_REVID_B0		0x1
 #define CNL_REVID_C0		0x2
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 41e3904ae6e8..7f8fe5e4c039 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -49,6 +49,10 @@ static const struct intel_step_info bxt_revids[] = {
 	[0xD] = { COMMON_STEPPING(E0) },
 };
 
+static const struct intel_step_info glk_revids[] = {
+	[3] = { COMMON_STEPPING(B0) },
+};
+
 static const struct intel_step_info tgl_uy_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
@@ -96,6 +100,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
+	} else if (IS_GEMINILAKE(i915)) {
+		revids = glk_revids;
+		size = ARRAY_SIZE(glk_revids);
 	} else if (IS_BROXTON(i915)) {
 		revids = bxt_revids;
 		size = ARRAY_SIZE(bxt_revids);
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 06/12] drm/i915/glk: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 06/12] drm/i915/glk: Use revid->stepping tables
> 
> Switch GLK to use a revid->stepping table as we're trying to do on all
> platforms going forward.  Pre-production and placeholder revisions are
> omitted.
> 
> Although nothing in the code is using the data from this table at the moment,
> we expect some upcoming DMC patches to start utilizing it.
> 
> Bspec: 19131
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

>  drivers/gpu/drm/i915/i915_drv.h   | 8 --------
>  drivers/gpu/drm/i915/intel_step.c | 7 +++++++
>  2 files changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index afb159f2a658..dac9ed2dfca5
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1522,14 +1522,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
>  	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since,
> until))
> 
> -#define GLK_REVID_A0		0x0
> -#define GLK_REVID_A1		0x1
> -#define GLK_REVID_A2		0x2
> -#define GLK_REVID_B0		0x3
> -
> -#define IS_GLK_REVID(dev_priv, since, until) \
> -	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> -
>  #define CNL_REVID_A0		0x0
>  #define CNL_REVID_B0		0x1
>  #define CNL_REVID_C0		0x2
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 41e3904ae6e8..7f8fe5e4c039 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -49,6 +49,10 @@ static const struct intel_step_info bxt_revids[] = {
>  	[0xD] = { COMMON_STEPPING(E0) },
>  };
> 
> +static const struct intel_step_info glk_revids[] = {
> +	[3] = { COMMON_STEPPING(B0) },
> +};
> +
>  static const struct intel_step_info tgl_uy_revids[] = {
>  	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -96,6
> +100,9 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_TIGERLAKE(i915)) {
>  		revids = tgl_revids;
>  		size = ARRAY_SIZE(tgl_revids);
> +	} else if (IS_GEMINILAKE(i915)) {
> +		revids = glk_revids;
> +		size = ARRAY_SIZE(glk_revids);
>  	} else if (IS_BROXTON(i915)) {
>  		revids = bxt_revids;
>  		size = ARRAY_SIZE(bxt_revids);
> --
> 2.25.4

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[Intel-gfx] [PATCH v2 07/12] drm/i915/icl: Use revid->stepping tables

[Matt Roper]

Switch ICL to use a revid->stepping table as we're trying to do on all
platforms going forward.  While we're at it, let's include some
additional steppings that have popped up, even if we don't yet have any
workarounds tied to those steppings (we probably need to audit our
workaround list soon to see if any of the bounds have moved or if new
workarounds have appeared).

Note that the current bspec table is missing information about how to
map PCI revision ID to GT/display steppings; it only provides an SoC
stepping.  The mapping to GT/display steppings (which aren't always the
same as the SoC stepping) used to be in the bspec, but was apparently
dropped during an update in Nov 2019; I've made my changes here based on
an older bspec snapshot that still had the necessary information.  We've
requested that the missing information be restored.

I'm only including the production revids in the table here since we're
past the point at which we usually stop trying to support pre-production
hardware.  An appropriate check is added to
intel_detect_preproduction_hw() to print an error and taint the kernel
just in case someone still tries to load the driver on old
pre-production hardware.

v2:
 - Drop pre-production steppings and add error/taint at startup when
   loading on pre-production hardware.

Bspec: 21141  # pre-Nov 2019 snapshot
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++------
 drivers/gpu/drm/i915/i915_drv.c             |  1 +
 drivers/gpu/drm/i915/i915_drv.h             | 10 ++--------
 drivers/gpu/drm/i915/intel_step.c           |  7 +++++++
 4 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6dfd564e078f..e2d8acb8c1c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -557,7 +557,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	/* Wa_1604370585:icl (pre-prod)
 	 * Formerly known as WaPushConstantDereferenceHoldDisable
 	 */
-	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
+	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 			     PUSH_CONSTANT_DEREF_DISABLE);
 
@@ -573,12 +573,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	/* Wa_2006611047:icl (pre-prod)
 	 * Formerly known as WaDisableImprovedTdlClkGating
 	 */
-	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
+	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 			     GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
 	/* Wa_2006665173:icl (pre-prod) */
-	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
+	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
 		wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
 			     GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
@@ -1023,13 +1023,13 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		    GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
 
 	/* Wa_1405779004:icl (pre-prod) */
-	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
+	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    MSCUNIT_CLKGATE_DIS);
 
 	/* Wa_1406838659:icl (pre-prod) */
-	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
+	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
 		wa_write_or(wal,
 			    INF_UNIT_LEVEL_CLKGATE,
 			    CGPSF_CLKGATE_DIS);
@@ -1725,7 +1725,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    PMFLUSHDONE_LNEBLK);
 
 		/* Wa_1406609255:icl (pre-prod) */
-		if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
+		if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
 			wa_write_or(wal,
 				    GEN7_SARCHKMD,
 				    GEN7_DISABLE_DEMAND_PREFETCH);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90136995f5eb..c43b698bf0b9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -275,6 +275,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 	pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 	pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 	pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
+	pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 
 	if (pre) {
 		drm_err(&dev_priv->drm, "This is a pre-production stepping. "
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dac9ed2dfca5..d4f705f06c73 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1529,14 +1529,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_CNL_REVID(p, since, until) \
 	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
-#define ICL_REVID_A0		0x0
-#define ICL_REVID_A2		0x1
-#define ICL_REVID_B0		0x3
-#define ICL_REVID_B2		0x4
-#define ICL_REVID_C0		0x5
-
-#define IS_ICL_REVID(p, since, until) \
-	(IS_ICELAKE(p) && IS_REVID(p, since, until))
+#define IS_ICL_GT_STEP(p, since, until) \
+	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
 
 #define EHL_REVID_A0            0x0
 #define EHL_REVID_B0            0x1
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 7f8fe5e4c039..f8be464d1179 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -53,6 +53,10 @@ static const struct intel_step_info glk_revids[] = {
 	[3] = { COMMON_STEPPING(B0) },
 };
 
+static const struct intel_step_info icl_revids[] = {
+	[7] = { COMMON_STEPPING(D0) },
+};
+
 static const struct intel_step_info tgl_uy_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
@@ -100,6 +104,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
+	} else if (IS_ICELAKE(i915)) {
+		revids = icl_revids;
+		size = ARRAY_SIZE(icl_revids);
 	} else if (IS_GEMINILAKE(i915)) {
 		revids = glk_revids;
 		size = ARRAY_SIZE(glk_revids);
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 07/12] drm/i915/icl: Use revid->stepping tables

[Souza, Jose]

On Fri, 2021-07-09 at 20:37 -0700, Matt Roper wrote:
> Switch ICL to use a revid->stepping table as we're trying to do on all
> platforms going forward.  While we're at it, let's include some
> additional steppings that have popped up, even if we don't yet have any
> workarounds tied to those steppings (we probably need to audit our
> workaround list soon to see if any of the bounds have moved or if new
> workarounds have appeared).
> 
> Note that the current bspec table is missing information about how to
> map PCI revision ID to GT/display steppings; it only provides an SoC
> stepping.  The mapping to GT/display steppings (which aren't always the
> same as the SoC stepping) used to be in the bspec, but was apparently
> dropped during an update in Nov 2019; I've made my changes here based on
> an older bspec snapshot that still had the necessary information.  We've
> requested that the missing information be restored.
> 
> I'm only including the production revids in the table here since we're
> past the point at which we usually stop trying to support pre-production
> hardware.  An appropriate check is added to
> intel_detect_preproduction_hw() to print an error and taint the kernel
> just in case someone still tries to load the driver on old
> pre-production hardware.
> 
> v2:
>  - Drop pre-production steppings and add error/taint at startup when
>    loading on pre-production hardware.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Bspec: 21141  # pre-Nov 2019 snapshot
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++------
>  drivers/gpu/drm/i915/i915_drv.c             |  1 +
>  drivers/gpu/drm/i915/i915_drv.h             | 10 ++--------
>  drivers/gpu/drm/i915/intel_step.c           |  7 +++++++
>  4 files changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6dfd564e078f..e2d8acb8c1c9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -557,7 +557,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	/* Wa_1604370585:icl (pre-prod)
>  	 * Formerly known as WaPushConstantDereferenceHoldDisable
>  	 */
> -	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
> +	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
>  		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
>  			     PUSH_CONSTANT_DEREF_DISABLE);
>  
> @@ -573,12 +573,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	/* Wa_2006611047:icl (pre-prod)
>  	 * Formerly known as WaDisableImprovedTdlClkGating
>  	 */
> -	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
> +	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
>  		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
>  			     GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
>  
>  	/* Wa_2006665173:icl (pre-prod) */
> -	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
> +	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
>  		wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
>  			     GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>  
> @@ -1023,13 +1023,13 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  		    GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
>  
>  	/* Wa_1405779004:icl (pre-prod) */
> -	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
> +	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    MSCUNIT_CLKGATE_DIS);
>  
>  	/* Wa_1406838659:icl (pre-prod) */
> -	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
> +	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
>  		wa_write_or(wal,
>  			    INF_UNIT_LEVEL_CLKGATE,
>  			    CGPSF_CLKGATE_DIS);
> @@ -1725,7 +1725,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  			    PMFLUSHDONE_LNEBLK);
>  
>  		/* Wa_1406609255:icl (pre-prod) */
> -		if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
> +		if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
>  			wa_write_or(wal,
>  				    GEN7_SARCHKMD,
>  				    GEN7_DISABLE_DEMAND_PREFETCH);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 90136995f5eb..c43b698bf0b9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -275,6 +275,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
>  	pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
>  	pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
>  	pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> +	pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
>  
>  	if (pre) {
>  		drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dac9ed2dfca5..d4f705f06c73 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1529,14 +1529,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_CNL_REVID(p, since, until) \
>  	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>  
> -#define ICL_REVID_A0		0x0
> -#define ICL_REVID_A2		0x1
> -#define ICL_REVID_B0		0x3
> -#define ICL_REVID_B2		0x4
> -#define ICL_REVID_C0		0x5
> -
> -#define IS_ICL_REVID(p, since, until) \
> -	(IS_ICELAKE(p) && IS_REVID(p, since, until))
> +#define IS_ICL_GT_STEP(p, since, until) \
> +	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
>  
>  #define EHL_REVID_A0            0x0
>  #define EHL_REVID_B0            0x1
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 7f8fe5e4c039..f8be464d1179 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -53,6 +53,10 @@ static const struct intel_step_info glk_revids[] = {
>  	[3] = { COMMON_STEPPING(B0) },
>  };
>  
> +static const struct intel_step_info icl_revids[] = {
> +	[7] = { COMMON_STEPPING(D0) },
> +};
> +
>  static const struct intel_step_info tgl_uy_revids[] = {
>  	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
> @@ -100,6 +104,9 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_TIGERLAKE(i915)) {
>  		revids = tgl_revids;
>  		size = ARRAY_SIZE(tgl_revids);
> +	} else if (IS_ICELAKE(i915)) {
> +		revids = icl_revids;
> +		size = ARRAY_SIZE(icl_revids);
>  	} else if (IS_GEMINILAKE(i915)) {
>  		revids = glk_revids;
>  		size = ARRAY_SIZE(glk_revids);

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Re: [Intel-gfx] [PATCH v2 07/12] drm/i915/icl: Use revid->stepping tables

[Lucas De Marchi]

On Fri, Jul 09, 2021 at 08:37:19PM -0700, Matt Roper wrote:
>Switch ICL to use a revid->stepping table as we're trying to do on all
>platforms going forward.  While we're at it, let's include some
>additional steppings that have popped up, even if we don't yet have any
>workarounds tied to those steppings (we probably need to audit our
>workaround list soon to see if any of the bounds have moved or if new
>workarounds have appeared).
>
>Note that the current bspec table is missing information about how to
>map PCI revision ID to GT/display steppings; it only provides an SoC
>stepping.  The mapping to GT/display steppings (which aren't always the
>same as the SoC stepping) used to be in the bspec, but was apparently
>dropped during an update in Nov 2019; I've made my changes here based on
>an older bspec snapshot that still had the necessary information.  We've
>requested that the missing information be restored.
>
>I'm only including the production revids in the table here since we're
>past the point at which we usually stop trying to support pre-production
>hardware.  An appropriate check is added to
>intel_detect_preproduction_hw() to print an error and taint the kernel
>just in case someone still tries to load the driver on old
>pre-production hardware.
>
>v2:
> - Drop pre-production steppings and add error/taint at startup when
>   loading on pre-production hardware.

oh... I forgot to send my review. Here is the commend I had:

It seems we are not actually dropping the WAs. We have several applying
only to A0 or A0/B0. From your first paragraph, is the intention to do
an audit of the WA ranges later?  Because we are currently running
without applying those WAs, so those are effectively dead code.

Lucas De Marchi
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Re: [Intel-gfx] [PATCH v2 07/12] drm/i915/icl: Use revid->stepping tables

[Matt Roper]

On Tue, Jul 13, 2021 at 12:57:07PM -0700, Lucas De Marchi wrote:
> On Fri, Jul 09, 2021 at 08:37:19PM -0700, Matt Roper wrote:
> > Switch ICL to use a revid->stepping table as we're trying to do on all
> > platforms going forward.  While we're at it, let's include some
> > additional steppings that have popped up, even if we don't yet have any
> > workarounds tied to those steppings (we probably need to audit our
> > workaround list soon to see if any of the bounds have moved or if new
> > workarounds have appeared).
> > 
> > Note that the current bspec table is missing information about how to
> > map PCI revision ID to GT/display steppings; it only provides an SoC
> > stepping.  The mapping to GT/display steppings (which aren't always the
> > same as the SoC stepping) used to be in the bspec, but was apparently
> > dropped during an update in Nov 2019; I've made my changes here based on
> > an older bspec snapshot that still had the necessary information.  We've
> > requested that the missing information be restored.
> > 
> > I'm only including the production revids in the table here since we're
> > past the point at which we usually stop trying to support pre-production
> > hardware.  An appropriate check is added to
> > intel_detect_preproduction_hw() to print an error and taint the kernel
> > just in case someone still tries to load the driver on old
> > pre-production hardware.
> > 
> > v2:
> > - Drop pre-production steppings and add error/taint at startup when
> >   loading on pre-production hardware.
> 
> oh... I forgot to send my review. Here is the commend I had:
> 
> It seems we are not actually dropping the WAs. We have several applying
> only to A0 or A0/B0. From your first paragraph, is the intention to do
> an audit of the WA ranges later?  Because we are currently running
> without applying those WAs, so those are effectively dead code.

The actual dropping of workarounds for pre-production steppings happens
in patch #12.  But a more in-depth audit will be done in the future.


Matt

> 
> Lucas De Marchi

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH v2 07/12] drm/i915/icl: Use revid->stepping tables

[Lucas De Marchi]

On Tue, Jul 13, 2021 at 12:59:53PM -0700, Matt Roper wrote:
>On Tue, Jul 13, 2021 at 12:57:07PM -0700, Lucas De Marchi wrote:
>> On Fri, Jul 09, 2021 at 08:37:19PM -0700, Matt Roper wrote:
>> > Switch ICL to use a revid->stepping table as we're trying to do on all
>> > platforms going forward.  While we're at it, let's include some
>> > additional steppings that have popped up, even if we don't yet have any
>> > workarounds tied to those steppings (we probably need to audit our
>> > workaround list soon to see if any of the bounds have moved or if new
>> > workarounds have appeared).
>> >
>> > Note that the current bspec table is missing information about how to
>> > map PCI revision ID to GT/display steppings; it only provides an SoC
>> > stepping.  The mapping to GT/display steppings (which aren't always the
>> > same as the SoC stepping) used to be in the bspec, but was apparently
>> > dropped during an update in Nov 2019; I've made my changes here based on
>> > an older bspec snapshot that still had the necessary information.  We've
>> > requested that the missing information be restored.
>> >
>> > I'm only including the production revids in the table here since we're
>> > past the point at which we usually stop trying to support pre-production
>> > hardware.  An appropriate check is added to
>> > intel_detect_preproduction_hw() to print an error and taint the kernel
>> > just in case someone still tries to load the driver on old
>> > pre-production hardware.
>> >
>> > v2:
>> > - Drop pre-production steppings and add error/taint at startup when
>> >   loading on pre-production hardware.
>>
>> oh... I forgot to send my review. Here is the commend I had:
>>
>> It seems we are not actually dropping the WAs. We have several applying
>> only to A0 or A0/B0. From your first paragraph, is the intention to do
>> an audit of the WA ranges later?  Because we are currently running
>> without applying those WAs, so those are effectively dead code.
>
>The actual dropping of workarounds for pre-production steppings happens
>in patch #12.  But a more in-depth audit will be done in the future.

ahh, ok. Makes sense then.

Thanks
Lucas De Marchi

>
>
>Matt
>
>>
>> Lucas De Marchi
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH v2 08/12] drm/i915/jsl_ehl: Use revid->stepping tables

[Matt Roper]

Switch JSL/EHL to use a revid->stepping table as we're trying to do on
all platforms going forward.

Bspec: 29153
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 9 ++++-----
 drivers/gpu/drm/i915/intel_step.c             | 8 ++++++++
 4 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 882bfd499e55..dfc31b682848 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2674,7 +2674,7 @@ static bool
 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
 	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
-		 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
+		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
 		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
 		 i915->dpll.ref_clks.nssc == 38400;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e2d8acb8c1c9..4c0c15bbdac2 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1043,7 +1043,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 
 	/* Wa_1607087056:icl,ehl,jsl */
 	if (IS_ICELAKE(i915) ||
-	    IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
+	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d4f705f06c73..b3ce2b73a143 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1532,11 +1532,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_GT_STEP(p, since, until) \
 	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
 
-#define EHL_REVID_A0            0x0
-#define EHL_REVID_B0            0x1
-
-#define IS_JSL_EHL_REVID(p, since, until) \
-	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
+#define IS_JSL_EHL_GT_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
+#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index f8be464d1179..6e1b132ecf38 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -57,6 +57,11 @@ static const struct intel_step_info icl_revids[] = {
 	[7] = { COMMON_STEPPING(D0) },
 };
 
+static const struct intel_step_info jsl_ehl_revids[] = {
+	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+	[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+};
+
 static const struct intel_step_info tgl_uy_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
@@ -104,6 +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
+	} else if (IS_JSL_EHL(i915)) {
+		revids = jsl_ehl_revids;
+		size = ARRAY_SIZE(jsl_ehl_revids);
 	} else if (IS_ICELAKE(i915)) {
 		revids = icl_revids;
 		size = ARRAY_SIZE(icl_revids);
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 08/12] drm/i915/jsl_ehl: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 08/12] drm/i915/jsl_ehl: Use revid->stepping tables
> 
> Switch JSL/EHL to use a revid->stepping table as we're trying to do on all
> platforms going forward.
> 
> Bspec: 29153
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h               | 9 ++++-----
>  drivers/gpu/drm/i915/intel_step.c             | 8 ++++++++
>  4 files changed, 14 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 882bfd499e55..dfc31b682848 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2674,7 +2674,7 @@ static bool
>  ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)  {
>  	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
> -		 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER))
> ||
> +		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER))
> ||
>  		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
>  		 i915->dpll.ref_clks.nssc == 38400;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e2d8acb8c1c9..4c0c15bbdac2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1043,7 +1043,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> 
>  	/* Wa_1607087056:icl,ehl,jsl */
>  	if (IS_ICELAKE(i915) ||
> -	    IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
> +	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); diff --
> git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d4f705f06c73..b3ce2b73a143 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1532,11 +1532,10 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_ICL_GT_STEP(p, since, until) \
>  	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
> 
> -#define EHL_REVID_A0            0x0
> -#define EHL_REVID_B0            0x1
> -
> -#define IS_JSL_EHL_REVID(p, since, until) \
> -	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
> +#define IS_JSL_EHL_GT_STEP(p, since, until) \
> +	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until)) #define
> +IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
> +	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
> 
>  #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
>  	(IS_TIGERLAKE(__i915) && \
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index f8be464d1179..6e1b132ecf38 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -57,6 +57,11 @@ static const struct intel_step_info icl_revids[] = {
>  	[7] = { COMMON_STEPPING(D0) },
>  };
> 
> +static const struct intel_step_info jsl_ehl_revids[] = {
> +	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> +	[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, };
> +
Here COMMON_STEEPING can be used.

Anusha
>  static const struct intel_step_info tgl_uy_revids[] = {
>  	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -104,6
> +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_TIGERLAKE(i915)) {
>  		revids = tgl_revids;
>  		size = ARRAY_SIZE(tgl_revids);
> +	} else if (IS_JSL_EHL(i915)) {
> +		revids = jsl_ehl_revids;
> +		size = ARRAY_SIZE(jsl_ehl_revids);
>  	} else if (IS_ICELAKE(i915)) {
>  		revids = icl_revids;
>  		size = ARRAY_SIZE(icl_revids);
> --
> 2.25.4

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[Intel-gfx] [PATCH v3 08/12] drm/i915/jsl_ehl: Use revid->stepping tables

[Matt Roper]

Switch JSL/EHL to use a revid->stepping table as we're trying to do on
all platforms going forward.

v2:
 - Use COMMON_STEPPING().  (Anusha)

Bspec: 29153
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 9 ++++-----
 drivers/gpu/drm/i915/intel_step.c             | 8 ++++++++
 4 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 882bfd499e55..dfc31b682848 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2674,7 +2674,7 @@ static bool
 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
 	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
-		 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
+		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
 		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
 		 i915->dpll.ref_clks.nssc == 38400;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e2d8acb8c1c9..4c0c15bbdac2 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1043,7 +1043,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 
 	/* Wa_1607087056:icl,ehl,jsl */
 	if (IS_ICELAKE(i915) ||
-	    IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
+	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d4f705f06c73..b3ce2b73a143 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1532,11 +1532,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_GT_STEP(p, since, until) \
 	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
 
-#define EHL_REVID_A0            0x0
-#define EHL_REVID_B0            0x1
-
-#define IS_JSL_EHL_REVID(p, since, until) \
-	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
+#define IS_JSL_EHL_GT_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
+#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 	(IS_TIGERLAKE(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index f8be464d1179..868606f8139f 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -57,6 +57,11 @@ static const struct intel_step_info icl_revids[] = {
 	[7] = { COMMON_STEPPING(D0) },
 };
 
+static const struct intel_step_info jsl_ehl_revids[] = {
+	[0] = { COMMON_STEPPING(A0) },
+	[1] = { COMMON_STEPPING(B0) },
+};
+
 static const struct intel_step_info tgl_uy_revids[] = {
 	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
@@ -104,6 +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_TIGERLAKE(i915)) {
 		revids = tgl_revids;
 		size = ARRAY_SIZE(tgl_revids);
+	} else if (IS_JSL_EHL(i915)) {
+		revids = jsl_ehl_revids;
+		size = ARRAY_SIZE(jsl_ehl_revids);
 	} else if (IS_ICELAKE(i915)) {
 		revids = icl_revids;
 		size = ARRAY_SIZE(icl_revids);
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v3 08/12] drm/i915/jsl_ehl: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Tuesday, July 13, 2021 9:15 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v3 08/12] drm/i915/jsl_ehl: Use revid->stepping tables
> 
> Switch JSL/EHL to use a revid->stepping table as we're trying to do on all
> platforms going forward.
> 
> v2:
>  - Use COMMON_STEPPING().  (Anusha)
> 
> Bspec: 29153
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h               | 9 ++++-----
>  drivers/gpu/drm/i915/intel_step.c             | 8 ++++++++
>  4 files changed, 14 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 882bfd499e55..dfc31b682848 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2674,7 +2674,7 @@ static bool
>  ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)  {
>  	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
> -		 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER))
> ||
> +		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER))
> ||
>  		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
>  		 i915->dpll.ref_clks.nssc == 38400;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e2d8acb8c1c9..4c0c15bbdac2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1043,7 +1043,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> 
>  	/* Wa_1607087056:icl,ehl,jsl */
>  	if (IS_ICELAKE(i915) ||
> -	    IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
> +	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); diff --
> git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d4f705f06c73..b3ce2b73a143 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1532,11 +1532,10 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_ICL_GT_STEP(p, since, until) \
>  	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
> 
> -#define EHL_REVID_A0            0x0
> -#define EHL_REVID_B0            0x1
> -
> -#define IS_JSL_EHL_REVID(p, since, until) \
> -	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
> +#define IS_JSL_EHL_GT_STEP(p, since, until) \
> +	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until)) #define
> +IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
> +	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
> 
>  #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
>  	(IS_TIGERLAKE(__i915) && \
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index f8be464d1179..868606f8139f 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -57,6 +57,11 @@ static const struct intel_step_info icl_revids[] = {
>  	[7] = { COMMON_STEPPING(D0) },
>  };
> 
> +static const struct intel_step_info jsl_ehl_revids[] = {
> +	[0] = { COMMON_STEPPING(A0) },
> +	[1] = { COMMON_STEPPING(B0) },
> +};
> +
>  static const struct intel_step_info tgl_uy_revids[] = {
>  	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -104,6
> +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_TIGERLAKE(i915)) {
>  		revids = tgl_revids;
>  		size = ARRAY_SIZE(tgl_revids);
> +	} else if (IS_JSL_EHL(i915)) {
> +		revids = jsl_ehl_revids;
> +		size = ARRAY_SIZE(jsl_ehl_revids);
>  	} else if (IS_ICELAKE(i915)) {
>  		revids = icl_revids;
>  		size = ARRAY_SIZE(icl_revids);
> --
> 2.25.4

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[Intel-gfx] [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables

[Matt Roper]

Switch RKL to use a revid->stepping table as we're trying to do on all
platforms going forward.

Bspec: 44501
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h          | 8 ++------
 drivers/gpu/drm/i915/intel_step.c        | 9 +++++++++
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9643624fe160..74b2aa3c2946 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -594,7 +594,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	if (intel_dp->psr.psr2_sel_fetch_enabled) {
 		/* WA 1408330847 */
 		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
+		    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
 			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
 				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
@@ -1342,7 +1342,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	/* WA 1408330847 */
 	if (intel_dp->psr.psr2_sel_fetch_enabled &&
 	    (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
+	     IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b3ce2b73a143..9195131cf90f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1549,12 +1549,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
 	 IS_GT_STEP(__i915, since, until))
 
-#define RKL_REVID_A0		0x0
-#define RKL_REVID_B0		0x1
-#define RKL_REVID_C0		0x4
-
-#define IS_RKL_REVID(p, since, until) \
-	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+#define IS_RKL_DISPLAY_STEP(p, since, until) \
+	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define DG1_REVID_A0		0x0
 #define DG1_REVID_B0		0x1
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 6e1b132ecf38..21211649e6bb 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -75,6 +75,12 @@ static const struct intel_step_info tgl_revids[] = {
 	[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
 };
 
+static const struct intel_step_info rkl_revids[] = {
+	[0] = { COMMON_STEPPING(A0) },
+	[1] = { COMMON_STEPPING(B0) },
+	[4] = { COMMON_STEPPING(C0) },
+};
+
 static const struct intel_step_info adls_revids[] = {
 	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
@@ -103,6 +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ALDERLAKE_S(i915)) {
 		revids = adls_revids;
 		size = ARRAY_SIZE(adls_revids);
+	} else if (IS_ROCKETLAKE(i915)) {
+		revids = rkl_revids;
+		size = ARRAY_SIZE(rkl_revids);
 	} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
 		revids = tgl_uy_revids;
 		size = ARRAY_SIZE(tgl_uy_revids);
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
> 
> Switch RKL to use a revid->stepping table as we're trying to do on all
> platforms going forward.
> 
> Bspec: 44501
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
>  drivers/gpu/drm/i915/i915_drv.h          | 8 ++------
>  drivers/gpu/drm/i915/intel_step.c        | 9 +++++++++
>  3 files changed, 13 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9643624fe160..74b2aa3c2946 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -594,7 +594,7 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>  	if (intel_dp->psr.psr2_sel_fetch_enabled) {
>  		/* WA 1408330847 */
>  		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> -		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> +		    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> @@ -1342,7 +1342,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>  	/* WA 1408330847 */
>  	if (intel_dp->psr.psr2_sel_fetch_enabled &&
>  	    (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> -	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> +	     IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index b3ce2b73a143..9195131cf90f
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1549,12 +1549,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>  	(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915))
> && \
>  	 IS_GT_STEP(__i915, since, until))
> 
> -#define RKL_REVID_A0		0x0
> -#define RKL_REVID_B0		0x1
> -#define RKL_REVID_C0		0x4
> -
> -#define IS_RKL_REVID(p, since, until) \
> -	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> +#define IS_RKL_DISPLAY_STEP(p, since, until) \
> +	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> 

If a platform has the same gt and display stepping, I wonder if we should stick to using IS_<PLATFORM>_GT_STEP while replacing IS<PLATFORM>_REVID instances. The previous patches have IS_<PLATFORMS>_GT_STEP.
Just a thought.

Anusha 

>  #define DG1_REVID_A0		0x0
>  #define DG1_REVID_B0		0x1
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 6e1b132ecf38..21211649e6bb 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -75,6 +75,12 @@ static const struct intel_step_info tgl_revids[] = {
>  	[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },  };
> 
> +static const struct intel_step_info rkl_revids[] = {
> +	[0] = { COMMON_STEPPING(A0) },
> +	[1] = { COMMON_STEPPING(B0) },
> +	[4] = { COMMON_STEPPING(C0) },
> +};
> +
>  static const struct intel_step_info adls_revids[] = {
>  	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, @@ -103,6
> +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_ALDERLAKE_S(i915)) {
>  		revids = adls_revids;
>  		size = ARRAY_SIZE(adls_revids);
> +	} else if (IS_ROCKETLAKE(i915)) {
> +		revids = rkl_revids;
> +		size = ARRAY_SIZE(rkl_revids);
>  	} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
>  		revids = tgl_uy_revids;
>  		size = ARRAY_SIZE(tgl_uy_revids);
> --
> 2.25.4

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Re: [Intel-gfx] [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables

[Matt Roper]

On Mon, Jul 12, 2021 at 03:51:15PM -0700, Srivatsa, Anusha wrote:
> 
> 
> > -----Original Message-----
> > From: Roper, Matthew D <matthew.d.roper@intel.com>
> > Sent: Friday, July 9, 2021 8:37 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>
> > Subject: [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
> > 
> > Switch RKL to use a revid->stepping table as we're trying to do on all
> > platforms going forward.
> > 
> > Bspec: 44501
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> >  drivers/gpu/drm/i915/i915_drv.h          | 8 ++------
> >  drivers/gpu/drm/i915/intel_step.c        | 9 +++++++++
> >  3 files changed, 13 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 9643624fe160..74b2aa3c2946 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -594,7 +594,7 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> >  	if (intel_dp->psr.psr2_sel_fetch_enabled) {
> >  		/* WA 1408330847 */
> >  		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> > -		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> > +		    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> >  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> >  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> >  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > @@ -1342,7 +1342,7 @@ static void intel_psr_disable_locked(struct intel_dp
> > *intel_dp)
> >  	/* WA 1408330847 */
> >  	if (intel_dp->psr.psr2_sel_fetch_enabled &&
> >  	    (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> > -	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> > +	     IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
> >  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> >  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index b3ce2b73a143..9195131cf90f
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1549,12 +1549,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> >  	(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915))
> > && \
> >  	 IS_GT_STEP(__i915, since, until))
> > 
> > -#define RKL_REVID_A0		0x0
> > -#define RKL_REVID_B0		0x1
> > -#define RKL_REVID_C0		0x4
> > -
> > -#define IS_RKL_REVID(p, since, until) \
> > -	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> > +#define IS_RKL_DISPLAY_STEP(p, since, until) \
> > +	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> > 
> 
> If a platform has the same gt and display stepping, I wonder if we
> should stick to using IS_<PLATFORM>_GT_STEP while replacing
> IS<PLATFORM>_REVID instances. The previous patches have
> IS_<PLATFORMS>_GT_STEP.
> Just a thought.

No, we want to be very explicit about which IP block the stepping
belongs to to avoid mistakes.  Just because the steppings are equivalent
right now doesn't mean a new revision won't show up in the future that
has different GT vs display steppings.  In that case it's easy to update
the table, but we don't want to have to dig through the rest of the code
looking for places where we used the wrong macro.  Plus, intentionally
using the wrong macro on a platform where it doesn't matter is going to
lead to copy/paste errors when people add additional platforms to a
workaround.


Matt

> 
> Anusha 
> 
> >  #define DG1_REVID_A0		0x0
> >  #define DG1_REVID_B0		0x1
> > diff --git a/drivers/gpu/drm/i915/intel_step.c
> > b/drivers/gpu/drm/i915/intel_step.c
> > index 6e1b132ecf38..21211649e6bb 100644
> > --- a/drivers/gpu/drm/i915/intel_step.c
> > +++ b/drivers/gpu/drm/i915/intel_step.c
> > @@ -75,6 +75,12 @@ static const struct intel_step_info tgl_revids[] = {
> >  	[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },  };
> > 
> > +static const struct intel_step_info rkl_revids[] = {
> > +	[0] = { COMMON_STEPPING(A0) },
> > +	[1] = { COMMON_STEPPING(B0) },
> > +	[4] = { COMMON_STEPPING(C0) },
> > +};
> > +
> >  static const struct intel_step_info adls_revids[] = {
> >  	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> >  	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, @@ -103,6
> > +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
> >  	} else if (IS_ALDERLAKE_S(i915)) {
> >  		revids = adls_revids;
> >  		size = ARRAY_SIZE(adls_revids);
> > +	} else if (IS_ROCKETLAKE(i915)) {
> > +		revids = rkl_revids;
> > +		size = ARRAY_SIZE(rkl_revids);
> >  	} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
> >  		revids = tgl_uy_revids;
> >  		size = ARRAY_SIZE(tgl_uy_revids);
> > --
> > 2.25.4
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Monday, July 12, 2021 3:56 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
> 
> On Mon, Jul 12, 2021 at 03:51:15PM -0700, Srivatsa, Anusha wrote:
> >
> >
> > > -----Original Message-----
> > > From: Roper, Matthew D <matthew.d.roper@intel.com>
> > > Sent: Friday, July 9, 2021 8:37 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> > > <matthew.d.roper@intel.com>
> > > Subject: [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
> > >
> > > Switch RKL to use a revid->stepping table as we're trying to do on
> > > all platforms going forward.
> > >
> > > Bspec: 44501
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> > >  drivers/gpu/drm/i915/i915_drv.h          | 8 ++------
> > >  drivers/gpu/drm/i915/intel_step.c        | 9 +++++++++
> > >  3 files changed, 13 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 9643624fe160..74b2aa3c2946 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -594,7 +594,7 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > >  	if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > >  		/* WA 1408330847 */
> > >  		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> > > -		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> > > +		    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> > >  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > >  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > >  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> @@ -1342,7 +1342,7 @@
> > > static void intel_psr_disable_locked(struct intel_dp
> > > *intel_dp)
> > >  	/* WA 1408330847 */
> > >  	if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > >  	    (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> > > -	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> > > +	     IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
> > >  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > >  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index b3ce2b73a143..9195131cf90f
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1549,12 +1549,8 @@ IS_SUBPLATFORM(const struct
> drm_i915_private
> > > *i915,
> > >  	(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915))
> > > && \
> > >  	 IS_GT_STEP(__i915, since, until))
> > >
> > > -#define RKL_REVID_A0		0x0
> > > -#define RKL_REVID_B0		0x1
> > > -#define RKL_REVID_C0		0x4
> > > -
> > > -#define IS_RKL_REVID(p, since, until) \
> > > -	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> > > +#define IS_RKL_DISPLAY_STEP(p, since, until) \
> > > +	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> > >
> >
> > If a platform has the same gt and display stepping, I wonder if we
> > should stick to using IS_<PLATFORM>_GT_STEP while replacing
> > IS<PLATFORM>_REVID instances. The previous patches have
> > IS_<PLATFORMS>_GT_STEP.
> > Just a thought.
> 
> No, we want to be very explicit about which IP block the stepping belongs to
> to avoid mistakes.  Just because the steppings are equivalent right now
> doesn't mean a new revision won't show up in the future that has different
> GT vs display steppings.  In that case it's easy to update the table, but we
> don't want to have to dig through the rest of the code looking for places
> where we used the wrong macro.  Plus, intentionally using the wrong macro
> on a platform where it doesn't matter is going to lead to copy/paste errors
> when people add additional platforms to a workaround.
> 
> 
> Matt
> 
> >
> > Anusha
> >
> > >  #define DG1_REVID_A0		0x0
> > >  #define DG1_REVID_B0		0x1
> > > diff --git a/drivers/gpu/drm/i915/intel_step.c
> > > b/drivers/gpu/drm/i915/intel_step.c
> > > index 6e1b132ecf38..21211649e6bb 100644
> > > --- a/drivers/gpu/drm/i915/intel_step.c
> > > +++ b/drivers/gpu/drm/i915/intel_step.c
> > > @@ -75,6 +75,12 @@ static const struct intel_step_info tgl_revids[] = {
> > >  	[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },  };
> > >
> > > +static const struct intel_step_info rkl_revids[] = {
> > > +	[0] = { COMMON_STEPPING(A0) },
> > > +	[1] = { COMMON_STEPPING(B0) },
> > > +	[4] = { COMMON_STEPPING(C0) },
> > > +};
> > > +
> > >  static const struct intel_step_info adls_revids[] = {
> > >  	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> > >  	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, @@ -103,6
> > > +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
> > >  	} else if (IS_ALDERLAKE_S(i915)) {
> > >  		revids = adls_revids;
> > >  		size = ARRAY_SIZE(adls_revids);
> > > +	} else if (IS_ROCKETLAKE(i915)) {
> > > +		revids = rkl_revids;
> > > +		size = ARRAY_SIZE(rkl_revids);
> > >  	} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
> > >  		revids = tgl_uy_revids;
> > >  		size = ARRAY_SIZE(tgl_uy_revids);
> > > --
> > > 2.25.4
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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[Intel-gfx] [PATCH v2 10/12] drm/i915/dg1: Use revid->stepping tables

[Matt Roper]

Switch DG1 to use a revid->stepping table as we're trying to do on all
platforms going forward.

This removes the last use of IS_REVID() and REVID_FOREVER, so remove
those now-unused macros as well to prevent their accidental use on
future platforms.

Bspec: 44463
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../gpu/drm/i915/display/intel_display_power.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c    |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c    | 10 +++++-----
 drivers/gpu/drm/i915/i915_drv.h                | 18 ++++--------------
 drivers/gpu/drm/i915/intel_pm.c                |  2 +-
 drivers/gpu/drm/i915/intel_step.c              |  8 ++++++++
 6 files changed, 20 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 285380079aab..975a7e25cea5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5799,7 +5799,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	int config, i;
 
 	if (IS_ALDERLAKE_S(dev_priv) ||
-	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
 	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		/* Wa_1409767108:tgl,dg1,adl-s */
 		table = wa_1409767108_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 1f43aba2e9e2..50d11a84e7a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
 static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
 				     u64 *start, u32 *size)
 {
-	if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
+	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
 		return false;
 
 	*start = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4c0c15bbdac2..62321e9149db 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1111,7 +1111,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1607087056:dg1 */
-	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1522,7 +1522,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
 	tgl_whitelist_build(engine);
 
 	/* GEN:BUG:1409280441:dg1 */
-	if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
 	    (engine->class == RENDER_CLASS ||
 	     engine->class == COPY_ENGINE_CLASS))
 		whitelist_reg_ext(w, RING_ID(engine->mmio_base),
@@ -1592,7 +1592,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
 	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
 		/*
 		 * Wa_1607138336:tgl[a0],dg1[a0]
@@ -1638,7 +1638,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 
 	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
-	    IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
 		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
@@ -1652,7 +1652,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 
 
-	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
 		/*
 		 * Wa_1607030317:tgl
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9195131cf90f..d462b9434541 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1323,19 +1323,10 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 #define IS_DISPLAY_VER(i915, from, until) \
 	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 
-#define REVID_FOREVER		0xff
 #define INTEL_REVID(dev_priv)	(to_pci_dev((dev_priv)->drm.dev)->revision)
 
 #define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)
 
-/*
- * Return true if revision is in range [since,until] inclusive.
- *
- * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
- */
-#define IS_REVID(p, since, until) \
-	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-
 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
 
@@ -1552,11 +1543,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_RKL_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
-#define DG1_REVID_A0		0x0
-#define DG1_REVID_B0		0x1
-
-#define IS_DG1_REVID(p, since, until) \
-	(IS_DG1(p) && IS_REVID(p, since, until))
+#define IS_DG1_GT_STEP(p, since, until) \
+	(IS_DG1(p) && IS_GT_STEP(p, since, until))
+#define IS_DG1_DISPLAY_STEP(p, since, until) \
+	(IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5fdb96e7d266..b933c9dc823a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7390,7 +7390,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
 	gen12lp_init_clock_gating(dev_priv);
 
 	/* Wa_1409836686:dg1[a0] */
-	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   DPT_GATING_DIS);
 }
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 21211649e6bb..36230d446f4a 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -81,6 +81,11 @@ static const struct intel_step_info rkl_revids[] = {
 	[4] = { COMMON_STEPPING(C0) },
 };
 
+static const struct intel_step_info dg1_revids[] = {
+	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+	[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+};
+
 static const struct intel_step_info adls_revids[] = {
 	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
@@ -109,6 +114,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ALDERLAKE_S(i915)) {
 		revids = adls_revids;
 		size = ARRAY_SIZE(adls_revids);
+	} else if (IS_DG1(i915)) {
+		revids = dg1_revids;
+		size = ARRAY_SIZE(dg1_revids);
 	} else if (IS_ROCKETLAKE(i915)) {
 		revids = rkl_revids;
 		size = ARRAY_SIZE(rkl_revids);
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 10/12] drm/i915/dg1: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 10/12] drm/i915/dg1: Use revid->stepping tables
> 
> Switch DG1 to use a revid->stepping table as we're trying to do on all
> platforms going forward.
> 
> This removes the last use of IS_REVID() and REVID_FOREVER, so remove
> those now-unused macros as well to prevent their accidental use on future
> platforms.
> 
> Bspec: 44463
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_power.c |  2 +-
>  drivers/gpu/drm/i915/gt/intel_region_lmem.c    |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c    | 10 +++++-----
>  drivers/gpu/drm/i915/i915_drv.h                | 18 ++++--------------
>  drivers/gpu/drm/i915/intel_pm.c                |  2 +-
>  drivers/gpu/drm/i915/intel_step.c              |  8 ++++++++
>  6 files changed, 20 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 285380079aab..975a7e25cea5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5799,7 +5799,7 @@ static void tgl_bw_buddy_init(struct
> drm_i915_private *dev_priv)
>  	int config, i;
> 
>  	if (IS_ALDERLAKE_S(dev_priv) ||
> -	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> +	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
>  	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		/* Wa_1409767108:tgl,dg1,adl-s */
>  		table = wa_1409767108_buddy_page_masks; diff --git
> a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 1f43aba2e9e2..50d11a84e7a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)  static
> bool get_legacy_lowmem_region(struct intel_uncore *uncore,
>  				     u64 *start, u32 *size)
>  {
> -	if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
> +	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
>  		return false;
> 
>  	*start = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4c0c15bbdac2..62321e9149db 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1111,7 +1111,7 @@ dg1_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
>  	gen12_gt_workarounds_init(i915, wal);
> 
>  	/* Wa_1607087056:dg1 */
> -	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); @@ -
> 1522,7 +1522,7 @@ static void dg1_whitelist_build(struct intel_engine_cs
> *engine)
>  	tgl_whitelist_build(engine);
> 
>  	/* GEN:BUG:1409280441:dg1 */
> -	if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
> +	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
>  	    (engine->class == RENDER_CLASS ||
>  	     engine->class == COPY_ENGINE_CLASS))
>  		whitelist_reg_ext(w, RING_ID(engine->mmio_base), @@ -
> 1592,7 +1592,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)  {
>  	struct drm_i915_private *i915 = engine->i915;
> 
> -	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>  	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
>  		/*
>  		 * Wa_1607138336:tgl[a0],dg1[a0]
> @@ -1638,7 +1638,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
>  	}
> 
>  	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> -	    IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> +	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>  	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>  		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
>  		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> @@ -1652,7 +1652,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
>  	}
> 
> 
> -	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>  	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>  		/*
>  		 * Wa_1607030317:tgl
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 9195131cf90f..d462b9434541
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1323,19 +1323,10 @@ static inline struct drm_i915_private
> *pdev_to_i915(struct pci_dev *pdev)  #define IS_DISPLAY_VER(i915, from,
> until) \
>  	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> 
> -#define REVID_FOREVER		0xff
>  #define INTEL_REVID(dev_priv)	(to_pci_dev((dev_priv)->drm.dev)-
> >revision)
> 
>  #define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)
> 
> -/*
> - * Return true if revision is in range [since,until] inclusive.
> - *
> - * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
> - */
> -#define IS_REVID(p, since, until) \
> -	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
> -
>  #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)-
> >step.display_step)
>  #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
> 
> @@ -1552,11 +1543,10 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_RKL_DISPLAY_STEP(p, since, until) \
>  	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> 
> -#define DG1_REVID_A0		0x0
> -#define DG1_REVID_B0		0x1
> -
> -#define IS_DG1_REVID(p, since, until) \
> -	(IS_DG1(p) && IS_REVID(p, since, until))
> +#define IS_DG1_GT_STEP(p, since, until) \
> +	(IS_DG1(p) && IS_GT_STEP(p, since, until)) #define
> +IS_DG1_DISPLAY_STEP(p, since, until) \
> +	(IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
> 
>  #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
>  	(IS_ALDERLAKE_S(__i915) && \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c index 5fdb96e7d266..b933c9dc823a
> 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7390,7 +7390,7 @@ static void dg1_init_clock_gating(struct
> drm_i915_private *dev_priv)
>  	gen12lp_init_clock_gating(dev_priv);
> 
>  	/* Wa_1409836686:dg1[a0] */
> -	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
> +	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
>  		intel_uncore_write(&dev_priv->uncore,
> GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore,
> GEN9_CLKGATE_DIS_3) |
>  			   DPT_GATING_DIS);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 21211649e6bb..36230d446f4a 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -81,6 +81,11 @@ static const struct intel_step_info rkl_revids[] = {
>  	[4] = { COMMON_STEPPING(C0) },
>  };
> 
> +static const struct intel_step_info dg1_revids[] = {
> +	[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> +	[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, };
> +

Same feedback as for JSL/EHL patch, here COMMON_STEP macro can be used.

Anusha
>  static const struct intel_step_info adls_revids[] = {
>  	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, @@ -109,6
> +114,9 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_ALDERLAKE_S(i915)) {
>  		revids = adls_revids;
>  		size = ARRAY_SIZE(adls_revids);
> +	} else if (IS_DG1(i915)) {
> +		revids = dg1_revids;
> +		size = ARRAY_SIZE(dg1_revids);
>  	} else if (IS_ROCKETLAKE(i915)) {
>  		revids = rkl_revids;
>  		size = ARRAY_SIZE(rkl_revids);
> --
> 2.25.4

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[Intel-gfx] [PATCH v3 10/12] drm/i915/dg1: Use revid->stepping tables

[Matt Roper]

Switch DG1 to use a revid->stepping table as we're trying to do on all
platforms going forward.

This removes the last use of IS_REVID() and REVID_FOREVER, so remove
those now-unused macros as well to prevent their accidental use on
future platforms.

v2:
 - Use COMMON_STEPPING() macro in table.  (Anusha)

Bspec: 44463
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../gpu/drm/i915/display/intel_display_power.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c    |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c    | 10 +++++-----
 drivers/gpu/drm/i915/i915_drv.h                | 18 ++++--------------
 drivers/gpu/drm/i915/intel_pm.c                |  2 +-
 drivers/gpu/drm/i915/intel_step.c              |  8 ++++++++
 6 files changed, 20 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 285380079aab..975a7e25cea5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5799,7 +5799,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	int config, i;
 
 	if (IS_ALDERLAKE_S(dev_priv) ||
-	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
 	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		/* Wa_1409767108:tgl,dg1,adl-s */
 		table = wa_1409767108_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 1f43aba2e9e2..50d11a84e7a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
 static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
 				     u64 *start, u32 *size)
 {
-	if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
+	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
 		return false;
 
 	*start = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4c0c15bbdac2..62321e9149db 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1111,7 +1111,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1607087056:dg1 */
-	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1522,7 +1522,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
 	tgl_whitelist_build(engine);
 
 	/* GEN:BUG:1409280441:dg1 */
-	if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
 	    (engine->class == RENDER_CLASS ||
 	     engine->class == COPY_ENGINE_CLASS))
 		whitelist_reg_ext(w, RING_ID(engine->mmio_base),
@@ -1592,7 +1592,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
 	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
 		/*
 		 * Wa_1607138336:tgl[a0],dg1[a0]
@@ -1638,7 +1638,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 
 	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
-	    IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
 		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
@@ -1652,7 +1652,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 	}
 
 
-	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
 		/*
 		 * Wa_1607030317:tgl
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9195131cf90f..d462b9434541 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1323,19 +1323,10 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 #define IS_DISPLAY_VER(i915, from, until) \
 	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 
-#define REVID_FOREVER		0xff
 #define INTEL_REVID(dev_priv)	(to_pci_dev((dev_priv)->drm.dev)->revision)
 
 #define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)
 
-/*
- * Return true if revision is in range [since,until] inclusive.
- *
- * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
- */
-#define IS_REVID(p, since, until) \
-	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-
 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
 
@@ -1552,11 +1543,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_RKL_DISPLAY_STEP(p, since, until) \
 	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
-#define DG1_REVID_A0		0x0
-#define DG1_REVID_B0		0x1
-
-#define IS_DG1_REVID(p, since, until) \
-	(IS_DG1(p) && IS_REVID(p, since, until))
+#define IS_DG1_GT_STEP(p, since, until) \
+	(IS_DG1(p) && IS_GT_STEP(p, since, until))
+#define IS_DG1_DISPLAY_STEP(p, since, until) \
+	(IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
 	(IS_ALDERLAKE_S(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5fdb96e7d266..b933c9dc823a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7390,7 +7390,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
 	gen12lp_init_clock_gating(dev_priv);
 
 	/* Wa_1409836686:dg1[a0] */
-	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   DPT_GATING_DIS);
 }
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index a6b2690f3947..c8f05ff6bfe5 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -81,6 +81,11 @@ static const struct intel_step_info rkl_revids[] = {
 	[4] = { COMMON_STEPPING(C0) },
 };
 
+static const struct intel_step_info dg1_revids[] = {
+	[0] = { COMMON_STEPPING(A0) },
+	[1] = { COMMON_STEPPING(B0) },
+};
+
 static const struct intel_step_info adls_revids[] = {
 	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
 	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
@@ -109,6 +114,9 @@ void intel_step_init(struct drm_i915_private *i915)
 	} else if (IS_ALDERLAKE_S(i915)) {
 		revids = adls_revids;
 		size = ARRAY_SIZE(adls_revids);
+	} else if (IS_DG1(i915)) {
+		revids = dg1_revids;
+		size = ARRAY_SIZE(dg1_revids);
 	} else if (IS_ROCKETLAKE(i915)) {
 		revids = rkl_revids;
 		size = ARRAY_SIZE(rkl_revids);
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v3 10/12] drm/i915/dg1: Use revid->stepping tables

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Tuesday, July 13, 2021 10:29 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v3 10/12] drm/i915/dg1: Use revid->stepping tables
> 
> Switch DG1 to use a revid->stepping table as we're trying to do on all
> platforms going forward.
> 
> This removes the last use of IS_REVID() and REVID_FOREVER, so remove
> those now-unused macros as well to prevent their accidental use on future
> platforms.
> 
> v2:
>  - Use COMMON_STEPPING() macro in table.  (Anusha)
> 
> Bspec: 44463
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_power.c |  2 +-
>  drivers/gpu/drm/i915/gt/intel_region_lmem.c    |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c    | 10 +++++-----
>  drivers/gpu/drm/i915/i915_drv.h                | 18 ++++--------------
>  drivers/gpu/drm/i915/intel_pm.c                |  2 +-
>  drivers/gpu/drm/i915/intel_step.c              |  8 ++++++++
>  6 files changed, 20 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 285380079aab..975a7e25cea5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5799,7 +5799,7 @@ static void tgl_bw_buddy_init(struct
> drm_i915_private *dev_priv)
>  	int config, i;
> 
>  	if (IS_ALDERLAKE_S(dev_priv) ||
> -	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> +	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
>  	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		/* Wa_1409767108:tgl,dg1,adl-s */
>  		table = wa_1409767108_buddy_page_masks; diff --git
> a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 1f43aba2e9e2..50d11a84e7a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)  static
> bool get_legacy_lowmem_region(struct intel_uncore *uncore,
>  				     u64 *start, u32 *size)
>  {
> -	if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
> +	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
>  		return false;
> 
>  	*start = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4c0c15bbdac2..62321e9149db 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1111,7 +1111,7 @@ dg1_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
>  	gen12_gt_workarounds_init(i915, wal);
> 
>  	/* Wa_1607087056:dg1 */
> -	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
>  		wa_write_or(wal,
>  			    SLICE_UNIT_LEVEL_CLKGATE,
>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); @@ -
> 1522,7 +1522,7 @@ static void dg1_whitelist_build(struct intel_engine_cs
> *engine)
>  	tgl_whitelist_build(engine);
> 
>  	/* GEN:BUG:1409280441:dg1 */
> -	if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
> +	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
>  	    (engine->class == RENDER_CLASS ||
>  	     engine->class == COPY_ENGINE_CLASS))
>  		whitelist_reg_ext(w, RING_ID(engine->mmio_base), @@ -
> 1592,7 +1592,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)  {
>  	struct drm_i915_private *i915 = engine->i915;
> 
> -	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>  	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
>  		/*
>  		 * Wa_1607138336:tgl[a0],dg1[a0]
> @@ -1638,7 +1638,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
>  	}
> 
>  	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> -	    IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> +	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>  	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>  		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
>  		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> @@ -1652,7 +1652,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
>  	}
> 
> 
> -	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> +	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
>  	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>  		/*
>  		 * Wa_1607030317:tgl
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 9195131cf90f..d462b9434541
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1323,19 +1323,10 @@ static inline struct drm_i915_private
> *pdev_to_i915(struct pci_dev *pdev)  #define IS_DISPLAY_VER(i915, from,
> until) \
>  	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> 
> -#define REVID_FOREVER		0xff
>  #define INTEL_REVID(dev_priv)	(to_pci_dev((dev_priv)->drm.dev)-
> >revision)
> 
>  #define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)
> 
> -/*
> - * Return true if revision is in range [since,until] inclusive.
> - *
> - * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
> - */
> -#define IS_REVID(p, since, until) \
> -	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
> -
>  #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)-
> >step.display_step)
>  #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
> 
> @@ -1552,11 +1543,10 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_RKL_DISPLAY_STEP(p, since, until) \
>  	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> 
> -#define DG1_REVID_A0		0x0
> -#define DG1_REVID_B0		0x1
> -
> -#define IS_DG1_REVID(p, since, until) \
> -	(IS_DG1(p) && IS_REVID(p, since, until))
> +#define IS_DG1_GT_STEP(p, since, until) \
> +	(IS_DG1(p) && IS_GT_STEP(p, since, until)) #define
> +IS_DG1_DISPLAY_STEP(p, since, until) \
> +	(IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
> 
>  #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
>  	(IS_ALDERLAKE_S(__i915) && \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c index 5fdb96e7d266..b933c9dc823a
> 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7390,7 +7390,7 @@ static void dg1_init_clock_gating(struct
> drm_i915_private *dev_priv)
>  	gen12lp_init_clock_gating(dev_priv);
> 
>  	/* Wa_1409836686:dg1[a0] */
> -	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
> +	if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
>  		intel_uncore_write(&dev_priv->uncore,
> GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore,
> GEN9_CLKGATE_DIS_3) |
>  			   DPT_GATING_DIS);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index a6b2690f3947..c8f05ff6bfe5 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -81,6 +81,11 @@ static const struct intel_step_info rkl_revids[] = {
>  	[4] = { COMMON_STEPPING(C0) },
>  };
> 
> +static const struct intel_step_info dg1_revids[] = {
> +	[0] = { COMMON_STEPPING(A0) },
> +	[1] = { COMMON_STEPPING(B0) },
> +};
> +
>  static const struct intel_step_info adls_revids[] = {
>  	[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
>  	[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, @@ -109,6
> +114,9 @@ void intel_step_init(struct drm_i915_private *i915)
>  	} else if (IS_ALDERLAKE_S(i915)) {
>  		revids = adls_revids;
>  		size = ARRAY_SIZE(adls_revids);
> +	} else if (IS_DG1(i915)) {
> +		revids = dg1_revids;
> +		size = ARRAY_SIZE(dg1_revids);
>  	} else if (IS_ROCKETLAKE(i915)) {
>  		revids = rkl_revids;
>  		size = ARRAY_SIZE(rkl_revids);
> --
> 2.25.4

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[Intel-gfx] [PATCH v2 11/12] drm/i915/cnl: Drop all workarounds

[Matt Roper]

All of the Cannon Lake hardware that came out had graphics fused off,
and our userspace drivers have already dropped their support for the
platform; CNL-specific code in i915 that isn't inherited by subsequent
platforms is effectively dead code.  Let's remove all of the
CNL-specific workarounds as a quick and easy first step.

References: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 55 ---------------------
 drivers/gpu/drm/i915/i915_drv.h             |  7 ---
 2 files changed, 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 62321e9149db..9b257a394305 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -514,35 +514,6 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
 		     GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 }
 
-static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
-				     struct i915_wa_list *wal)
-{
-	/* WaForceContextSaveRestoreNonCoherent:cnl */
-	wa_masked_en(wal, CNL_HDC_CHICKEN0,
-		     HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
-
-	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
-	wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
-		     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-
-	/* WaPushConstantDereferenceHoldDisable:cnl */
-	wa_masked_en(wal, GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
-
-	/* FtrEnableFastAnisoL1BankingFix:cnl */
-	wa_masked_en(wal, HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
-
-	/* WaDisable3DMidCmdPreemption:cnl */
-	wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
-
-	/* WaDisableGPGPUMidCmdPreemption:cnl */
-	wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
-			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
-			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
-
-	/* WaDisableEarlyEOT:cnl */
-	wa_masked_en(wal, GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
-}
-
 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
@@ -704,8 +675,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 		gen12_ctx_workarounds_init(engine, wal);
 	else if (GRAPHICS_VER(i915) == 11)
 		icl_ctx_workarounds_init(engine, wal);
-	else if (IS_CANNONLAKE(i915))
-		cnl_ctx_workarounds_init(engine, wal);
 	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
 		cfl_ctx_workarounds_init(engine, wal);
 	else if (IS_GEMINILAKE(i915))
@@ -982,15 +951,6 @@ icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
 }
 
-static void
-cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
-{
-	/* WaInPlaceDecompressionHang:cnl */
-	wa_write_or(wal,
-		    GEN9_GAMT_ECO_REG_RW_IA,
-		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-}
-
 static void
 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
@@ -1140,8 +1100,6 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		gen12_gt_workarounds_init(i915, wal);
 	else if (GRAPHICS_VER(i915) == 11)
 		icl_gt_workarounds_init(i915, wal);
-	else if (IS_CANNONLAKE(i915))
-		cnl_gt_workarounds_init(i915, wal);
 	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
 		cfl_gt_workarounds_init(i915, wal);
 	else if (IS_GEMINILAKE(i915))
@@ -1418,17 +1376,6 @@ static void cml_whitelist_build(struct intel_engine_cs *engine)
 	cfl_whitelist_build(engine);
 }
 
-static void cnl_whitelist_build(struct intel_engine_cs *engine)
-{
-	struct i915_wa_list *w = &engine->whitelist;
-
-	if (engine->class != RENDER_CLASS)
-		return;
-
-	/* WaEnablePreemptionGranularityControlByUMD:cnl */
-	whitelist_reg(w, GEN8_CS_CHICKEN1);
-}
-
 static void icl_whitelist_build(struct intel_engine_cs *engine)
 {
 	struct i915_wa_list *w = &engine->whitelist;
@@ -1542,8 +1489,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 		tgl_whitelist_build(engine);
 	else if (GRAPHICS_VER(i915) == 11)
 		icl_whitelist_build(engine);
-	else if (IS_CANNONLAKE(i915))
-		cnl_whitelist_build(engine);
 	else if (IS_COMETLAKE(i915))
 		cml_whitelist_build(engine);
 	else if (IS_COFFEELAKE(i915))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d462b9434541..8682a5f557c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1513,13 +1513,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 
-#define CNL_REVID_A0		0x0
-#define CNL_REVID_B0		0x1
-#define CNL_REVID_C0		0x2
-
-#define IS_CNL_REVID(p, since, until) \
-	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
-
 #define IS_ICL_GT_STEP(p, since, until) \
 	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
 
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 11/12] drm/i915/cnl: Drop all workarounds

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 11/12] drm/i915/cnl: Drop all workarounds
> 
> All of the Cannon Lake hardware that came out had graphics fused off, and
> our userspace drivers have already dropped their support for the platform;
> CNL-specific code in i915 that isn't inherited by subsequent platforms is
> effectively dead code.  Let's remove all of the CNL-specific workarounds as a
> quick and easy first step.
> 
> References: https://gitlab.freedesktop.org/mesa/mesa/-
> /merge_requests/6899
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 55 ---------------------
>  drivers/gpu/drm/i915/i915_drv.h             |  7 ---
>  2 files changed, 62 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 62321e9149db..9b257a394305 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -514,35 +514,6 @@ static void cfl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> 
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>  }
> 
> -static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
> -				     struct i915_wa_list *wal)
> -{
> -	/* WaForceContextSaveRestoreNonCoherent:cnl */
> -	wa_masked_en(wal, CNL_HDC_CHICKEN0,
> -
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> -
> -	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
> -	wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
> -		     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> -
> -	/* WaPushConstantDereferenceHoldDisable:cnl */
> -	wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> PUSH_CONSTANT_DEREF_DISABLE);
> -
> -	/* FtrEnableFastAnisoL1BankingFix:cnl */
> -	wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> CNL_FAST_ANISO_L1_BANKING_FIX);
> -
> -	/* WaDisable3DMidCmdPreemption:cnl */
> -	wa_masked_dis(wal, GEN8_CS_CHICKEN1,
> GEN9_PREEMPT_3D_OBJECT_LEVEL);
> -
> -	/* WaDisableGPGPUMidCmdPreemption:cnl */
> -	wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
> -			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> -			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
> -
> -	/* WaDisableEarlyEOT:cnl */
> -	wa_masked_en(wal, GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
> -}
> -
>  static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  				     struct i915_wa_list *wal)
>  {
> @@ -704,8 +675,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs
> *engine,
>  		gen12_ctx_workarounds_init(engine, wal);
>  	else if (GRAPHICS_VER(i915) == 11)
>  		icl_ctx_workarounds_init(engine, wal);
> -	else if (IS_CANNONLAKE(i915))
> -		cnl_ctx_workarounds_init(engine, wal);
>  	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
>  		cfl_ctx_workarounds_init(engine, wal);
>  	else if (IS_GEMINILAKE(i915))
> @@ -982,15 +951,6 @@ icl_wa_init_mcr(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
>  	wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);  }
> 
> -static void
> -cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal) -{
> -	/* WaInPlaceDecompressionHang:cnl */
> -	wa_write_or(wal,
> -		    GEN9_GAMT_ECO_REG_RW_IA,
> -		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> -}
> -
>  static void
>  icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)  { @@ -1140,8 +1100,6 @@ gt_init_workarounds(struct
> drm_i915_private *i915, struct i915_wa_list *wal)
>  		gen12_gt_workarounds_init(i915, wal);
>  	else if (GRAPHICS_VER(i915) == 11)
>  		icl_gt_workarounds_init(i915, wal);
> -	else if (IS_CANNONLAKE(i915))
> -		cnl_gt_workarounds_init(i915, wal);
>  	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
>  		cfl_gt_workarounds_init(i915, wal);
>  	else if (IS_GEMINILAKE(i915))
> @@ -1418,17 +1376,6 @@ static void cml_whitelist_build(struct
> intel_engine_cs *engine)
>  	cfl_whitelist_build(engine);
>  }
> 
> -static void cnl_whitelist_build(struct intel_engine_cs *engine) -{
> -	struct i915_wa_list *w = &engine->whitelist;
> -
> -	if (engine->class != RENDER_CLASS)
> -		return;
> -
> -	/* WaEnablePreemptionGranularityControlByUMD:cnl */
> -	whitelist_reg(w, GEN8_CS_CHICKEN1);
> -}
> -
>  static void icl_whitelist_build(struct intel_engine_cs *engine)  {
>  	struct i915_wa_list *w = &engine->whitelist; @@ -1542,8 +1489,6
> @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  		tgl_whitelist_build(engine);
>  	else if (GRAPHICS_VER(i915) == 11)
>  		icl_whitelist_build(engine);
> -	else if (IS_CANNONLAKE(i915))
> -		cnl_whitelist_build(engine);
>  	else if (IS_COMETLAKE(i915))
>  		cml_whitelist_build(engine);
>  	else if (IS_COFFEELAKE(i915))
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index d462b9434541..8682a5f557c5
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1513,13 +1513,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
>  	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since,
> until))
> 
> -#define CNL_REVID_A0		0x0
> -#define CNL_REVID_B0		0x1
> -#define CNL_REVID_C0		0x2
> -
> -#define IS_CNL_REVID(p, since, until) \
> -	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
> -
>  #define IS_ICL_GT_STEP(p, since, until) \
>  	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
> 
> --
> 2.25.4

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[Intel-gfx] [PATCH v2 12/12] drm/i915/icl: Drop workarounds that only apply to pre-production steppings

[Matt Roper]

We're past the point at which we usually drop workarounds that were
never needed on production hardware.  The driver will already print an
error and apply taint if loaded on pre-production hardware.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ---------------------
 drivers/gpu/drm/i915/i915_drv.h             |  3 --
 2 files changed, 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9b257a394305..5ace14cdfa85 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -517,21 +517,12 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
-	struct drm_i915_private *i915 = engine->i915;
-
 	/* WaDisableBankHangMode:icl */
 	wa_write(wal,
 		 GEN8_L3CNTLREG,
 		 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
 		 GEN8_ERRDETBCTRL);
 
-	/* Wa_1604370585:icl (pre-prod)
-	 * Formerly known as WaPushConstantDereferenceHoldDisable
-	 */
-	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
-		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
-			     PUSH_CONSTANT_DEREF_DISABLE);
-
 	/* WaForceEnableNonCoherent:icl
 	 * This is not the same workaround as in early Gen9 platforms, where
 	 * lacking this could cause system hangs, but coherency performance
@@ -541,18 +532,6 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	 */
 	wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
 
-	/* Wa_2006611047:icl (pre-prod)
-	 * Formerly known as WaDisableImprovedTdlClkGating
-	 */
-	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
-		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
-			     GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
-
-	/* Wa_2006665173:icl (pre-prod) */
-	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
-		wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
-			     GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
-
 	/* WaEnableFloatBlendOptimization:icl */
 	wa_write_clr_set(wal,
 			 GEN10_CACHE_MODE_SS,
@@ -982,18 +961,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		    GEN8_GAMW_ECO_DEV_RW_IA,
 		    GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
 
-	/* Wa_1405779004:icl (pre-prod) */
-	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
-		wa_write_or(wal,
-			    SLICE_UNIT_LEVEL_CLKGATE,
-			    MSCUNIT_CLKGATE_DIS);
-
-	/* Wa_1406838659:icl (pre-prod) */
-	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
-		wa_write_or(wal,
-			    INF_UNIT_LEVEL_CLKGATE,
-			    CGPSF_CLKGATE_DIS);
-
 	/* Wa_1406463099:icl
 	 * Formerly known as WaGamTlbPendError
 	 */
@@ -1669,12 +1636,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    PMFLUSH_GAPL3UNBLOCK |
 			    PMFLUSHDONE_LNEBLK);
 
-		/* Wa_1406609255:icl (pre-prod) */
-		if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
-			wa_write_or(wal,
-				    GEN7_SARCHKMD,
-				    GEN7_DISABLE_DEMAND_PREFETCH);
-
 		/* Wa_1606682166:icl */
 		wa_write_or(wal,
 			    GEN7_SARCHKMD,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8682a5f557c5..da5f230e2d4b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1513,9 +1513,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 
-#define IS_ICL_GT_STEP(p, since, until) \
-	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
-
 #define IS_JSL_EHL_GT_STEP(p, since, until) \
 	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
-- 
2.25.4

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Re: [Intel-gfx] [PATCH v2 12/12] drm/i915/icl: Drop workarounds that only apply to pre-production steppings

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v2 12/12] drm/i915/icl: Drop workarounds that only apply to
> pre-production steppings
> 
> We're past the point at which we usually drop workarounds that were never
> needed on production hardware.  The driver will already print an error and
> apply taint if loaded on pre-production hardware.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Definitely cleans up the code. 

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ---------------------
>  drivers/gpu/drm/i915/i915_drv.h             |  3 --
>  2 files changed, 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9b257a394305..5ace14cdfa85 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -517,21 +517,12 @@ static void cfl_ctx_workarounds_init(struct
> intel_engine_cs *engine,  static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>  				     struct i915_wa_list *wal)
>  {
> -	struct drm_i915_private *i915 = engine->i915;
> -
>  	/* WaDisableBankHangMode:icl */
>  	wa_write(wal,
>  		 GEN8_L3CNTLREG,
>  		 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
>  		 GEN8_ERRDETBCTRL);
> 
> -	/* Wa_1604370585:icl (pre-prod)
> -	 * Formerly known as WaPushConstantDereferenceHoldDisable
> -	 */
> -	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
> -		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> -			     PUSH_CONSTANT_DEREF_DISABLE);
> -
>  	/* WaForceEnableNonCoherent:icl
>  	 * This is not the same workaround as in early Gen9 platforms, where
>  	 * lacking this could cause system hangs, but coherency performance
> @@ -541,18 +532,6 @@ static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>  	 */
>  	wa_masked_en(wal, ICL_HDC_MODE,
> HDC_FORCE_NON_COHERENT);
> 
> -	/* Wa_2006611047:icl (pre-prod)
> -	 * Formerly known as WaDisableImprovedTdlClkGating
> -	 */
> -	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
> -		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> -			     GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
> -
> -	/* Wa_2006665173:icl (pre-prod) */
> -	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
> -		wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> -			     GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
> -
>  	/* WaEnableFloatBlendOptimization:icl */
>  	wa_write_clr_set(wal,
>  			 GEN10_CACHE_MODE_SS,
> @@ -982,18 +961,6 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
>  		    GEN8_GAMW_ECO_DEV_RW_IA,
>  		    GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
> 
> -	/* Wa_1405779004:icl (pre-prod) */
> -	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
> -		wa_write_or(wal,
> -			    SLICE_UNIT_LEVEL_CLKGATE,
> -			    MSCUNIT_CLKGATE_DIS);
> -
> -	/* Wa_1406838659:icl (pre-prod) */
> -	if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
> -		wa_write_or(wal,
> -			    INF_UNIT_LEVEL_CLKGATE,
> -			    CGPSF_CLKGATE_DIS);
> -
>  	/* Wa_1406463099:icl
>  	 * Formerly known as WaGamTlbPendError
>  	 */
> @@ -1669,12 +1636,6 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
>  			    PMFLUSH_GAPL3UNBLOCK |
>  			    PMFLUSHDONE_LNEBLK);
> 
> -		/* Wa_1406609255:icl (pre-prod) */
> -		if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
> -			wa_write_or(wal,
> -				    GEN7_SARCHKMD,
> -				    GEN7_DISABLE_DEMAND_PREFETCH);
> -
>  		/* Wa_1606682166:icl */
>  		wa_write_or(wal,
>  			    GEN7_SARCHKMD,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 8682a5f557c5..da5f230e2d4b
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1513,9 +1513,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,  #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
>  	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since,
> until))
> 
> -#define IS_ICL_GT_STEP(p, since, until) \
> -	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
> -
>  #define IS_JSL_EHL_GT_STEP(p, since, until) \
>  	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))  #define
> IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
> --
> 2.25.4

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Minor revid/stepping and workaround cleanup (rev2)

[Patchwork]

== Series Details ==

Series: Minor revid/stepping and workaround cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/92299/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
602f2fe49dc0 drm/i915/step: s/<platform>_revid_tbl/<platform>_revids
023cab2a2100 drm/i915: Make pre-production detection use direct revid comparison
f260bb283918 drm/i915/skl: Use revid->stepping tables
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_drv.h:1518:
+#define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 80 lines checked
02447a87c0cc drm/i915/kbl: Drop pre-production revision from stepping table
2ee48fd0d6f6 drm/i915/bxt: Use revid->stepping tables
c506016c4648 drm/i915/glk: Use revid->stepping tables
db965751e531 drm/i915/icl: Use revid->stepping tables
-:116: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#116: FILE: drivers/gpu/drm/i915/i915_drv.h:1532:
+#define IS_ICL_GT_STEP(p, since, until) \
+	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 87 lines checked
fc2b6164fa50 drm/i915/jsl_ehl: Use revid->stepping tables
-:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#51: FILE: drivers/gpu/drm/i915/i915_drv.h:1535:
+#define IS_JSL_EHL_GT_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))

-:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#53: FILE: drivers/gpu/drm/i915/i915_drv.h:1537:
+#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))

total: 0 errors, 0 warnings, 2 checks, 51 lines checked
c53e1e6ba585 drm/i915/rkl: Use revid->stepping tables
-:48: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#48: FILE: drivers/gpu/drm/i915/i915_drv.h:1552:
+#define IS_RKL_DISPLAY_STEP(p, since, until) \
+	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 51 lines checked
36d6af0814ee drm/i915/dg1: Use revid->stepping tables
-:124: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#124: FILE: drivers/gpu/drm/i915/i915_drv.h:1546:
+#define IS_DG1_GT_STEP(p, since, until) \
+	(IS_DG1(p) && IS_GT_STEP(p, since, until))

-:126: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#126: FILE: drivers/gpu/drm/i915/i915_drv.h:1548:
+#define IS_DG1_DISPLAY_STEP(p, since, until) \
+	(IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))

total: 0 errors, 0 warnings, 2 checks, 118 lines checked
febbb9864d60 drm/i915/cnl: Drop all workarounds
4fbd5e59cb10 drm/i915/icl: Drop workarounds that only apply to pre-production steppings


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[Intel-gfx] ✓ Fi.CI.BAT: success for Minor revid/stepping and workaround cleanup (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 2819 bytes --]

== Series Details ==

Series: Minor revid/stepping and workaround cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/92299/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10329 -> Patchwork_20568
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/index.html

Known issues
------------

  Here are the changes found in Patchwork_20568 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [FAIL][1] ([i915#1372]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  
#### Warnings ####

  * igt@runner@aborted:
    - fi-ilk-650:         [FAIL][3] ([i915#3744]) -> [FAIL][4] ([i915#2426])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/fi-ilk-650/igt@runner@aborted.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/fi-ilk-650/igt@runner@aborted.html

  
  [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#3744]: https://gitlab.freedesktop.org/drm/intel/issues/3744


Participating hosts (41 -> 39)
------------------------------

  Missing    (2): fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_10329 -> Patchwork_20568

  CI-20190529: 20190529
  CI_DRM_10329: 2c76b98f510f1e4284285813024bc4cbba6a776e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6134: cd63c83e23789eb194d38b8d272247a88122f2f6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20568: 4fbd5e59cb1093058dccbe32b3d37ba24a5d4219 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4fbd5e59cb10 drm/i915/icl: Drop workarounds that only apply to pre-production steppings
febbb9864d60 drm/i915/cnl: Drop all workarounds
36d6af0814ee drm/i915/dg1: Use revid->stepping tables
c53e1e6ba585 drm/i915/rkl: Use revid->stepping tables
fc2b6164fa50 drm/i915/jsl_ehl: Use revid->stepping tables
db965751e531 drm/i915/icl: Use revid->stepping tables
c506016c4648 drm/i915/glk: Use revid->stepping tables
2ee48fd0d6f6 drm/i915/bxt: Use revid->stepping tables
02447a87c0cc drm/i915/kbl: Drop pre-production revision from stepping table
f260bb283918 drm/i915/skl: Use revid->stepping tables
023cab2a2100 drm/i915: Make pre-production detection use direct revid comparison
602f2fe49dc0 drm/i915/step: s/<platform>_revid_tbl/<platform>_revids

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/index.html

[-- Attachment #1.2: Type: text/html, Size: 3521 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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[Intel-gfx] ✗ Fi.CI.IGT: failure for Minor revid/stepping and workaround cleanup (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30273 bytes --]

== Series Details ==

Series: Minor revid/stepping and workaround cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/92299/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10329_full -> Patchwork_20568_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20568_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20568_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20568_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_ccs:
    - {shard-rkl}:        [FAIL][1] ([i915#3678]) -> [SKIP][2] +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-2/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_ccs.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_ccs.html

  

### Piglit changes ###

#### Possible regressions ####

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat2_array5-int_ivec3 (NEW):
    - pig-skl-6260u:      NOTRUN -> [INCOMPLETE][3] +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/pig-skl-6260u/spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat2_array5-int_ivec3.html

  
New tests
---------

  New tests have been introduced between CI_DRM_10329_full and Patchwork_20568_full:

### New Piglit tests (4) ###

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat2_array5-int_ivec3:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-float_mat3x2-double_dmat2x3:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-int_ivec3-double_dmat3_array2:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-uint_uvec3-double_dvec4_array2:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_20568_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@legacy-engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +5 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [PASS][5] -> [FAIL][6] ([i915#2410])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-iclb:         [PASS][12] -> [FAIL][13] ([i915#2842]) +2 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
    - shard-kbl:          [PASS][14] -> [SKIP][15] ([fdo#109271])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_reloc@basic-wide-active@bcs0:
    - shard-apl:          NOTRUN -> [FAIL][16] ([i915#3633]) +3 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl2/igt@gem_exec_reloc@basic-wide-active@bcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@big-copy:
    - shard-skl:          [PASS][18] -> [FAIL][19] ([i915#307])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl10/igt@gem_mmap_gtt@big-copy.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl10/igt@gem_mmap_gtt@big-copy.html

  * igt@gem_mmap_gtt@cpuset-medium-copy-odd:
    - shard-iclb:         [PASS][20] -> [FAIL][21] ([i915#2428])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-iclb4/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb2/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][22] ([i915#3318])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl7/igt@gem_userptr_blits@vma-merge.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [PASS][23] -> [DMESG-WARN][24] ([i915#1436] / [i915#716])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-glk4/igt@gen9_exec_parse@allowed-all.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk3/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-skl:          [PASS][25] -> [INCOMPLETE][26] ([i915#151])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl8/igt@i915_pm_rpm@system-suspend-execbuf.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl6/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-snb:          NOTRUN -> [FAIL][27] ([i915#3745])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-snb2/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-skl:          [PASS][28] -> [FAIL][29] ([i915#2521])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip.html
    - shard-kbl:          [PASS][30] -> [FAIL][31] ([i915#2521])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-kbl7/igt@kms_async_flips@alternate-sync-async-flip.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl2/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][32] ([fdo#109271]) +89 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl2/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_cdclk@mode-transition:
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271]) +330 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl7/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-skl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl8/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@hdmi-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +29 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl3/igt@kms_chamelium@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
    - shard-snb:          NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +15 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium@vga-hpd-without-ddc:
    - shard-iclb:         NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb5/igt@kms_chamelium@vga-hpd-without-ddc.html

  * igt@kms_color@pipe-b-ctm-0-25:
    - shard-skl:          [PASS][38] -> [DMESG-WARN][39] ([i915#1982])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl3/igt@kms_color@pipe-b-ctm-0-25.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl10/igt@kms_color@pipe-b-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-a-ctm-0-75:
    - shard-kbl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +9 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl2/igt@kms_color_chamelium@pipe-a-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
    - shard-glk:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk5/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html

  * igt@kms_content_protection@atomic:
    - shard-kbl:          NOTRUN -> [TIMEOUT][42] ([i915#1319]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl7/igt@kms_content_protection@atomic.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#109278]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb5/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html

  * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
    - shard-snb:          NOTRUN -> [SKIP][44] ([fdo#109271]) +366 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-snb2/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
    - shard-skl:          NOTRUN -> [SKIP][45] ([fdo#109271]) +63 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl8/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][46] -> [FAIL][47] ([i915#72])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-skl:          [PASS][48] -> [FAIL][49] ([i915#2346])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-skl:          [PASS][50] -> [FAIL][51] ([i915#79]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-suspend@b-dp1:
    - shard-apl:          [PASS][52] -> [DMESG-WARN][53] ([i915#180])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-apl3/igt@kms_flip@flip-vs-suspend@b-dp1.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl1/igt@kms_flip@flip-vs-suspend@b-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-apl:          NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#2672])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-glk:          NOTRUN -> [SKIP][55] ([fdo#109271]) +12 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk5/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][56] ([fdo#109280])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][57] -> [FAIL][58] ([i915#1188])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [PASS][59] -> [DMESG-WARN][60] ([i915#180]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533]) +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#533])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl8/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][63] ([i915#265])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
    - shard-kbl:          NOTRUN -> [FAIL][64] ([fdo#108145] / [i915#265])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
    - shard-skl:          NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][67] -> [FAIL][68] ([fdo#108145] / [i915#265])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
    - shard-kbl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658]) +3 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
    - shard-glk:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +6 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
    - shard-skl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +1 similar issue
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][73] -> [SKIP][74] ([fdo#109441]) +3 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][75] -> [DMESG-WARN][76] ([i915#180] / [i915#295])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2437])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl6/igt@kms_writeback@writeback-check-output.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][78] -> [FAIL][79] ([i915#1542])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl4/igt@perf@polling-parameterized.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl2/igt@perf@polling-parameterized.html

  * igt@perf_pmu@module-unload:
    - shard-skl:          [PASS][80] -> [DMESG-WARN][81] ([i915#1982] / [i915#262])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl10/igt@perf_pmu@module-unload.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl10/igt@perf_pmu@module-unload.html

  * igt@sysfs_clients@fair-1:
    - shard-apl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2994]) +6 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl2/igt@sysfs_clients@fair-1.html

  
#### Possible fixes ####

  * igt@fbdev@unaligned-read:
    - {shard-rkl}:        [SKIP][83] ([i915#2582]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-5/igt@fbdev@unaligned-read.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@fbdev@unaligned-read.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - shard-apl:          [DMESG-WARN][85] ([i915#180]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-apl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vecs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [FAIL][87] ([i915#2846]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-glk8/igt@gem_exec_fair@basic-deadline.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk1/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [FAIL][89] ([i915#2842]) -> [PASS][90] +1 similar issue
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_schedule@u-independent@vecs0:
    - {shard-rkl}:        [FAIL][91] -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-6/igt@gem_exec_schedule@u-independent@vecs0.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-1/igt@gem_exec_schedule@u-independent@vecs0.html

  * igt@gem_exec_whisper@basic-contexts-priority-all:
    - shard-glk:          [DMESG-WARN][93] ([i915#118] / [i915#95]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-glk1/igt@gem_exec_whisper@basic-contexts-priority-all.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk5/igt@gem_exec_whisper@basic-contexts-priority-all.html

  * igt@gem_mmap_offset@clear:
    - shard-iclb:         [FAIL][95] ([i915#3160]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-iclb1/igt@gem_mmap_offset@clear.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb1/igt@gem_mmap_offset@clear.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-skl:          [DMESG-WARN][97] ([i915#1982]) -> [PASS][98] +2 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl3/igt@i915_module_load@reload-with-fault-injection.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl1/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_backlight@fade:
    - {shard-rkl}:        [SKIP][99] ([i915#3012]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-5/igt@i915_pm_backlight@fade.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@i915_pm_backlight@fade.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - {shard-rkl}:        [SKIP][101] ([i915#1397]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-5/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@gem-execbuf:
    - {shard-rkl}:        [SKIP][103] ([fdo#109308]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-1/igt@i915_pm_rpm@gem-execbuf.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@i915_pm_rpm@gem-execbuf.html

  * igt@i915_suspend@sysfs-reader:
    - {shard-rkl}:        [FAIL][105] ([fdo#103375]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-6/igt@i915_suspend@sysfs-reader.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-2/igt@i915_suspend@sysfs-reader.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180:
    - {shard-rkl}:        [SKIP][107] ([i915#3721]) -> [PASS][108] +4 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-5/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
    - {shard-rkl}:        [SKIP][109] ([i915#3638]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-2/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - {shard-rkl}:        [FAIL][111] ([i915#3678]) -> [PASS][112] +6 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-1/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_color@pipe-a-ctm-0-75:
    - {shard-rkl}:        [SKIP][113] ([i915#1149] / [i915#1849]) -> [PASS][114] +2 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-5/igt@kms_color@pipe-a-ctm-0-75.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-75.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
    - {shard-rkl}:        [SKIP][115] ([fdo#112022]) -> [PASS][116] +14 similar issues
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html

  * igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size:
    - shard-kbl:          [INCOMPLETE][117] ([fdo#109052]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-kbl2/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl1/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - {shard-rkl}:        [SKIP][119] ([fdo#111825]) -> [PASS][120] +5 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-skl:          [FAIL][121] ([i915#2346]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * {igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a}:
    - shard-iclb:         [SKIP][123] -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-iclb2/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-iclb3/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
    - {shard-rkl}:        [SKIP][125] ([fdo#111314]) -> [PASS][126] +6 similar issues
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][127] ([i915#79]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [FAIL][129] ([i915#79]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][131] ([i915#180]) -> [PASS][132] +5 similar issues
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1:
    - shard-skl:          [FAIL][133] ([i915#2122]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl8/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl4/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html

  * igt@kms_flip_tiling@flip-changes-tiling-yf@edp-1-pipe-a:
    - shard-skl:          [FAIL][135] ([i915#699]) -> [PASS][136]
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-skl3/igt@kms_flip_tiling@flip-changes-tiling-yf@edp-1-pipe-a.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-skl6/igt@kms_flip_tiling@flip-changes-tiling-yf@edp-1-pipe-a.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
    - {shard-rkl}:        [SKIP][137] ([i915#1849]) -> [PASS][138] +39 similar issues
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-5/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/shard-rkl-6/igt@kms_pipe_crc_basic@read-crc-pipe-c.html

  * igt@kms_plane@plane-panning-top-left@pipe-b-planes:
    - {shard-rkl}:        [SKIP][139] ([i915#3558]) -> [PASS][140] +4 similar issues
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10329/shard-rkl-5/igt@kms_plane@plane-panning-top-left@pipe-b-planes.html
   [140]: https://inte

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20568/index.html

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Minor revid/stepping and workaround cleanup (rev4)

[Patchwork]

== Series Details ==

Series: Minor revid/stepping and workaround cleanup (rev4)
URL   : https://patchwork.freedesktop.org/series/92299/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
62d758aadfe3 drm/i915/step: s/<platform>_revid_tbl/<platform>_revids
76bd03989163 drm/i915: Make pre-production detection use direct revid comparison
5c84247d6ac9 drm/i915/skl: Use revid->stepping tables
-:57: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#57: FILE: drivers/gpu/drm/i915/i915_drv.h:1518:
+#define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 80 lines checked
1c898561ba39 drm/i915/kbl: Drop pre-production revision from stepping table
27320b6e947b drm/i915/bxt: Use revid->stepping tables
bfc4af69ce3b drm/i915/glk: Use revid->stepping tables
ea04a99db33e drm/i915/icl: Use revid->stepping tables
-:116: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#116: FILE: drivers/gpu/drm/i915/i915_drv.h:1532:
+#define IS_ICL_GT_STEP(p, since, until) \
+	(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 87 lines checked
95aec3b31d70 drm/i915/jsl_ehl: Use revid->stepping tables
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_drv.h:1535:
+#define IS_JSL_EHL_GT_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))

-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/i915_drv.h:1537:
+#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
+	(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))

total: 0 errors, 0 warnings, 2 checks, 51 lines checked
d515112313b0 drm/i915/rkl: Use revid->stepping tables
-:49: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#49: FILE: drivers/gpu/drm/i915/i915_drv.h:1552:
+#define IS_RKL_DISPLAY_STEP(p, since, until) \
+	(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 51 lines checked
28dea784c5d3 drm/i915/dg1: Use revid->stepping tables
-:129: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#129: FILE: drivers/gpu/drm/i915/i915_drv.h:1546:
+#define IS_DG1_GT_STEP(p, since, until) \
+	(IS_DG1(p) && IS_GT_STEP(p, since, until))

-:131: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#131: FILE: drivers/gpu/drm/i915/i915_drv.h:1548:
+#define IS_DG1_DISPLAY_STEP(p, since, until) \
+	(IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))

total: 0 errors, 0 warnings, 2 checks, 118 lines checked
a66bc53c20b3 drm/i915/cnl: Drop all workarounds
d62d0ec1b3aa drm/i915/icl: Drop workarounds that only apply to pre-production steppings


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[Intel-gfx] ✓ Fi.CI.BAT: success for Minor revid/stepping and workaround cleanup (rev4)

[Patchwork]

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== Series Details ==

Series: Minor revid/stepping and workaround cleanup (rev4)
URL   : https://patchwork.freedesktop.org/series/92299/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10342 -> Patchwork_20588
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20588/index.html

Known issues
------------

  Here are the changes found in Patchwork_20588 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@query-info:
    - fi-bsw-kefka:       NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20588/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html

  * igt@gem_exec_gttfill@basic:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][2] ([fdo#109271])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20588/fi-bsw-n3050/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-bsw-n3050:       NOTRUN -> [INCOMPLETE][3] ([i915#3159])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20588/fi-bsw-n3050/igt@gem_exec_suspend@basic-s3.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-soraka:      [DMESG-WARN][4] ([i915#1982]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10342/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20588/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-kefka:       [INCOMPLETE][6] ([i915#2782] / [i915#2940]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10342/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20588/fi-bsw-kefka/igt@i915_selftest@live@execlists.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3159]: https://gitlab.freedesktop.org/drm/intel/issues/3159
  [i915#3717]: https://gitlab.freedesktop.org/drm/intel/issues/3717


Participating hosts (38 -> 36)
------------------------------

  Additional (1): fi-bsw-n3050 
  Missing    (3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_10342 -> Patchwork_20588

  CI-20190529: 20190529
  CI_DRM_10342: 308b278ffbef846356ca6b220ef1aa908c22c5fd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6137: 2fee489255f7a8cd6a584373c30e3d44a07a78ea @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20588: d62d0ec1b3aa504119130e0c61f1b16ad15f06a2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d62d0ec1b3aa drm/i915/icl: Drop workarounds that only apply to pre-production steppings
a66bc53c20b3 drm/i915/cnl: Drop all workarounds
28dea784c5d3 drm/i915/dg1: Use revid->stepping tables
d515112313b0 drm/i915/rkl: Use revid->stepping tables
95aec3b31d70 drm/i915/jsl_ehl: Use revid->stepping tables
ea04a99db33e drm/i915/icl: Use revid->stepping tables
bfc4af69ce3b drm/i915/glk: Use revid->stepping tables
27320b6e947b drm/i915/bxt: Use revid->stepping tables
1c898561ba39 drm/i915/kbl: Drop pre-production revision from stepping table
5c84247d6ac9 drm/i915/skl: Use revid->stepping tables
76bd03989163 drm/i915: Make pre-production detection use direct revid comparison
62d758aadfe3 drm/i915/step: s/<platform>_revid_tbl/<platform>_revids

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20588/index.html

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