* [PATCH 0/3] STM32MP15 OTG params updates
@ 2020-11-23 9:01 Amelie Delaunay
2020-11-23 9:01 ` [PATCH 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS Amelie Delaunay
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Amelie Delaunay @ 2020-11-23 9:01 UTC (permalink / raw)
To: Minas Harutyunyan, Felipe Balbi, Greg Kroah-Hartman
Cc: linux-usb, linux-kernel, linux-stm32, Fabrice Gasnier, Amelie Delaunay
This patchset brings some updates on STM32MP15 OTG HS and FS.
It sets ahbcfg parameter for both HS and FS as the value reported by the
hardware is not recommended.
It also disables Link Power Management on OTG HS because with some Host
controllers (at least seen with some USB 3.2 Gen2 controllers), OTG doesn't
succeed to exit L1 state.
It also enables FS/LS PHY clock selection when the Core is in FS Host mode,
to have 6MHz PHY clock when the connected device is LS, and 48Mhz PHY clock
otherwise.
Amelie Delaunay (3):
usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS
usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG
usb: dwc2: disable Link Power Management on STM32MP15 HS OTG
drivers/usb/dwc2/params.c | 8 ++++++++
1 file changed, 8 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS
2020-11-23 9:01 [PATCH 0/3] STM32MP15 OTG params updates Amelie Delaunay
@ 2020-11-23 9:01 ` Amelie Delaunay
2020-11-30 6:16 ` Minas Harutyunyan
2020-11-23 9:01 ` [PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG Amelie Delaunay
2020-11-23 9:01 ` [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG Amelie Delaunay
2 siblings, 1 reply; 7+ messages in thread
From: Amelie Delaunay @ 2020-11-23 9:01 UTC (permalink / raw)
To: Minas Harutyunyan, Felipe Balbi, Greg Kroah-Hartman
Cc: linux-usb, linux-kernel, linux-stm32, Fabrice Gasnier, Amelie Delaunay
STM32MP15 ahbcfg register default value sets Burst length/type (HBSTLEN)
to Single (32-bit accesses on AHB), which is not recommended, according
to STM32MP157 Reference manual [1].
This patch sets Burst length/type (HBSTLEN) so that bus transactions
target 16x32 bit accesses. This improves OTG controller performance.
[1] https://www.st.com/resource/en/reference_manual/dm00327659.pdf, p.3149
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
drivers/usb/dwc2/params.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 267543c3dc38..0df693319f0a 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -177,6 +177,7 @@ static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
p->i2c_enable = false;
p->activate_stm_fs_transceiver = true;
p->activate_stm_id_vb_detection = true;
+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
}
@@ -189,6 +190,7 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
p->host_rx_fifo_size = 440;
p->host_nperio_tx_fifo_size = 256;
p->host_perio_tx_fifo_size = 256;
+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS
2020-11-23 9:01 ` [PATCH 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS Amelie Delaunay
@ 2020-11-30 6:16 ` Minas Harutyunyan
0 siblings, 0 replies; 7+ messages in thread
From: Minas Harutyunyan @ 2020-11-30 6:16 UTC (permalink / raw)
To: Amelie Delaunay, Felipe Balbi, Greg Kroah-Hartman
Cc: linux-usb, linux-kernel, linux-stm32, Fabrice Gasnier
On 11/23/2020 1:01 PM, Amelie Delaunay wrote:
> STM32MP15 ahbcfg register default value sets Burst length/type (HBSTLEN)
> to Single (32-bit accesses on AHB), which is not recommended, according
> to STM32MP157 Reference manual [1].
> This patch sets Burst length/type (HBSTLEN) so that bus transactions
> target 16x32 bit accesses. This improves OTG controller performance.
>
> [1] https://urldefense.com/v3/__https://www.st.com/resource/en/reference_manual/dm00327659.pdf__;!!A4F2R9G_pg!J1HTs3kobvYfS453htoIdnxhej4_os5Y5xwMfRtfhptE_QSeVw3O1mozY-v4AvE$ , p.3149
>
> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Acked-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
> ---
> drivers/usb/dwc2/params.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 267543c3dc38..0df693319f0a 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -177,6 +177,7 @@ static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
> p->i2c_enable = false;
> p->activate_stm_fs_transceiver = true;
> p->activate_stm_id_vb_detection = true;
> + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
> p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
> }
>
> @@ -189,6 +190,7 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
> p->host_rx_fifo_size = 440;
> p->host_nperio_tx_fifo_size = 256;
> p->host_perio_tx_fifo_size = 256;
> + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
> p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
> }
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG
2020-11-23 9:01 [PATCH 0/3] STM32MP15 OTG params updates Amelie Delaunay
2020-11-23 9:01 ` [PATCH 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS Amelie Delaunay
@ 2020-11-23 9:01 ` Amelie Delaunay
2020-11-30 6:17 ` Minas Harutyunyan
2020-11-23 9:01 ` [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG Amelie Delaunay
2 siblings, 1 reply; 7+ messages in thread
From: Amelie Delaunay @ 2020-11-23 9:01 UTC (permalink / raw)
To: Minas Harutyunyan, Felipe Balbi, Greg Kroah-Hartman
Cc: linux-usb, linux-kernel, linux-stm32, Fabrice Gasnier, Amelie Delaunay
When the core is in FS host mode, using the FS transceiver, and a Low-Speed
device is connected, transceiver clock is 6Mhz.
So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
so that the PHY supplies a 6 MHz clock during Low-Speed mode.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
drivers/usb/dwc2/params.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 0df693319f0a..9e5dd7f3f2f6 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -179,6 +179,8 @@ static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
p->activate_stm_id_vb_detection = true;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+ p->host_support_fs_ls_low_power = true;
+ p->host_ls_low_power_phy_clk = true;
}
static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG
2020-11-23 9:01 ` [PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG Amelie Delaunay
@ 2020-11-30 6:17 ` Minas Harutyunyan
0 siblings, 0 replies; 7+ messages in thread
From: Minas Harutyunyan @ 2020-11-30 6:17 UTC (permalink / raw)
To: Amelie Delaunay, Felipe Balbi, Greg Kroah-Hartman
Cc: linux-usb, linux-kernel, linux-stm32, Fabrice Gasnier
On 11/23/2020 1:01 PM, Amelie Delaunay wrote:
> When the core is in FS host mode, using the FS transceiver, and a Low-Speed
> device is connected, transceiver clock is 6Mhz.
> So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
> so that the PHY supplies a 6 MHz clock during Low-Speed mode.
>
> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Acked-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
> ---
> drivers/usb/dwc2/params.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 0df693319f0a..9e5dd7f3f2f6 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -179,6 +179,8 @@ static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
> p->activate_stm_id_vb_detection = true;
> p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
> p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
> + p->host_support_fs_ls_low_power = true;
> + p->host_ls_low_power_phy_clk = true;
> }
>
> static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG
2020-11-23 9:01 [PATCH 0/3] STM32MP15 OTG params updates Amelie Delaunay
2020-11-23 9:01 ` [PATCH 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS Amelie Delaunay
2020-11-23 9:01 ` [PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG Amelie Delaunay
@ 2020-11-23 9:01 ` Amelie Delaunay
2020-11-30 6:17 ` Minas Harutyunyan
2 siblings, 1 reply; 7+ messages in thread
From: Amelie Delaunay @ 2020-11-23 9:01 UTC (permalink / raw)
To: Minas Harutyunyan, Felipe Balbi, Greg Kroah-Hartman
Cc: linux-usb, linux-kernel, linux-stm32, Fabrice Gasnier, Amelie Delaunay
Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities
with some Host controllers. OTG core fails to exit L1 state in 200us:
"dwc2 49000000.usb-otg: Failed to exit L1 sleep state in 200us."
Then the device is still not enumerated.
To avoid this issue, disable Link Power Management on STM32MP15 HS OTG.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
drivers/usb/dwc2/params.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 9e5dd7f3f2f6..92df3d620f7d 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -194,6 +194,10 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
p->host_perio_tx_fifo_size = 256;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+ p->lpm = false;
+ p->lpm_clock_gating = false;
+ p->besl = false;
+ p->hird_threshold_en = false;
}
const struct of_device_id dwc2_of_match_table[] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG
2020-11-23 9:01 ` [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG Amelie Delaunay
@ 2020-11-30 6:17 ` Minas Harutyunyan
0 siblings, 0 replies; 7+ messages in thread
From: Minas Harutyunyan @ 2020-11-30 6:17 UTC (permalink / raw)
To: Amelie Delaunay, Felipe Balbi, Greg Kroah-Hartman
Cc: linux-usb, linux-kernel, linux-stm32, Fabrice Gasnier
On 11/23/2020 1:01 PM, Amelie Delaunay wrote:
> Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities
> with some Host controllers. OTG core fails to exit L1 state in 200us:
> "dwc2 49000000.usb-otg: Failed to exit L1 sleep state in 200us."
> Then the device is still not enumerated.
>
> To avoid this issue, disable Link Power Management on STM32MP15 HS OTG.
>
> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Acked-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
> ---
> drivers/usb/dwc2/params.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 9e5dd7f3f2f6..92df3d620f7d 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -194,6 +194,10 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
> p->host_perio_tx_fifo_size = 256;
> p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
> p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
> + p->lpm = false;
> + p->lpm_clock_gating = false;
> + p->besl = false;
> + p->hird_threshold_en = false;
> }
>
> const struct of_device_id dwc2_of_match_table[] = {
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-11-30 6:18 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-23 9:01 [PATCH 0/3] STM32MP15 OTG params updates Amelie Delaunay
2020-11-23 9:01 ` [PATCH 1/3] usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS Amelie Delaunay
2020-11-30 6:16 ` Minas Harutyunyan
2020-11-23 9:01 ` [PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG Amelie Delaunay
2020-11-30 6:17 ` Minas Harutyunyan
2020-11-23 9:01 ` [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG Amelie Delaunay
2020-11-30 6:17 ` Minas Harutyunyan
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