[PATCH 0/8] net: several updates to support i.MX

[PATCH 0/8] net: several updates to support i.MX

[Peng Fan]

The patchset is to upstream NXP downstream network patches that
runs on i.MX platforms, including eqos update, sharded mdio support,
mac addr accessing and etc.

Fugang Duan (3):
  net: phy: realtek: add rx delay support for RTL8211F
  net: dwc_eth_qos: add dwc eqos for imx support
  net: eqos: implement callbaks to get interface and set txclk rate

Peng Fan (1):
  net: eth-uclass: add return value check

Ye Li (4):
  net: Add eth phy generic driver for shared MDIO
  net: Update eQos driver and FEC driver to use eth phy interfaces
  fec: Move imx_get_mac_from_fuse declare to imx file
  eQos: Implement the read_rom_hwaddr callback

 arch/arm/include/asm/mach-imx/sys_proto.h |   2 +
 drivers/net/Kconfig                       |   6 +
 drivers/net/Makefile                      |   1 +
 drivers/net/dwc_eth_qos.c                 | 284 +++++++++++++++++++++++++++---
 drivers/net/eth-phy-uclass.c              | 123 +++++++++++++
 drivers/net/fec_mxc.c                     |  16 +-
 drivers/net/fec_mxc.h                     |   2 -
 drivers/net/phy/realtek.c                 |  11 ++
 include/dm/uclass-id.h                    |   1 +
 include/eth_phy.h                         |  17 ++
 net/eth-uclass.c                          |  17 +-
 11 files changed, 446 insertions(+), 34 deletions(-)
 create mode 100644 drivers/net/eth-phy-uclass.c
 create mode 100644 include/eth_phy.h

-- 
2.16.4

[PATCH 1/8] net: eth-uclass: add return value check

[Peng Fan]

Add return value check

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 net/eth-uclass.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 8bf2eabe90..950a48d520 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -40,8 +40,12 @@ static int eth_errno;
 static struct eth_uclass_priv *eth_get_uclass_priv(void)
 {
 	struct uclass *uc;
+	int ret;
+
+	ret = uclass_get(UCLASS_ETH, &uc);
+	if (ret)
+		return NULL;
 
-	uclass_get(UCLASS_ETH, &uc);
 	assert(uc);
 	return uc->priv;
 }
@@ -102,6 +106,7 @@ struct udevice *eth_get_dev_by_name(const char *devname)
 	struct udevice *it;
 	struct uclass *uc;
 	int len = strlen("eth");
+	int ret;
 
 	/* Must be longer than 3 to be an alias */
 	if (!strncmp(devname, "eth", len) && strlen(devname) > len) {
@@ -109,7 +114,10 @@ struct udevice *eth_get_dev_by_name(const char *devname)
 		seq = simple_strtoul(startp, &endp, 10);
 	}
 
-	uclass_get(UCLASS_ETH, &uc);
+	ret = uclass_get(UCLASS_ETH, &uc);
+	if (ret)
+		return NULL;
+
 	uclass_foreach_dev(it, uc) {
 		/*
 		 * We need the seq to be valid, so try to probe it.
-- 
2.16.4

[PATCH 2/8] net: Add eth phy generic driver for shared MDIO

[Peng Fan]

From: Ye Li <ye.li@nxp.com>

For dual ethernet controllers, the HW design may connect ETH phys to
one MDIO ports. So two different ethernet drivers have to share MDIO bus.
Since two ethernet drivers are independent, we can't ensure their probe
order.

To resolve this problem, introduce an eth phy generic driver and uclass.

After eth-uclass binds, we search the mdio node and binds the phy node
with the eth-phy-generic driver.

When one eth driver get its phy device, the parent of phy device will
probe prior than phy device. So this ensure the eth driver ownes the
MDIO bus will be probed before using its MDIO.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/net/Kconfig          |   6 +++
 drivers/net/Makefile         |   1 +
 drivers/net/eth-phy-uclass.c | 122 ++++++++++++++++++++++++++++++++++++++++++
 include/dm/uclass-id.h       |   1 +
 include/eth_phy.h            |  17 ++++++
 net/eth-uclass.c             |   5 ++
 6 files changed, 152 insertions(+)
 create mode 100644 drivers/net/eth-phy-uclass.c
 create mode 100644 include/eth_phy.h

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..d77bb221e0 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -57,6 +57,12 @@ config MDIO_MUX_SANDBOX
 
 	  This driver is used for testing in test/dm/mdio.c
 
+config DM_ETH_PHY
+	bool "Enable Driver Model for Ethernet Generic PHY drivers"
+	depends on DM
+	help
+	  Enable driver model for Ethernet Generic PHY .
+
 menuconfig NETDEVICES
 	bool "Network device support"
 	depends on NET
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6e0a68834d..f6c5ae4fe7 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
 obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
 obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 obj-$(CONFIG_DNET) += dnet.o
+obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
new file mode 100644
index 0000000000..e87c7aee80
--- /dev/null
+++ b/drivers/net/eth-phy-uclass.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <dm/lists.h>
+
+struct eth_phy_device_priv {
+	struct mii_dev *mdio_bus;
+};
+
+int eth_phy_binds_nodes(struct udevice *eth_dev)
+{
+	ofnode mdio_node, phy_node;
+	const char *node_name;
+	int ret;
+
+	mdio_node = dev_read_subnode(eth_dev, "mdio");
+	if (!ofnode_valid(mdio_node)) {
+		debug("%s: %s mdio subnode not found!", __func__,
+		      eth_dev->name);
+		return -ENXIO;
+	}
+
+	ofnode_for_each_subnode(phy_node, mdio_node) {
+		node_name = ofnode_get_name(phy_node);
+
+		debug("* Found child node: '%s'\n", node_name);
+
+		ret = device_bind_driver_to_node(eth_dev,
+						 "eth_phy_generic_drv",
+						 node_name, phy_node, NULL);
+		if (ret) {
+			debug("  - Eth phy binding error: %d\n", ret);
+			continue;
+		}
+
+		debug("  - bound phy device: '%s'\n", node_name);
+	}
+
+	return 0;
+}
+
+int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus)
+{
+	struct udevice *dev;
+	struct eth_phy_device_priv *uc_priv;
+
+	for (uclass_first_device(UCLASS_ETH_PHY, &dev); dev;
+	     uclass_next_device(&dev)) {
+		if (dev->parent == eth_dev) {
+			uc_priv = (struct eth_phy_device_priv *)(dev->uclass_priv);
+
+			if (!uc_priv->mdio_bus)
+				uc_priv->mdio_bus = mdio_bus;
+		}
+	}
+
+	return 0;
+}
+
+struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev)
+{
+	int ret;
+	struct udevice *phy_dev;
+	struct eth_phy_device_priv *uc_priv;
+
+	/* Will probe the parent of phy device, then phy device */
+	ret = uclass_get_device_by_phandle(UCLASS_ETH_PHY, eth_dev,
+					   "phy-handle", &phy_dev);
+	if (!ret) {
+		if (eth_dev != phy_dev->parent) {
+			/*
+			 * phy_dev is shared and controlled by
+			 * other eth controller
+			 */
+			uc_priv = (struct eth_phy_device_priv *)(phy_dev->uclass_priv);
+			if (uc_priv->mdio_bus)
+				printf("Get shared mii bus on %s\n", eth_dev->name);
+			else
+				printf("Can't get shared mii bus on %s\n", eth_dev->name);
+
+			return uc_priv->mdio_bus;
+		}
+	} else {
+		printf("FEC: can't find phy-handle\n");
+	}
+
+	return NULL;
+}
+
+int eth_phy_get_addr(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle_args;
+	int reg;
+
+	if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+				       &phandle_args)) {
+		debug("Failed to find phy-handle");
+		return -ENODEV;
+	}
+
+	reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+	return reg;
+}
+
+UCLASS_DRIVER(eth_phy_generic) = {
+	.id		= UCLASS_ETH_PHY,
+	.name		= "eth_phy_generic",
+	.per_device_auto_alloc_size = sizeof(struct eth_phy_device_priv),
+};
+
+U_BOOT_DRIVER(eth_phy_generic_drv) = {
+	.name		= "eth_phy_generic_drv",
+	.id		= UCLASS_ETH_PHY,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 37ada51f9f..7837d459f1 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -47,6 +47,7 @@ enum uclass_id {
 	UCLASS_DMA,		/* Direct Memory Access */
 	UCLASS_EFI,		/* EFI managed devices */
 	UCLASS_ETH,		/* Ethernet device */
+	UCLASS_ETH_PHY,		/* Ethernet PHY device */
 	UCLASS_FIRMWARE,	/* Firmware */
 	UCLASS_FS_FIRMWARE_LOADER,		/* Generic loader */
 	UCLASS_GPIO,		/* Bank of general-purpose I/O pins */
diff --git a/include/eth_phy.h b/include/eth_phy.h
new file mode 100644
index 0000000000..50c496ff42
--- /dev/null
+++ b/include/eth_phy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef _eth_phy_h_
+#define _eth_phy_h_
+
+#include <dm.h>
+#include <phy.h>
+
+int eth_phy_binds_nodes(struct udevice *eth_dev);
+int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus);
+struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev);
+int eth_phy_get_addr(struct udevice *dev);
+
+#endif
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 950a48d520..48560d59f6 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -13,6 +13,7 @@
 #include <dm/uclass-internal.h>
 #include <net/pcap.h>
 #include "eth_internal.h"
+#include <eth_phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -461,6 +462,10 @@ static int eth_post_bind(struct udevice *dev)
 		return -EINVAL;
 	}
 
+#ifdef CONFIG_DM_ETH_PHY
+	eth_phy_binds_nodes(dev);
+#endif
+
 	return 0;
 }
 
-- 
2.16.4

[PATCH 3/8] net: Update eQos driver and FEC driver to use eth phy interfaces

[Peng Fan]

From: Ye Li <ye.li@nxp.com>

Update eQoS and fec ethernet drivers to support shared MDIO framework

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/net/dwc_eth_qos.c | 45 +++++++++++++++++++++++++++++++--------------
 drivers/net/fec_mxc.c     | 16 ++++++++++++++--
 2 files changed, 45 insertions(+), 16 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec..dc2299dd69 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -41,6 +41,7 @@
 #include <wait_bit.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <eth_phy.h>
 
 /* Core registers */
 
@@ -1083,7 +1084,14 @@ static int eqos_start(struct udevice *dev)
 	 * don't need to reconnect/reconfigure again
 	 */
 	if (!eqos->phy) {
-		eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev,
+		int addr = -1;
+#ifdef CONFIG_DM_ETH_PHY
+		addr = eth_phy_get_addr(dev);
+#endif
+#ifdef DWC_NET_PHYADDR
+		addr = DWC_NET_PHYADDR;
+#endif
+		eqos->phy = phy_connect(eqos->mii, addr, dev,
 					eqos->config->interface(dev));
 		if (!eqos->phy) {
 			pr_err("phy_connect() failed");
@@ -1810,23 +1818,32 @@ static int eqos_probe(struct udevice *dev)
 		goto err_remove_resources_core;
 	}
 
-	eqos->mii = mdio_alloc();
+#ifdef CONFIG_DM_ETH_PHY
+	eqos->mii = eth_phy_get_mdio_bus(dev);
+#endif
 	if (!eqos->mii) {
-		pr_err("mdio_alloc() failed");
-		ret = -ENOMEM;
-		goto err_remove_resources_tegra;
-	}
-	eqos->mii->read = eqos_mdio_read;
-	eqos->mii->write = eqos_mdio_write;
-	eqos->mii->priv = eqos;
-	strcpy(eqos->mii->name, dev->name);
+		eqos->mii = mdio_alloc();
+		if (!eqos->mii) {
+			pr_err("mdio_alloc() failed");
+			ret = -ENOMEM;
+			goto err_remove_resources_tegra;
+		}
+		eqos->mii->read = eqos_mdio_read;
+		eqos->mii->write = eqos_mdio_write;
+		eqos->mii->priv = eqos;
+		strcpy(eqos->mii->name, dev->name);
 
-	ret = mdio_register(eqos->mii);
-	if (ret < 0) {
-		pr_err("mdio_register() failed: %d", ret);
-		goto err_free_mdio;
+		ret = mdio_register(eqos->mii);
+		if (ret < 0) {
+			pr_err("mdio_register() failed: %d", ret);
+			goto err_free_mdio;
+		}
 	}
 
+#ifdef CONFIG_DM_ETH_PHY
+	eth_phy_set_mdio_bus(dev, eqos->mii);
+#endif
+
 	debug("%s: OK\n", __func__);
 	return 0;
 
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index bc5b63d788..2c8f743a58 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -28,6 +28,7 @@
 #include <asm-generic/gpio.h>
 
 #include "fec_mxc.h"
+#include <eth_phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -1420,16 +1421,27 @@ static int fecmxc_probe(struct udevice *dev)
 	fec_reg_setup(priv);
 
 	priv->dev_id = dev->seq;
+
+#ifdef CONFIG_DM_ETH_PHY
+	bus = eth_phy_get_mdio_bus(dev);
+#endif
+
+	if (!bus) {
 #ifdef CONFIG_FEC_MXC_MDIO_BASE
-	bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
+		bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
 #else
-	bus = fec_get_miibus((ulong)priv->eth, dev->seq);
+		bus = fec_get_miibus((ulong)priv->eth, dev->seq);
 #endif
+	}
 	if (!bus) {
 		ret = -ENOMEM;
 		goto err_mii;
 	}
 
+#ifdef CONFIG_DM_ETH_PHY
+	eth_phy_set_mdio_bus(dev, bus);
+#endif
+
 	priv->bus = bus;
 	priv->interface = pdata->phy_interface;
 	switch (priv->interface) {
-- 
2.16.4

[PATCH 4/8] net: phy: realtek: add rx delay support for RTL8211F

[Peng Fan]

From: Fugang Duan <fugang.duan@nxp.com>

Add RX delay enable support for RTL8211F PHY.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/net/phy/realtek.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 8f1d759632..8f0a897a46 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -56,6 +56,7 @@
 
 #define MIIM_RTL8211F_PAGE_SELECT      0x1f
 #define MIIM_RTL8211F_TX_DELAY		0x100
+#define MIIM_RTL8211F_RX_DELAY		0x8
 #define MIIM_RTL8211F_LCR		0x10
 
 static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
@@ -183,6 +184,16 @@ static int rtl8211f_config(struct phy_device *phydev)
 		reg &= ~MIIM_RTL8211F_TX_DELAY;
 
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
+
+	/* enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+		reg |= MIIM_RTL8211F_RX_DELAY;
+	else
+		reg &= ~MIIM_RTL8211F_RX_DELAY;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg);
+
 	/* restore to default page 0 */
 	phy_write(phydev, MDIO_DEVAD_NONE,
 		  MIIM_RTL8211F_PAGE_SELECT, 0x0);
-- 
2.16.4

[PATCH 5/8] net: dwc_eth_qos: add dwc eqos for imx support

[Peng Fan]

From: Fugang Duan <fugang.duan@nxp.com>

Add dwc eqos for imx support.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/net/dwc_eth_qos.c | 187 ++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 173 insertions(+), 14 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index dc2299dd69..d63ea5cfb4 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -81,6 +81,7 @@ struct eqos_mac_regs {
 #define EQOS_MAC_CONFIGURATION_PS			BIT(15)
 #define EQOS_MAC_CONFIGURATION_FES			BIT(14)
 #define EQOS_MAC_CONFIGURATION_DM			BIT(13)
+#define EQOS_MAC_CONFIGURATION_LM			BIT(12)
 #define EQOS_MAC_CONFIGURATION_TE			BIT(1)
 #define EQOS_MAC_CONFIGURATION_RE			BIT(0)
 
@@ -102,11 +103,19 @@ struct eqos_mac_regs {
 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT			0
 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK			0xff
 
+#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT		8
+#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT		2
+#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT		1
+#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT		0
+
 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT		6
 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK		0x1f
 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT		0
 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK		0x1f
 
+#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT			28
+#define EQOS_MAC_HW_FEATURE3_ASP_MASK			0x3
+
 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT			21
 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT			16
 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT			8
@@ -154,6 +163,8 @@ struct eqos_mtl_regs {
 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK		0x3f
 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC		BIT(7)
 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF		BIT(5)
+#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP		BIT(4)
+#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP		BIT(3)
 
 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT			16
 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK			0x7fff
@@ -368,7 +379,7 @@ static void eqos_inval_desc_tegra186(void *desc)
 #endif
 }
 
-static void eqos_inval_desc_stm32(void *desc)
+static void eqos_inval_desc_generic(void *desc)
 {
 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 	unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
@@ -386,7 +397,7 @@ static void eqos_flush_desc_tegra186(void *desc)
 #endif
 }
 
-static void eqos_flush_desc_stm32(void *desc)
+static void eqos_flush_desc_generic(void *desc)
 {
 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 	unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
@@ -405,7 +416,7 @@ static void eqos_inval_buffer_tegra186(void *buf, size_t size)
 	invalidate_dcache_range(start, end);
 }
 
-static void eqos_inval_buffer_stm32(void *buf, size_t size)
+static void eqos_inval_buffer_generic(void *buf, size_t size)
 {
 	unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
 	unsigned long end = roundup((unsigned long)buf + size,
@@ -419,7 +430,7 @@ static void eqos_flush_buffer_tegra186(void *buf, size_t size)
 	flush_cache((unsigned long)buf, size);
 }
 
-static void eqos_flush_buffer_stm32(void *buf, size_t size)
+static void eqos_flush_buffer_generic(void *buf, size_t size)
 {
 	unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
 	unsigned long end = roundup((unsigned long)buf + size,
@@ -522,6 +533,7 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
 
 static int eqos_start_clks_tegra186(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 	int ret;
 
@@ -562,10 +574,12 @@ static int eqos_start_clks_tegra186(struct udevice *dev)
 		pr_err("clk_enable(clk_tx) failed: %d", ret);
 		goto err_disable_clk_ptp_ref;
 	}
+#endif
 
 	debug("%s: OK\n", __func__);
 	return 0;
 
+#ifdef CONFIG_CLK
 err_disable_clk_ptp_ref:
 	clk_disable(&eqos->clk_ptp_ref);
 err_disable_clk_rx:
@@ -577,10 +591,12 @@ err_disable_clk_slave_bus:
 err:
 	debug("%s: FAILED: %d\n", __func__, ret);
 	return ret;
+#endif
 }
 
 static int eqos_start_clks_stm32(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 	int ret;
 
@@ -611,10 +627,12 @@ static int eqos_start_clks_stm32(struct udevice *dev)
 			goto err_disable_clk_tx;
 		}
 	}
+#endif
 
 	debug("%s: OK\n", __func__);
 	return 0;
 
+#ifdef CONFIG_CLK
 err_disable_clk_tx:
 	clk_disable(&eqos->clk_tx);
 err_disable_clk_rx:
@@ -624,10 +642,17 @@ err_disable_clk_master_bus:
 err:
 	debug("%s: FAILED: %d\n", __func__, ret);
 	return ret;
+#endif
+}
+
+static int eqos_start_clks_imx(struct udevice *dev)
+{
+	return 0;
 }
 
 static void eqos_stop_clks_tegra186(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 
 	debug("%s(dev=%p):\n", __func__, dev);
@@ -637,12 +662,14 @@ static void eqos_stop_clks_tegra186(struct udevice *dev)
 	clk_disable(&eqos->clk_rx);
 	clk_disable(&eqos->clk_master_bus);
 	clk_disable(&eqos->clk_slave_bus);
+#endif
 
 	debug("%s: OK\n", __func__);
 }
 
 static void eqos_stop_clks_stm32(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 
 	debug("%s(dev=%p):\n", __func__, dev);
@@ -652,10 +679,16 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
 	clk_disable(&eqos->clk_master_bus);
 	if (clk_valid(&eqos->clk_ck))
 		clk_disable(&eqos->clk_ck);
+#endif
 
 	debug("%s: OK\n", __func__);
 }
 
+static void eqos_stop_clks_imx(struct udevice *dev)
+{
+	/* empty */
+}
+
 static int eqos_start_resets_tegra186(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -723,6 +756,11 @@ static int eqos_start_resets_stm32(struct udevice *dev)
 	return 0;
 }
 
+static int eqos_start_resets_imx(struct udevice *dev)
+{
+	return 0;
+}
+
 static int eqos_stop_resets_tegra186(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -750,6 +788,11 @@ static int eqos_stop_resets_stm32(struct udevice *dev)
 	return 0;
 }
 
+static int eqos_stop_resets_imx(struct udevice *dev)
+{
+	return 0;
+}
+
 static int eqos_calibrate_pads_tegra186(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -804,16 +847,30 @@ static int eqos_disable_calibration_tegra186(struct udevice *dev)
 
 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 
 	return clk_get_rate(&eqos->clk_slave_bus);
+#else
+	return 0;
+#endif
 }
 
 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 
 	return clk_get_rate(&eqos->clk_master_bus);
+#else
+	return 0;
+#endif
+}
+
+static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
+{
+	/* TODO: retrieve from CSR clock */
+	return 100 * 1000000;
 }
 
 static int eqos_calibrate_pads_stm32(struct udevice *dev)
@@ -821,11 +878,21 @@ static int eqos_calibrate_pads_stm32(struct udevice *dev)
 	return 0;
 }
 
+static int eqos_calibrate_pads_imx(struct udevice *dev)
+{
+	return 0;
+}
+
 static int eqos_disable_calibration_stm32(struct udevice *dev)
 {
 	return 0;
 }
 
+static int eqos_disable_calibration_imx(struct udevice *dev)
+{
+	return 0;
+}
+
 static int eqos_set_full_duplex(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -890,6 +957,7 @@ static int eqos_set_mii_speed_10(struct udevice *dev)
 
 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 	ulong rate;
 	int ret;
@@ -916,6 +984,7 @@ static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
 		pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
 		return ret;
 	}
+#endif
 
 	return 0;
 }
@@ -925,6 +994,11 @@ static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
 	return 0;
 }
 
+static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
+{
+	return 0;
+}
+
 static int eqos_adjust_link(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1131,6 +1205,7 @@ static int eqos_start(struct udevice *dev)
 	}
 
 	/* Configure MTL */
+	writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
 
 	/* Enable Store and Forward mode for TX */
 	/* Program Tx operating mode */
@@ -1144,7 +1219,9 @@ static int eqos_start(struct udevice *dev)
 
 	/* Enable Store and Forward mode for RX, since no jumbo frame */
 	setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
-		     EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
+		     EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
+		     EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
+		     EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
 
 	/* Transmit/Receive queue fifo size; use all RAM for 1 queue */
 	val = readl(&eqos->mac_regs->hw_feature1);
@@ -1220,6 +1297,19 @@ static int eqos_start(struct udevice *dev)
 			eqos->config->config_mac <<
 			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
 
+	clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
+			EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
+			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
+			0x2 <<
+			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
+
+	/* Multicast and Broadcast Queue Enable */
+	setbits_le32(&eqos->mac_regs->unused_0a4,
+		     0x00100000);
+	/* enable promise mode */
+	setbits_le32(&eqos->mac_regs->unused_004[1],
+		     0x1);
+
 	/* Set TX flow control parameters */
 	/* Set Pause Time */
 	setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
@@ -1297,6 +1387,11 @@ static int eqos_start(struct udevice *dev)
 		rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
 					     (i * EQOS_MAX_PACKET_SIZE));
 		rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+		mb();
+		eqos->config->ops->eqos_flush_desc(rx_desc);
+		eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
+						(i * EQOS_MAX_PACKET_SIZE),
+						EQOS_MAX_PACKET_SIZE);
 	}
 	eqos->config->ops->eqos_flush_desc(eqos->descs);
 
@@ -1311,14 +1406,12 @@ static int eqos_start(struct udevice *dev)
 	       &eqos->dma_regs->ch0_rxdesc_ring_length);
 
 	/* Enable everything */
-
-	setbits_le32(&eqos->mac_regs->configuration,
-		     EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
-
 	setbits_le32(&eqos->dma_regs->ch0_tx_control,
 		     EQOS_DMA_CH0_TX_CONTROL_ST);
 	setbits_le32(&eqos->dma_regs->ch0_rx_control,
 		     EQOS_DMA_CH0_RX_CONTROL_SR);
+	setbits_le32(&eqos->mac_regs->configuration,
+		     EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
 
 	/* TX tail pointer not written until we need to TX a packet */
 	/*
@@ -1450,6 +1543,7 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
 	debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
 
 	rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+	eqos->config->ops->eqos_inval_desc(rx_desc);
 	if (rx_desc->des3 & EQOS_DESC3_OWN) {
 		debug("%s: RX packet not available\n", __func__);
 		return -EAGAIN;
@@ -1481,6 +1575,8 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
 		return -EINVAL;
 	}
 
+	eqos->config->ops->eqos_inval_buffer(packet, length);
+
 	rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
 	rx_desc->des0 = (u32)(ulong)packet;
 	rx_desc->des1 = 0;
@@ -1749,17 +1845,42 @@ static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
 	return PHY_INTERFACE_MODE_MII;
 }
 
+static int eqos_probe_resources_imx(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	phy_interface_t interface;
+
+	debug("%s(dev=%p):\n", __func__, dev);
+
+	interface = eqos->config->interface(dev);
+
+	if (interface == PHY_INTERFACE_MODE_NONE) {
+		pr_err("Invalid PHY interface\n");
+		return -EINVAL;
+	}
+
+	debug("%s: OK\n", __func__);
+	return 0;
+}
+
+static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
+{
+	return PHY_INTERFACE_MODE_RGMII;
+}
+
 static int eqos_remove_resources_tegra186(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
 
 	debug("%s(dev=%p):\n", __func__, dev);
 
+#ifdef CONFIG_CLK
 	clk_free(&eqos->clk_tx);
 	clk_free(&eqos->clk_ptp_ref);
 	clk_free(&eqos->clk_rx);
 	clk_free(&eqos->clk_slave_bus);
 	clk_free(&eqos->clk_master_bus);
+#endif
 	dm_gpio_free(dev, &eqos->phy_reset_gpio);
 	reset_free(&eqos->reset_ctl);
 
@@ -1769,6 +1890,7 @@ static int eqos_remove_resources_tegra186(struct udevice *dev)
 
 static int eqos_remove_resources_stm32(struct udevice *dev)
 {
+#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 
 	debug("%s(dev=%p):\n", __func__, dev);
@@ -1778,6 +1900,7 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
 	clk_free(&eqos->clk_master_bus);
 	if (clk_valid(&eqos->clk_ck))
 		clk_free(&eqos->clk_ck);
+#endif
 
 	if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
 		dm_gpio_free(dev, &eqos->phy_reset_gpio);
@@ -1786,6 +1909,11 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
 	return 0;
 }
 
+static int eqos_remove_resources_imx(struct udevice *dev)
+{
+	return 0;
+}
+
 static int eqos_probe(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1911,10 +2039,10 @@ static const struct eqos_config eqos_tegra186_config = {
 };
 
 static struct eqos_ops eqos_stm32_ops = {
-	.eqos_inval_desc = eqos_inval_desc_stm32,
-	.eqos_flush_desc = eqos_flush_desc_stm32,
-	.eqos_inval_buffer = eqos_inval_buffer_stm32,
-	.eqos_flush_buffer = eqos_flush_buffer_stm32,
+	.eqos_inval_desc = eqos_inval_desc_generic,
+	.eqos_flush_desc = eqos_flush_desc_generic,
+	.eqos_inval_buffer = eqos_inval_buffer_generic,
+	.eqos_flush_buffer = eqos_flush_buffer_generic,
 	.eqos_probe_resources = eqos_probe_resources_stm32,
 	.eqos_remove_resources = eqos_remove_resources_stm32,
 	.eqos_stop_resets = eqos_stop_resets_stm32,
@@ -1937,6 +2065,33 @@ static const struct eqos_config eqos_stm32_config = {
 	.ops = &eqos_stm32_ops
 };
 
+static struct eqos_ops eqos_imx_ops = {
+	.eqos_inval_desc = eqos_inval_desc_generic,
+	.eqos_flush_desc = eqos_flush_desc_generic,
+	.eqos_inval_buffer = eqos_inval_buffer_generic,
+	.eqos_flush_buffer = eqos_flush_buffer_generic,
+	.eqos_probe_resources = eqos_probe_resources_imx,
+	.eqos_remove_resources = eqos_remove_resources_imx,
+	.eqos_stop_resets = eqos_stop_resets_imx,
+	.eqos_start_resets = eqos_start_resets_imx,
+	.eqos_stop_clks = eqos_stop_clks_imx,
+	.eqos_start_clks = eqos_start_clks_imx,
+	.eqos_calibrate_pads = eqos_calibrate_pads_imx,
+	.eqos_disable_calibration = eqos_disable_calibration_imx,
+	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
+	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
+};
+
+struct eqos_config eqos_imx_config = {
+	.reg_access_always_ok = false,
+	.mdio_wait = 10000,
+	.swr_wait = 50,
+	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+	.interface = eqos_get_interface_imx,
+	.ops = &eqos_imx_ops
+};
+
 static const struct udevice_id eqos_ids[] = {
 	{
 		.compatible = "nvidia,tegra186-eqos",
@@ -1946,6 +2101,10 @@ static const struct udevice_id eqos_ids[] = {
 		.compatible = "snps,dwmac-4.20a",
 		.data = (ulong)&eqos_stm32_config
 	},
+	{
+		.compatible = "fsl,imx-eqos",
+		.data = (ulong)&eqos_imx_config
+	},
 
 	{ }
 };
@@ -1953,7 +2112,7 @@ static const struct udevice_id eqos_ids[] = {
 U_BOOT_DRIVER(eth_eqos) = {
 	.name = "eth_eqos",
 	.id = UCLASS_ETH,
-	.of_match = eqos_ids,
+	.of_match = of_match_ptr(eqos_ids),
 	.probe = eqos_probe,
 	.remove = eqos_remove,
 	.ops = &eqos_ops,
-- 
2.16.4

[PATCH 6/8] net: eqos: implement callbaks to get interface and set txclk rate

[Peng Fan]

From: Fugang Duan <fugang.duan@nxp.com>

Implement the callbacks to get phy mode interface and txclk
rate configuration.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/net/dwc_eth_qos.c | 42 ++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index d63ea5cfb4..85afaf124c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -39,6 +39,7 @@
 #include <phy.h>
 #include <reset.h>
 #include <wait_bit.h>
+#include <asm/arch/clock.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <eth_phy.h>
@@ -870,7 +871,7 @@ static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
 {
 	/* TODO: retrieve from CSR clock */
-	return 100 * 1000000;
+	return imx_get_eqos_csr_clk();
 }
 
 static int eqos_calibrate_pads_stm32(struct udevice *dev)
@@ -996,6 +997,33 @@ static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
 
 static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
 {
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	ulong rate;
+	int ret;
+
+	debug("%s(dev=%p):\n", __func__, dev);
+
+	switch (eqos->phy->speed) {
+	case SPEED_1000:
+		rate = 125 * 1000 * 1000;
+		break;
+	case SPEED_100:
+		rate = 25 * 1000 * 1000;
+		break;
+	case SPEED_10:
+		rate = 2.5 * 1000 * 1000;
+		break;
+	default:
+		pr_err("invalid speed %d", eqos->phy->speed);
+		return -EINVAL;
+	}
+
+	ret = imx_eqos_txclk_set_rate(rate);
+	if (ret < 0) {
+		pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
+		return ret;
+	}
+
 	return 0;
 }
 
@@ -1865,7 +1893,17 @@ static int eqos_probe_resources_imx(struct udevice *dev)
 
 static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
 {
-	return PHY_INTERFACE_MODE_RGMII;
+	const char *phy_mode;
+	phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
+
+	debug("%s(dev=%p):\n", __func__, dev);
+
+	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+			       NULL);
+	if (phy_mode)
+		interface = phy_get_interface_by_name(phy_mode);
+
+	return interface;
 }
 
 static int eqos_remove_resources_tegra186(struct udevice *dev)
-- 
2.16.4

[PATCH 7/8] fec: Move imx_get_mac_from_fuse declare to imx file

[Peng Fan]

From: Ye Li <ye.li@nxp.com>

imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++
 drivers/net/fec_mxc.h                     | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 35b39b1f86..ba930a2088 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -188,4 +188,6 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
 				unsigned long *reg1, unsigned long reg2,
 				unsigned long reg3);
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 #endif
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 159aec8967..18f7c727db 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -271,8 +271,6 @@ struct fec_priv {
 	u32 clk_rate;
 };
 
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-
 /**
  * @brief Numbers of buffer descriptors for receiving
  *
-- 
2.16.4

[PATCH 8/8] eQos: Implement the read_rom_hwaddr callback

[Peng Fan]

From: Ye Li <ye.li@nxp.com>

Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/net/dwc_eth_qos.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 85afaf124c..37b279af35 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -43,6 +43,9 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <eth_phy.h>
+#ifdef CONFIG_ARCH_IMX8M
+#include <asm/mach-imx/sys_proto.h>
+#endif
 
 /* Core registers */
 
@@ -1134,6 +1137,16 @@ static int eqos_write_hwaddr(struct udevice *dev)
 	return 0;
 }
 
+static int eqos_read_rom_hwaddr(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+
+#ifdef CONFIG_ARCH_IMX8M
+	imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr);
+#endif
+	return !is_valid_ethaddr(pdata->enetaddr);
+}
+
 static int eqos_start(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -2047,6 +2060,7 @@ static const struct eth_ops eqos_ops = {
 	.recv = eqos_recv,
 	.free_pkt = eqos_free_pkt,
 	.write_hwaddr = eqos_write_hwaddr,
+	.read_rom_hwaddr	= eqos_read_rom_hwaddr,
 };
 
 static struct eqos_ops eqos_tegra186_ops = {
-- 
2.16.4

[PATCH 5/8] net: dwc_eth_qos: add dwc eqos for imx support

[Daniil Stas]

Hi, i think there are some issues with this patch.

> @@ -1131,6 +1205,7 @@ static int eqos_start(struct udevice *dev)
>  	}
>  
>  	/* Configure MTL */
> +	writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
>  
>  	/* Enable Store and Forward mode for TX */
>  	/* Program Tx operating mode */

What is this address: &eqos->mtl_regs->txq0_quantum_weight - 0x100?
Isn't it outside of MTL registers range?

> @@ -1144,7 +1219,9 @@ static int eqos_start(struct udevice *dev)
>  
>  	/* Enable Store and Forward mode for RX, since no jumbo frame */
>  	setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
> -		     EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
> +		     EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
> +		     EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
> +		     EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
>  
>  	/* Transmit/Receive queue fifo size; use all RAM for 1 queue */
>  	val = readl(&eqos->mac_regs->hw_feature1);

Why do you set FEP and FUP bits? It can lead to data corruption as they
allow accepting erroneous packets.

I think these options should only be used in some debugging mode but not
in production.

> @@ -1220,6 +1297,19 @@ static int eqos_start(struct udevice *dev)
>  			eqos->config->config_mac <<
>  			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
>  
> +	clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
> +			EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
> +			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
> +			0x2 <<
> +			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
> +

This line just overrides the value set in the previous line.
Is it a mistake?

> +	/* enable promise mode */
> +	setbits_le32(&eqos->mac_regs->unused_004[1],
> +		     0x1);
> +

Isn't this mode also useful only for debugging?