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From: "André Almeida" <andrealmeid@igalia.com>
To: "Maíra Canal" <mairacanal@riseup.net>
Cc: magalilemes00@gmail.com, Xinhui.Pan@amd.com,
	Aurabindo Pillai <aurabindo.pillai@amd.com>,
	Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
	Alex Deucher <alexander.deucher@amd.com>,
	Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
	Leo Li <sunpeng.li@amd.com>,
	Harry Wentland <harry.wentland@amd.com>,
	tales.aparecida@gmail.com, linux-kernel@vger.kernel.org,
	amd-gfx@lists.freedesktop.org, mwen@igalia.com,
	Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
	Isabella Basso <isabbasso@riseup.net>,
	andrealmeid@riseup.net, christian.koenig@amd.com,
	Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Subject: Re: [PATCH 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl
Date: Thu, 21 Jul 2022 10:31:25 -0300	[thread overview]
Message-ID: <69e8eb22-0350-a88c-de7a-880da9bb02b1@igalia.com> (raw)
In-Reply-To: <20220720182228.259119-1-mairacanal@riseup.net>

Às 15:22 de 20/07/22, Maíra Canal escreveu:
> As the enum dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not
> used on the codebase, this commit drops those entries from enum
> dm_swizzle_mode.
> 

dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not enums, but
rather enum items or enum entries.

And, as per Linux documentation

Describe your changes in imperative mood, e.g. “make xyzzy do frotz”
instead of “[This patch] makes xyzzy do frotz”

So replace /this commit drops/drop/

> Signed-off-by: Maíra Canal <mairacanal@riseup.net>
> ---
>  .../dc/dml/dcn20/display_mode_vba_20.c        | 26 +++++-------------
>  .../dc/dml/dcn20/display_mode_vba_20v2.c      | 26 +++++-------------
>  .../dc/dml/dcn21/display_mode_vba_21.c        | 27 +++++--------------
>  .../amd/display/dc/dml/display_mode_enums.h   |  2 --
>  .../display/dc/dml/dml_wrapper_translation.c  |  9 -------
>  5 files changed, 19 insertions(+), 71 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index d3b5b6fedf04..4e4cb0927057 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3347,26 +3347,12 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index 63bbdf8b8678..eaa0cdb599ba 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> @@ -998,7 +998,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3454,26 +3454,12 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> index 8a7485e21d53..198d81861ac5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> @@ -1342,7 +1342,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3579,26 +3579,13 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k]
> +								== dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> index f394b3f3922a..0e06727d40b3 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> @@ -89,8 +89,6 @@ enum dm_swizzle_mode {
>  	dm_sw_var_s_x = 29,
>  	dm_sw_var_d_x = 30,
>  	dm_sw_var_r_x = 31,
> -	dm_sw_gfx7_2d_thin_l_vp,
> -	dm_sw_gfx7_2d_thin_gl,
>  };
>  enum lb_depth {
>  	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> index 4ec5310a2962..9edcb6fc83c1 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> @@ -35,15 +35,6 @@ static void gfx10array_mode_to_dml_params(
>  	case DC_ARRAY_LINEAR_GENERAL:
>  		*sw_mode = dm_sw_linear;
>  		break;
> -	case DC_ARRAY_2D_TILED_THIN1:
> -// DC_LEGACY_TILING_ADDR_GEN_ZERO - undefined as per current code hence removed
> -#if 0
> -		if (compat_level == DC_LEGACY_TILING_ADDR_GEN_ZERO)
> -			*sw_mode = dm_sw_gfx7_2d_thin_l_vp;
> -		else
> -			*sw_mode = dm_sw_gfx7_2d_thin_gl;
> -#endif
> -		break;
>  	default:
>  		ASSERT(0); /* Not supported */
>  		break;

WARNING: multiple messages have this Message-ID (diff)
From: "André Almeida" <andrealmeid@igalia.com>
To: "Maíra Canal" <mairacanal@riseup.net>
Cc: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
	magalilemes00@gmail.com, David Airlie <airlied@linux.ie>,
	tales.aparecida@gmail.com, Xinhui.Pan@amd.com,
	Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
	linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org,
	Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
	mwen@igalia.com, Leo Li <sunpeng.li@amd.com>,
	Aurabindo Pillai <aurabindo.pillai@amd.com>,
	Daniel Vetter <daniel@ffwll.ch>,
	Alex Deucher <alexander.deucher@amd.com>,
	Isabella Basso <isabbasso@riseup.net>,
	andrealmeid@riseup.net, Harry Wentland <harry.wentland@amd.com>,
	christian.koenig@amd.com
Subject: Re: [PATCH 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl
Date: Thu, 21 Jul 2022 10:31:25 -0300	[thread overview]
Message-ID: <69e8eb22-0350-a88c-de7a-880da9bb02b1@igalia.com> (raw)
In-Reply-To: <20220720182228.259119-1-mairacanal@riseup.net>

Às 15:22 de 20/07/22, Maíra Canal escreveu:
> As the enum dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not
> used on the codebase, this commit drops those entries from enum
> dm_swizzle_mode.
> 

dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not enums, but
rather enum items or enum entries.

And, as per Linux documentation

Describe your changes in imperative mood, e.g. “make xyzzy do frotz”
instead of “[This patch] makes xyzzy do frotz”

So replace /this commit drops/drop/

> Signed-off-by: Maíra Canal <mairacanal@riseup.net>
> ---
>  .../dc/dml/dcn20/display_mode_vba_20.c        | 26 +++++-------------
>  .../dc/dml/dcn20/display_mode_vba_20v2.c      | 26 +++++-------------
>  .../dc/dml/dcn21/display_mode_vba_21.c        | 27 +++++--------------
>  .../amd/display/dc/dml/display_mode_enums.h   |  2 --
>  .../display/dc/dml/dml_wrapper_translation.c  |  9 -------
>  5 files changed, 19 insertions(+), 71 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index d3b5b6fedf04..4e4cb0927057 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3347,26 +3347,12 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index 63bbdf8b8678..eaa0cdb599ba 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> @@ -998,7 +998,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3454,26 +3454,12 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> index 8a7485e21d53..198d81861ac5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> @@ -1342,7 +1342,7 @@ static unsigned int CalculateVMAndRowBytes(
>  		*MetaRowByte = 0;
>  	}
>  
> -	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> +	if (SurfaceTiling == dm_sw_linear) {
>  		MacroTileSizeBytes = 256;
>  		MacroTileHeight = BlockHeight256Bytes;
>  	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
> @@ -3579,26 +3579,13 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>  										== dm_420_8
>  								|| mode_lib->vba.SourcePixelFormat[k]
>  										== dm_420_10))
> -				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
> -						|| mode_lib->vba.SurfaceTiling[k]
> -								== dm_sw_gfx7_2d_thin_l_vp)
> -						&& !((mode_lib->vba.SourcePixelFormat[k]
> -								== dm_444_64
> +				|| (mode_lib->vba.DCCEnable[k] == true
> +						&& (mode_lib->vba.SurfaceTiling[k]
> +								== dm_sw_linear
>  								|| mode_lib->vba.SourcePixelFormat[k]
> -										== dm_444_32)
> -								&& mode_lib->vba.SourceScan[k]
> -										== dm_horz
> -								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> -										== true
> -								&& mode_lib->vba.DCCEnable[k]
> -										== false))
> -						|| (mode_lib->vba.DCCEnable[k] == true
> -								&& (mode_lib->vba.SurfaceTiling[k]
> -										== dm_sw_linear
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_8
> -										|| mode_lib->vba.SourcePixelFormat[k]
> -												== dm_420_10)))) {
> +										== dm_420_8
> +								|| mode_lib->vba.SourcePixelFormat[k]
> +										== dm_420_10))) {
>  			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> index f394b3f3922a..0e06727d40b3 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> @@ -89,8 +89,6 @@ enum dm_swizzle_mode {
>  	dm_sw_var_s_x = 29,
>  	dm_sw_var_d_x = 30,
>  	dm_sw_var_r_x = 31,
> -	dm_sw_gfx7_2d_thin_l_vp,
> -	dm_sw_gfx7_2d_thin_gl,
>  };
>  enum lb_depth {
>  	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> index 4ec5310a2962..9edcb6fc83c1 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c
> @@ -35,15 +35,6 @@ static void gfx10array_mode_to_dml_params(
>  	case DC_ARRAY_LINEAR_GENERAL:
>  		*sw_mode = dm_sw_linear;
>  		break;
> -	case DC_ARRAY_2D_TILED_THIN1:
> -// DC_LEGACY_TILING_ADDR_GEN_ZERO - undefined as per current code hence removed
> -#if 0
> -		if (compat_level == DC_LEGACY_TILING_ADDR_GEN_ZERO)
> -			*sw_mode = dm_sw_gfx7_2d_thin_l_vp;
> -		else
> -			*sw_mode = dm_sw_gfx7_2d_thin_gl;
> -#endif
> -		break;
>  	default:
>  		ASSERT(0); /* Not supported */
>  		break;

  parent reply	other threads:[~2022-07-21 13:31 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-20 18:22 [PATCH 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl Maíra Canal
2022-07-20 18:22 ` Maíra Canal
2022-07-20 18:22 ` [PATCH 2/4] drm/amd/display: Remove duplicated CalculateWriteBackDISPCLK Maíra Canal
2022-07-20 18:22   ` Maíra Canal
2022-07-21 13:34   ` André Almeida
2022-07-21 13:34     ` André Almeida
2022-07-20 18:22 ` [PATCH 3/4] drm/amd/display: Remove parameters from rq_dlg_get_dlg_reg Maíra Canal
2022-07-20 18:22   ` Maíra Canal
2022-07-20 18:22 ` [PATCH 4/4] drm/amd/display: Rewrite CalculateWriteBackDISPCLK function Maíra Canal
2022-07-20 18:22   ` Maíra Canal
2022-07-21 13:31 ` André Almeida [this message]
2022-07-21 13:31   ` [PATCH 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl André Almeida
2022-07-21 18:26   ` Maíra Canal
2022-07-21 18:26     ` Maíra Canal

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