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From: BAndViG <bandvig@mail.ru>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] OpenRISC 1.3 spec
Date: Wed, 8 May 2019 21:05:58 +0300	[thread overview]
Message-ID: <6CFC558D2E0643BAA8C0CFCB1AEE95BB@BAndViG> (raw)
In-Reply-To: <20190507211254.GD11006@lianli.shorne-pla.net>

> From: Stafford Horne
> Sent: Wednesday, May 08, 2019 12:12 AM
> To: Richard Henderson
> Cc: BAndViG ; Openrisc
> Subject: Re: [OpenRISC] OpenRISC 1.3 spec

> On Tue, May 07, 2019 at 08:28:45AM -0700, Richard Henderson wrote:
> > On 4/25/19 2:17 PM, Stafford Horne wrote:
> > > This is implemented in binutils now. See my patches here:
> > >
> > >   - https://github.com/stffrdhrn/binutils-gdb/commits/orfpx64a32-3
> > >
> > > I have not squashed the commits because it makes it a bit easier for 
> > > reviewing
> > > what I did to get these flags working.
> >
> > I've implemented this for qemu,
> >
> >   https://github.com/rth7680/qemu/commits/tgt-or1k
> >
> > although untested so far.  I need to regenerate my
> > cross-testing environment for or1k...

> This looks good, I like how you do (rD1 + rD1Offset + 1) instead of what I 
> was
> doing (rD1 + (rD1Offset ? 2 : 1 )).  I will fix my matches to use your 
> method.

Ah, I implemented similar approach in MAROCCHINO independently :), see latest 
commit to fp_unordered_cmp branch:
https://github.com/openrisc/or1k_marocchino/commit/313b256875c8b619f5b16db47d915e5dfaedfff7

> Also, just a reminder, the latest patches for GCC FPU support are up here.  I
> have rebased to the 9.1.0 release.  Also, added a new REG CLASS for REG PAIRS 
> to
> fix an issue for when (rD1 + rD1Offset + 1) overflows.

>   https://github.com/stffrdhrn/gcc/commits/or1k-fpu-2

Btw, earlier you wrote "... on one end 64-bit openrisc doesn't looks to even be 
coming ...". Actually I think it wouldn't be a very difficult for me to create 
64-bit OpeRISC by some re-factoring of MAROCCHINO's modules. At the same time 
is anybody interested in it?

Additionally, is anybody interested in little endian support? I've been 
thinking to implement it as a parameter, like OPTION_ENDIAN = "BIG"/"LITTLE". 
With the approach SR[LEE]:
  - should be set at compile time in according with OPTION_ENDIAN value
  - couldn't be changed by writing into SR

WBR
Andrey 


  reply	other threads:[~2019-05-08 18:05 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-12 20:56 [OpenRISC] OpenRISC 1.3 spec Stafford Horne
2019-04-12 21:17 ` Richard Henderson
2019-04-12 21:48   ` Stafford Horne
2019-04-13  8:11     ` Richard Henderson
2019-04-13  8:47       ` Stafford Horne
2019-04-14  9:41         ` BAndViG
2019-04-25 21:17           ` Stafford Horne
2019-04-26 22:22             ` Stafford Horne
2019-05-02 12:22               ` BAndViG
2019-05-07 15:28             ` Richard Henderson
2019-05-07 21:12               ` Stafford Horne
2019-05-08 18:05                 ` BAndViG [this message]
2019-05-09 20:29                   ` Stafford Horne
2019-05-09 21:47                   ` Richard Henderson
2019-05-10  7:56                     ` BAndViG
2019-05-11 10:04                       ` Stafford Horne
2019-05-12 19:58                         ` BAndViG
2019-05-12 23:09                           ` Stafford Horne
2019-06-06 22:11                           ` Stafford Horne
2019-06-15  6:14                             ` Stafford Horne
2019-04-13  8:03 ` Richard Henderson
2019-04-14  6:30   ` Stafford Horne
2019-04-14  6:48     ` Stafford Horne

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