All of lore.kernel.org
 help / color / mirror / Atom feed
From: Richard Henderson <rth@twiddle.net>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] OpenRISC 1.3 spec
Date: Fri, 12 Apr 2019 11:17:46 -1000	[thread overview]
Message-ID: <afc760d8-0e01-6470-c8d2-6ddc366f3d10@twiddle.net> (raw)
In-Reply-To: <CAAfxs77GkWenpN0s1pM_YeVgNZabBx55fCqLfxoMffTSa-E=cw@mail.gmail.com>

On 4/12/19 10:56 AM, Stafford Horne wrote:
> P14 https://openrisc.io/proposals/orfpx64a32 - 64-bit fpu implemented in
> marocchino (gcc/bintuils patches under review)

I don't see an encoding for this in the proposal.

I'm a tad nervous about forcing the (weird) ABI into the ISA, by using reg+2
when reg >= 16.  Are there 3 bits in the instruction that could be used to flag
reg+1 vs reg+2?  Then it's a matter of using

	lf.add.d rd1, rd2, ra1, ra2, rb1, rb2

in the assembler, and having the assembler enforce rx2 = rx1+{1,2}, and setting
the appropriate bit in the instruction.

I realize this comment is coming in quite late to your development...


r~

  reply	other threads:[~2019-04-12 21:17 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-12 20:56 [OpenRISC] OpenRISC 1.3 spec Stafford Horne
2019-04-12 21:17 ` Richard Henderson [this message]
2019-04-12 21:48   ` Stafford Horne
2019-04-13  8:11     ` Richard Henderson
2019-04-13  8:47       ` Stafford Horne
2019-04-14  9:41         ` BAndViG
2019-04-25 21:17           ` Stafford Horne
2019-04-26 22:22             ` Stafford Horne
2019-05-02 12:22               ` BAndViG
2019-05-07 15:28             ` Richard Henderson
2019-05-07 21:12               ` Stafford Horne
2019-05-08 18:05                 ` BAndViG
2019-05-09 20:29                   ` Stafford Horne
2019-05-09 21:47                   ` Richard Henderson
2019-05-10  7:56                     ` BAndViG
2019-05-11 10:04                       ` Stafford Horne
2019-05-12 19:58                         ` BAndViG
2019-05-12 23:09                           ` Stafford Horne
2019-06-06 22:11                           ` Stafford Horne
2019-06-15  6:14                             ` Stafford Horne
2019-04-13  8:03 ` Richard Henderson
2019-04-14  6:30   ` Stafford Horne
2019-04-14  6:48     ` Stafford Horne

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=afc760d8-0e01-6470-c8d2-6ddc366f3d10@twiddle.net \
    --to=rth@twiddle.net \
    --cc=openrisc@lists.librecores.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.