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From: Xianting TIan <xianting.tian@linux.alibaba.com>
To: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, guoren@kernel.org, arnd@arndb.de
Subject: Re: [PATCH] riscv: add ARCH_DMA_MINALIGN support
Date: Mon, 9 Aug 2021 09:55:43 +0800	[thread overview]
Message-ID: <6a189d9d-b35d-3a15-5bfa-172c50e60c8c@linux.alibaba.com> (raw)
In-Reply-To: <20210809003044.6692ddce@xhacker>


在 2021/8/9 上午12:30, Jisheng Zhang 写道:
> On Sat,  7 Aug 2021 22:55:37 +0800
> Xianting Tian <xianting.tian@linux.alibaba.com> wrote:
>
>> Introduce ARCH_DMA_MINALIGN to riscv arch.
>>
>> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
>> ---
>>   arch/riscv/include/asm/cache.h | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
>> index 9b58b1045..2945bbe2b 100644
>> --- a/arch/riscv/include/asm/cache.h
>> +++ b/arch/riscv/include/asm/cache.h
>> @@ -11,6 +11,8 @@
>>   
>>   #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
>>   
>> +#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
> It's not a good idea to blindly set this for all riscv. For "coherent"
> platforms, this is not necessary and will waste memory.
>
thanks for the reply,

So riscv is the "coherent" platform?

I submit this patch as I got a fix suggestion of another patch to use 
ARCH_DMA_MINALIGN, but riscv doesn't define it.

https://lkml.org/lkml/2021/8/6/723 <https://lkml.org/lkml/2021/8/6/723>

Considering the portability of the code, in my opinion, it is better to 
define it for riscv if it is not "coherent" platform.

>> +
>>   /*
>>    * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
>>    * the flat loader aligns it accordingly.

WARNING: multiple messages have this Message-ID (diff)
From: Xianting TIan <xianting.tian@linux.alibaba.com>
To: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, guoren@kernel.org, arnd@arndb.de
Subject: Re: [PATCH] riscv: add ARCH_DMA_MINALIGN support
Date: Mon, 9 Aug 2021 09:55:43 +0800	[thread overview]
Message-ID: <6a189d9d-b35d-3a15-5bfa-172c50e60c8c@linux.alibaba.com> (raw)
In-Reply-To: <20210809003044.6692ddce@xhacker>


在 2021/8/9 上午12:30, Jisheng Zhang 写道:
> On Sat,  7 Aug 2021 22:55:37 +0800
> Xianting Tian <xianting.tian@linux.alibaba.com> wrote:
>
>> Introduce ARCH_DMA_MINALIGN to riscv arch.
>>
>> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
>> ---
>>   arch/riscv/include/asm/cache.h | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
>> index 9b58b1045..2945bbe2b 100644
>> --- a/arch/riscv/include/asm/cache.h
>> +++ b/arch/riscv/include/asm/cache.h
>> @@ -11,6 +11,8 @@
>>   
>>   #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
>>   
>> +#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
> It's not a good idea to blindly set this for all riscv. For "coherent"
> platforms, this is not necessary and will waste memory.
>
thanks for the reply,

So riscv is the "coherent" platform?

I submit this patch as I got a fix suggestion of another patch to use 
ARCH_DMA_MINALIGN, but riscv doesn't define it.

https://lkml.org/lkml/2021/8/6/723 <https://lkml.org/lkml/2021/8/6/723>

Considering the portability of the code, in my opinion, it is better to 
define it for riscv if it is not "coherent" platform.

>> +
>>   /*
>>    * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
>>    * the flat loader aligns it accordingly.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2021-08-09  1:55 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-07 14:55 [PATCH] riscv: add ARCH_DMA_MINALIGN support Xianting Tian
2021-08-07 14:55 ` Xianting Tian
2021-08-08 16:30 ` Jisheng Zhang
2021-08-08 16:30   ` Jisheng Zhang
2021-08-09  1:55   ` Xianting TIan [this message]
2021-08-09  1:55     ` Xianting TIan
2021-08-10  1:30     ` Guo Ren
2021-08-10  1:30       ` Guo Ren
2021-08-09  6:20   ` Xianting TIan
2021-08-09  6:20     ` Xianting TIan
2021-08-09  7:49     ` Arnd Bergmann
2021-08-09  7:49       ` Arnd Bergmann
2021-08-09  9:00       ` Xianting TIan
2021-08-09  9:00         ` Xianting TIan
2021-08-09 19:19       ` Atish Patra
2021-08-09 19:19         ` Atish Patra

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