[PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[Alex Deucher]

Not all vbios images seem to set the version appropriately.
Switch the check based on asic type instead.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 365e735..ea3a250 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -86,19 +86,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
 	return false;
 }
 
-static bool is_atom_fw(uint8_t *bios)
-{
-	uint16_t bios_header_start = bios[0x48] | (bios[0x49] << 8);
-	uint8_t frev = bios[bios_header_start + 2];
-	uint8_t crev = bios[bios_header_start + 3];
-
-	if ((frev < 3) ||
-	    ((frev == 3) && (crev < 3)))
-		return false;
-
-	return true;
-}
-
 /* If you boot an IGP board with a discrete card as the primary,
  * the IGP rom is not accessible via the rom bar as the IGP rom is
  * part of the system bios.  On boot, the system bios puts a
@@ -455,6 +442,6 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
 	return false;
 
 success:
-	adev->is_atom_fw = is_atom_fw(adev->bios);
+	adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true : false;
 	return true;
 }
-- 
2.5.5

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[PATCH 2/3] drm/amdgpu/atomfirmware: implement vram_width for APUs

[Alex Deucher]

Implement support using the new atomfirmware system info table.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 33 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h |  1 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 4bdda56..7a0212b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -130,3 +130,36 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 	ctx->scratch_size_bytes = usage_bytes;
 	return 0;
 }
+
+union igp_info {
+	struct atom_integrated_system_info_v1_11 v11;
+};
+
+/*
+ * Return vram width from integrated system info table, if available,
+ * or 0 if not.
+ */
+int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
+{
+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+						integratedsysteminfo);
+	u16 data_offset, size;
+	union igp_info *igp_info;
+	u8 frev, crev;
+
+	/* get any igp specific overrides */
+	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
+				   &frev, &crev, &data_offset)) {
+		igp_info = (union igp_info *)
+			(mode_info->atom_context->bios + data_offset);
+		switch (crev) {
+		case 11:
+			return igp_info->v11.umachannelnumber * 64;
+		default:
+			return 0;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index a2c3ebe..e37e4c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -31,5 +31,6 @@ void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev);
 void amdgpu_atomfirmware_scratch_regs_engine_hung(struct amdgpu_device *adev,
 						  bool hung);
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
+int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
 
 #endif
-- 
2.5.5

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[PATCH 3/3] drm/amdgpu/gmc9: get vram width from atom for Raven

[Alex Deucher]

Get it from the system info table.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 76 ++++++++++++++++++-----------------
 1 file changed, 40 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 175ba5f..19f3ffb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -23,6 +23,7 @@
 #include <linux/firmware.h>
 #include "amdgpu.h"
 #include "gmc_v9_0.h"
+#include "amdgpu_atomfirmware.h"
 
 #include "vega10/soc15ip.h"
 #include "vega10/HDP/hdp_4_0_offset.h"
@@ -442,43 +443,46 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 	u32 tmp;
 	int chansize, numchan;
 
-	/* hbm memory channel size */
-	chansize = 128;
-
-	tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
-	tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
-	tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
-	switch (tmp) {
-	case 0:
-	default:
-		numchan = 1;
-		break;
-	case 1:
-		numchan = 2;
-		break;
-	case 2:
-		numchan = 0;
-		break;
-	case 3:
-		numchan = 4;
-		break;
-	case 4:
-		numchan = 0;
-		break;
-	case 5:
-		numchan = 8;
-		break;
-	case 6:
-		numchan = 0;
-		break;
-	case 7:
-		numchan = 16;
-		break;
-	case 8:
-		numchan = 2;
-		break;
+	adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
+	if (!adev->mc.vram_width) {
+		/* hbm memory channel size */
+		chansize = 128;
+
+		tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
+		tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+		tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
+		switch (tmp) {
+		case 0:
+		default:
+			numchan = 1;
+			break;
+		case 1:
+			numchan = 2;
+			break;
+		case 2:
+			numchan = 0;
+			break;
+		case 3:
+			numchan = 4;
+			break;
+		case 4:
+			numchan = 0;
+			break;
+		case 5:
+			numchan = 8;
+			break;
+		case 6:
+			numchan = 0;
+			break;
+		case 7:
+			numchan = 16;
+			break;
+		case 8:
+			numchan = 2;
+			break;
+		}
+		adev->mc.vram_width = numchan * chansize;
 	}
-	adev->mc.vram_width = numchan * chansize;
 
 	/* Could aper size report 0 ? */
 	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
-- 
2.5.5

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RE: [PATCH 2/3] drm/amdgpu/atomfirmware: implement vram_width for APUs

[Zhang, Hawking]

Series are Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Alex Deucher
Sent: Thursday, July 06, 2017 3:51
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH 2/3] drm/amdgpu/atomfirmware: implement vram_width for APUs

Implement support using the new atomfirmware system info table.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 33 ++++++++++++++++++++++++  drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h |  1 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 4bdda56..7a0212b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -130,3 +130,36 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 	ctx->scratch_size_bytes = usage_bytes;
 	return 0;
 }
+
+union igp_info {
+	struct atom_integrated_system_info_v1_11 v11; };
+
+/*
+ * Return vram width from integrated system info table, if available,
+ * or 0 if not.
+ */
+int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev) {
+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+						integratedsysteminfo);
+	u16 data_offset, size;
+	union igp_info *igp_info;
+	u8 frev, crev;
+
+	/* get any igp specific overrides */
+	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
+				   &frev, &crev, &data_offset)) {
+		igp_info = (union igp_info *)
+			(mode_info->atom_context->bios + data_offset);
+		switch (crev) {
+		case 11:
+			return igp_info->v11.umachannelnumber * 64;
+		default:
+			return 0;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index a2c3ebe..e37e4c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -31,5 +31,6 @@ void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev);  void amdgpu_atomfirmware_scratch_regs_engine_hung(struct amdgpu_device *adev,
 						  bool hung);
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
+int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
 
 #endif
--
2.5.5

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Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[Christian König]

Am 05.07.2017 um 21:51 schrieb Alex Deucher:
> Not all vbios images seem to set the version appropriately.
> Switch the check based on asic type instead.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 15 +--------------
>   1 file changed, 1 insertion(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> index 365e735..ea3a250 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> @@ -86,19 +86,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
>   	return false;
>   }
>   
> -static bool is_atom_fw(uint8_t *bios)
> -{
> -	uint16_t bios_header_start = bios[0x48] | (bios[0x49] << 8);
> -	uint8_t frev = bios[bios_header_start + 2];
> -	uint8_t crev = bios[bios_header_start + 3];
> -
> -	if ((frev < 3) ||
> -	    ((frev == 3) && (crev < 3)))
> -		return false;
> -
> -	return true;
> -}
> -
>   /* If you boot an IGP board with a discrete card as the primary,
>    * the IGP rom is not accessible via the rom bar as the IGP rom is
>    * part of the system bios.  On boot, the system bios puts a
> @@ -455,6 +442,6 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
>   	return false;
>   
>   success:
> -	adev->is_atom_fw = is_atom_fw(adev->bios);
> +	adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true : false;

The "? true : false" part looks a bit superfluous.

Apart from that the series is Acked-by: Christian König 
<christian.koenig@amd.com>.

Regards,
Christian.

>   	return true;
>   }


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Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[Marek Olšák]

Hi Alex,

This commit causes that clock_crystal_freq is 0 on Raven, demoting
OpenGL support from 4.5 to 3.2. Can I revert?

Marek

On Wed, Jul 5, 2017 at 9:51 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Not all vbios images seem to set the version appropriately.
> Switch the check based on asic type instead.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 15 +--------------
>  1 file changed, 1 insertion(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> index 365e735..ea3a250 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> @@ -86,19 +86,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
>         return false;
>  }
>
> -static bool is_atom_fw(uint8_t *bios)
> -{
> -       uint16_t bios_header_start = bios[0x48] | (bios[0x49] << 8);
> -       uint8_t frev = bios[bios_header_start + 2];
> -       uint8_t crev = bios[bios_header_start + 3];
> -
> -       if ((frev < 3) ||
> -           ((frev == 3) && (crev < 3)))
> -               return false;
> -
> -       return true;
> -}
> -
>  /* If you boot an IGP board with a discrete card as the primary,
>   * the IGP rom is not accessible via the rom bar as the IGP rom is
>   * part of the system bios.  On boot, the system bios puts a
> @@ -455,6 +442,6 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
>         return false;
>
>  success:
> -       adev->is_atom_fw = is_atom_fw(adev->bios);
> +       adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true : false;
>         return true;
>  }
> --
> 2.5.5
>
> _______________________________________________
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RE: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[Deucher, Alexander]

> -----Original Message-----
> From: Marek Olšák [mailto:maraeo@gmail.com]
> Sent: Saturday, July 08, 2017 7:08 PM
> To: Alex Deucher
> Cc: amd-gfx mailing list; Deucher, Alexander
> Subject: Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check
> 
> Hi Alex,
> 
> This commit causes that clock_crystal_freq is 0 on Raven, demoting
> OpenGL support from 4.5 to 3.2. Can I revert?

The problem is, it's just reading garbage right now.  It would be better to just hardcode the reference clock until I can figure out where the reference clock is in atomfirmware.

Alex

> 
> Marek
> 
> On Wed, Jul 5, 2017 at 9:51 PM, Alex Deucher <alexdeucher@gmail.com>
> wrote:
> > Not all vbios images seem to set the version appropriately.
> > Switch the check based on asic type instead.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 15 +--------------
> >  1 file changed, 1 insertion(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> > index 365e735..ea3a250 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> > @@ -86,19 +86,6 @@ static bool check_atom_bios(uint8_t *bios, size_t
> size)
> >         return false;
> >  }
> >
> > -static bool is_atom_fw(uint8_t *bios)
> > -{
> > -       uint16_t bios_header_start = bios[0x48] | (bios[0x49] << 8);
> > -       uint8_t frev = bios[bios_header_start + 2];
> > -       uint8_t crev = bios[bios_header_start + 3];
> > -
> > -       if ((frev < 3) ||
> > -           ((frev == 3) && (crev < 3)))
> > -               return false;
> > -
> > -       return true;
> > -}
> > -
> >  /* If you boot an IGP board with a discrete card as the primary,
> >   * the IGP rom is not accessible via the rom bar as the IGP rom is
> >   * part of the system bios.  On boot, the system bios puts a
> > @@ -455,6 +442,6 @@ bool amdgpu_get_bios(struct amdgpu_device
> *adev)
> >         return false;
> >
> >  success:
> > -       adev->is_atom_fw = is_atom_fw(adev->bios);
> > +       adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true :
> false;
> >         return true;
> >  }
> > --
> > 2.5.5
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[Marek Olšák]

[-- Attachment #1.1: Type: text/plain, Size: 806 bytes --]

On Mon, Jul 10, 2017 at 3:49 PM, Deucher, Alexander <
Alexander.Deucher-5C7GfCeVMHo@public.gmane.org> wrote:

> > -----Original Message-----
> > From: Marek Olšák [mailto:maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org]
> > Sent: Saturday, July 08, 2017 7:08 PM
> > To: Alex Deucher
> > Cc: amd-gfx mailing list; Deucher, Alexander
> > Subject: Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check
> >
> > Hi Alex,
> >
> > This commit causes that clock_crystal_freq is 0 on Raven, demoting
> > OpenGL support from 4.5 to 3.2. Can I revert?
>
> The problem is, it's just reading garbage right now.  It would be better
> to just hardcode the reference clock until I can figure out where the
> reference clock is in atomfirmware.
>

OK. I'll find a way to work around it in Mesa.

Marek

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RE: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[Deucher, Alexander]

[-- Attachment #1.1: Type: text/plain, Size: 1104 bytes --]

I just sent patches to fix it.  Sorry my internet service has been out all day.  I'm just catching up now.

Alex

From: Marek Olšák [mailto:maraeo@gmail.com]
Sent: Monday, July 10, 2017 10:08 AM
To: Deucher, Alexander
Cc: Alex Deucher; amd-gfx mailing list
Subject: Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

On Mon, Jul 10, 2017 at 3:49 PM, Deucher, Alexander <Alexander.Deucher@amd.com<mailto:Alexander.Deucher@amd.com>> wrote:
> -----Original Message-----
> From: Marek Olšák [mailto:maraeo@gmail.com<mailto:maraeo@gmail.com>]
> Sent: Saturday, July 08, 2017 7:08 PM
> To: Alex Deucher
> Cc: amd-gfx mailing list; Deucher, Alexander
> Subject: Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check
>
> Hi Alex,
>
> This commit causes that clock_crystal_freq is 0 on Raven, demoting
> OpenGL support from 4.5 to 3.2. Can I revert?

The problem is, it's just reading garbage right now.  It would be better to just hardcode the reference clock until I can figure out where the reference clock is in atomfirmware.

OK. I'll find a way to work around it in Mesa.
Marek

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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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