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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Marek Vasut <marex@denx.de>,
	Sandra Loosemore <sandra@codesourcery.com>,
	Chris Wulff <crwulff@gmail.com>,
	Wentong Wu <wentong.wu@intel.com>
Subject: Re: [PATCH v2 1/3] target/nios2: Move IIC code into CPU object proper
Date: Mon, 30 Nov 2020 13:13:09 +0100	[thread overview]
Message-ID: <6ac9a9b2-f8f9-2437-c4f1-953b8c66729d@amsat.org> (raw)
In-Reply-To: <20201129174022.26530-2-peter.maydell@linaro.org>

On 11/29/20 6:40 PM, Peter Maydell wrote:
> The Nios2 architecture supports two different interrupt controller
> options:
> 
>  * The IIC (Internal Interrupt Controller) is part of the CPU itself;
>    it has 32 IRQ input lines and no NMI support.  Interrupt status is
>    queried and controlled via the CPU's ipending and istatus
>    registers.
> 
>  * The EIC (External Interrupt Controller) interface allows the CPU
>    to connect to an external interrupt controller.  The interface
>    allows the interrupt controller to present a packet of information
>    containing:
>     - handler address
>     - interrupt level
>     - register set
>     - NMI mode
> 
> QEMU does not model an EIC currently.  We do model the IIC, but its
> implementation is split across code in hw/nios2/cpu_pic.c and
> hw/intc/nios2_iic.c.  The code in those two files has no state of its
> own -- the IIC state is in the Nios2CPU state struct.
> 
> Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they
> can have GPIO input lines themselves, so we can implement the IIC
> directly in the CPU object the same way that real hardware does.
> 
> Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the
> only user of the IIC wire up directly to those instead.
> 
> Note that the old code had an "NMI" concept which was entirely unused
> and also as far as I can see not architecturally correct, since only
> the EIC has a concept of an NMI.
> 
> This fixes a Coverity-reported trivial memory leak of the IRQ array
> allocated in nios2_cpu_pic_init().
> 
> Fixes: Coverity CID 1421916
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/nios2/cpu.h        |  1 -
>  hw/intc/nios2_iic.c       | 95 ---------------------------------------
>  hw/nios2/10m50_devboard.c | 13 +-----
>  hw/nios2/cpu_pic.c        | 31 -------------
>  target/nios2/cpu.c        | 30 +++++++++++++
>  MAINTAINERS               |  1 -
>  hw/intc/meson.build       |  1 -
>  7 files changed, 32 insertions(+), 140 deletions(-)
>  delete mode 100644 hw/intc/nios2_iic.c

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  parent reply	other threads:[~2020-11-30 12:14 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-29 17:40 [PATCH v2 0/3] target/nios2: Roll cpu_pic/nios2_iic code into CPU itself Peter Maydell
2020-11-29 17:40 ` [PATCH v2 1/3] target/nios2: Move IIC code into CPU object proper Peter Maydell
2020-11-30  5:41   ` Wu, Wentong
2020-11-30  9:53     ` Peter Maydell
2020-11-30 13:12       ` Wu, Wentong
2020-11-30 12:13   ` Philippe Mathieu-Daudé [this message]
2020-11-29 17:40 ` [PATCH v2 2/3] target/nios2: Move nios2_check_interrupts() into target/nios2 Peter Maydell
2020-11-30  5:43   ` Wu, Wentong
2020-11-29 17:40 ` [PATCH v2 3/3] target/nios2: Use deposit32() to update ipending register Peter Maydell
2020-11-30  9:55   ` Philippe Mathieu-Daudé
2020-12-11 14:05 ` [PATCH v2 0/3] target/nios2: Roll cpu_pic/nios2_iic code into CPU itself Peter Maydell

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