From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org,
mark.rutland@arm.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V4 03/17] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0
Date: Tue, 19 May 2020 11:44:33 +0100 [thread overview]
Message-ID: <6bbdb3e5-d6bd-db8f-4de9-a964f19c9ac4@arm.com> (raw)
In-Reply-To: <1589881254-10082-4-git-send-email-anshuman.khandual@arm.com>
On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
> Double lock feature can have the following possible values.
>
> 0b0000 - Double lock implemented
> 0b1111 - Double lock not implemented
>
> But in case of a conflict the safe value should be 0b1111. Hence this must
> be a signed feature instead. Also change FTR_EXACT to FTR_LOWER_SAFE. While
> here, fix the erroneous bit width value from 28 to 4.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org,
linux-kernel@vger.kernel.org, maz@kernel.org
Subject: Re: [PATCH V4 03/17] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0
Date: Tue, 19 May 2020 11:44:33 +0100 [thread overview]
Message-ID: <6bbdb3e5-d6bd-db8f-4de9-a964f19c9ac4@arm.com> (raw)
In-Reply-To: <1589881254-10082-4-git-send-email-anshuman.khandual@arm.com>
On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
> Double lock feature can have the following possible values.
>
> 0b0000 - Double lock implemented
> 0b1111 - Double lock not implemented
>
> But in case of a conflict the safe value should be 0b1111. Hence this must
> be a signed feature instead. Also change FTR_EXACT to FTR_LOWER_SAFE. While
> here, fix the erroneous bit width value from 28 to 4.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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next prev parent reply other threads:[~2020-05-19 10:39 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 9:40 [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 01/17] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 02/17] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 03/17] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:44 ` Suzuki K Poulose [this message]
2020-05-19 10:44 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 04/17] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 05/17] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:46 ` Suzuki K Poulose
2020-05-19 10:46 ` Suzuki K Poulose
2020-05-19 10:46 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 06/17] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:50 ` Suzuki K Poulose
2020-05-19 10:50 ` Suzuki K Poulose
2020-05-19 10:50 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 07/17] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 08/17] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:53 ` Suzuki K Poulose
2020-05-19 10:53 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 09/17] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 10:56 ` Suzuki K Poulose
2020-05-19 10:56 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 10/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 11:11 ` Suzuki K Poulose
2020-05-19 11:11 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 11/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 11:13 ` Suzuki K Poulose
2020-05-19 11:13 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 12/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 13:32 ` Suzuki K Poulose
2020-05-19 13:32 ` Suzuki K Poulose
2020-05-24 23:08 ` Anshuman Khandual
2020-05-24 23:08 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 13:44 ` Suzuki K Poulose
2020-05-19 13:44 ` Suzuki K Poulose
2020-05-24 1:09 ` Anshuman Khandual
2020-05-24 1:09 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 14/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-20 13:56 ` Suzuki K Poulose
2020-05-20 13:56 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 15/17] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-20 13:57 ` Suzuki K Poulose
2020-05-20 13:57 ` Suzuki K Poulose
2020-05-24 1:08 ` Anshuman Khandual
2020-05-24 1:08 ` Anshuman Khandual
2020-05-25 10:46 ` Suzuki K Poulose
2020-05-25 10:46 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 16/17] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 17/17] arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context Anshuman Khandual
2020-05-19 9:40 ` Anshuman Khandual
2020-05-20 13:58 ` Suzuki K Poulose
2020-05-20 13:58 ` Suzuki K Poulose
2020-05-21 15:19 ` [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Will Deacon
2020-05-21 15:19 ` Will Deacon
2020-05-21 15:19 ` Will Deacon
2020-05-25 12:39 ` Anshuman Khandual
2020-05-25 12:39 ` Anshuman Khandual
2020-05-25 12:39 ` Anshuman Khandual
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