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From: Alexandre IOOSS <erdnaxe@crans.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	"open list:STM32F100" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC
Date: Tue, 15 Jun 2021 09:49:59 +0200	[thread overview]
Message-ID: <6bcf8d1b-7caf-ded5-937a-4c1bf96e2d85@crans.org> (raw)
In-Reply-To: <CAKmqyKMs4Sr9oXR8k3jeXo=Umy3F6k-CfQW4Fz3zB++uFKkmDg@mail.gmail.com>


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On 6/15/21 9:41 AM, Alistair Francis wrote:
> Aren't you missing some timers, like timer[5] 0x4000_0C00?
> 
> Alistair

I double-checked using the reference manual and the datasheet and there 
is not timer[5]:
- page 36 of 
https://www.st.com/resource/en/reference_manual/cd00246267-stm32f100xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
- page 30 of https://www.st.com/resource/en/datasheet/stm32f100cb.pdf

I believe ST is skipping numbers to guarantee that timer[n] will have a 
consistent address on different STM32 SoC.

Thanks,
-- Alexandre


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  reply	other threads:[~2021-06-15  7:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-08 16:10 [PATCH 0/2] STM32VLDISCOVERY Machine Model Alexandre Iooss
2021-06-08 16:10 ` [PATCH 1/2] stm32f100: Add the stm32f100 SoC Alexandre Iooss
2021-06-14 16:04   ` Peter Maydell
2021-06-15  7:56     ` Alexandre IOOSS
2021-06-15  7:41   ` Alistair Francis
2021-06-15  7:49     ` Alexandre IOOSS [this message]
2021-06-15  8:04       ` Alistair Francis
2021-06-15  9:15         ` Alexandre IOOSS
2021-06-15 10:40           ` Alistair Francis
2021-06-08 16:10 ` [PATCH 2/2] stm32vldiscovery: Add the STM32VLDISCOVERY Machine Alexandre Iooss
2021-06-14 15:52   ` Peter Maydell
2021-06-15  7:16     ` Alexandre IOOSS
2021-06-15  7:50       ` Alistair Francis
2021-06-15  9:07       ` Peter Maydell
2021-06-14 16:05 ` [PATCH 0/2] STM32VLDISCOVERY Machine Model Peter Maydell
2021-06-14 16:16   ` Philippe Mathieu-Daudé

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